40912 lines
3.0 MiB
40912 lines
3.0 MiB
; --------------------------------------------------------------------------------
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; @Title: CYT6BJx On-Chip Peripherals
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; @Props: Released
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; @Author: JDU, NEJ
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; @Changelog: 2023-05-17 JDU
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; 2023-11-06 NEJ
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; @Manufacturer: INFINEON - Infineon Technologies AG
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; @Doc: Generated (TRACE32, build: 164232.), based on:
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; cyt6bj.svd (Ver. 1.0)
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; @Core: Cortex-M0+, Cortex-M7F
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; @Chip: CYT6BJ8-CM0+, CYT6BJ8-CM7, CYT6BJ8-CM7-0, CYT6BJ8-CM7-1, CYT6BJ8-CM7-2,
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; CYT6BJ8-CM7-3, CYT6BJB-CM0+, CYT6BJB-CM7, CYT6BJB-CM7-0, CYT6BJB-CM7-1,
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; CYT6BJB-CM7-2, CYT6BJB-CM7-3, CYT6BJC-CM0+, CYT6BJC-CM7, CYT6BJC-CM7-0,
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; CYT6BJC-CM7-1, CYT6BJC-CM7-2, CYT6BJC-CM7-3
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; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: percyt6bj.per 16948 2023-11-08 11:06:33Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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sif (CORENAME()=="CORTEXM7F")
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tree.close "Core Registers (Cortex-M7F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 28. " DISFPUISSOPT ,DISFPUISSOPT" "No,Yes"
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bitfld.long 0x00 27. " DISCRITAXIRUW ,Disables critical AXI read-under-write" "No,Yes"
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bitfld.long 0x00 26. " DISDYNADD ,Disables dynamic allocation of ADD and SUB instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 21.--25. " DISISSCH1 ,DISISSCH1" "Normal,Not issued in ch1,,,,,,,,,,,,,,,,,,,,Direct branches,Indirect branches,Loaded to PC,Integer MAC and MUL,VFP,?..."
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bitfld.long 0x00 16.--20. " DISDI ,DISDI" "Normal,ch1,,,,,,,,,,,,,,,Direct branches,Indirect branches,Loaded to PC,Integer MAC and MUL,VFP,?..."
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bitfld.long 0x00 15. " DISCRITAXIRUR ,Disables critical AXI read-under-read" "No,Yes"
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textline " "
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bitfld.long 0x00 14. " DISBTACALLOC ,DISBTACALLOC" "No,Yes"
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bitfld.long 0x00 13. " DISBTACREAD ,DISBTACREAD" "No,Yes"
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bitfld.long 0x00 12. " DISITMATBFLUSH ,Disables ITM and DWT ATB flush" "No,Yes"
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textline " "
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bitfld.long 0x00 11. " DISRAMODE ,Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions" "No,Yes"
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bitfld.long 0x00 10. " FPEXCODIS ,Disables FPU exception outputs" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables dual-issue functionality" "No,Yes"
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textline ""
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group.long 0x10++0x03
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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group.long 0x14++0x07
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line.long 0x00 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x00 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x04 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPUID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Indicates implementer"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,Revision 1,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "Patch 0,Patch 1,Patch 2,?..."
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control and State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,On writes, makes the NMI exception active. On reads, indicates the state of the exception" "Inactive,Active"
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setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET ,On writes, sets the PendSV exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
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setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
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textline " "
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rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
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rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt"
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textline " "
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rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key"
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rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,Writing 1 to this bit causes a local system reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration and Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,Determines whether the exception entry sequence guarantees 8-byte stack frame alignment, adjusting the SP if necessary before saving state" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise data access faults on handlers running at priority -1 or priority -2" "Lockup,Ignored"
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bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
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bitfld.long 0x10 0. " NONBASETHRDENA ,Controls whether the processor can enter Thread mode at an execution priority level other than base level" "Disabled,Enabled"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,MemManage" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall status" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault status" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage status" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault status" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick status" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV status" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor status" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall status" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault status" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault status" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage status" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x13
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line.long 0x00 "HFSR,HardFault Status Register"
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eventfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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eventfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred"
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eventfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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eventfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not occurred,Occurred"
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eventfld.long 0x04 3. " VCATCH ,Indicates triggering of a Vector catch" "Not occurred,Occurred"
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eventfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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eventfld.long 0x04 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not occurred,Occurred"
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eventfld.long 0x04 0. " HALTED ,Indicates a debug event generated by a C_HALT or C_STEP request or a step request triggered by setting DEMCR.MON_STEP to 1" "Not occurred,Occurred"
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line.long 0x08 "MMFAR,MemManage Fault Address Register"
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line.long 0x0C "BFAR,BusFault Address Register"
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line.long 0x10 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Denied,Privileged,,Full"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Denied,Privileged,,Full"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Denied,Privileged,,Full"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Denied,Privileged,,Full"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Denied,Privileged,,Full"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Denied,Privileged,,Full"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Denied,Privileged,,Full"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Denied,Privileged,,Full"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Denied,Privileged,,Full"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Denied,Privileged,,Full"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Triggered Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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tree "Memory System"
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width 10.
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rgroup.long 0xD78++0x0B
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line.long 0x00 "CLIDR,Cache Level ID Register"
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bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "Level 1,level 2,?..."
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bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,level 2,?..."
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bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,?..."
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textline " "
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bitfld.long 0x00 15.--17. " CL6 ,Cache type field level 6" "No cache,?..."
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bitfld.long 0x00 12.--14. " CL5 ,Cache type field level 5" "No cache,?..."
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bitfld.long 0x00 9.--11. " CL4 ,Cache type field level 4" "No cache,?..."
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textline " "
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bitfld.long 0x00 6.--8. " CL3 ,Cache type field level 3" "No cache,?..."
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bitfld.long 0x00 3.--5. " CL2 ,Cache type field level 2" "No cache,?..."
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bitfld.long 0x00 0.--2. " CL1 ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..."
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line.long 0x04 "CTR,Cache Type Register"
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bitfld.long 0x04 29.--31. " FORMAT ,Indicates the implemented CTR format" ",,,,ARMv7,?..."
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bitfld.long 0x04 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,?..."
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bitfld.long 0x04 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,?..."
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textline " "
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bitfld.long 0x04 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x08 "CCSIDR,Cache Size ID Register"
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bitfld.long 0x08 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported"
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bitfld.long 0x08 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported"
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bitfld.long 0x08 29. " RA ,Indicates support available for read allocation" "Not supported,Supported"
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textline " "
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bitfld.long 0x08 28. " WA ,Indicates support available for write allocation" "Not supported,Supported"
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hexmask.long.word 0x08 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1"
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hexmask.long.word 0x08 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
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textline " "
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bitfld.long 0x08 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
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group.long 0xD84++0x03
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line.long 0x00 "CSSELR,Cache Size Selection Register"
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bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,?..."
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bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data,Instruction"
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wgroup.long 0xF50++0x03
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line.long 0x00 "ICIALLU,Instruction cache invalidate all to Point of Unification"
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wgroup.long 0xF58++0x1F
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line.long 0x00 "ICIMVAU,Instruction cache invalidate by address to PoU"
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line.long 0x04 "DCIMVAC,Data cache invalidate by address to Point of Coherency (PoC)"
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line.long 0x08 "DCISW,Data cache invalidate by set/way"
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line.long 0x0C "DCCMVAU,Data cache by address to PoU"
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line.long 0x10 "DCCMVAC,Data cache clean by address to PoC"
|
|
line.long 0x14 "DCCSW,Data cache clean by set/way"
|
|
line.long 0x18 "DCCIMVAC,Data cache clean and invalidate by address to PoC"
|
|
line.long 0x1C "DCCISW,Data cache clean and invalidate by set/way"
|
|
group.long 0xF90++0x13
|
|
line.long 0x00 "ITCMCR,Instruction Tightly-Coupled Memory Control Register"
|
|
bitfld.long 0x00 3.--6. " SZ ,TCM size" "Not implemented,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB"
|
|
bitfld.long 0x00 2. " RETEN ,Retry phase enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RMW ,Read-Modify-Write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,TCM enable" "Disabled,Enabled"
|
|
line.long 0x04 "DTCMCR,Data Tightly-Coupled Memory Control Register"
|
|
bitfld.long 0x04 3.--6. " SZ ,TCM size" "Not implemented,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB"
|
|
bitfld.long 0x04 2. " RETEN ,Retry phase enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RMW ,Read-Modify-Write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " EN ,TCM enable" "Disabled,Enabled"
|
|
line.long 0x08 "AHBPCR,AHBP control register"
|
|
bitfld.long 0x08 1.--3. " SZ ,AHBP size" "AHBP disabled,64 MB,128 MB,256 MB,512 MB,?..."
|
|
bitfld.long 0x08 0. " EN ,AHBP enable" "Disabled,Enabled"
|
|
line.long 0x0C "CACR,L1 Cache Control Register"
|
|
bitfld.long 0x0C 2. " FORCEWT ,Enables Force Write-through in the data cache" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " ECCDIS ,Disables ECC in the instruction and data cache" "No,Yes"
|
|
bitfld.long 0x0C 0. " SIWT ,Enables limited cache coherency usage" "Disabled,Enabled"
|
|
line.long 0x10 "AHBSCR,AHB Slave Control Register"
|
|
bitfld.long 0x10 11.--15. " INITCOUNT ,Fairness counter initialization value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x10 2.--10. 1. " TPRI ,Threshold execution priority for AHBS traffic demotion"
|
|
bitfld.long 0x10 0.--1. " CTL ,AHBS prioritization control" "AHBS,Software,AHBSCR.INITCOUNT,AHBSPRI"
|
|
group.long 0xFA8++0x03
|
|
line.long 0x00 "ABFSR,Auxiliary Bus Fault Status Register"
|
|
bitfld.long 0x00 8.--9. " AXIMTYPE ,Indicates the type of fault on the AXIM interface" "OKAY,EXOKAY,SLVERR,DECERR"
|
|
bitfld.long 0x00 4. " EPPB ,Asynchronous fault on EPPB interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " AXIM ,Asynchronous fault on AXIM interface" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AHBP ,Asynchronous fault on AHBP interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " DTCM ,Asynchronous fault on DTCM interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " ITCM ,Asynchronous fault on ITCM interface" "Not occurred,Occurred"
|
|
group.long 0xFB0++0x03
|
|
line.long 0x00 "IEBR0,Instruction Error bank Register 0"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
group.long 0xFB4++0x03
|
|
line.long 0x00 "IEBR1,Instruction Error bank Register 1"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
group.long 0xFB8++0x03
|
|
line.long 0x00 "DEBR0,Data Error bank Register 0"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
group.long 0xFBC++0x03
|
|
line.long 0x00 "DEBR1,Data Error bank Register 1"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
tree.end
|
|
tree "Feature Registers"
|
|
width 10.
|
|
rgroup.long 0xD40++0x0B
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
|
|
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
|
|
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
|
|
hgroup.long 0xD4C++0x03
|
|
hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
rgroup.long 0xD50++0x03
|
|
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
|
|
bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
|
|
bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
|
|
hgroup.long 0xD54++0x03
|
|
hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
|
|
rgroup.long 0xD58++0x03
|
|
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
|
|
bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
|
|
rgroup.long 0xD60++0x13
|
|
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
|
|
bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
|
|
bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
|
|
bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
|
|
bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
|
|
line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
|
|
bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
|
|
bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
|
|
bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
|
|
line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
|
|
bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
|
|
bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
|
|
bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
|
|
bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
|
|
bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
|
|
line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
|
|
bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
tree "CoreSight Identification Registers"
|
|
width 6.
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit (MPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM7F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
newline
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
newline
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
newline
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x0B
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
newline
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
line.long 0x08 "MVFR2,Media and FP Feature Register 2"
|
|
bitfld.long 0x08 4.--7. " VFP_MISC ,Indicates the hardware support for FP miscellaneous features" "Not supported,,,,Supported,?..."
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
newline
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
newline
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
newline
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
newline
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
endif
|
|
sif (CORENAME()=="CORTEXM0+")
|
|
tree.close "Core Registers (Cortex-M0+)"
|
|
AUTOINDENT.PUSH
|
|
AUTOINDENT.OFF
|
|
tree "System Control"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0x8
|
|
if (CORENAME()=="CORTEXM1")
|
|
group.long 0x10++0x0b
|
|
line.long 0x00 "STCSR,SysTick Control and Status Register"
|
|
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
|
|
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
|
|
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
|
|
line.long 0x04 "STRVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
|
|
line.long 0x08 "STCVR,SysTick Current Value Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
|
|
else
|
|
group.long 0x10++0x0b
|
|
line.long 0x00 "STCSR,SysTick Control and Status Register"
|
|
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
|
|
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
|
|
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
|
|
line.long 0x04 "STRVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
|
|
line.long 0x08 "STCVR,SysTick Current Value Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
|
|
endif
|
|
if (CORENAME()=="CORTEXM1")
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "STCR,SysTick Calibration Value Register"
|
|
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
|
|
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
|
|
else
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "STCR,SysTick Calibration Value Register"
|
|
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
|
|
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
|
|
endif
|
|
rgroup.long 0xd00++0x03
|
|
line.long 0x00 "CPUID,CPU ID Base Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
|
|
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
|
|
textline " "
|
|
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
|
|
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
|
|
group.long 0xd04++0x03
|
|
line.long 0x00 "ICSR,Interrupt Control State Register"
|
|
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
|
|
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
|
|
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
|
|
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
|
|
if (CORENAME()=="CORTEXM0+")
|
|
group.long 0xd08++0x03
|
|
line.long 0x00 "VTOR,Vector Table Offset Register"
|
|
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
|
|
else
|
|
textline " "
|
|
endif
|
|
group.long 0xd0c++0x03
|
|
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
|
|
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
|
|
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
|
|
group.long 0xd10++0x03
|
|
line.long 0x00 "SCR,System Control Register"
|
|
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
|
|
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
|
|
rgroup.long 0xd14++0x03
|
|
line.long 0x00 "CCR,Configuration and Control Register"
|
|
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
|
|
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
|
|
group.long 0xd1c++0x0b
|
|
line.long 0x00 "SHPR2,System Handler Priority Register 2"
|
|
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
|
|
line.long 0x04 "SHPR3,System Handler Priority Register 3"
|
|
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
|
|
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
|
|
line.long 0x08 "SHCSR,System Handler Control and State Register"
|
|
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
|
|
if (CORENAME()=="CORTEXM0+")
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "ACTLR,Auxiliary Control Register"
|
|
else
|
|
textline " "
|
|
endif
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit (MPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
tree.end
|
|
width 6.
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x00 "INT0,Interrupt Priority Register"
|
|
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
|
|
line.long 0x04 "INT1,Interrupt Priority Register"
|
|
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
|
|
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
|
|
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
|
|
line.long 0x08 "INT2,Interrupt Priority Register"
|
|
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
|
|
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
|
|
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
|
|
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
|
|
line.long 0x0C "INT3,Interrupt Priority Register"
|
|
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
|
|
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
|
|
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
|
|
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
|
|
line.long 0x10 "INT4,Interrupt Priority Register"
|
|
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
|
|
line.long 0x14 "INT5,Interrupt Priority Register"
|
|
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
endif
|
|
tree "BACKUP (SRSS Backup Domain)"
|
|
base ad:0x40270000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "EN_CHARGE_KEY,When set to 3C the supercap charger circuit is enabled. Any other code disables the supercap charger. THIS CHARGING CIRCUIT IS FOR A SUPERCAP ONLY AND CANNOT SAFELY CHARGE A BATTERY. DO NOT WRITE THIS KEY WHEN VBACKUP IS CONNECTED TO A.."
|
|
newline
|
|
bitfld.long 0x0 19. "VBACKUP_MEAS,Connect vbackup supply to the vbackup_meas output for measurement by an ADC attached to amuxbusa_adft_vddd. The vbackup_meas signal is scaled to 10 percent of vbackup so it is within the supply range of the ADC." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17.--18. "VDDBAK_CTL,Controls the behavior of the switch that generates vddbak from vbackup or vddd." "0: automatically select vddd if its brownout..,?,?,3: force vddbak and vmax to select vbackup"
|
|
newline
|
|
bitfld.long 0x0 16. "WCO_BYPASS,Configures the WCO for different board-level connections to the WCO pins. For example this can be used to connect an external watch crystal oscillator instead of a watch crystal. In all cases the two related GPIO pins (WCO input and.." "0: Watch crystal,1: Clock signal"
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newline
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bitfld.long 0x0 12.--13. "PRESCALER,N/A" "0,1,2,3"
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|
newline
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bitfld.long 0x0 8.--9. "CLK_SEL,Clock select for RTC clock" "0: Watch-crystal oscillator input available in..,1: This allows to use the LFCLK selection as an..,2: Internal Low frequency Oscillator available in..,3: Low-power external crystal oscillator prescaler.."
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newline
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bitfld.long 0x0 3. "WCO_EN,Watch-crystal oscillator (WCO) enable. If there is a write in progress when this bit is cleared the WCO will be internally kept on until the write completes." "0,1"
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|
group.long 0x8++0x7
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|
line.long 0x0 "RTC_RW,RTC Read Write register"
|
|
bitfld.long 0x0 1. "WRITE,Write bit" "0,1"
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|
newline
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bitfld.long 0x0 0. "READ,Read bit" "0,1"
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|
line.long 0x4 "CAL_CTL,Oscillator calibration for absolute frequency"
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|
bitfld.long 0x4 31. "CAL_OUT,Output enable for wave signal for calibration and allow CALIB_VAL to be written." "0,1"
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newline
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bitfld.long 0x4 28.--29. "CAL_SEL,Select calibration wave output signal" "0: 512Hz wave not affected by calibration setting..,1: N/A,2: 2Hz wave includes the effect of the calibration..,3: 1Hz wave includes the effect of the calibration.."
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newline
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bitfld.long 0x4 16.--17. "CAL_COMP_PER_MIN,Select how many time calibration is performed per minute per step of 64 each time a 64 step is added or substracted one unit 2/4/8/16*CALIB_VAL is substracted." "0: Calibration of 64 each is performed twice per..,1: Calibration of 64 each is performed four times..,2: Calibration of 64 each is performed eight times..,3: Ca6libration of 64 each is performed sixteen.."
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newline
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bitfld.long 0x4 6. "CALIB_SIGN,Calibration sign:" "0: Negative sign: remove pulses,1: Positive sign: add pulses"
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newline
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hexmask.long.byte 0x4 0.--5. 1. "CALIB_VAL,Calibration value for absolute frequency (at a fixed temperature). Each step causes 128 ticks to be added or removed each hour. Effectively that means that each step is 1.085ppm (= 128/(60*60*32 768)) when CAL_COMP_PER_MIN is set at default.."
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|
rgroup.long 0x10++0x3
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line.long 0x0 "STATUS,Status"
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bitfld.long 0x0 2. "WCO_OK,Indicates that output has transitioned." "0,1"
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newline
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bitfld.long 0x0 0. "RTC_BUSY,Pending RTC write" "0,1"
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|
group.long 0x14++0x23
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line.long 0x0 "RTC_TIME,Calendar Seconds. Minutes. Hours. Day of Week"
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bitfld.long 0x0 24.--26. "RTC_DAY,Calendar Day of the week 1-7" "?,1: Monday is recommended,?,?,?,?,?,?"
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newline
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bitfld.long 0x0 22. "CTRL_12HR,Select 12/24HR mode: 1=12HR 0=24HR" "0,1"
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newline
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hexmask.long.byte 0x0 16.--20. 1. "RTC_HOUR,Calendar hours value depending on 12/24HR mode"
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newline
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hexmask.long.byte 0x0 8.--13. 1. "RTC_MIN,Calendar minutes 0-59"
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newline
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hexmask.long.byte 0x0 0.--5. 1. "RTC_SEC,Calendar seconds 0-59"
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|
line.long 0x4 "RTC_DATE,Calendar Day of Month. Month. Year"
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|
hexmask.long.byte 0x4 16.--22. 1. "RTC_YEAR,Calendar year 0-99"
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newline
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hexmask.long.byte 0x4 8.--11. 1. "RTC_MON,Calendar Month 1-12"
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newline
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hexmask.long.byte 0x4 0.--4. 1. "RTC_DATE,Calendar Day of the Month 1-31"
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line.long 0x8 "ALM1_TIME,Alarm 1 Seconds. Minute. Hours. Day of Week"
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bitfld.long 0x8 31. "ALM_DAY_EN,Alarm Day of the Week enable: 0=ignore 1=match" "0: ignore,1: match"
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newline
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bitfld.long 0x8 24.--26. "ALM_DAY,Alarm Day of the week 1-7" "?,1: Monday is recommended,?,?,?,?,?,?"
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newline
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bitfld.long 0x8 23. "ALM_HOUR_EN,Alarm hour enable: 0=ignore 1=match" "0: ignore,1: match"
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newline
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hexmask.long.byte 0x8 16.--20. 1. "ALM_HOUR,Alarm hours value depending on 12/24HR mode"
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newline
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bitfld.long 0x8 15. "ALM_MIN_EN,Alarm minutes enable: 0=ignore 1=match" "0: ignore,1: match"
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newline
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hexmask.long.byte 0x8 8.--13. 1. "ALM_MIN,Alarm minutes 0-59"
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newline
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bitfld.long 0x8 7. "ALM_SEC_EN,Alarm second enable: 0=ignore 1=match" "0: ignore,1: match"
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newline
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hexmask.long.byte 0x8 0.--5. 1. "ALM_SEC,Alarm seconds 0-59"
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line.long 0xC "ALM1_DATE,Alarm 1 Day of Month. Month"
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bitfld.long 0xC 31. "ALM_EN,Master enable for alarm 1." "0: Alarm 1 is disabled,1: Alarm 1 is enabled"
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newline
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bitfld.long 0xC 15. "ALM_MON_EN,Alarm Month enable: 0=ignore 1=match" "0: ignore,1: match"
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newline
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hexmask.long.byte 0xC 8.--11. 1. "ALM_MON,Alarm Month 1-12"
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newline
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bitfld.long 0xC 7. "ALM_DATE_EN,Alarm Day of the Month enable: 0=ignore 1=match" "0: ignore,1: match"
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newline
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hexmask.long.byte 0xC 0.--4. 1. "ALM_DATE,Alarm Day of the Month 1-31"
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line.long 0x10 "ALM2_TIME,Alarm 2 Seconds. Minute. Hours. Day of Week"
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bitfld.long 0x10 31. "ALM_DAY_EN,Alarm Day of the Week enable: 0=ignore 1=match" "0: ignore,1: match"
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newline
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bitfld.long 0x10 24.--26. "ALM_DAY,Alarm Day of the week 1-7" "?,1: Monday is recommended,?,?,?,?,?,?"
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newline
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bitfld.long 0x10 23. "ALM_HOUR_EN,Alarm hour enable: 0=ignore 1=match" "0: ignore,1: match"
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newline
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hexmask.long.byte 0x10 16.--20. 1. "ALM_HOUR,Alarm hours value depending on 12/24HR mode"
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newline
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bitfld.long 0x10 15. "ALM_MIN_EN,Alarm minutes enable: 0=ignore 1=match" "0: ignore,1: match"
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newline
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hexmask.long.byte 0x10 8.--13. 1. "ALM_MIN,Alarm minutes 0-59"
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newline
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bitfld.long 0x10 7. "ALM_SEC_EN,Alarm second enable: 0=ignore 1=match" "0: ignore,1: match"
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newline
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hexmask.long.byte 0x10 0.--5. 1. "ALM_SEC,Alarm seconds 0-59"
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line.long 0x14 "ALM2_DATE,Alarm 2 Day of Month. Month"
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bitfld.long 0x14 31. "ALM_EN,Master enable for alarm 2." "0: Alarm 2 is disabled,1: Alarm 2 is enabled"
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newline
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bitfld.long 0x14 15. "ALM_MON_EN,Alarm Month enable: 0=ignore 1=match" "0: ignore,1: match"
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newline
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hexmask.long.byte 0x14 8.--11. 1. "ALM_MON,Alarm Month 1-12"
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newline
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bitfld.long 0x14 7. "ALM_DATE_EN,Alarm Day of the Month enable: 0=ignore 1=match" "0: ignore,1: match"
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newline
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hexmask.long.byte 0x14 0.--4. 1. "ALM_DATE,Alarm Day of the Month 1-31"
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|
line.long 0x18 "INTR,Interrupt request register"
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bitfld.long 0x18 2. "CENTURY,Century overflow interrupt" "0,1"
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newline
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bitfld.long 0x18 1. "ALARM2,Alarm 2 Interrupt" "0,1"
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newline
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bitfld.long 0x18 0. "ALARM1,Alarm 1 Interrupt" "0,1"
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line.long 0x1C "INTR_SET,Interrupt set request register"
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bitfld.long 0x1C 2. "CENTURY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x1C 1. "ALARM2,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x1C 0. "ALARM1,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x20 "INTR_MASK,Interrupt mask register"
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|
bitfld.long 0x20 2. "CENTURY,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x20 1. "ALARM2,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x20 0. "ALARM1,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0x38++0x3
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line.long 0x0 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x0 2. "CENTURY,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "ALARM2,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "ALARM1,Logical and of corresponding request and mask bits." "0,1"
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group.long 0x44++0x7
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line.long 0x0 "PMIC_CTL,PMIC control register"
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bitfld.long 0x0 31. "PMIC_EN,Enable for external PMIC that supplies vddd (if present). This bit will only clear if UNLOCK was written correctly in a previous write operation and PMIC_ALWAYSEN=0. When PMIC_EN=0 the system functions normally until vddd is no longer present.." "0,1"
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newline
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bitfld.long 0x0 30. "PMIC_ALWAYSEN,Override normal PMIC controls to prevent accidentally turning off the PMIC by errant firmware." "0: Normal operation,1: PMIC_EN and PMIC_OUTEN are ignored and the.."
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newline
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bitfld.long 0x0 29. "PMIC_EN_OUTEN,Output enable for the output driver in the PMIC_EN pad." "0: Output pad is tristate for PMIC_EN pin,1: Output pad is enabled for PMIC_EN pin"
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newline
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bitfld.long 0x0 16. "POLARITY,N/A" "0,1"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "UNLOCK,This byte must be set to 0x3A for PMIC to be disabled. When the UNLOCK code is not present: writes to PMIC_EN field are ignored and the hardware ignores the value in PMIC_EN. Do not change PMIC_EN in the same write cycle as setting/clearing the.."
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|
line.long 0x4 "RESET,Backup reset register"
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bitfld.long 0x4 31. "RESET,Writing 1 to this register resets the backup logic. Hardware clears it when the reset is complete. After setting this register firmware should confirm it reads as 0 before attempting to write other backup registers." "0,1"
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|
group.long 0x80++0x7
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line.long 0x0 "LPECO_CTL,Low-power external crystal oscillator control"
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|
bitfld.long 0x0 31. "LPECO_EN,Master enable for LPECO oscillator. This also disables the LPECO prescaler." "0,1"
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newline
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bitfld.long 0x0 30. "LPECO_AMPDET_EN,Minimum amplitude detector enable/disable. Ignored when LPECO_EN==0." "0: Initially enabled,1: Keep minimum amplitude detector enabled as long.."
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newline
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bitfld.long 0x0 28. "LPECO_DIV_ENABLE,LPECO prescaler enable. Do not set this to '1' when LPECO_EN==0. SW sets this field to '1' to enable the divider and HW sets this field to '0' to indicate that divider enabling has completed. When the divider is enabled its integer.." "0,1"
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newline
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bitfld.long 0x0 12. "LPECO_AMP_SEL,Selects the oscillation amplitude. WARNING: the crystal can be permanently damaged by selecting an amplitude that exceeds the crystal limits." "0: maximum amplitude is 1,1: maximum amplitude is 1"
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newline
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bitfld.long 0x0 8. "LPECO_FRANGE,Specifies the crystal frequency range." "0: Crystal frequency is in range [4,1: Crystal frequency is in range [6"
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newline
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bitfld.long 0x0 4.--5. "LPECO_CRANGE,Specifies the load capacitance of the chosen crystal." "0: load is in range [5pF,1: load is in range,2: load is in range,3: load is in range"
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line.long 0x4 "LPECO_PRESCALE,Low-power external crystal oscillator prescaler"
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hexmask.long.word 0x4 16.--25. 1. "LPECO_INT_DIV,Integer divide value allows for LPECO frequencies up to 8MHz to generate 32768 Hz. Subtract one from the desired divide value when writing this field. For example to divide by 1 write LPECO_INT_DIV=0. Do not change this setting when.."
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newline
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hexmask.long.byte 0x4 8.--15. 1. "LPECO_FRAC_DIV,Fractional value sufficient to get prescaler output within the +/-65ppm calibration range. Do not change this setting when LPECO Prescaler is enabled."
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newline
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rbitfld.long 0x4 0. "LPECO_DIV_ENABLED,LPECO prescaler enabled. HW sets this field to '1' as a result of an BACKUP_LPECO_CTL.LPECO_DIV_ENABLE. HW sets this field to '0' as a result of writing CLK_LPECO_CONFIG.LPECO_EN==0. This field does not update unless LPECO clock is.." "0,1"
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rgroup.long 0x88++0x3
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line.long 0x0 "LPECO_STATUS,Low-power external crystal oscillator status"
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bitfld.long 0x0 1. "LPECO_READY,Indicates the LPECO has had enough time to start. This field is driven by a stabilization counter clocked by IMO." "0,1"
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newline
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bitfld.long 0x0 0. "LPECO_AMPDET_OK,Indicates sufficient oscillation amplitude reported by LPECO amplitude detector. This field will read as zero when the amplitude detector is off (see LPECO_CTL.LPECO_AMPDET_EN)." "0,1"
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tree "CSV_BAK (CSV registers for clk_bak clock)"
|
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base ad:0x40270100
|
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tree "CSV (clk_bak Backup domain Clock Supervisor registers)"
|
|
group.long 0x0++0xB
|
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line.long 0x0 "REF_CTL,Clock Supervision Reference Control"
|
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bitfld.long 0x0 31. "CSV_EN,Enables clock supervision both frequency and loss." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "STARTUP,Startup delay time -1 (in reference clock cycles) after enable from reference clock start to monitored clock start."
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line.long 0x4 "REF_LIMIT,Clock Supervision Reference Limits"
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hexmask.long.byte 0x4 16.--23. 1. "UPPER,Cycle time upper limit. Set the upper limit -1 in reference clock cycles before (or same time) the next monitored clock event must happen. If a monitored clock event does not happen before this limit is reached or does not happen at all (clock.."
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hexmask.long.byte 0x4 0.--7. 1. "LOWER,Cycle time lower limit. Set the lower limit -1 in reference clock cycles before the next monitored clock event is allowed to happen. If a monitored clock event happens before this limit is reached a CSV error is detected."
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line.long 0x8 "MON_CTL,Clock Supervision Monitor Control"
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hexmask.long.byte 0x8 0.--7. 1. "PERIOD,Period time. Set the Period -1 in monitored clock cycles before the next monitored clock event happens."
|
|
tree.end
|
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tree.end
|
|
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1000)++0x3
|
|
line.long 0x0 "BREG[$1],Backup register region"
|
|
hexmask.long 0x0 0.--31. 1. "BREG,Backup memory that contains application-specific data. Memory is retained on vbackup supply."
|
|
repeat.end
|
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tree.end
|
|
tree "CANFD (CAN Controller)"
|
|
base ad:0x0
|
|
tree "CANFD0"
|
|
base ad:0x40520000
|
|
repeat 5. (list 0x0 0x1 0x2 0x3 0x4)(list ad:0x40520000 ad:0x40520200 ad:0x40520400 ad:0x40520600 ad:0x40520800)
|
|
tree "CH[$1]"
|
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base $2
|
|
tree "M_TTCAN (TTCAN 3PIP includes FD)"
|
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rgroup.long ($2)++0x7
|
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line.long 0x0 "CREL,Core Release Register"
|
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hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release"
|
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hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release"
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newline
|
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hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year"
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|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day"
|
|
line.long 0x4 "ENDN,Endian Register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value"
|
|
group.long ($2+0xC)++0x23
|
|
line.long 0x0 "DBTP,Data Bit Timing & Prescaler Register"
|
|
bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation" "0: Transmitter Delay Compensation disabled,1: Transmitter Delay Compensation enabled"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Bit Rate Prescaler"
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|
newline
|
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hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re)Synchronization Jump Width"
|
|
line.long 0x4 "TEST,Test Register"
|
|
rbitfld.long 0x4 7. "RX,Receive Pin" "0: The CAN bus is dominant,1: The CAN bus is recessive"
|
|
bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0,1,2,3"
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|
newline
|
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bitfld.long 0x4 4. "LBCK,Loop Back Mode" "0: Reset value,1: Loop Back Mode is enabled"
|
|
bitfld.long 0x4 3. "CAT,ASC is not supported by M_TTCAN" "0: Output pin m_ttcan_asct = '0',?"
|
|
newline
|
|
bitfld.long 0x4 2. "CAM,ASC is not supported by M_TTCAN" "0: Output pin m_ttcan_ascm = '0',1: Output pin m_ttcan_ascm = '1'"
|
|
bitfld.long 0x4 1. "TAT,ASC is not supported by M_TTCAN" "0: Level at pin m_ttcan_asct controlled by FSE,1: Level at pin m_ttcan_asct = '1'"
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|
newline
|
|
bitfld.long 0x4 0. "TAM,ASC is not supported by M_TTCAN" "0: Level at pin m_ttcan_ascm controlled by FSE,1: Level at pin m_ttcan_ascm = '1'"
|
|
line.long 0x8 "RWD,RAM Watchdog"
|
|
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration"
|
|
line.long 0xC "CCCR,CC Control Register"
|
|
bitfld.long 0xC 15. "NISO,Non ISO Operation" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.."
|
|
bitfld.long 0xC 14. "TXP,Transmit Pause" "0: Transmit pause disabled,1: Transmit pause enabled"
|
|
newline
|
|
bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
|
|
bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
|
|
newline
|
|
bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
|
|
bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled"
|
|
newline
|
|
bitfld.long 0xC 7. "TEST,Test Mode Enable" "0: Normal operation,1: Test Mode"
|
|
bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
|
|
newline
|
|
bitfld.long 0xC 5. "MON_,Bus Monitoring Mode" "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled"
|
|
bitfld.long 0xC 4. "CSR,Clock Stop Request not supported by M_TTCAN use CTL.STOP_REQ at the group level instead." "0: No clock stop is requested,1: Clock stop requested"
|
|
newline
|
|
bitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: M_TTCAN may be set in power down by stopping.."
|
|
bitfld.long 0xC 2. "ASM,Restricted Operation Mode" "0: Normal CAN operation,1: Restricted Operation Mode active"
|
|
newline
|
|
bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
|
|
bitfld.long 0xC 0. "INIT,Initialization" "0: Normal Operation,1: Initialization is started"
|
|
line.long 0x10 "NBTP,Nominal Bit Timing & Prescaler Register"
|
|
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width"
|
|
hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point"
|
|
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point"
|
|
line.long 0x14 "TSCC,Timestamp Counter Configuration"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler (still used for TOCC)"
|
|
bitfld.long 0x14 0.--1. "TSS,Timestamp Select should always be set to external timestamp counter" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,?,?"
|
|
line.long 0x18 "TSCV,Timestamp Counter Value"
|
|
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter not used for M_TTCAN"
|
|
line.long 0x1C "TOCC,Timeout Counter Configuration"
|
|
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period"
|
|
bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,?,?"
|
|
newline
|
|
bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled,1: Timeout Counter enabled"
|
|
line.long 0x20 "TOCV,Timeout Counter Value"
|
|
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter"
|
|
rgroup.long ($2+0x40)++0x7
|
|
line.long 0x0 "ECR,Error Counter Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging"
|
|
bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter"
|
|
line.long 0x4 "PSR,Protocol Status Register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
|
|
bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
|
|
newline
|
|
bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0: Since this bit was reset by the CPU,1: Message in CAN FD format with FDF flag set has.."
|
|
bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set"
|
|
newline
|
|
bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set"
|
|
bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7"
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|
newline
|
|
bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The M_CAN is not Bus_Off,1: The M_CAN is in Bus_Off state"
|
|
bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
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|
newline
|
|
bitfld.long 0x4 5. "EP,Error Passive" "0: The M_CAN is in the Error_Active state,1: The M_CAN is in the Error_Passive state"
|
|
bitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing,1: Idle,?,?"
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|
newline
|
|
bitfld.long 0x4 0.--2. "LEC,Last Error Code " "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: AckError: The message transmitted by the M_TTCAN..,4: Bit1Error: During the transmission of a message,5: Bit0Error: During the transmission of a message,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol Status.."
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|
group.long ($2+0x48)++0x3
|
|
line.long 0x0 "TDCR,Transmitter Delay Compensation Register"
|
|
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
|
|
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length"
|
|
group.long ($2+0x50)++0xF
|
|
line.long 0x0 "IR,Interrupt Register"
|
|
bitfld.long 0x0 29. "ARA,N/A" "0,1"
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|
bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit Time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected"
|
|
newline
|
|
bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase (Nominal Bit Time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected"
|
|
bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY"
|
|
newline
|
|
bitfld.long 0x0 25. "BO_,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
|
|
bitfld.long 0x0 24. "EW_,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
|
|
newline
|
|
bitfld.long 0x0 23. "EP_,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
|
|
bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow,1: Overflow of CAN Error Logging Counter occurred"
|
|
newline
|
|
bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Bit error detected"
|
|
bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0,1"
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|
newline
|
|
bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0: No Rx Buffer updated,1: At least one received message stored into a Rx.."
|
|
bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached"
|
|
newline
|
|
bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
|
|
bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
|
|
newline
|
|
bitfld.long 0x0 15. "TEFL_,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost"
|
|
bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full"
|
|
newline
|
|
bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark,1: Tx Event FIFO fill level reached watermark"
|
|
bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element"
|
|
newline
|
|
bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
|
|
bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
|
|
newline
|
|
bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed"
|
|
bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received"
|
|
newline
|
|
bitfld.long 0x0 7. "RF1L_,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
|
|
bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark"
|
|
bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
|
|
newline
|
|
bitfld.long 0x0 3. "RF0L_,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
|
|
bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
newline
|
|
bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark"
|
|
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
|
|
line.long 0x4 "IE,Interrupt Enable"
|
|
bitfld.long 0x4 29. "ARAE,N/A" "0,1"
|
|
bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable (not used in M_TTCAN)" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 12. "TEFNE,Tx Event FIDO New Entry Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt Disabled,1: Interrupt EnabledTx FIFO Empty Interrupt Enable"
|
|
bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
line.long 0x8 "ILS,Interrupt Line Select"
|
|
bitfld.long 0x8 29. "ARAL,N/A" "0,1"
|
|
bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 24. "EWL,Warning Status Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 23. "EPL,Error Passive Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Select (not used in M_TTCAN)" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
line.long 0xC "ILE,Interrupt Line Enable"
|
|
bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line m_ttcan_int1 disabled,1: Interrupt line m_ttcan_int1 enabled"
|
|
bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line m_ttcan_int0 disabled,1: Interrupt line m_ttcan_int0 enabled"
|
|
group.long ($2+0x80)++0xB
|
|
line.long 0x0 "GFC,Global Filter Configuration"
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
|
|
newline
|
|
bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
|
|
bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs"
|
|
line.long 0x4 "SIDFC,Standard ID Filter Configuration"
|
|
hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard"
|
|
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address"
|
|
line.long 0x8 "XIDFC,Extended ID Filter Configuration"
|
|
hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended"
|
|
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address"
|
|
group.long ($2+0x90)++0x3
|
|
line.long 0x0 "XIDAM,Extended ID AND Mask"
|
|
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask"
|
|
rgroup.long ($2+0x94)++0x3
|
|
line.long 0x0 "HPMS,High Priority Message Status"
|
|
bitfld.long 0x0 15. "FLST,Filter List" "0: Standard Filter List,1: Extended Filter List"
|
|
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO message lost,?,?"
|
|
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index"
|
|
group.long ($2+0x98)++0xB
|
|
line.long 0x0 "NDAT1,New Data 1"
|
|
hexmask.long 0x0 0.--31. 1. "ND,New Data"
|
|
line.long 0x4 "NDAT2,New Data 2"
|
|
hexmask.long 0x4 0.--31. 1. "ND,New Data"
|
|
line.long 0x8 "RXF0C,Rx FIFO 0 Configuration"
|
|
bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address"
|
|
rgroup.long ($2+0xA4)++0x3
|
|
line.long 0x0 "RXF0S,Rx FIFO 0 Status"
|
|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
|
|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index"
|
|
hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level"
|
|
group.long ($2+0xA8)++0xB
|
|
line.long 0x0 "RXF0A,Rx FIFO 0 Acknowledge"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index"
|
|
line.long 0x4 "RXBC,Rx Buffer Configuration"
|
|
hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address"
|
|
line.long 0x8 "RXF1C,Rx FIFO 1 Configuration"
|
|
bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address"
|
|
rgroup.long ($2+0xB4)++0x3
|
|
line.long 0x0 "RXF1S,Rx FIFO 1 Status"
|
|
bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state,1: Debug message A received,?,?"
|
|
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
|
|
newline
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index"
|
|
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level"
|
|
group.long ($2+0xB8)++0xB
|
|
line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index"
|
|
line.long 0x4 "RXESC,Rx Buffer / FIFO Element Size Configuration"
|
|
bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "TXBC,Tx Buffer Configuration"
|
|
bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation"
|
|
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
|
|
hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address"
|
|
rgroup.long ($2+0xC4)++0x3
|
|
line.long 0x0 "TXFQS,Tx FIFO/Queue Status"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index"
|
|
hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level"
|
|
group.long ($2+0xC8)++0x3
|
|
line.long 0x0 "TXESC,Tx Buffer Element Size Configuration"
|
|
bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
|
|
rgroup.long ($2+0xCC)++0x3
|
|
line.long 0x0 "TXBRP,Tx Buffer Request Pending"
|
|
hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request Pending"
|
|
group.long ($2+0xD0)++0x7
|
|
line.long 0x0 "TXBAR,Tx Buffer Add Request"
|
|
hexmask.long 0x0 0.--31. 1. "AR,Add Request"
|
|
line.long 0x4 "TXBCR,Tx Buffer Cancellation Request"
|
|
hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request"
|
|
rgroup.long ($2+0xD8)++0x7
|
|
line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred"
|
|
hexmask.long 0x0 0.--31. 1. "TO,Transmission Occurred"
|
|
line.long 0x4 "TXBCF,Tx Buffer Cancellation Finished"
|
|
hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished"
|
|
group.long ($2+0xE0)++0x7
|
|
line.long 0x0 "TXBTIE,Tx Buffer Transmission Interrupt Enable"
|
|
hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt Enable"
|
|
line.long 0x4 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
|
|
hexmask.long 0x4 0.--31. 1. "CFIE,Cancellation Finished Interrupt Enable"
|
|
group.long ($2+0xF0)++0x3
|
|
line.long 0x0 "TXEFC,Tx Event FIFO Configuration"
|
|
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark"
|
|
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address"
|
|
rgroup.long ($2+0xF4)++0x3
|
|
line.long 0x0 "TXEFS,Tx Event FIFO Status"
|
|
bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index"
|
|
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level"
|
|
group.long ($2+0xF8)++0x3
|
|
line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge"
|
|
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index"
|
|
group.long ($2+0x100)++0x2B
|
|
line.long 0x0 "TTTMC,TT Trigger Memory Configuration"
|
|
hexmask.long.byte 0x0 16.--22. 1. "TME,Trigger Memory Elements"
|
|
hexmask.long.word 0x0 2.--15. 1. "TMSA,Trigger Memory Start Address"
|
|
line.long 0x4 "TTRMC,TT Reference Message Configuration"
|
|
bitfld.long 0x4 31. "RMPS,Reference Message Payload Select" "0: Reference message has no additional payload,1: bytes 2-8"
|
|
bitfld.long 0x4 30. "XTD,Extended Identifier" "0,1"
|
|
newline
|
|
hexmask.long 0x4 0.--28. 1. "RID,Reference Identifier"
|
|
line.long 0x8 "TTOCF,TT Operation Configuration"
|
|
bitfld.long 0x8 26. "EVTP,Event Trigger Polarity" "0: Rising edge trigger,1: Falling edge trigger"
|
|
bitfld.long 0x8 25. "ECC,Enable Clock Calibration" "0: Automatic clock calibration in TTCAN Level 0,1: Automatic clock calibration in TTCAN Level 0"
|
|
newline
|
|
bitfld.long 0x8 24. "EGTF,Enable Global Time Filtering" "0: Global time filtering in TTCAN Level 0,1: Global time filtering in TTCAN Level 0"
|
|
hexmask.long.byte 0x8 16.--23. 1. "AWL,Application Watchdog Limit"
|
|
newline
|
|
bitfld.long 0x8 15. "EECS,Enable External Clock Synchronization" "0: External clock synchronization in TTCAN Level 0,1: External clock synchronization in TTCAN Level 0"
|
|
hexmask.long.byte 0x8 8.--14. 1. "IRTO,Initial Reference Trigger Offset"
|
|
newline
|
|
bitfld.long 0x8 5.--7. "LDSDL,LD of Synchronization Deviation Limit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 4. "TM,Time Master" "0: Time Master function disabled,1: Potential Time Master"
|
|
newline
|
|
bitfld.long 0x8 3. "GEN,Gap Enable" "0: Strictly time-triggered operation,1: External event-synchronized time-triggered.."
|
|
bitfld.long 0x8 0.--1. "OM,Operation Mode" "0: Event-driven CAN communication,1: TTCAN level 1,?,?"
|
|
line.long 0xC "TTMLM,TT Matrix Limits"
|
|
hexmask.long.word 0xC 16.--27. 1. "ENTT,Expected Number of Tx Triggers"
|
|
hexmask.long.byte 0xC 8.--11. 1. "TXEW,Tx Enable Window"
|
|
newline
|
|
bitfld.long 0xC 6.--7. "CSS,N/A" "0,1,2,3"
|
|
hexmask.long.byte 0xC 0.--5. 1. "CCM,N/A"
|
|
line.long 0x10 "TURCF,TUR Configuration"
|
|
bitfld.long 0x10 31. "ELT,Enable Local Time" "0: Local time is stopped,1: Local time is enabled"
|
|
hexmask.long.word 0x10 16.--29. 1. "DC,Denominator Configuration"
|
|
newline
|
|
hexmask.long.word 0x10 0.--15. 1. "NCL,Numerator Configuration Low"
|
|
line.long 0x14 "TTOCN,TT Operation Control"
|
|
rbitfld.long 0x14 15. "LCKC,TT Operation Control Register Locked" "0: Write access to TTOCN enabled,1: Write access to TTOCN locked"
|
|
bitfld.long 0x14 13. "ESCN,External Synchronization Control" "0: External synchronization disabled,1: External synchronization enabled"
|
|
newline
|
|
bitfld.long 0x14 12. "NIG,Next is Gap" "0: No action,1: Transmit next reference message with Next_is_Gap.."
|
|
bitfld.long 0x14 11. "TMG,Time Mark Gap" "0: Reset by each reference message,1: Next reference message started when Register.."
|
|
newline
|
|
bitfld.long 0x14 10. "FGP,Finish Gap" "0: No reference message requested,1: Application requested start of reference message"
|
|
bitfld.long 0x14 9. "GCS,Gap Control Select" "0: Gap control independent from m_ttcan_evt,1: Gap control by input pin m_ttcan_evt"
|
|
newline
|
|
bitfld.long 0x14 8. "TTIE,Trigger Time Mark Interrupt Pulse Enable" "0: Trigger Time Mark Interrupt output m_ttcan_tmp..,1: Trigger Time Mark Interrupt output m_ttcan_tmp.."
|
|
bitfld.long 0x14 6.--7. "TMC,Register Time Mark Compare" "0: No Register Time Mark Interrupt generated,1: Register Time Mark Interrupt if Time Mark =..,?,?"
|
|
newline
|
|
bitfld.long 0x14 5. "RTIE,Register Time Mark Interrupt Pulse Enable" "0: Register Time Mark Interrupt output m_ttcan_rtp..,1: Register Time Mark Interrupt output m_ttcan_rtp.."
|
|
bitfld.long 0x14 3.--4. "SWS,Stop Watch Source" "0: Stop Watch disabled,1: Actual value of cycle time is copied to TTCPT,?,?"
|
|
newline
|
|
bitfld.long 0x14 2. "SWP,Stop Watch Polarity" "0: Rising edge trigger,1: Falling edge trigger"
|
|
bitfld.long 0x14 1. "ECS,External Clock Synchronization" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "SGT,Set Global time" "0,1"
|
|
line.long 0x18 "TTGTP,TT Global Time Preset"
|
|
hexmask.long.word 0x18 16.--31. 1. "CTP,Cycle Time Target Phase"
|
|
hexmask.long.word 0x18 0.--15. 1. "TP,N/A"
|
|
line.long 0x1C "TTTMK,TT Time Mark"
|
|
rbitfld.long 0x1C 31. "LCKM,TT Time Mark Register Locked" "0: Write access to TTTMK enabled,1: Write access to TTTMK locked"
|
|
hexmask.long.byte 0x1C 16.--22. 1. "TICC,Time Mark Cycle Code"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--15. 1. "TM_,Time Mark"
|
|
line.long 0x20 "TTIR,TT Interrupt Register"
|
|
bitfld.long 0x20 18. "CER,Configuration Error" "0: No error found in trigger list,1: Error found in trigger list"
|
|
bitfld.long 0x20 17. "AW,Application Watchdog" "0: Application watchdog served in time,1: Application watchdog not served in time"
|
|
newline
|
|
bitfld.long 0x20 16. "WT,Watch Trigger" "0: cycle time 0xFF00),1: Missing reference message"
|
|
bitfld.long 0x20 15. "IWT,Initialization Watch Trigger" "0: No missing reference message during system startup,1: No system startup due to missing reference message"
|
|
newline
|
|
bitfld.long 0x20 14. "ELC,Error Level Changed" "0: No change in error level,1: Error level changed"
|
|
bitfld.long 0x20 13. "SE2,Scheduling Error 2" "0: No scheduling error 2,1: Scheduling error 2 occurred"
|
|
newline
|
|
bitfld.long 0x20 12. "SE1,Scheduling Error 1" "0: No scheduling error 1,1: Scheduling error 1 occurred"
|
|
bitfld.long 0x20 11. "TXO,Tx Count Overflow" "0: Number of Tx Trigger as expected,1: More Tx trigger than expected in one matrix cycle"
|
|
newline
|
|
bitfld.long 0x20 10. "TXU,Tx Count Underflow" "0: Number of Tx Trigger as expected,1: Less Tx trigger than expected in one matrix cycle"
|
|
bitfld.long 0x20 9. "GTE,Global Time Error" "0: Synchronization deviation within limit,1: Synchronization deviation exceeded limit"
|
|
newline
|
|
bitfld.long 0x20 8. "GTD,Global Time Discontinuity" "0: No discontinuity of global time,1: Discontinuity of global time"
|
|
bitfld.long 0x20 7. "GTW,Global Time Wrap" "0: No global time wrap occurred,1: Global time wrap from 0xFFFF to 0x0000 occurred"
|
|
newline
|
|
bitfld.long 0x20 6. "SWE,Stop Watch Event" "0: No rising/falling edge at stop watch trigger pin..,1: Rising/falling edge at stop watch trigger pin.."
|
|
bitfld.long 0x20 5. "TTMI,Trigger Time Mark Event Internal" "0: cycle time TTOCF,1: Time mark reached"
|
|
newline
|
|
bitfld.long 0x20 4. "RTMI,Register Time Mark Interrupt" "0: Time mark not reached,1: Time mark reached"
|
|
bitfld.long 0x20 3. "SOG,Start of Gap" "0: No reference message seen with Next_is_Gap bit set,1: Reference message with Next_is_Gap bit set.."
|
|
newline
|
|
bitfld.long 0x20 2. "CSM_,Change of Synchronization Mode" "0: No change in master to slave relation or..,1: Master to slave relation or schedule.."
|
|
bitfld.long 0x20 1. "SMC,Start of Matrix Cycle" "0: No Matrix Cycle started since bit has been reset,1: Matrix Cycle started"
|
|
newline
|
|
bitfld.long 0x20 0. "SBC,Start of Basic Cycle" "0: No Basic Cycle started since bit has been reset,1: Basic Cycle started"
|
|
line.long 0x24 "TTIE,TT Interrupt Enable"
|
|
bitfld.long 0x24 18. "CERE,Configuration Error Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 17. "AWE_,Application Watchdog Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 16. "WTE,Watch Trigger Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 15. "IWTE,Initialization Watch Trigger Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 14. "ELCE,Change Error Level Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 13. "SE2E,Scheduling Error 2 Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 12. "SE1E,Scheduling Error 1 Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 11. "TXOE,Tx Count Overflow Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 10. "TXUE,Tx Count Underflow Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 9. "GTEE,Global Time Error Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 8. "GTDE,Global Time Discontinuity Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 7. "GTWE,Global Time Wrap Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 6. "SWEE,Stop Watch Event Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 5. "TTMIE,Trigger Time Mark Event Internal Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 4. "RTMIE,Register Time Mark Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 3. "SOGE,Start of Gap Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 2. "CSME,Change of Synchronization Mode Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 1. "SMCE,Start of Matrix Cycle Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 0. "SBCE,Start of Basic Cycle Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
line.long 0x28 "TTILS,TT Interrupt Line Select"
|
|
bitfld.long 0x28 18. "CERL,Configuration Error Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 17. "AWL_,Application Watchdog Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 16. "WTL,Watch Trigger Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 15. "IWTL,Initialization Watch Trigger Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 14. "ELCL,Change Error Level Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 13. "SE2L,Scheduling Error 2 Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 12. "SE1L,Scheduling Error 1 Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 11. "TXOL,Tx Count Overflow Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 10. "TXUL,Tx Count Underflow Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 9. "GTEL,Global Time Error Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 8. "GTDL,Global Time Discontinuity Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 7. "GTWL,Global Time Wrap Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 6. "SWEL,Stop Watch Event Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 5. "TTMIL,Trigger Time Mark Event Internal Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 4. "RTMIL,Register Time Mark Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 3. "SOGL,Start of Gap Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 2. "CSML,Change of Synchronization Mode Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 1. "SMCL,Start of Matrix Cycle Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 0. "SBCL,Start of Basic Cycle Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
rgroup.long ($2+0x12C)++0x17
|
|
line.long 0x0 "TTOST,TT Operation Status"
|
|
bitfld.long 0x0 31. "SPL,Schedule Phase Lock" "0: Phase outside range,1: Phase inside range"
|
|
bitfld.long 0x0 30. "WECS,Wait for External Clock Synchronization" "0: No external clock synchronization pending,1: Node waits for external clock synchronization to.."
|
|
newline
|
|
bitfld.long 0x0 29. "AWE,Application Watchdog Event" "0: Application Watchdog served in time,1: Failed to serve Application Watchdog in time"
|
|
bitfld.long 0x0 28. "WFE,Wait for Event" "0: No Gap announced,1: Reference message with Next_is_Gap = '1' received"
|
|
newline
|
|
bitfld.long 0x0 27. "GSI,Gap Started Indicator" "0: No Gap in schedule,1: Gap time after Basic Cycle has started"
|
|
bitfld.long 0x0 24.--26. "TMP,Time Master Priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 23. "GFI,Gap Finished Indicator" "0: Reset at the end of each reference message,1: Gap finished by M_TTCAN"
|
|
bitfld.long 0x0 22. "WGTD,Wait for Global Time Discontinuity" "0: No global time preset pending,1: Node waits for the global time preset to take.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RTO,Reference Trigger Offset"
|
|
bitfld.long 0x0 7. "QCS,Quality of Clock Speed" "0: Local clock speed not synchronized to Time..,1: Synchronization Deviation <= SDL"
|
|
newline
|
|
bitfld.long 0x0 6. "QGTP,Quality of Global Time Phase" "0: Global time not valid,1: Global time in phase with Time Master"
|
|
bitfld.long 0x0 4.--5. "SYS,Synchronization State" "0: Out of Synchronization,1: Synchronizing to TTCAN communication,?,?"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MS,Master State" "0: Master_Off,1: Operating as Time Slave,?,?"
|
|
bitfld.long 0x0 0.--1. "EL,Error Level" "0: Severity 0,1: Severity 1,?,?"
|
|
line.long 0x4 "TURNA,TUR Numerator Actual"
|
|
hexmask.long.tbyte 0x4 0.--17. 1. "NAV,N/A"
|
|
line.long 0x8 "TTLGT,TT Local & Global Time"
|
|
hexmask.long.word 0x8 16.--31. 1. "GT,Global Time"
|
|
hexmask.long.word 0x8 0.--15. 1. "LT,Local Time"
|
|
line.long 0xC "TTCTC,TT Cycle Time & Count"
|
|
hexmask.long.byte 0xC 16.--21. 1. "CC,Cycle Count"
|
|
hexmask.long.word 0xC 0.--15. 1. "CT,Cycle Time"
|
|
line.long 0x10 "TTCPT,TT Capture Time"
|
|
hexmask.long.word 0x10 16.--31. 1. "SWV,Stop Watch Value"
|
|
hexmask.long.byte 0x10 0.--5. 1. "CCV,Cycle Count Value"
|
|
line.long 0x14 "TTCSM,TT Cycle Sync Mark"
|
|
hexmask.long.word 0x14 0.--15. 1. "CSM,Cycle Sync Mark"
|
|
tree.end
|
|
group.long ($2+0x180)++0x3
|
|
newline
|
|
line.long 0x0 "RXFTOP_CTL,Receive FIFO Top control"
|
|
bitfld.long 0x0 1. "F1TPE,FIFO 1 Top Pointer Enable." "0,1"
|
|
bitfld.long 0x0 0. "F0TPE,FIFO 0 Top Pointer Enable." "0,1"
|
|
rgroup.long ($2+0x1A0)++0x3
|
|
line.long 0x0 "RXFTOP0_STAT,Receive FIFO 0 Top Status"
|
|
hexmask.long.word 0x0 0.--15. 1. "F0TA,Current FIFO 0 Top Address."
|
|
rgroup.long ($2+0x1A8)++0x3
|
|
line.long 0x0 "RXFTOP0_DATA,Receive FIFO 0 Top Data"
|
|
hexmask.long 0x0 0.--31. 1. "F0TD,When enabled (F0TPE=1) read data from MRAM at location FnTA. This register can have a read side effect if the following conditions are met:"
|
|
rgroup.long ($2+0x1B0)++0x3
|
|
line.long 0x0 "RXFTOP1_STAT,Receive FIFO 1 Top Status"
|
|
hexmask.long.word 0x0 0.--15. 1. "F1TA,See F0TA description"
|
|
rgroup.long ($2+0x1B8)++0x3
|
|
line.long 0x0 "RXFTOP1_DATA,Receive FIFO 1 Top Data"
|
|
hexmask.long 0x0 0.--31. 1. "F1TD,See F0TD description"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40520000
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CTL,Global CAN control register"
|
|
bitfld.long 0x0 31. "MRAM_OFF,MRAM off" "0: Default MRAM on,1: Switch MRAM off"
|
|
hexmask.long.byte 0x0 0.--7. 1. "STOP_REQ,Clock Stop Request for each TTCAN IP ."
|
|
rgroup.long 0x1004++0x3
|
|
line.long 0x0 "STATUS,Global CAN status register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "STOP_ACK,Clock Stop Acknowledge for each TTCAN IP."
|
|
rgroup.long 0x1010++0x7
|
|
line.long 0x0 "INTR0_CAUSE,Consolidated interrupt0 cause register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT0,Show pending m_ttcan_int0 of each channel"
|
|
line.long 0x4 "INTR1_CAUSE,Consolidated interrupt1 cause register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "INT1,Show pending m_ttcan_int1 of each channel"
|
|
group.long 0x1020++0x7
|
|
line.long 0x0 "TS_CTL,Time Stamp control register"
|
|
bitfld.long 0x0 31. "ENABLED,Counter enable bit" "0: Count disabled,1: Count enabled"
|
|
hexmask.long.word 0x0 0.--15. 1. "PRESCALE,Time Stamp counter prescale value."
|
|
line.long 0x4 "TS_CNT,Time Stamp counter value"
|
|
hexmask.long.word 0x4 0.--15. 1. "VALUE,The counter value of the Time Stamp Counter."
|
|
group.long 0x1080++0x7
|
|
line.long 0x0 "ECC_CTL,ECC control"
|
|
bitfld.long 0x0 16. "ECC_EN,Enable ECC for CANFD SRAM" "0,1"
|
|
line.long 0x4 "ECC_ERR_INJ,ECC error injection"
|
|
hexmask.long.byte 0x4 24.--30. 1. "ERR_PAR,ECC Parity bits to use for ECC error injection at address ERR_ADDR."
|
|
bitfld.long 0x4 20. "ERR_EN,Enable error injection (ECC_EN must be 1)." "0,1"
|
|
hexmask.long.word 0x4 2.--15. 1. "ERR_ADDR,Specifies the address of the word where an error will be injected on write or an non-correctable error will be suppressed."
|
|
tree.end
|
|
tree "CANFD1"
|
|
base ad:0x40540000
|
|
repeat 5. (list 0x0 0x1 0x2 0x3 0x4)(list ad:0x40540000 ad:0x40540200 ad:0x40540400 ad:0x40540600 ad:0x40540800)
|
|
tree "CH[$1]"
|
|
base $2
|
|
tree "M_TTCAN (TTCAN 3PIP includes FD)"
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "CREL,Core Release Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day"
|
|
line.long 0x4 "ENDN,Endian Register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value"
|
|
group.long ($2+0xC)++0x23
|
|
line.long 0x0 "DBTP,Data Bit Timing & Prescaler Register"
|
|
bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation" "0: Transmitter Delay Compensation disabled,1: Transmitter Delay Compensation enabled"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Bit Rate Prescaler"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re)Synchronization Jump Width"
|
|
line.long 0x4 "TEST,Test Register"
|
|
rbitfld.long 0x4 7. "RX,Receive Pin" "0: The CAN bus is dominant,1: The CAN bus is recessive"
|
|
bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 4. "LBCK,Loop Back Mode" "0: Reset value,1: Loop Back Mode is enabled"
|
|
bitfld.long 0x4 3. "CAT,ASC is not supported by M_TTCAN" "0: Output pin m_ttcan_asct = '0',?"
|
|
newline
|
|
bitfld.long 0x4 2. "CAM,ASC is not supported by M_TTCAN" "0: Output pin m_ttcan_ascm = '0',1: Output pin m_ttcan_ascm = '1'"
|
|
bitfld.long 0x4 1. "TAT,ASC is not supported by M_TTCAN" "0: Level at pin m_ttcan_asct controlled by FSE,1: Level at pin m_ttcan_asct = '1'"
|
|
newline
|
|
bitfld.long 0x4 0. "TAM,ASC is not supported by M_TTCAN" "0: Level at pin m_ttcan_ascm controlled by FSE,1: Level at pin m_ttcan_ascm = '1'"
|
|
line.long 0x8 "RWD,RAM Watchdog"
|
|
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration"
|
|
line.long 0xC "CCCR,CC Control Register"
|
|
bitfld.long 0xC 15. "NISO,Non ISO Operation" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.."
|
|
bitfld.long 0xC 14. "TXP,Transmit Pause" "0: Transmit pause disabled,1: Transmit pause enabled"
|
|
newline
|
|
bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
|
|
bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
|
|
newline
|
|
bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
|
|
bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled"
|
|
newline
|
|
bitfld.long 0xC 7. "TEST,Test Mode Enable" "0: Normal operation,1: Test Mode"
|
|
bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
|
|
newline
|
|
bitfld.long 0xC 5. "MON_,Bus Monitoring Mode" "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled"
|
|
bitfld.long 0xC 4. "CSR,Clock Stop Request not supported by M_TTCAN use CTL.STOP_REQ at the group level instead." "0: No clock stop is requested,1: Clock stop requested"
|
|
newline
|
|
bitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: M_TTCAN may be set in power down by stopping.."
|
|
bitfld.long 0xC 2. "ASM,Restricted Operation Mode" "0: Normal CAN operation,1: Restricted Operation Mode active"
|
|
newline
|
|
bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
|
|
bitfld.long 0xC 0. "INIT,Initialization" "0: Normal Operation,1: Initialization is started"
|
|
line.long 0x10 "NBTP,Nominal Bit Timing & Prescaler Register"
|
|
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width"
|
|
hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point"
|
|
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point"
|
|
line.long 0x14 "TSCC,Timestamp Counter Configuration"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler (still used for TOCC)"
|
|
bitfld.long 0x14 0.--1. "TSS,Timestamp Select should always be set to external timestamp counter" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,?,?"
|
|
line.long 0x18 "TSCV,Timestamp Counter Value"
|
|
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter not used for M_TTCAN"
|
|
line.long 0x1C "TOCC,Timeout Counter Configuration"
|
|
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period"
|
|
bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,?,?"
|
|
newline
|
|
bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled,1: Timeout Counter enabled"
|
|
line.long 0x20 "TOCV,Timeout Counter Value"
|
|
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter"
|
|
rgroup.long ($2+0x40)++0x7
|
|
line.long 0x0 "ECR,Error Counter Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging"
|
|
bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter"
|
|
line.long 0x4 "PSR,Protocol Status Register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
|
|
bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
|
|
newline
|
|
bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0: Since this bit was reset by the CPU,1: Message in CAN FD format with FDF flag set has.."
|
|
bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set"
|
|
newline
|
|
bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set"
|
|
bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The M_CAN is not Bus_Off,1: The M_CAN is in Bus_Off state"
|
|
bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
|
|
newline
|
|
bitfld.long 0x4 5. "EP,Error Passive" "0: The M_CAN is in the Error_Active state,1: The M_CAN is in the Error_Passive state"
|
|
bitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing,1: Idle,?,?"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "LEC,Last Error Code " "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: AckError: The message transmitted by the M_TTCAN..,4: Bit1Error: During the transmission of a message,5: Bit0Error: During the transmission of a message,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol Status.."
|
|
group.long ($2+0x48)++0x3
|
|
line.long 0x0 "TDCR,Transmitter Delay Compensation Register"
|
|
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
|
|
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length"
|
|
group.long ($2+0x50)++0xF
|
|
line.long 0x0 "IR,Interrupt Register"
|
|
bitfld.long 0x0 29. "ARA,N/A" "0,1"
|
|
bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit Time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected"
|
|
newline
|
|
bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase (Nominal Bit Time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected"
|
|
bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY"
|
|
newline
|
|
bitfld.long 0x0 25. "BO_,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
|
|
bitfld.long 0x0 24. "EW_,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
|
|
newline
|
|
bitfld.long 0x0 23. "EP_,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
|
|
bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow,1: Overflow of CAN Error Logging Counter occurred"
|
|
newline
|
|
bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Bit error detected"
|
|
bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0: No Rx Buffer updated,1: At least one received message stored into a Rx.."
|
|
bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached"
|
|
newline
|
|
bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
|
|
bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
|
|
newline
|
|
bitfld.long 0x0 15. "TEFL_,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost"
|
|
bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full"
|
|
newline
|
|
bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark,1: Tx Event FIFO fill level reached watermark"
|
|
bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element"
|
|
newline
|
|
bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
|
|
bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
|
|
newline
|
|
bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed"
|
|
bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received"
|
|
newline
|
|
bitfld.long 0x0 7. "RF1L_,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
|
|
bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark"
|
|
bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
|
|
newline
|
|
bitfld.long 0x0 3. "RF0L_,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
|
|
bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
newline
|
|
bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark"
|
|
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
|
|
line.long 0x4 "IE,Interrupt Enable"
|
|
bitfld.long 0x4 29. "ARAE,N/A" "0,1"
|
|
bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable (not used in M_TTCAN)" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 12. "TEFNE,Tx Event FIDO New Entry Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt Disabled,1: Interrupt EnabledTx FIFO Empty Interrupt Enable"
|
|
bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
line.long 0x8 "ILS,Interrupt Line Select"
|
|
bitfld.long 0x8 29. "ARAL,N/A" "0,1"
|
|
bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 24. "EWL,Warning Status Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 23. "EPL,Error Passive Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Select (not used in M_TTCAN)" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
line.long 0xC "ILE,Interrupt Line Enable"
|
|
bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line m_ttcan_int1 disabled,1: Interrupt line m_ttcan_int1 enabled"
|
|
bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line m_ttcan_int0 disabled,1: Interrupt line m_ttcan_int0 enabled"
|
|
group.long ($2+0x80)++0xB
|
|
line.long 0x0 "GFC,Global Filter Configuration"
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
|
|
newline
|
|
bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
|
|
bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs"
|
|
line.long 0x4 "SIDFC,Standard ID Filter Configuration"
|
|
hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard"
|
|
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address"
|
|
line.long 0x8 "XIDFC,Extended ID Filter Configuration"
|
|
hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended"
|
|
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address"
|
|
group.long ($2+0x90)++0x3
|
|
line.long 0x0 "XIDAM,Extended ID AND Mask"
|
|
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask"
|
|
rgroup.long ($2+0x94)++0x3
|
|
line.long 0x0 "HPMS,High Priority Message Status"
|
|
bitfld.long 0x0 15. "FLST,Filter List" "0: Standard Filter List,1: Extended Filter List"
|
|
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO message lost,?,?"
|
|
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index"
|
|
group.long ($2+0x98)++0xB
|
|
line.long 0x0 "NDAT1,New Data 1"
|
|
hexmask.long 0x0 0.--31. 1. "ND,New Data"
|
|
line.long 0x4 "NDAT2,New Data 2"
|
|
hexmask.long 0x4 0.--31. 1. "ND,New Data"
|
|
line.long 0x8 "RXF0C,Rx FIFO 0 Configuration"
|
|
bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address"
|
|
rgroup.long ($2+0xA4)++0x3
|
|
line.long 0x0 "RXF0S,Rx FIFO 0 Status"
|
|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
|
|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index"
|
|
hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level"
|
|
group.long ($2+0xA8)++0xB
|
|
line.long 0x0 "RXF0A,Rx FIFO 0 Acknowledge"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index"
|
|
line.long 0x4 "RXBC,Rx Buffer Configuration"
|
|
hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address"
|
|
line.long 0x8 "RXF1C,Rx FIFO 1 Configuration"
|
|
bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address"
|
|
rgroup.long ($2+0xB4)++0x3
|
|
line.long 0x0 "RXF1S,Rx FIFO 1 Status"
|
|
bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state,1: Debug message A received,?,?"
|
|
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
|
|
newline
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index"
|
|
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level"
|
|
group.long ($2+0xB8)++0xB
|
|
line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index"
|
|
line.long 0x4 "RXESC,Rx Buffer / FIFO Element Size Configuration"
|
|
bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "TXBC,Tx Buffer Configuration"
|
|
bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation"
|
|
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
|
|
hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address"
|
|
rgroup.long ($2+0xC4)++0x3
|
|
line.long 0x0 "TXFQS,Tx FIFO/Queue Status"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index"
|
|
hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level"
|
|
group.long ($2+0xC8)++0x3
|
|
line.long 0x0 "TXESC,Tx Buffer Element Size Configuration"
|
|
bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
|
|
rgroup.long ($2+0xCC)++0x3
|
|
line.long 0x0 "TXBRP,Tx Buffer Request Pending"
|
|
hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request Pending"
|
|
group.long ($2+0xD0)++0x7
|
|
line.long 0x0 "TXBAR,Tx Buffer Add Request"
|
|
hexmask.long 0x0 0.--31. 1. "AR,Add Request"
|
|
line.long 0x4 "TXBCR,Tx Buffer Cancellation Request"
|
|
hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request"
|
|
rgroup.long ($2+0xD8)++0x7
|
|
line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred"
|
|
hexmask.long 0x0 0.--31. 1. "TO,Transmission Occurred"
|
|
line.long 0x4 "TXBCF,Tx Buffer Cancellation Finished"
|
|
hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished"
|
|
group.long ($2+0xE0)++0x7
|
|
line.long 0x0 "TXBTIE,Tx Buffer Transmission Interrupt Enable"
|
|
hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt Enable"
|
|
line.long 0x4 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
|
|
hexmask.long 0x4 0.--31. 1. "CFIE,Cancellation Finished Interrupt Enable"
|
|
group.long ($2+0xF0)++0x3
|
|
line.long 0x0 "TXEFC,Tx Event FIFO Configuration"
|
|
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark"
|
|
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address"
|
|
rgroup.long ($2+0xF4)++0x3
|
|
line.long 0x0 "TXEFS,Tx Event FIFO Status"
|
|
bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index"
|
|
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level"
|
|
group.long ($2+0xF8)++0x3
|
|
line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge"
|
|
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index"
|
|
group.long ($2+0x100)++0x2B
|
|
line.long 0x0 "TTTMC,TT Trigger Memory Configuration"
|
|
hexmask.long.byte 0x0 16.--22. 1. "TME,Trigger Memory Elements"
|
|
hexmask.long.word 0x0 2.--15. 1. "TMSA,Trigger Memory Start Address"
|
|
line.long 0x4 "TTRMC,TT Reference Message Configuration"
|
|
bitfld.long 0x4 31. "RMPS,Reference Message Payload Select" "0: Reference message has no additional payload,1: bytes 2-8"
|
|
bitfld.long 0x4 30. "XTD,Extended Identifier" "0,1"
|
|
newline
|
|
hexmask.long 0x4 0.--28. 1. "RID,Reference Identifier"
|
|
line.long 0x8 "TTOCF,TT Operation Configuration"
|
|
bitfld.long 0x8 26. "EVTP,Event Trigger Polarity" "0: Rising edge trigger,1: Falling edge trigger"
|
|
bitfld.long 0x8 25. "ECC,Enable Clock Calibration" "0: Automatic clock calibration in TTCAN Level 0,1: Automatic clock calibration in TTCAN Level 0"
|
|
newline
|
|
bitfld.long 0x8 24. "EGTF,Enable Global Time Filtering" "0: Global time filtering in TTCAN Level 0,1: Global time filtering in TTCAN Level 0"
|
|
hexmask.long.byte 0x8 16.--23. 1. "AWL,Application Watchdog Limit"
|
|
newline
|
|
bitfld.long 0x8 15. "EECS,Enable External Clock Synchronization" "0: External clock synchronization in TTCAN Level 0,1: External clock synchronization in TTCAN Level 0"
|
|
hexmask.long.byte 0x8 8.--14. 1. "IRTO,Initial Reference Trigger Offset"
|
|
newline
|
|
bitfld.long 0x8 5.--7. "LDSDL,LD of Synchronization Deviation Limit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 4. "TM,Time Master" "0: Time Master function disabled,1: Potential Time Master"
|
|
newline
|
|
bitfld.long 0x8 3. "GEN,Gap Enable" "0: Strictly time-triggered operation,1: External event-synchronized time-triggered.."
|
|
bitfld.long 0x8 0.--1. "OM,Operation Mode" "0: Event-driven CAN communication,1: TTCAN level 1,?,?"
|
|
line.long 0xC "TTMLM,TT Matrix Limits"
|
|
hexmask.long.word 0xC 16.--27. 1. "ENTT,Expected Number of Tx Triggers"
|
|
hexmask.long.byte 0xC 8.--11. 1. "TXEW,Tx Enable Window"
|
|
newline
|
|
bitfld.long 0xC 6.--7. "CSS,N/A" "0,1,2,3"
|
|
hexmask.long.byte 0xC 0.--5. 1. "CCM,N/A"
|
|
line.long 0x10 "TURCF,TUR Configuration"
|
|
bitfld.long 0x10 31. "ELT,Enable Local Time" "0: Local time is stopped,1: Local time is enabled"
|
|
hexmask.long.word 0x10 16.--29. 1. "DC,Denominator Configuration"
|
|
newline
|
|
hexmask.long.word 0x10 0.--15. 1. "NCL,Numerator Configuration Low"
|
|
line.long 0x14 "TTOCN,TT Operation Control"
|
|
rbitfld.long 0x14 15. "LCKC,TT Operation Control Register Locked" "0: Write access to TTOCN enabled,1: Write access to TTOCN locked"
|
|
bitfld.long 0x14 13. "ESCN,External Synchronization Control" "0: External synchronization disabled,1: External synchronization enabled"
|
|
newline
|
|
bitfld.long 0x14 12. "NIG,Next is Gap" "0: No action,1: Transmit next reference message with Next_is_Gap.."
|
|
bitfld.long 0x14 11. "TMG,Time Mark Gap" "0: Reset by each reference message,1: Next reference message started when Register.."
|
|
newline
|
|
bitfld.long 0x14 10. "FGP,Finish Gap" "0: No reference message requested,1: Application requested start of reference message"
|
|
bitfld.long 0x14 9. "GCS,Gap Control Select" "0: Gap control independent from m_ttcan_evt,1: Gap control by input pin m_ttcan_evt"
|
|
newline
|
|
bitfld.long 0x14 8. "TTIE,Trigger Time Mark Interrupt Pulse Enable" "0: Trigger Time Mark Interrupt output m_ttcan_tmp..,1: Trigger Time Mark Interrupt output m_ttcan_tmp.."
|
|
bitfld.long 0x14 6.--7. "TMC,Register Time Mark Compare" "0: No Register Time Mark Interrupt generated,1: Register Time Mark Interrupt if Time Mark =..,?,?"
|
|
newline
|
|
bitfld.long 0x14 5. "RTIE,Register Time Mark Interrupt Pulse Enable" "0: Register Time Mark Interrupt output m_ttcan_rtp..,1: Register Time Mark Interrupt output m_ttcan_rtp.."
|
|
bitfld.long 0x14 3.--4. "SWS,Stop Watch Source" "0: Stop Watch disabled,1: Actual value of cycle time is copied to TTCPT,?,?"
|
|
newline
|
|
bitfld.long 0x14 2. "SWP,Stop Watch Polarity" "0: Rising edge trigger,1: Falling edge trigger"
|
|
bitfld.long 0x14 1. "ECS,External Clock Synchronization" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "SGT,Set Global time" "0,1"
|
|
line.long 0x18 "TTGTP,TT Global Time Preset"
|
|
hexmask.long.word 0x18 16.--31. 1. "CTP,Cycle Time Target Phase"
|
|
hexmask.long.word 0x18 0.--15. 1. "TP,N/A"
|
|
line.long 0x1C "TTTMK,TT Time Mark"
|
|
rbitfld.long 0x1C 31. "LCKM,TT Time Mark Register Locked" "0: Write access to TTTMK enabled,1: Write access to TTTMK locked"
|
|
hexmask.long.byte 0x1C 16.--22. 1. "TICC,Time Mark Cycle Code"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--15. 1. "TM_,Time Mark"
|
|
line.long 0x20 "TTIR,TT Interrupt Register"
|
|
bitfld.long 0x20 18. "CER,Configuration Error" "0: No error found in trigger list,1: Error found in trigger list"
|
|
bitfld.long 0x20 17. "AW,Application Watchdog" "0: Application watchdog served in time,1: Application watchdog not served in time"
|
|
newline
|
|
bitfld.long 0x20 16. "WT,Watch Trigger" "0: cycle time 0xFF00),1: Missing reference message"
|
|
bitfld.long 0x20 15. "IWT,Initialization Watch Trigger" "0: No missing reference message during system startup,1: No system startup due to missing reference message"
|
|
newline
|
|
bitfld.long 0x20 14. "ELC,Error Level Changed" "0: No change in error level,1: Error level changed"
|
|
bitfld.long 0x20 13. "SE2,Scheduling Error 2" "0: No scheduling error 2,1: Scheduling error 2 occurred"
|
|
newline
|
|
bitfld.long 0x20 12. "SE1,Scheduling Error 1" "0: No scheduling error 1,1: Scheduling error 1 occurred"
|
|
bitfld.long 0x20 11. "TXO,Tx Count Overflow" "0: Number of Tx Trigger as expected,1: More Tx trigger than expected in one matrix cycle"
|
|
newline
|
|
bitfld.long 0x20 10. "TXU,Tx Count Underflow" "0: Number of Tx Trigger as expected,1: Less Tx trigger than expected in one matrix cycle"
|
|
bitfld.long 0x20 9. "GTE,Global Time Error" "0: Synchronization deviation within limit,1: Synchronization deviation exceeded limit"
|
|
newline
|
|
bitfld.long 0x20 8. "GTD,Global Time Discontinuity" "0: No discontinuity of global time,1: Discontinuity of global time"
|
|
bitfld.long 0x20 7. "GTW,Global Time Wrap" "0: No global time wrap occurred,1: Global time wrap from 0xFFFF to 0x0000 occurred"
|
|
newline
|
|
bitfld.long 0x20 6. "SWE,Stop Watch Event" "0: No rising/falling edge at stop watch trigger pin..,1: Rising/falling edge at stop watch trigger pin.."
|
|
bitfld.long 0x20 5. "TTMI,Trigger Time Mark Event Internal" "0: cycle time TTOCF,1: Time mark reached"
|
|
newline
|
|
bitfld.long 0x20 4. "RTMI,Register Time Mark Interrupt" "0: Time mark not reached,1: Time mark reached"
|
|
bitfld.long 0x20 3. "SOG,Start of Gap" "0: No reference message seen with Next_is_Gap bit set,1: Reference message with Next_is_Gap bit set.."
|
|
newline
|
|
bitfld.long 0x20 2. "CSM_,Change of Synchronization Mode" "0: No change in master to slave relation or..,1: Master to slave relation or schedule.."
|
|
bitfld.long 0x20 1. "SMC,Start of Matrix Cycle" "0: No Matrix Cycle started since bit has been reset,1: Matrix Cycle started"
|
|
newline
|
|
bitfld.long 0x20 0. "SBC,Start of Basic Cycle" "0: No Basic Cycle started since bit has been reset,1: Basic Cycle started"
|
|
line.long 0x24 "TTIE,TT Interrupt Enable"
|
|
bitfld.long 0x24 18. "CERE,Configuration Error Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 17. "AWE_,Application Watchdog Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 16. "WTE,Watch Trigger Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 15. "IWTE,Initialization Watch Trigger Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 14. "ELCE,Change Error Level Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 13. "SE2E,Scheduling Error 2 Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 12. "SE1E,Scheduling Error 1 Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 11. "TXOE,Tx Count Overflow Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 10. "TXUE,Tx Count Underflow Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 9. "GTEE,Global Time Error Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 8. "GTDE,Global Time Discontinuity Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 7. "GTWE,Global Time Wrap Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 6. "SWEE,Stop Watch Event Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 5. "TTMIE,Trigger Time Mark Event Internal Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 4. "RTMIE,Register Time Mark Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 3. "SOGE,Start of Gap Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 2. "CSME,Change of Synchronization Mode Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x24 1. "SMCE,Start of Matrix Cycle Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x24 0. "SBCE,Start of Basic Cycle Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
line.long 0x28 "TTILS,TT Interrupt Line Select"
|
|
bitfld.long 0x28 18. "CERL,Configuration Error Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 17. "AWL_,Application Watchdog Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 16. "WTL,Watch Trigger Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 15. "IWTL,Initialization Watch Trigger Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 14. "ELCL,Change Error Level Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 13. "SE2L,Scheduling Error 2 Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 12. "SE1L,Scheduling Error 1 Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 11. "TXOL,Tx Count Overflow Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 10. "TXUL,Tx Count Underflow Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 9. "GTEL,Global Time Error Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 8. "GTDL,Global Time Discontinuity Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 7. "GTWL,Global Time Wrap Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 6. "SWEL,Stop Watch Event Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 5. "TTMIL,Trigger Time Mark Event Internal Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 4. "RTMIL,Register Time Mark Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 3. "SOGL,Start of Gap Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 2. "CSML,Change of Synchronization Mode Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
bitfld.long 0x28 1. "SMCL,Start of Matrix Cycle Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
newline
|
|
bitfld.long 0x28 0. "SBCL,Start of Basic Cycle Interrupt Select" "0: Assign to interrupt enabled by ILE,1: Assign to interrupt enabled by ILE"
|
|
rgroup.long ($2+0x12C)++0x17
|
|
line.long 0x0 "TTOST,TT Operation Status"
|
|
bitfld.long 0x0 31. "SPL,Schedule Phase Lock" "0: Phase outside range,1: Phase inside range"
|
|
bitfld.long 0x0 30. "WECS,Wait for External Clock Synchronization" "0: No external clock synchronization pending,1: Node waits for external clock synchronization to.."
|
|
newline
|
|
bitfld.long 0x0 29. "AWE,Application Watchdog Event" "0: Application Watchdog served in time,1: Failed to serve Application Watchdog in time"
|
|
bitfld.long 0x0 28. "WFE,Wait for Event" "0: No Gap announced,1: Reference message with Next_is_Gap = '1' received"
|
|
newline
|
|
bitfld.long 0x0 27. "GSI,Gap Started Indicator" "0: No Gap in schedule,1: Gap time after Basic Cycle has started"
|
|
bitfld.long 0x0 24.--26. "TMP,Time Master Priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 23. "GFI,Gap Finished Indicator" "0: Reset at the end of each reference message,1: Gap finished by M_TTCAN"
|
|
bitfld.long 0x0 22. "WGTD,Wait for Global Time Discontinuity" "0: No global time preset pending,1: Node waits for the global time preset to take.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RTO,Reference Trigger Offset"
|
|
bitfld.long 0x0 7. "QCS,Quality of Clock Speed" "0: Local clock speed not synchronized to Time..,1: Synchronization Deviation <= SDL"
|
|
newline
|
|
bitfld.long 0x0 6. "QGTP,Quality of Global Time Phase" "0: Global time not valid,1: Global time in phase with Time Master"
|
|
bitfld.long 0x0 4.--5. "SYS,Synchronization State" "0: Out of Synchronization,1: Synchronizing to TTCAN communication,?,?"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MS,Master State" "0: Master_Off,1: Operating as Time Slave,?,?"
|
|
bitfld.long 0x0 0.--1. "EL,Error Level" "0: Severity 0,1: Severity 1,?,?"
|
|
line.long 0x4 "TURNA,TUR Numerator Actual"
|
|
hexmask.long.tbyte 0x4 0.--17. 1. "NAV,N/A"
|
|
line.long 0x8 "TTLGT,TT Local & Global Time"
|
|
hexmask.long.word 0x8 16.--31. 1. "GT,Global Time"
|
|
hexmask.long.word 0x8 0.--15. 1. "LT,Local Time"
|
|
line.long 0xC "TTCTC,TT Cycle Time & Count"
|
|
hexmask.long.byte 0xC 16.--21. 1. "CC,Cycle Count"
|
|
hexmask.long.word 0xC 0.--15. 1. "CT,Cycle Time"
|
|
line.long 0x10 "TTCPT,TT Capture Time"
|
|
hexmask.long.word 0x10 16.--31. 1. "SWV,Stop Watch Value"
|
|
hexmask.long.byte 0x10 0.--5. 1. "CCV,Cycle Count Value"
|
|
line.long 0x14 "TTCSM,TT Cycle Sync Mark"
|
|
hexmask.long.word 0x14 0.--15. 1. "CSM,Cycle Sync Mark"
|
|
tree.end
|
|
group.long ($2+0x180)++0x3
|
|
newline
|
|
line.long 0x0 "RXFTOP_CTL,Receive FIFO Top control"
|
|
bitfld.long 0x0 1. "F1TPE,FIFO 1 Top Pointer Enable." "0,1"
|
|
bitfld.long 0x0 0. "F0TPE,FIFO 0 Top Pointer Enable." "0,1"
|
|
rgroup.long ($2+0x1A0)++0x3
|
|
line.long 0x0 "RXFTOP0_STAT,Receive FIFO 0 Top Status"
|
|
hexmask.long.word 0x0 0.--15. 1. "F0TA,Current FIFO 0 Top Address."
|
|
rgroup.long ($2+0x1A8)++0x3
|
|
line.long 0x0 "RXFTOP0_DATA,Receive FIFO 0 Top Data"
|
|
hexmask.long 0x0 0.--31. 1. "F0TD,When enabled (F0TPE=1) read data from MRAM at location FnTA. This register can have a read side effect if the following conditions are met:"
|
|
rgroup.long ($2+0x1B0)++0x3
|
|
line.long 0x0 "RXFTOP1_STAT,Receive FIFO 1 Top Status"
|
|
hexmask.long.word 0x0 0.--15. 1. "F1TA,See F0TA description"
|
|
rgroup.long ($2+0x1B8)++0x3
|
|
line.long 0x0 "RXFTOP1_DATA,Receive FIFO 1 Top Data"
|
|
hexmask.long 0x0 0.--31. 1. "F1TD,See F0TD description"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40540000
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CTL,Global CAN control register"
|
|
bitfld.long 0x0 31. "MRAM_OFF,MRAM off" "0: Default MRAM on,1: Switch MRAM off"
|
|
hexmask.long.byte 0x0 0.--7. 1. "STOP_REQ,Clock Stop Request for each TTCAN IP ."
|
|
rgroup.long 0x1004++0x3
|
|
line.long 0x0 "STATUS,Global CAN status register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "STOP_ACK,Clock Stop Acknowledge for each TTCAN IP."
|
|
rgroup.long 0x1010++0x7
|
|
line.long 0x0 "INTR0_CAUSE,Consolidated interrupt0 cause register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT0,Show pending m_ttcan_int0 of each channel"
|
|
line.long 0x4 "INTR1_CAUSE,Consolidated interrupt1 cause register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "INT1,Show pending m_ttcan_int1 of each channel"
|
|
group.long 0x1020++0x7
|
|
line.long 0x0 "TS_CTL,Time Stamp control register"
|
|
bitfld.long 0x0 31. "ENABLED,Counter enable bit" "0: Count disabled,1: Count enabled"
|
|
hexmask.long.word 0x0 0.--15. 1. "PRESCALE,Time Stamp counter prescale value."
|
|
line.long 0x4 "TS_CNT,Time Stamp counter value"
|
|
hexmask.long.word 0x4 0.--15. 1. "VALUE,The counter value of the Time Stamp Counter."
|
|
group.long 0x1080++0x7
|
|
line.long 0x0 "ECC_CTL,ECC control"
|
|
bitfld.long 0x0 16. "ECC_EN,Enable ECC for CANFD SRAM" "0,1"
|
|
line.long 0x4 "ECC_ERR_INJ,ECC error injection"
|
|
hexmask.long.byte 0x4 24.--30. 1. "ERR_PAR,ECC Parity bits to use for ECC error injection at address ERR_ADDR."
|
|
bitfld.long 0x4 20. "ERR_EN,Enable error injection (ECC_EN must be 1)." "0,1"
|
|
hexmask.long.word 0x4 2.--15. 1. "ERR_ADDR,Specifies the address of the word where an error will be injected on write or an non-correctable error will be suppressed."
|
|
tree.end
|
|
tree.end
|
|
tree "CPUSS (CPU Subsystem)"
|
|
base ad:0x40200000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "IDENTITY,Identity"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MS,This field specifies the bus master identifier of the transfer that reads the register."
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,This field specifies the protection context of the transfer that reads the register."
|
|
newline
|
|
bitfld.long 0x0 1. "NS,This field specifies the security setting ('0': secure mode; '1': non-secure mode) of the transfer that reads the register." "0,1"
|
|
bitfld.long 0x0 0. "P,This field specifies the privileged setting ('0': user mode; '1': privileged mode) of the transfer that reads the register." "0,1"
|
|
line.long 0x4 "CM7_0_STATUS,CM7 0 status"
|
|
bitfld.long 0x4 17. "TCMC_CM7_3_MS,Outstanding transactions from CM7 3." "0,1"
|
|
bitfld.long 0x4 16. "TCMC_CM7_2_MS,Outstanding transactions from CM7 2." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "TCMC_AHB_MS,Ongoing AHB transaction." "0,1"
|
|
bitfld.long 0x4 11. "TCMC_EXT_MS_3,Outstanding transactions from external AXI master 3." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "TCMC_EXT_MS_2_TO_0,Outstanding transactions from external AXI masters 2 to 0." "0,1"
|
|
bitfld.long 0x4 9. "TCMC_CM7_1_MS,Outstanding transactions from CM7 1." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PWR_DONE,After a PWR_MODE change this flag indicates if the new power mode has taken effect or not." "0,1"
|
|
bitfld.long 0x4 1. "SLEEPDEEP,Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "SLEEPING,Specifies if the CPU is in Active Sleep or DeepSleep power mode:" "0,1"
|
|
group.long 0x8++0x7
|
|
line.long 0x0 "FAST_0_CLOCK_CTL,Fast 0 clock control"
|
|
hexmask.long.byte 0x0 8.--15. 1. "INT_DIV,Integer division by (1+INT_DIV). Allows for integer divisions in the range [1 256] (INT_DIV is in the range [0 255])."
|
|
hexmask.long.byte 0x0 3.--7. 1. "FRAC_DIV,Fractional division by (FRAC_DIV/32). Allows for fractional divisions in the range [0 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf<x>' cycle longer than other clock periods."
|
|
line.long 0x4 "CM7_0_CTL,CM7 0 control"
|
|
bitfld.long 0x4 31. "IDC_MASK,CPU FPU exception mask for the CPU's FPCSR.IDC 'input denormalized' exception condition:" "0,1"
|
|
bitfld.long 0x4 28. "IXC_MASK,CPU FPU exception mask for the CPU's FPCSR.IXC 'inexact' exception condition:" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "UFC_MASK,CPU FPU exception mask for the CPU's FPCSR.UFC 'underflow' exception condition:" "0,1"
|
|
bitfld.long 0x4 26. "OFC_MASK,CPU FPU exception mask for the CPU's FPCSR.OFC 'overflow' exception condition:" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "DZC_MASK,CPU FPU exception mask for the CPU's FPCSR.DZC 'divide by zero' exception condition:" "0,1"
|
|
bitfld.long 0x4 24. "IOC_MASK,CPU floating point unit (FPU) exception mask for the CPU's FPCSR.IOC 'invalid operation' exception condition:" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "TCMC_EN,CM7 TCMC access control:" "0,1"
|
|
bitfld.long 0x4 22. "DTCM_READ_WS,DTCM read wait states (writes have no wait states)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "DTCM_ECC_INJ_EN,DTCM ECC error injection enable:" "0,1"
|
|
bitfld.long 0x4 20. "DTCM_ECC_EN,DTCM ECC enable:" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "ITCM_ECC_CHECK_DIS,Disable ECC checking and thus fault reports. This also disables ECC correction (required to enable initialization). Intended usage is initialization. This bit is ignored when TCM_ECC_EN=0." "0,1"
|
|
bitfld.long 0x4 18. "ITCM_READ_WS,ITCM read wait states (writes have no wait states)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "ITCM_ECC_INJ_EN,ITCM ECC error injection enable:" "0,1"
|
|
bitfld.long 0x4 16. "ITCM_ECC_EN,ITCM ECC enable:" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "INIT_RMW_EN,TCM read-modify-write enable initialization after reset:" "0: ITCM,1: DTCM,?,?"
|
|
bitfld.long 0x4 8.--9. "INIT_TCM_EN,TCM enable initialization after reset:" "0: ITCM,1: DTCM,?,?"
|
|
newline
|
|
bitfld.long 0x4 4. "CPU_WAIT,When this signal is '1' out of reset it forces the CPU into a quiescent state that delays its boot-up sequence and instruction execution until this signal is driven '0'. This allows the TCMs to be loaded by the system before the CPU performs.." "0,1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PPB_LOCK,Write disable for specific CPU registers:"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x100)++0x3
|
|
line.long 0x0 "CM7_0_INT_STATUS[$1],CM7 0 interrupt status"
|
|
bitfld.long 0x0 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x0 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM7_0 activated system interrupt index for CPU interrupt."
|
|
repeat.end
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "CM7_0_VECTOR_TABLE_BASE,CM7 0 vector table base"
|
|
hexmask.long 0x0 7.--31. 1. "ADDR25,The default CM7 vector table base address is 0x0100:0000 (CM7 VTOR and reset exception handler address after reset). This is the location of the system ROM memory."
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x240)++0x3
|
|
line.long 0x0 "CM7_0_NMI_CTL[$1],CM7 0 NMI control"
|
|
hexmask.long.word 0x0 0.--9. 1. "SYSTEM_INT_IDX,System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset."
|
|
repeat.end
|
|
group.long 0x300++0x7
|
|
line.long 0x0 "UDB_PWR_CTL,UDB power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Set Power mode for UDBs" "0: See CM7_0_PWR_CTL,1: See CM7_0_PWR_CTL,2: See CM7_0_PWR_CTL,3: See CM7_0_PWR_CTL"
|
|
line.long 0x4 "UDB_PWR_DELAY_CTL,UDB power control"
|
|
hexmask.long.word 0x4 0.--9. 1. "UP,Number clock cycles delay needed after power domain power up"
|
|
group.long 0x320++0x3
|
|
line.long 0x0 "TRC_DBG_CLOCK_CTL,Trace and debug clock control"
|
|
hexmask.long.byte 0x0 8.--15. 1. "INT_DIV,Integer division by (1+INT_DIV). Allows for integer divisions in the range [1 256] (INT_DIV is in the range [0 255])."
|
|
rgroup.long 0x404++0x3
|
|
line.long 0x0 "CM7_1_STATUS,CM7 1status"
|
|
bitfld.long 0x0 17. "TCMC_CM7_3_MS,Outstanding transactions from CM7 3." "0,1"
|
|
bitfld.long 0x0 16. "TCMC_CM7_2_MS,Outstanding transactions from CM7 2." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "TCMC_AHB_MS,Refer CM7_0_STATUS description." "0,1"
|
|
bitfld.long 0x0 11. "TCMC_EXT_MS_3,Refer CM7_0_STATUS description." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "TCMC_EXT_MS_2_TO_0,Refer CM7_0_STATUS description." "0,1"
|
|
bitfld.long 0x0 8. "TCMC_CM7_0_MS,Outstanding transactions from CM7 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PWR_DONE,After a PWR_MODE change this flag indicates if the new power mode has taken effect or not." "0,1"
|
|
bitfld.long 0x0 1. "SLEEPDEEP,Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SLEEPING,Specifies if the CPU is in Active Sleep or DeepSleep power mode:" "0,1"
|
|
group.long 0x408++0x7
|
|
line.long 0x0 "FAST_1_CLOCK_CTL,Fast 1 clock control"
|
|
hexmask.long.byte 0x0 8.--15. 1. "INT_DIV,Refer FAST_0_CLOCK_CTL description."
|
|
hexmask.long.byte 0x0 3.--7. 1. "FRAC_DIV,Refer FAST_0_CLOCK_CTL description."
|
|
line.long 0x4 "CM7_1_CTL,CM7 1 control"
|
|
bitfld.long 0x4 31. "IDC_MASK,Refer CM7_0_CTL description." "0,1"
|
|
bitfld.long 0x4 28. "IXC_MASK,Refer CM7_0_CTL description." "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "UFC_MASK,Refer CM7_0_CTL description." "0,1"
|
|
bitfld.long 0x4 26. "OFC_MASK,Refer CM7_0_CTL description." "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "DZC_MASK,Refer CM7_0_CTL description." "0,1"
|
|
bitfld.long 0x4 24. "IOC_MASK,Refer CM7_0_CTL description." "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "TCMC_EN,Refer CM7_0_CTL description." "0,1"
|
|
bitfld.long 0x4 22. "DTCM_READ_WS,Refer CM7_0_CTL description." "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "DTCM_ECC_INJ_EN,Refer CM7_0_CTL description." "0,1"
|
|
bitfld.long 0x4 20. "DTCM_ECC_EN,Refer CM7_0_CTL description." "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "ITCM_ECC_CHECK_DIS,Disable ECC checking and thus fault reports. This also disables ECC correction (required to enable initialization). Intended usage is initialization. This bit is ignored when TCM_ECC_EN=0." "0,1"
|
|
bitfld.long 0x4 18. "ITCM_READ_WS,Refer CM7_0_CTL description." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "ITCM_ECC_INJ_EN,Refer CM7_0_CTL description." "0,1"
|
|
bitfld.long 0x4 16. "ITCM_ECC_EN,Refer CM7_0_CTL description." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "INIT_RMW_EN,Refer CM7_0_CTL description." "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "INIT_TCM_EN,Refer CM7_0_CTL description." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 4. "CPU_WAIT,Refer CM7_0_CTL description." "0,1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PPB_LOCK,Refer CM7_0_CTL description."
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x500)++0x3
|
|
line.long 0x0 "CM7_1_INT_STATUS[$1],CM7 1 interrupt status"
|
|
bitfld.long 0x0 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x0 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM7_1 activated system interrupt index for CPU interrupt 0."
|
|
repeat.end
|
|
group.long 0x600++0x3
|
|
line.long 0x0 "CM7_1_VECTOR_TABLE_BASE,CM7 1 vector table base"
|
|
hexmask.long 0x0 7.--31. 1. "ADDR25,The default CM7 vector table base address is 0x0100:0000 (CM7 VTOR and reset exception handler address after reset). This is the location of the system ROM memory."
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x640)++0x3
|
|
line.long 0x0 "CM7_1_NMI_CTL[$1],CM7 1 NMI control"
|
|
hexmask.long.word 0x0 0.--9. 1. "SYSTEM_INT_IDX,Refer CM7_0_NMI_CTL description."
|
|
repeat.end
|
|
rgroup.long 0x804++0x3
|
|
line.long 0x0 "CM7_2_STATUS,CM7 2 status"
|
|
bitfld.long 0x0 17. "TCMC_CM7_3_MS,Outstanding transactions from CM7 3." "0,1"
|
|
bitfld.long 0x0 12. "TCMC_AHB_MS,Refer CM7_0_STATUS description." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TCMC_EXT_MS_3,Refer CM7_0_STATUS description." "0,1"
|
|
bitfld.long 0x0 10. "TCMC_EXT_MS_2_TO_0,Refer CM7_0_STATUS description." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TCMC_CM7_1_MS,Outstanding transactions from CM7 1." "0,1"
|
|
bitfld.long 0x0 8. "TCMC_CM7_0_MS,Outstanding transactions from CM7 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PWR_DONE,After a PWR_MODE change this flag indicates if the new power mode has taken effect or not." "0,1"
|
|
bitfld.long 0x0 1. "SLEEPDEEP,Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SLEEPING,Specifies if the CPU is in Active Sleep or DeepSleep power mode:" "0,1"
|
|
group.long 0x808++0x7
|
|
line.long 0x0 "FAST_2_CLOCK_CTL,Fast 2 clock control"
|
|
hexmask.long.byte 0x0 8.--15. 1. "INT_DIV,Refer FAST_0_CLOCK_CTL description."
|
|
hexmask.long.byte 0x0 3.--7. 1. "FRAC_DIV,Refer FAST_0_CLOCK_CTL description."
|
|
line.long 0x4 "CM7_2_CTL,CM7 2 control"
|
|
bitfld.long 0x4 31. "IDC_MASK,Refer CM7_0_CTL description." "0,1"
|
|
bitfld.long 0x4 28. "IXC_MASK,Refer CM7_0_CTL description." "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "UFC_MASK,Refer CM7_0_CTL description." "0,1"
|
|
bitfld.long 0x4 26. "OFC_MASK,Refer CM7_0_CTL description." "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "DZC_MASK,Refer CM7_0_CTL description." "0,1"
|
|
bitfld.long 0x4 24. "IOC_MASK,Refer CM7_0_CTL description." "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "TCMC_EN,Refer CM7_0_CTL description." "0,1"
|
|
bitfld.long 0x4 22. "DTCM_READ_WS,Refer CM7_0_CTL description." "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "DTCM_ECC_INJ_EN,Refer CM7_0_CTL description." "0,1"
|
|
bitfld.long 0x4 20. "DTCM_ECC_EN,Refer CM7_0_CTL description." "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "ITCM_ECC_CHECK_DIS,Disable ECC checking and thus fault reports. This also disables ECC correction (required to enable initialization). Intended usage is initialization. This bit is ignored when TCM_ECC_EN=0." "0,1"
|
|
bitfld.long 0x4 18. "ITCM_READ_WS,Refer CM7_0_CTL description." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "ITCM_ECC_INJ_EN,Refer CM7_0_CTL description." "0,1"
|
|
bitfld.long 0x4 16. "ITCM_ECC_EN,Refer CM7_0_CTL description." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "INIT_RMW_EN,Refer CM7_0_CTL description." "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "INIT_TCM_EN,Refer CM7_0_CTL description." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 4. "CPU_WAIT,Refer CM7_0_CTL description." "0,1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PPB_LOCK,Refer CM7_0_CTL description."
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x900)++0x3
|
|
line.long 0x0 "CM7_2_INT_STATUS[$1],CM7 2 interrupt status"
|
|
bitfld.long 0x0 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x0 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM7_2 activated system interrupt index for CPU interrupt 0."
|
|
repeat.end
|
|
group.long 0xA00++0x3
|
|
line.long 0x0 "CM7_2_VECTOR_TABLE_BASE,CM7 2 vector table base"
|
|
hexmask.long 0x0 7.--31. 1. "ADDR25,The default CM7 vector table base address is 0x0100:0000 (CM7 VTOR and reset exception handler address after reset). This is the location of the system ROM memory."
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xA40)++0x3
|
|
line.long 0x0 "CM7_2_NMI_CTL[$1],CM7 2 NMI control"
|
|
hexmask.long.word 0x0 0.--9. 1. "SYSTEM_INT_IDX,Refer CM7_0_NMI_CTL description."
|
|
repeat.end
|
|
rgroup.long 0xC04++0x3
|
|
line.long 0x0 "CM7_3_STATUS,CM7 3 status"
|
|
bitfld.long 0x0 16. "TCMC_CM7_2_MS,Outstanding transactions from CM7 2." "0,1"
|
|
bitfld.long 0x0 12. "TCMC_AHB_MS,Refer CM7_0_STATUS description." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TCMC_EXT_MS_3,Refer CM7_0_STATUS description." "0,1"
|
|
bitfld.long 0x0 10. "TCMC_EXT_MS_2_TO_0,Refer CM7_0_STATUS description." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TCMC_CM7_1_MS,Outstanding transactions from CM7 1." "0,1"
|
|
bitfld.long 0x0 8. "TCMC_CM7_0_MS,Outstanding transactions from CM7 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PWR_DONE,After a PWR_MODE change this flag indicates if the new power mode has taken effect or not." "0,1"
|
|
bitfld.long 0x0 1. "SLEEPDEEP,Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SLEEPING,Specifies if the CPU is in Active Sleep or DeepSleep power mode:" "0,1"
|
|
group.long 0xC08++0x7
|
|
line.long 0x0 "FAST_3_CLOCK_CTL,Fast 3 clock control"
|
|
hexmask.long.byte 0x0 8.--15. 1. "INT_DIV,Refer FAST_0_CLOCK_CTL description."
|
|
hexmask.long.byte 0x0 3.--7. 1. "FRAC_DIV,Refer FAST_0_CLOCK_CTL description."
|
|
line.long 0x4 "CM7_3_CTL,CM7 3 control"
|
|
bitfld.long 0x4 31. "IDC_MASK,Refer CM7_0_CTL description." "0,1"
|
|
bitfld.long 0x4 28. "IXC_MASK,Refer CM7_0_CTL description." "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "UFC_MASK,Refer CM7_0_CTL description." "0,1"
|
|
bitfld.long 0x4 26. "OFC_MASK,Refer CM7_0_CTL description." "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "DZC_MASK,Refer CM7_0_CTL description." "0,1"
|
|
bitfld.long 0x4 24. "IOC_MASK,Refer CM7_0_CTL description." "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "TCMC_EN,Refer CM7_0_CTL description." "0,1"
|
|
bitfld.long 0x4 22. "DTCM_READ_WS,Refer CM7_0_CTL description." "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "DTCM_ECC_INJ_EN,Refer CM7_0_CTL description." "0,1"
|
|
bitfld.long 0x4 20. "DTCM_ECC_EN,Refer CM7_0_CTL description." "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "ITCM_ECC_CHECK_DIS,Disable ECC checking and thus fault reports. This also disables ECC correction (required to enable initialization). Intended usage is initialization. This bit is ignored when TCM_ECC_EN=0." "0,1"
|
|
bitfld.long 0x4 18. "ITCM_READ_WS,Refer CM7_0_CTL description." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "ITCM_ECC_INJ_EN,Refer CM7_0_CTL description." "0,1"
|
|
bitfld.long 0x4 16. "ITCM_ECC_EN,Refer CM7_0_CTL description." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "INIT_RMW_EN,Refer CM7_0_CTL description." "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "INIT_TCM_EN,Refer CM7_0_CTL description." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 4. "CPU_WAIT,Refer CM7_0_CTL description." "0,1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PPB_LOCK,Refer CM7_0_CTL description."
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0xD00)++0x3
|
|
line.long 0x0 "CM7_3_INT_STATUS[$1],CM7 3 interrupt status"
|
|
bitfld.long 0x0 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x0 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM7_3 activated system interrupt index for CPU interrupt 0."
|
|
repeat.end
|
|
group.long 0xE00++0x3
|
|
line.long 0x0 "CM7_3_VECTOR_TABLE_BASE,CM7 3 vector table base"
|
|
hexmask.long 0x0 7.--31. 1. "ADDR25,The default CM7 vector table base address is 0x0100:0000 (CM7 VTOR and reset exception handler address after reset). This is the location of the system ROM memory."
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xE40)++0x3
|
|
line.long 0x0 "CM7_3_NMI_CTL[$1],CM7 3 NMI control"
|
|
hexmask.long.word 0x0 0.--9. 1. "SYSTEM_INT_IDX,Refer CM7_0_NMI_CTL description."
|
|
repeat.end
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CM0_CTL,CM0+ control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x0 1. "ENABLED,Processor enable:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SLV_STALL,Processor debug access control:" "0,1"
|
|
rgroup.long 0x1004++0x3
|
|
line.long 0x0 "CM0_STATUS,CM0+ status"
|
|
bitfld.long 0x0 1. "SLEEPDEEP,Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field." "0,1"
|
|
bitfld.long 0x0 0. "SLEEPING,Specifies if the CPU is in Active Sleep or DeepSleep power mode:" "0,1"
|
|
group.long 0x1008++0xB
|
|
line.long 0x0 "SLOW_CLOCK_CTL,Slow clock control"
|
|
hexmask.long.byte 0x0 8.--15. 1. "INT_DIV,Specifies the slow clock divider (from the memory/AXI clock 'clk_mem' to the slow clock 'clk_slow'). Integer division by (1+INT_DIV). Allows for integer divisions in the range [1 256] (INT_DIV is in the range [0 255])."
|
|
line.long 0x4 "PERI_CLOCK_CTL,Peripheral interconnect clock control"
|
|
hexmask.long.byte 0x4 8.--15. 1. "INT_DIV,Integer division by (1+INT_DIV). Allows for integer divisions in the range [1 256] (INT_DIV is in the range [0 255])."
|
|
line.long 0x8 "MEM_CLOCK_CTL,Memory clock control"
|
|
hexmask.long.byte 0x8 8.--15. 1. "INT_DIV,Integer division by (1+INT_DIV). Allows for integer divisions in the range [1 256] (INT_DIV is in the range [0 255])."
|
|
rgroup.long 0x1100++0x1F
|
|
line.long 0x0 "CM0_INT0_STATUS,CM0+ interrupt 0 status"
|
|
bitfld.long 0x0 31. "SYSTEM_INT_VALID,Valid indication for SYSTEM_INT_IDX. When '0' no system interrupt for CPU interrupt 0 is valid/activated." "0,1"
|
|
hexmask.long.word 0x0 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 0."
|
|
line.long 0x4 "CM0_INT1_STATUS,CM0+ interrupt 1 status"
|
|
bitfld.long 0x4 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 1."
|
|
line.long 0x8 "CM0_INT2_STATUS,CM0+ interrupt 2 status"
|
|
bitfld.long 0x8 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x8 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 2."
|
|
line.long 0xC "CM0_INT3_STATUS,CM0+ interrupt 3 status"
|
|
bitfld.long 0xC 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0xC 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 3."
|
|
line.long 0x10 "CM0_INT4_STATUS,CM0+ interrupt 4 status"
|
|
bitfld.long 0x10 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x10 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 4."
|
|
line.long 0x14 "CM0_INT5_STATUS,CM0+ interrupt 5 status"
|
|
bitfld.long 0x14 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x14 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 5."
|
|
line.long 0x18 "CM0_INT6_STATUS,CM0+ interrupt 6 status"
|
|
bitfld.long 0x18 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x18 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 6."
|
|
line.long 0x1C "CM0_INT7_STATUS,CM0+ interrupt 7 status"
|
|
bitfld.long 0x1C 31. "SYSTEM_INT_VALID,See description of CM0_INT0_STATUS." "0,1"
|
|
hexmask.long.word 0x1C 0.--9. 1. "SYSTEM_INT_IDX,Lowest CM0+ activated system interrupt index for CPU interrupt 7."
|
|
group.long 0x1120++0x3
|
|
line.long 0x0 "CM0_VECTOR_TABLE_BASE,CM0+ vector table base"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR24,The default CM0+ vector table base address is 0x0000:0000 (CM0+ VTOR and reset exception handler address after reset). This is the location of the mirror system ROM memory."
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1140)++0x3
|
|
line.long 0x0 "CM0_NMI_CTL[$1],CM0+ NMI control"
|
|
hexmask.long.word 0x0 0.--9. 1. "SYSTEM_INT_IDX,System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset."
|
|
repeat.end
|
|
group.long 0x1200++0x7
|
|
line.long 0x0 "CM7_0_PWR_CTL,CM7 0 power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Power mode." "0: Switch CM7_0 off Power off clock off isolate..,1: Reset CM7_0 Clock off no isolated no retain and..,2: Put CM7_0 in Retained mode This can only become..,3: Switch CM7_0 on. Power on clock on no isolate no.."
|
|
line.long 0x4 "CM7_0_PWR_DELAY_CTL,CM7 0 power delay control"
|
|
hexmask.long.word 0x4 0.--9. 1. "UP,Number clock cycles delay needed after power domain power up"
|
|
group.long 0x1210++0x7
|
|
line.long 0x0 "CM7_1_PWR_CTL,CM7 1 power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,Refer CM7_0_PWR_CTL description."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Refer CM7_0_PWR_CTL description." "0: Refer CM7_0_PWR_CTL description.,1: Refer CM7_0_PWR_CTL description.,2: Refer CM7_0_PWR_CTL description.,3: Refer CM7_0_PWR_CTL description."
|
|
line.long 0x4 "CM7_1_PWR_DELAY_CTL,CM7 1 power delay control"
|
|
hexmask.long.word 0x4 0.--9. 1. "UP,Number clock cycles delay needed after power domain power up"
|
|
group.long 0x1220++0x7
|
|
line.long 0x0 "CM7_2_PWR_CTL,CM7 2 power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,Refer CM7_0_PWR_CTL description."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Refer CM7_0_PWR_CTL description." "0: Refer CM7_0_PWR_CTL description.,1: Refer CM7_0_PWR_CTL description.,2: Refer CM7_0_PWR_CTL description.,3: Refer CM7_0_PWR_CTL description."
|
|
line.long 0x4 "CM7_2_PWR_DELAY_CTL,CM7 2 power delay control"
|
|
hexmask.long.word 0x4 0.--9. 1. "UP,Number clock cycles delay needed after power domain power up"
|
|
group.long 0x1230++0x7
|
|
line.long 0x0 "CM7_3_PWR_CTL,CM7 3 power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,Refer CM7_0_PWR_CTL description."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Refer CM7_0_PWR_CTL description." "0: Refer CM7_0_PWR_CTL description.,1: Refer CM7_0_PWR_CTL description.,2: Refer CM7_0_PWR_CTL description.,3: Refer CM7_0_PWR_CTL description."
|
|
line.long 0x4 "CM7_3_PWR_DELAY_CTL,CM7 3 power delay control"
|
|
hexmask.long.word 0x4 0.--9. 1. "UP,Number clock cycles delay needed after power domain power up"
|
|
group.long 0x1300++0x3
|
|
line.long 0x0 "RAM0_CTL0,RAM 0 control"
|
|
bitfld.long 0x0 19. "ECC_CHECK_DIS,Disable ECC checking and thus fault reports. This also disables ECC correction (required to enable initialization). Intended usage is initialization. This bit is ignored when ECC_EN=0." "0,1"
|
|
bitfld.long 0x0 18. "ECC_INJ_EN,Enable ECC parity injection. Instead of calculating the parity from the write data to the RAM the parity is taken from ECC_CTL PARITY upon a match of ECC_CTL WORD_ADDR. The write data can be of any size. This bit is ignored when ECC_EN=0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ECC_AUTO_CORRECT,HW ECC autocorrect functionality:" "0,1"
|
|
bitfld.long 0x0 16. "ECC_EN,Enable ECC checking:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "FAST_WS,Memory wait states for the fast clock domain ('clk_fast_0/1') interface. The number of wait states is expressed in 'clk_mem' clock domain cycles." "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "SLOW_WS,Memory wait states for the slow clock domain ('clk_slow') intefrace. The number of wait states is expressed in 'clk_mem' clock domain cycles." "0,1,2,3"
|
|
rgroup.long 0x1304++0x3
|
|
line.long 0x0 "RAM0_STATUS,RAM 0 status"
|
|
bitfld.long 0x0 0. "WB_EMPTY,Write buffer empty. This information is used when entering DeepSleep power mode: WB_EMPTY must be '1' before a transition to system DeepSleep power mode." "0,1"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1340)++0x3
|
|
line.long 0x0 "RAM0_PWR_MACRO_CTL[$1],RAM 0 power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Power mode." "0: Turn OFF the SRAM. This will trun OFF both array..,1: undefined,2: Keep SRAM in Retained mode. This will turn OFF..,3: Enable SRAM for regular operation."
|
|
repeat.end
|
|
group.long 0x1380++0x3
|
|
line.long 0x0 "RAM1_CTL0,RAM 1 control"
|
|
bitfld.long 0x0 19. "ECC_CHECK_DIS,Disable ECC checking and thus fault reports. This also disables ECC correction (required to enable initialization). Intended usage is initialization. This bit is ignored when ECC_EN=0." "0,1"
|
|
bitfld.long 0x0 18. "ECC_INJ_EN,Enable ECC parity injection. Instead of calculating the parity from the write data to the RAM the parity is taken from ECC_CTL PARITY upon a match of ECC_CTL WORD_ADDR. The write data can be of any size. This bit is ignored when ECC_EN=0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ECC_AUTO_CORRECT,Refer RAM0_CTL0 descriotion." "0,1"
|
|
bitfld.long 0x0 16. "ECC_EN,Refer RAM0_CTL0 descriotion." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "FAST_WS,Refer RAM0_CTL0 descriotion." "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "SLOW_WS,Refer RAM0_CTL0 descriotion." "0,1,2,3"
|
|
rgroup.long 0x1384++0x3
|
|
line.long 0x0 "RAM1_STATUS,RAM 1 status"
|
|
bitfld.long 0x0 0. "WB_EMPTY,Refer RAM0_STATUS description." "0,1"
|
|
group.long 0x1388++0x3
|
|
line.long 0x0 "RAM1_PWR_CTL,RAM 1 power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,Refer RAM0_PWR_MACRO_CTL description."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Power mode." "0: Refer RAM0_PWR_MACRO_CTL description.,1: Undefined.,2: Refer RAM0_PWR_MACRO_CTL description.,3: Refer RAM0_PWR_MACRO_CTL description."
|
|
group.long 0x13A0++0x3
|
|
line.long 0x0 "RAM2_CTL0,RAM 2 control"
|
|
bitfld.long 0x0 19. "ECC_CHECK_DIS,Disable ECC checking and thus fault reports. This also disables ECC correction (required to enable initialization). Intended usage is initialization. This bit is ignored when ECC_EN=0." "0,1"
|
|
bitfld.long 0x0 18. "ECC_INJ_EN,Enable ECC parity injection. Instead of calculating the parity from the write data to the RAM the parity is taken from ECC_CTL PARITY upon a match of ECC_CTL WORD_ADDR. The write data can be of any size. This bit is ignored when ECC_EN=0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ECC_AUTO_CORRECT,Refer RAM0_CTL0 descriotion." "0,1"
|
|
bitfld.long 0x0 16. "ECC_EN,Refer RAM0_CTL0 descriotion." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "FAST_WS,Refer RAM0_CTL0 descriotion." "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "SLOW_WS,Refer RAM0_CTL0 descriotion." "0,1,2,3"
|
|
rgroup.long 0x13A4++0x3
|
|
line.long 0x0 "RAM2_STATUS,RAM 2 status"
|
|
bitfld.long 0x0 0. "WB_EMPTY,Refer RAM0_STATUS description." "0,1"
|
|
group.long 0x13A8++0x3
|
|
line.long 0x0 "RAM2_PWR_CTL,RAM 2 power control"
|
|
hexmask.long.word 0x0 16.--31. 1. "VECTKEYSTAT,Refer RAM0_PWR_MACRO_CTL description."
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Power mode." "0: Refer RAM0_PWR_MACRO_CTL description.,1: Undefined.,2: Refer RAM0_PWR_MACRO_CTL description.,3: Refer RAM0_PWR_MACRO_CTL description."
|
|
group.long 0x13C0++0xB
|
|
line.long 0x0 "RAM_PWR_DELAY_CTL,Power up delay used for all SRAM power domains"
|
|
hexmask.long.word 0x0 0.--9. 1. "UP,Number clock cycles delay needed after power domain power up"
|
|
line.long 0x4 "ROM_CTL,ROM control"
|
|
bitfld.long 0x4 8.--9. "FAST_WS,Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_mem' clock domain cycles." "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "SLOW_WS,Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_mem' clock domain cycles." "0,1,2,3"
|
|
line.long 0x8 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x8 24.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR. For the DTCM which has only 7 parity bits PARITY[6:0] is used as ECC parity."
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "WORD_ADDR,Specifies the word address where an error will be injected."
|
|
rgroup.long 0x1400++0x3
|
|
line.long 0x0 "PRODUCT_ID,Product identifier and version (same as CoreSight RomTables)"
|
|
hexmask.long.byte 0x0 20.--23. 1. "MINOR_REV,Minir Revision starts with 1 increments with metal layer only tape-out (implemented with metal ECO-able tie-off)"
|
|
hexmask.long.byte 0x0 16.--19. 1. "MAJOR_REV,Major Revision starts with 1 increments with all layer tape-out (implemented with metal ECO-able tie-off)"
|
|
newline
|
|
hexmask.long.word 0x0 0.--11. 1. "FAMILY_ID,Family ID. Common ID for a product family."
|
|
rgroup.long 0x1410++0x3
|
|
line.long 0x0 "DP_STATUS,Debug port status"
|
|
bitfld.long 0x0 2. "SWJ_JTAG_SEL,Specifies if the JTAG or SWD interface is selected. This signal is valid when DP_CTL.PTM_SEL is '0' (SWJ mode selected) and SWJ_CONNECTED is '1' (SWJ is connected)." "0,1"
|
|
bitfld.long 0x0 1. "SWJ_DEBUG_EN,Specifies if SWJ debug is enabled i.e. CDBGPWRUPACK is '1' and thus debug clocks are on:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWJ_CONNECTED,Specifies if the SWJ debug port is connected; i.e. debug host interface is active:" "0,1"
|
|
group.long 0x1414++0x3
|
|
line.long 0x0 "AP_CTL,Access port control"
|
|
bitfld.long 0x0 18. "SYS_DISABLE,Disables the system AP interface:" "0,1"
|
|
bitfld.long 0x0 17. "CM7_DISABLE,Disables the CM7_0 and CM7_1 and CM7_2 and CM7_3 AP interface:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CM0_DISABLE,Disables the CM0 AP interface:" "0,1"
|
|
bitfld.long 0x0 2. "SYS_ENABLE,Enables the system AP interface:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CM7_ENABLE,Enables the CM7_0 and CM7_1 and CM7_2 and CM7_3 AP interface:" "0,1"
|
|
bitfld.long 0x0 0. "CM0_ENABLE,Enables the CM0 AP interface:" "0,1"
|
|
group.long 0x1500++0x3
|
|
line.long 0x0 "BUFF_CTL,Buffer control"
|
|
bitfld.long 0x0 0. "WRITE_BUFF,Specifies if write transfer can be buffered in the bus infrastructure bridges:" "0,1"
|
|
group.long 0x1600++0x3
|
|
line.long 0x0 "SYSTICK_CTL,SysTick timer control"
|
|
bitfld.long 0x0 31. "NOREF,Specifies if an external clock source is provided:" "0,1"
|
|
bitfld.long 0x0 30. "SKEW,Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz). This affects the suitability of the SysTick timer as a SW real-time clock:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "CLOCK_SOURCE,Specifies an external clock source:" "0,1,2,3"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "TENMS,Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g. for a 32 768 Hz reference clock TENMS is 328 - 1 = 327."
|
|
rgroup.long 0x1704++0x3
|
|
line.long 0x0 "MBIST_STAT,Memory BIST status"
|
|
bitfld.long 0x0 1. "SFP_FAIL,Report status of the BIST run only valid if SFP_READY=1" "0,1"
|
|
bitfld.long 0x0 0. "SFP_READY,Flag indicating the BIST run is done. Note that after starting a BIST run this flag must be set before a new run can be started. For the first BIST run this will be 0." "0,1"
|
|
group.long 0x1800++0x7
|
|
line.long 0x0 "CAL_SUP_SET,Calibration support set and read"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Read without side effect write 1 to set"
|
|
line.long 0x4 "CAL_SUP_CLR,Calibration support clear and reset"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Read side effect: when read all bits are cleared write 1 to clear a specific bit"
|
|
group.long 0x2000++0x3
|
|
line.long 0x0 "CM0_PC_CTL,CM0+ protection context control"
|
|
hexmask.long.byte 0x0 0.--3. 1. "VALID,Valid fields for the protection context handler CM0_PCi_HANDLER registers:"
|
|
group.long 0x2040++0xF
|
|
line.long 0x0 "CM0_PC0_HANDLER,CM0+ protection context 0 handler"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Address of the protection context 0 handler. This field is used to detect entry to Cypress 'trusted' code through an exception/interrupt."
|
|
line.long 0x4 "CM0_PC1_HANDLER,CM0+ protection context 1 handler"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,Address of the protection context 1 handler."
|
|
line.long 0x8 "CM0_PC2_HANDLER,CM0+ protection context 2 handler"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,Address of the protection context 2 handler."
|
|
line.long 0xC "CM0_PC3_HANDLER,CM0+ protection context 3 handler"
|
|
hexmask.long 0xC 0.--31. 1. "ADDR,Address of the protection context 3 handler."
|
|
group.long 0x20C4++0x3
|
|
line.long 0x0 "PROTECTION,Protection status"
|
|
bitfld.long 0x0 0.--2. "STATE,Protection state:" "0: N/A,1: N/A,2: N/A,3: N/A,4: N/A,?,?,?"
|
|
group.long 0x2100++0xF
|
|
line.long 0x0 "TRIM_ROM_CTL,ROM trim control"
|
|
hexmask.long 0x0 0.--31. 1. "TRIM,N/A"
|
|
line.long 0x4 "TRIM_RAM_CTL,RAM trim control for less than 100MHz SRAMs"
|
|
hexmask.long 0x4 0.--31. 1. "TRIM,N/A"
|
|
line.long 0x8 "TRIM_RAM200_CTL,RAM trim control for 100MHz - 200MHz SRAMs"
|
|
hexmask.long 0x8 0.--31. 1. "TRIM,See TRIM_RAM_CTL for description."
|
|
line.long 0xC "TRIM_RAM350_CTL,RAM trim control for more than 200MHz SRAMs"
|
|
hexmask.long 0xC 0.--31. 1. "TRIM,See TRIM_RAM_CTL for description."
|
|
repeat 1023. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x8000)++0x3
|
|
line.long 0x0 "CM0_SYSTEM_INT_CTL[$1],CM0+ system interrupt control"
|
|
bitfld.long 0x0 31. "CPU_INT_VALID,Interrupt enable:" "0,1"
|
|
bitfld.long 0x0 0.--2. "CM0_CPU_INT_IDX,CPU interrupt index (legal range [0 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g. if CPU_INT_IDX is '6' the system interrupt is mapped to CPU interrupt '6'." "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
repeat 1023. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xA000)++0x3
|
|
line.long 0x0 "CM7_0_SYSTEM_INT_CTL[$1],CM7 0 system interrupt control"
|
|
bitfld.long 0x0 31. "CPU_INT_VALID,Interrupt enable:" "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CPU_INT_IDX,CPU interrupt index (legal range [0 15]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g. if CPU_INT_IDX is '6' the system interrupt is mapped to CPU interrupt '6'."
|
|
repeat.end
|
|
repeat 1023. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xC000)++0x3
|
|
line.long 0x0 "CM7_1_SYSTEM_INT_CTL[$1],CM7 1 system interrupt control"
|
|
bitfld.long 0x0 31. "CPU_INT_VALID,Refer CM7_0_SYSTEM_INT_CTL description." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CPU_INT_IDX,Refer CM7_0_SYSTEM_INT_CTL description."
|
|
repeat.end
|
|
repeat 1023. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xD000)++0x3
|
|
line.long 0x0 "CM7_2_SYSTEM_INT_CTL[$1],CM7 2 system interrupt control"
|
|
bitfld.long 0x0 31. "CPU_INT_VALID,Refer CM7_2_SYSTEM_INT_CTL description." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CPU_INT_IDX,Refer CM7_2_SYSTEM_INT_CTL description."
|
|
repeat.end
|
|
repeat 1023. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xE000)++0x3
|
|
line.long 0x0 "CM7_3_SYSTEM_INT_CTL[$1],CM7 3 system interrupt control"
|
|
bitfld.long 0x0 31. "CPU_INT_VALID,Refer CM7_3_SYSTEM_INT_CTL description." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CPU_INT_IDX,Refer CM7_3_SYSTEM_INT_CTL description."
|
|
repeat.end
|
|
tree.end
|
|
tree "CRYPTO (Cryptography Component)"
|
|
base ad:0x40100000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "ENABLED,IP enable:" "0: N/A,1: N/A"
|
|
bitfld.long 0x0 17. "ECC_INJ_EN,Enable parity injection for SRAM." "0,1"
|
|
bitfld.long 0x0 16. "ECC_EN,Enable ECC checking:" "0,1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
newline
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
group.long 0x8++0xB
|
|
line.long 0x0 "RAM_PWR_CTL,SRAM power control"
|
|
bitfld.long 0x0 0.--1. "PWR_MODE,Set power mode for memory buffer SRAM." "0: See CM4_PWR_CTL,1: undefined,2: See CM4_PWR_CTL,3: See CM4_PWR_CTL"
|
|
line.long 0x4 "RAM_PWR_DELAY_CTL,SRAM power delay control"
|
|
hexmask.long.word 0x4 0.--9. 1. "UP,Number clock cycles delay needed after power domain power up"
|
|
line.long 0x8 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x8 25.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR."
|
|
hexmask.long.word 0x8 0.--12. 1. "WORD_ADDR,Specifies the word address where the parity is injected."
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "ERROR_STATUS0,Error status 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Specifies error description information."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "ERROR_STATUS1,Error status 1"
|
|
bitfld.long 0x0 31. "VALID,Specifies if ERROR_STATUS0 and ERROR_STATUS1 specify valid error information. No new error information is captured as long as VALID is '1'; i.e. the error information of the first detected error is NOT overwritten." "0,1"
|
|
rbitfld.long 0x0 24.--26. "IDX,Error source:" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "DATA24,Specifies error description information."
|
|
group.long 0x100++0xB
|
|
line.long 0x0 "INTR,Interrupt register"
|
|
bitfld.long 0x0 21. "INSTR_DEV_KEY_ERROR,This interrupt cause is activated (HW sets the field to '1') when the LOAD_DEV_KEY instruction tries to load a device key whose DEV_KEY_ADDR_CTL.VALID or DEV_KEY_CTL.ALLOWED is set to '0'." "0,1"
|
|
bitfld.long 0x0 20. "TR_RC_DETECT_ERROR,This interrupt cause is activated (HW sets the field to '1') when the true random number generator monitor adaptive proportion test detects a disproportionate occurrence of a specific bit value." "0,1"
|
|
bitfld.long 0x0 19. "TR_AP_DETECT_ERROR,This interrupt cause is activated (HW sets the field to '1') when the true random number generator monitor adaptive proportion test detects a repetition of a specific bit value." "0,1"
|
|
bitfld.long 0x0 18. "BUS_ERROR,This interrupt cause is activated (HW sets the field to '1') when a AHB-Lite bus error is observed on the AHB-Lite master interface." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "INSTR_CC_ERROR,This interrupt cause is activated (HW sets the field to '1') when the instruction decoder encounters an instruction with a non-defined condition code. This error is only generated for VU instructions." "0,1"
|
|
bitfld.long 0x0 16. "INSTR_OPC_ERROR,This interrupt cause is activated (HW sets the field to '1') when the instruction decoder encounters an instruction with a non-defined operation code (opcode)." "0,1"
|
|
bitfld.long 0x0 4. "PR_DATA_AVAILABLE,This interrupt cause is activated (HW sets the field to '1') when the pseudo random number generator has generated a data value." "0,1"
|
|
bitfld.long 0x0 3. "TR_DATA_AVAILABLE,This interrupt cause is activated (HW sets the field to '1') when the true random number generator has generated a data value of the specified bit size." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TR_INITIALIZED,This interrupt cause is activated (HW sets the field to '1') when the true random number generator is initialized." "0,1"
|
|
bitfld.long 0x0 1. "INSTR_FF_OVERFLOW,This interrupt cause is activated (HW sets the field to '1') when the instruction FIFO overflows (an attempt is made to write to a full FIFO)." "0,1"
|
|
bitfld.long 0x0 0. "INSTR_FF_LEVEL,This interrupt cause is activated (HW sets the field to '1') when the instruction FIFO event is activated." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set register"
|
|
bitfld.long 0x4 21. "INSTR_DEV_KEY_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x4 20. "TR_RC_DETECT_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x4 19. "TR_AP_DETECT_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x4 18. "BUS_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "INSTR_CC_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x4 16. "INSTR_OPC_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x4 4. "PR_DATA_AVAILABLE,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x4 3. "TR_DATA_AVAILABLE,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TR_INITIALIZED,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x4 1. "INSTR_FF_OVERFLOW,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x4 0. "INSTR_FF_LEVEL,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x8 21. "INSTR_DEV_KEY_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x8 20. "TR_RC_DETECT_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x8 19. "TR_AP_DETECT_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x8 18. "BUS_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "INSTR_CC_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x8 16. "INSTR_OPC_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x8 4. "PR_DATA_AVAILABLE,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x8 3. "TR_DATA_AVAILABLE,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "TR_INITIALIZED,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x8 1. "INSTR_FF_OVERFLOW,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
bitfld.long 0x8 0. "INSTR_FF_LEVEL,Mask bit for corresponding field in interrupt request register." "0,1"
|
|
rgroup.long 0x10C++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked register"
|
|
bitfld.long 0x0 21. "INSTR_DEV_KEY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 20. "TR_RC_DETECT_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 19. "TR_AP_DETECT_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 18. "BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "INSTR_CC_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 16. "INSTR_OPC_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 4. "PR_DATA_AVAILABLE,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 3. "TR_DATA_AVAILABLE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TR_INITIALIZED,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 1. "INSTR_FF_OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 0. "INSTR_FF_LEVEL,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0x200++0x13
|
|
line.long 0x0 "PR_LFSR_CTL0,Pseudo random LFSR control 0"
|
|
hexmask.long 0x0 0.--31. 1. "LFSR32,State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to generate a pseudo random bit sequence. This register needs to be initialized by SW. The initialization value should be different from '0'."
|
|
line.long 0x4 "PR_LFSR_CTL1,Pseudo random LFSR control 1"
|
|
hexmask.long 0x4 0.--30. 1. "LFSR31,State of a 31-bit Linear Feedback Shift Registers (LFSR) that is used to generate a pseudo random bit sequence. See PR_LFSR_CTL0."
|
|
line.long 0x8 "PR_LFSR_CTL2,Pseudo random LFSR control 2"
|
|
hexmask.long 0x8 0.--28. 1. "LFSR29,State of a 29-bit Linear Feedback Shift Registers (LFSR) that is used to generate a pseudo random bit sequence. See PR_LFSR_CTL0."
|
|
line.long 0xC "PR_MAX_CTL,Pseudo random maximum control"
|
|
hexmask.long 0xC 0.--31. 1. "DATA32,Maximum value of to be generated random number"
|
|
line.long 0x10 "PR_CMD,Pseudo random command"
|
|
bitfld.long 0x10 0. "START,Pseudo random command. On a generated number HW sets this field to '0' and sets INTR.PR_DATA_AVAILABLE to '1." "0,1"
|
|
group.long 0x218++0x3
|
|
line.long 0x0 "PR_RESULT,Pseudo random result"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Result of a pseudo random number generation operation. The resulting value DATA is in the range [0 PR_MAX_CTL.DATA32]. The PR_DATA_AVAILABLE interrupt cause is activated when the number is generated."
|
|
group.long 0x280++0xB
|
|
line.long 0x0 "TR_CTL0,True random control 0"
|
|
bitfld.long 0x0 29. "STOP_ON_RC_DETECT,Specifies if TRNG functionality is stopped on a repetition count test detection (when HW sets INTR.TR_RC_DETECT to '1'):" "0,1"
|
|
bitfld.long 0x0 28. "STOP_ON_AP_DETECT,Specifies if TRNG functionality is stopped on an adaptive proportion test detection (when HW sets INTR.TR_AP_DETECT to '1'):" "0,1"
|
|
bitfld.long 0x0 24. "VON_NEUMANN_CORR,Specifies if the 'von Neumann corrector' is disabled or enabled:" "0,1"
|
|
hexmask.long.byte 0x0 16.--23. 1. "INIT_DELAY,Specifies an initialization delay: number of removed/dropped samples before reduced bits are generated. This field should be programmed in the range [1 255]. After starting the oscillators at least the first 2 samples should be.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RED_CLOCK_DIV,Specifies the clock divider that is used to produce reduced bits."
|
|
hexmask.long.byte 0x0 0.--7. 1. "SAMPLE_CLOCK_DIV,Specifies the clock divider that is used to sample oscillator data. This clock divider is wrt. 'clk_sys'."
|
|
line.long 0x4 "TR_CTL1,True random control 1"
|
|
bitfld.long 0x4 5. "FIRO31_EN,FW sets this field to '1' to enable the programmable Fibonacci ring oscillator with up to 31 inverters. The TR_FIRO_CTL register specifies the programmable polynomial." "0,1"
|
|
bitfld.long 0x4 4. "FIRO15_EN,FW sets this field to '1' to enable the fixed Fibonacci ring oscillator with 15 inverters." "0,1"
|
|
bitfld.long 0x4 3. "GARO31_EN,FW sets this field to '1' to enable the programmable Galois ring oscillator with up to 31 inverters. The TR_GARO_CTL register specifies the programmable polynomial." "0,1"
|
|
bitfld.long 0x4 2. "GARO15_EN,FW sets this field to '1' to enable the fixed Galois ring oscillator with 15 inverters." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RO15_EN,FW sets this field to '1' to enable the ring oscillator with 15 inverters." "0,1"
|
|
bitfld.long 0x4 0. "RO11_EN,FW sets this field to '1' to enable the ring oscillator with 11 inverters." "0,1"
|
|
line.long 0x8 "TR_CTL2,True random control 2"
|
|
hexmask.long.byte 0x8 0.--5. 1. "SIZE,Bit size of generated random number in TR_RESULT. Legal range is in [0 32]."
|
|
rgroup.long 0x28C++0x3
|
|
line.long 0x0 "TR_STATUS,True random status"
|
|
bitfld.long 0x0 0. "INITIALIZED,Reflects the state of the true random number generator:" "0,1"
|
|
group.long 0x290++0x3
|
|
line.long 0x0 "TR_CMD,True random command"
|
|
bitfld.long 0x0 0. "START,True random command. On completion of the command HW sets this field to '0' and sets INTR.TR_DATA_AVAILABLE to '1 when:" "0,1"
|
|
group.long 0x298++0x3
|
|
line.long 0x0 "TR_RESULT,True random result"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Generated true random number. HW generates the number in the least significant bit positions (TR_CTL2.SIZE) of this field. The TR_DATA_AVAILABLE interrupt cause is activated when the number is generated."
|
|
group.long 0x2A0++0x7
|
|
line.long 0x0 "TR_GARO_CTL,True random GARO control"
|
|
hexmask.long 0x0 0.--30. 1. "POLYNOMIAL31,Polynomial for programmable Galois ring oscillator. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned such that the more significant bits (bit 30 and down) contain the.."
|
|
line.long 0x4 "TR_FIRO_CTL,True random FIRO control"
|
|
hexmask.long 0x4 0.--30. 1. "POLYNOMIAL31,Polynomial for programmable Fibonacci ring oscillator. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned such that the more significant bits (bit 30 and down) contain.."
|
|
group.long 0x2C0++0x3
|
|
line.long 0x0 "TR_MON_CTL,True random monitor control"
|
|
bitfld.long 0x0 0.--1. "BITSTREAM_SEL,Selection of the bitstream:" "0,1,2,3"
|
|
group.long 0x2C8++0x3
|
|
line.long 0x0 "TR_MON_CMD,True random monitor command"
|
|
bitfld.long 0x0 1. "START_RC,Repetition count (RC) test enable:" "0,1"
|
|
bitfld.long 0x0 0. "START_AP,Adaptive proportion (AP) test enable:" "0,1"
|
|
group.long 0x2D0++0x3
|
|
line.long 0x0 "TR_MON_RC_CTL,True random monitor RC control"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CUTOFF_COUNT8,Cutoff count (legal range is [1 255]):"
|
|
rgroup.long 0x2D8++0x7
|
|
line.long 0x0 "TR_MON_RC_STATUS0,True random monitor RC status 0"
|
|
bitfld.long 0x0 0. "BIT,Current active bit value:" "0,1"
|
|
line.long 0x4 "TR_MON_RC_STATUS1,True random monitor RC status 1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "REP_COUNT,Number of repetitions of the current active bit counter:"
|
|
group.long 0x2E0++0x3
|
|
line.long 0x0 "TR_MON_AP_CTL,True random monitor AP control"
|
|
hexmask.long.word 0x0 16.--31. 1. "WINDOW_SIZE,Window size (minus 1) :"
|
|
hexmask.long.word 0x0 0.--15. 1. "CUTOFF_COUNT16,Cutoff count (legal range is [1 65535])."
|
|
rgroup.long 0x2E8++0x7
|
|
line.long 0x0 "TR_MON_AP_STATUS0,True random monitor AP status 0"
|
|
bitfld.long 0x0 0. "BIT,Current active bit value:" "0,1"
|
|
line.long 0x4 "TR_MON_AP_STATUS1,True random monitor AP status 1"
|
|
hexmask.long.word 0x4 16.--31. 1. "WINDOW_INDEX,Counter to keep track of the current index in the window (counts from '0' to TR_MON_AP_CTL.WINDOW_SIZE to '0')."
|
|
hexmask.long.word 0x4 0.--15. 1. "OCC_COUNT,Number of occurrences of the current active bit counter:"
|
|
rgroup.long 0x1004++0x3
|
|
line.long 0x0 "STATUS,Status"
|
|
bitfld.long 0x0 31. "BUSY,Reflects the state of the IP:" "0,1"
|
|
group.long 0x1040++0x3
|
|
line.long 0x0 "INSTR_FF_CTL,Instruction FIFO control"
|
|
bitfld.long 0x0 17. "BLOCK,This field specifies the behavior when an instruction is written to a full FIFO (INSTR_FIFO_WR MMIO register):" "0,1"
|
|
bitfld.long 0x0 16. "CLEAR,When '1' the instruction FIFO is cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is.." "0,1"
|
|
bitfld.long 0x0 0.--2. "EVENT_LEVEL,Event level. When the number of entries in the instruction FIFO is less than the amount of this field an event is generated:" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x1044++0x3
|
|
line.long 0x0 "INSTR_FF_STATUS,Instruction FIFO status"
|
|
bitfld.long 0x0 16. "EVENT,Instruction FIFO event." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "USED,Number of instructions in the instruction FIFO. The value of this field ranges from 0 to 8."
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "INSTR_FF_WR,Instruction FIFO write"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Instruction or instruction operand data that is written to the instruction FIFO."
|
|
rgroup.long 0x10C0++0x3
|
|
line.long 0x0 "LOAD0_FF_STATUS,Load 0 FIFO status"
|
|
bitfld.long 0x0 31. "BUSY,Reflects the state of the FIFO:" "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "USED5,Number of Bytes in the FIFO. The value of this field is in the range [0 19]."
|
|
rgroup.long 0x10D0++0x3
|
|
line.long 0x0 "LOAD1_FF_STATUS,Load 1 FIFO status"
|
|
bitfld.long 0x0 31. "BUSY,See LOAD1_FF_STATUS.BUSY." "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "USED5,See LOAD1_FF_STATUS.USED."
|
|
rgroup.long 0x10F0++0x3
|
|
line.long 0x0 "STORE_FF_STATUS,Store FIFO status"
|
|
bitfld.long 0x0 31. "BUSY,Reflects the state of the FIFO:" "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "USED5,Number of Bytes in the FIFO. The value of this field is in the range [0 16]."
|
|
group.long 0x1100++0x3
|
|
line.long 0x0 "AES_CTL,AES control"
|
|
bitfld.long 0x0 0.--1. "KEY_SIZE,AES key size:" "0: N/A,1: N/A,2: N/A,?"
|
|
group.long 0x1180++0x3
|
|
line.long 0x0 "RESULT,Result"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,BLOCK_CMP operation (DATA[0]):"
|
|
group.long 0x1400++0x3
|
|
line.long 0x0 "CRC_CTL,CRC control"
|
|
bitfld.long 0x0 8. "REM_REVERSE,Specifies whether the remainder is bit reversed (reversal is performed after XORing):" "0,1"
|
|
bitfld.long 0x0 0. "DATA_REVERSE,Specifies the bit order in which a data Byte is processed (reversal is performed after XORing):" "0,1"
|
|
group.long 0x1410++0x3
|
|
line.long 0x0 "CRC_DATA_CTL,CRC data control"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA_XOR,Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal."
|
|
group.long 0x1420++0x3
|
|
line.long 0x0 "CRC_POL_CTL,CRC polynomial control"
|
|
hexmask.long 0x0 0.--31. 1. "POLYNOMIAL,CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less.."
|
|
group.long 0x1440++0x3
|
|
line.long 0x0 "CRC_REM_CTL,CRC remainder control"
|
|
hexmask.long 0x0 0.--31. 1. "REM_XOR,Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal."
|
|
rgroup.long 0x1448++0x3
|
|
line.long 0x0 "CRC_REM_RESULT,CRC remainder result"
|
|
hexmask.long 0x0 0.--31. 1. "REM,Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE:"
|
|
group.long 0x1480++0xB
|
|
line.long 0x0 "VU_CTL0,Vector unit control 0"
|
|
bitfld.long 0x0 0. "ALWAYS_EXECUTE,Specifies if a conditional instruction is executed or not when its condition code evaluates to false/'0'." "0,1"
|
|
line.long 0x4 "VU_CTL1,Vector unit control 1"
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "ADDR24,Specifies the memory address for the vector unit operand memory region. The register-file registers provide 13-bit word offsets within this memory region. Given ADDR[31:8] VU_VTL2.MASK[14:8] and a 13-bit word offset offset[14:2] a vector operand.."
|
|
line.long 0x8 "VU_CTL2,Vector unit control 2"
|
|
hexmask.long.byte 0x8 8.--14. 1. "MASK,Specifies the size of the vector operand memory region. Legal values:"
|
|
rgroup.long 0x1490++0x3
|
|
line.long 0x0 "VU_STATUS,Vector unit status"
|
|
bitfld.long 0x0 3. "ONE,STATUS ONE field." "0,1"
|
|
bitfld.long 0x0 2. "ZERO,STATUS ZERO field." "0,1"
|
|
bitfld.long 0x0 1. "EVEN,STATUS EVEN field." "0,1"
|
|
bitfld.long 0x0 0. "CARRY,STATUS CARRY field." "0,1"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x14C0)++0x3
|
|
line.long 0x0 "VU_RF_DATA[$1],Vector unit register-file"
|
|
hexmask.long 0x0 0.--31. 1. "DATA32,Vector unit register-file data. A register-file register has the following layout:"
|
|
repeat.end
|
|
group.long 0x2000++0x7
|
|
line.long 0x0 "DEV_KEY_ADDR0_CTL,Device key address 0 control"
|
|
bitfld.long 0x0 31. "VALID,Specifies if the address in the associated DEV_KEY_ADDR0 is valid:" "0,1"
|
|
line.long 0x4 "DEV_KEY_ADDR0,Device key address 0"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR32,Specifies the memory address of the device key in memory. A LOAD_DEV_KEY instruction uses this address to load a device key from memory into the IP register buffer blocks 4 and 5."
|
|
group.long 0x2020++0x7
|
|
line.long 0x0 "DEV_KEY_ADDR1_CTL,Device key address 1 control"
|
|
bitfld.long 0x0 31. "VALID,See DEV_KEY_ADDR0_CTL." "0,1"
|
|
line.long 0x4 "DEV_KEY_ADDR1,Device key address 1 control"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR32,See DEV_KEY_ADDR0."
|
|
rgroup.long 0x2080++0x3
|
|
line.long 0x0 "DEV_KEY_STATUS,Device key status"
|
|
bitfld.long 0x0 0. "LOADED,Specifies if a device key is present in the IP register buffer blocks 4 and 5." "0,1"
|
|
group.long 0x2100++0x3
|
|
line.long 0x0 "DEV_KEY_CTL0,Device key control 0"
|
|
bitfld.long 0x0 0. "ALLOWED,Specifies if a LOAD_DEV_KEY instruction is allowed to use the device key in memory:" "0,1"
|
|
group.long 0x2120++0x3
|
|
line.long 0x0 "DEV_KEY_CTL1,Device key control 1"
|
|
bitfld.long 0x0 0. "ALLOWED,See DEV_KEY_CTL0." "0,1"
|
|
tree.end
|
|
tree "DMAC (Direct Memory Access Controller)"
|
|
base ad:0x402A0000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "ENABLED,IP enable:" "0: N/A,1: N/A"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "ACTIVE,Active channels"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ACTIVE,Specifies active channels; i.e. enabled channels whose trigger got activated."
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x402A1000 ad:0x402A1100 ad:0x402A1200 ad:0x402A1300 ad:0x402A1400 ad:0x402A1500 ad:0x402A1600 ad:0x402A1700)
|
|
tree "CH[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x10)++0xB
|
|
line.long 0x0 "IDX,Channel current indices"
|
|
hexmask.long.word 0x0 16.--31. 1. "Y,Specifies the Y loop index with Y_COUNT taken from the current descriptor."
|
|
hexmask.long.word 0x0 0.--15. 1. "X,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "SRC,Channel current source address"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,Current address of source location."
|
|
line.long 0x8 "DST,Channel current destination address"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,Current address of destination location."
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "CURR,Channel current descriptor pointer"
|
|
hexmask.long 0x0 2.--31. 1. "PTR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
group.long ($2+0x28)++0x3
|
|
line.long 0x0 "TR_CMD,Channle software trigger"
|
|
bitfld.long 0x0 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
rgroup.long ($2+0x40)++0x3
|
|
line.long 0x0 "DESCR_STATUS,Channel descriptor status"
|
|
bitfld.long 0x0 31. "VALID,Indicates whether the descriptor information present in DESCR_CTL DESCR_SRC DESCR_DST DESCR_X_SIZE DESCR_X_INCR DESCR_Y_SIZE DESCR_Y_INCR DESCR_NEXT status registers is valid or not." "0,1"
|
|
rgroup.long ($2+0x60)++0x1F
|
|
line.long 0x0 "DESCR_CTL,Channel descriptor control"
|
|
bitfld.long 0x0 28.--30. "DESCR_TYPE,Specifies the descriptor type (not to be confused with the trigger type):" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 27. "DST_TRANSFER_SIZE,Specifies the bus transfer size to the destination location:" "0,1"
|
|
bitfld.long 0x0 26. "SRC_TRANSFER_SIZE,Specifies the bus transfer size to the source location:" "0,1"
|
|
bitfld.long 0x0 24. "CH_DISABLE,Specifies whether the channel is disabled or not after completion of the current descriptor (independent of the value of the DESCR_NEXT_PTR value):" "0,1"
|
|
bitfld.long 0x0 16.--17. "DATA_SIZE,Specifies the data element size:" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8. "DATA_PREFETCH,Source data prefetch:" "0,1"
|
|
bitfld.long 0x0 6.--7. "TR_IN_TYPE,Specifies the input trigger type (not to be confused with the descriptor type):" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "TR_OUT_TYPE,Specifies when an output trigger is generated:" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "INTR_TYPE,Specifies when a completion interrupt is generated (CH_STATUS.INTR_CAUSE is set to COMPLETION):" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "WAIT_FOR_DEACT,Specifies whether the controller should wait for the input trigger to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller with the agent that generated the trigger. This field is.." "0,1,2,3"
|
|
line.long 0x4 "DESCR_SRC,Channel descriptor source"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,Base address of source location."
|
|
line.long 0x8 "DESCR_DST,Channel descriptor destination"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,Base address of destination location."
|
|
line.long 0xC "DESCR_X_SIZE,Channel descriptor X size"
|
|
hexmask.long.word 0xC 0.--15. 1. "X_COUNT,Number of iterations (minus 1) of the 'X loop' (X_COUNT+1 is the number of single transfers in a 1D transfer). This field is an unsigned number in the range [0 65535] representing 1 through 65536 iterations."
|
|
line.long 0x10 "DESCR_X_INCR,Channel descriptor X increment"
|
|
hexmask.long.word 0x10 16.--31. 1. "DST_X,Specifies increment of destination address for each X loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number (sign-magnitude format) in the range [-32768 32767]. If this field is '0' the destination address is not.."
|
|
hexmask.long.word 0x10 0.--15. 1. "SRC_X,Specifies increment of source address for each X loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number (sign-magnitude format) in the range [-32768 32767]. If this field is '0' the source address is not incremented."
|
|
line.long 0x14 "DESCR_Y_SIZE,Channel descriptor Y size"
|
|
hexmask.long.word 0x14 0.--15. 1. "Y_COUNT,Number of iterations (minus 1) of the 'Y loop' (X_COUNT+1)*(Y_COUNT+1) is the number of single transfers in a 2D transfer). This field is an unsigned number in the range [0 65535] representing 1 through 65536 iterations."
|
|
line.long 0x18 "DESCR_Y_INCR,Channel descriptor Y increment"
|
|
hexmask.long.word 0x18 16.--31. 1. "DST_Y,Specifies increment of destination address for each Y loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-32768 32767]."
|
|
hexmask.long.word 0x18 0.--15. 1. "SRC_Y,Specifies increment of source address for each Y loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-32768 32767]."
|
|
line.long 0x1C "DESCR_NEXT,Channel descriptor next pointer"
|
|
hexmask.long 0x1C 2.--31. 1. "PTR,Address of next descriptor in descriptor list. When this field is '0' this is the last descriptor in the descriptor list."
|
|
group.long ($2+0x80)++0xB
|
|
line.long 0x0 "INTR,Interrupt"
|
|
bitfld.long 0x0 7. "DESCR_BUS_ERROR,Activated (set to '1') on a bus error for a load of the descriptor." "0,1"
|
|
bitfld.long 0x0 6. "ACTIVE_CH_DISABLED,Activated (set to '1') if the channel is disabled by SW (accidentally/incorrectly) when the data transfer engine is busy." "0,1"
|
|
bitfld.long 0x0 5. "CURR_PTR_NULL,Activated (set to '1') when the channel is enabled (CH_CTL.ENABLED is '1') and CH_CURR_PTR is '0'." "0,1"
|
|
bitfld.long 0x0 4. "DST_MISAL,Activated (set to '1') on a misalignment of the destination address." "0,1"
|
|
bitfld.long 0x0 3. "SRC_MISAL,Activated (set to '1') on a misalignment of the source address." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DST_BUS_ERROR,Activated (set to '1') on a bus error for a store to the destination." "0,1"
|
|
bitfld.long 0x0 1. "SRC_BUS_ERROR,Activated (set to '1') on a bus error for a load from the source." "0,1"
|
|
bitfld.long 0x0 0. "COMPLETION,Activated (set to '1') on completion of data transfer(s) as specified by the descriptor's CH_DESCR_CTL.INTR_TYPE." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set"
|
|
bitfld.long 0x4 7. "DESCR_BUS_ERROR,Write this field with '1' to set INTR.DESCR_BUS_ERROR field to '1' (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 6. "ACTIVE_CH_DISABLED,Write this field with '1' to set INTR.ACT_CH_DISABLED field to '1' (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 5. "CURR_PTR_NULL,Write this field with '1' to set INTR.CURR_PTR_NULL field to '1' (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 4. "DST_MISAL,Write this field with '1' to set INTR.DST_MISAL field to '1' (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 3. "SRC_MISAL,Write this field with '1' to set INTR.SRC_MISAL field to '1' (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DST_BUS_ERROR,Write this field with '1' to set INTR.DST_BUS_ERROR field to '1' (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 1. "SRC_BUS_ERROR,Write this field with '1' to set INTR.SRC_BUS_ERROR field to '1' (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 0. "COMPLETION,Write this field with '1' to set INTR.COMPLETION field to '1' (a write of '0' has no effect)." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x8 7. "DESCR_BUS_ERROR,Mask for INTR.DESCR_BUS_ERROR interrupt." "0,1"
|
|
bitfld.long 0x8 6. "ACTIVE_CH_DISABLED,Mask for INTR.ACTIVE_CH_DISABLED interrupt." "0,1"
|
|
bitfld.long 0x8 5. "CURR_PTR_NULL,Mask for INTR.CURR_PTR_NULL interrupt." "0,1"
|
|
bitfld.long 0x8 4. "DST_MISAL,Mask for INTR.DST_MISAL interrupt." "0,1"
|
|
bitfld.long 0x8 3. "SRC_MISAL,Mask for INTR.SRC_MISAL interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "DST_BUS_ERROR,Mask for INTR.DST_BUS_ERROR interrupt." "0,1"
|
|
bitfld.long 0x8 1. "SRC_BUS_ERROR,Mask for INTR.SRC_BUS_ERROR interrupt." "0,1"
|
|
bitfld.long 0x8 0. "COMPLETION,Mask for INTR.COMPLETION interrupt." "0,1"
|
|
rgroup.long ($2+0x8C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 7. "DESCR_BUS_ERROR,Logical and of corresponding INTR.DESCR_BUS_ERROR and INTR_MASK.DESCR_BUS_ERROR fields." "0,1"
|
|
bitfld.long 0x0 6. "ACTIVE_CH_DISABLED,Logical and of corresponding INTR.ACTIVE_CH_DISABLED and INTR_MASK.ACTIVE_CH_DISABLED fields." "0,1"
|
|
bitfld.long 0x0 5. "CURR_PTR_NULL,Logical and of corresponding INTR.CURR_PTR_NULL and INTR_MASK.CURR_PTR_NULL fields." "0,1"
|
|
bitfld.long 0x0 4. "DST_MISAL,Logical and of corresponding INTR.DST_MISAL and INTR_MASK.DST_MISAL fields." "0,1"
|
|
bitfld.long 0x0 3. "SRC_MISAL,Logical and of corresponding INTR.SRC_MISAL and INTR_MASK.SRC_MISAL fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DST_BUS_ERROR,Logical and of corresponding INTR.DST_BUS_ERROR and INTR_MASK.DST_BUS_ERROR fields." "0,1"
|
|
bitfld.long 0x0 1. "SRC_BUS_ERROR,Logical and of corresponding INTR.SRC_BUS_ERROR and INTR_MASK.SRC_BUS_ERROR fields." "0,1"
|
|
bitfld.long 0x0 0. "COMPLETION,Logical and of corresponding INTR.COMPLETION and INTR_MASK.COMPLETION fields." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "DW (Datawire Controller)"
|
|
base ad:0x0
|
|
tree "DW0"
|
|
base ad:0x40280000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "ENABLED,IP enable:" "0,1"
|
|
bitfld.long 0x0 1. "ECC_INJ_EN,Enable parity injection for SRAM." "0,1"
|
|
bitfld.long 0x0 0. "ECC_EN,Enable ECC checking:" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Status"
|
|
bitfld.long 0x0 31. "ACTIVE,Active channel present:" "0,1"
|
|
bitfld.long 0x0 28.--30. "STATE,State of the DW controller." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 16.--24. 1. "CH_IDX,Active channel index."
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Active channel preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Active channel priority." "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Active channel protection context."
|
|
newline
|
|
bitfld.long 0x0 2. "B,Active channel non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Active channel secure/non-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,Active channel user/privileged access control:" "0,1"
|
|
rgroup.long 0x20++0xB
|
|
line.long 0x0 "ACT_DESCR_CTL,Active descriptor control"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "ACT_DESCR_SRC,Active descriptor source"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Copy of DESCR_SRC of the currently active descriptor."
|
|
line.long 0x8 "ACT_DESCR_DST,Active descriptor destination"
|
|
hexmask.long 0x8 0.--31. 1. "DATA,Copy of DESCR_DST of the currently active descriptor."
|
|
rgroup.long 0x30++0xB
|
|
line.long 0x0 "ACT_DESCR_X_CTL,Active descriptor X loop control"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Copy of DESCR_X_CTL of the currently active descriptor."
|
|
line.long 0x4 "ACT_DESCR_Y_CTL,Active descriptor Y loop control"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Copy of DESCR_Y_CTL of the currently active descriptor."
|
|
line.long 0x8 "ACT_DESCR_NEXT_PTR,Active descriptor next pointer"
|
|
hexmask.long 0x8 2.--31. 1. "ADDR,Copy of DESCR_NEXT_PTR of the currently active descriptor."
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x0 "ACT_SRC,Active source"
|
|
hexmask.long 0x0 0.--31. 1. "SRC_ADDR,Current address of source location."
|
|
line.long 0x4 "ACT_DST,Active destination"
|
|
hexmask.long 0x4 0.--31. 1. "DST_ADDR,Current address of destination location."
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x0 25.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR."
|
|
hexmask.long.word 0x0 0.--9. 1. "WORD_ADDR,Specifies the word address where an error will be injected."
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "CRC_CTL,CRC control"
|
|
bitfld.long 0x0 8. "REM_REVERSE,Specifies whether the remainder is bit reversed (reversal is performed after XORing):" "0,1"
|
|
bitfld.long 0x0 0. "DATA_REVERSE,Specifies the bit order in which a data Byte is processed (reversal is performed after XORing):" "0,1"
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "CRC_DATA_CTL,CRC data control"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA_XOR,Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal."
|
|
group.long 0x120++0x3
|
|
line.long 0x0 "CRC_POL_CTL,CRC polynomial control"
|
|
hexmask.long 0x0 0.--31. 1. "POLYNOMIAL,CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less.."
|
|
group.long 0x130++0x3
|
|
line.long 0x0 "CRC_LFSR_CTL,CRC LFSR control"
|
|
hexmask.long 0x0 0.--31. 1. "LFSR32,State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC. This register needs to be initialized by SW to provide the CRC seed value."
|
|
group.long 0x140++0x3
|
|
line.long 0x0 "CRC_REM_CTL,CRC remainder control"
|
|
hexmask.long 0x0 0.--31. 1. "REM_XOR,Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal."
|
|
rgroup.long 0x148++0x3
|
|
line.long 0x0 "CRC_REM_RESULT,CRC remainder result"
|
|
hexmask.long 0x0 0.--31. 1. "REM,Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE:"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40288000 ad:0x40288040 ad:0x40288080 ad:0x402880C0 ad:0x40288100 ad:0x40288140 ad:0x40288180 ad:0x402881C0 ad:0x40288200 ad:0x40288240 ad:0x40288280 ad:0x402882C0 ad:0x40288300 ad:0x40288340 ad:0x40288380 ad:0x402883C0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x40288400 ad:0x40288440 ad:0x40288480 ad:0x402884C0 ad:0x40288500 ad:0x40288540 ad:0x40288580 ad:0x402885C0 ad:0x40288600 ad:0x40288640 ad:0x40288680 ad:0x402886C0 ad:0x40288700 ad:0x40288740 ad:0x40288780 ad:0x402887C0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F)(list ad:0x40288800 ad:0x40288840 ad:0x40288880 ad:0x402888C0 ad:0x40288900 ad:0x40288940 ad:0x40288980 ad:0x402889C0 ad:0x40288A00 ad:0x40288A40 ad:0x40288A80 ad:0x40288AC0 ad:0x40288B00 ad:0x40288B40 ad:0x40288B80 ad:0x40288BC0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F)(list ad:0x40288C00 ad:0x40288C40 ad:0x40288C80 ad:0x40288CC0 ad:0x40288D00 ad:0x40288D40 ad:0x40288D80 ad:0x40288DC0 ad:0x40288E00 ad:0x40288E40 ad:0x40288E80 ad:0x40288EC0 ad:0x40288F00 ad:0x40288F40 ad:0x40288F80 ad:0x40288FC0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F)(list ad:0x40289000 ad:0x40289040 ad:0x40289080 ad:0x402890C0 ad:0x40289100 ad:0x40289140 ad:0x40289180 ad:0x402891C0 ad:0x40289200 ad:0x40289240 ad:0x40289280 ad:0x402892C0 ad:0x40289300 ad:0x40289340 ad:0x40289380 ad:0x402893C0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F)(list ad:0x40289400 ad:0x40289440 ad:0x40289480 ad:0x402894C0 ad:0x40289500 ad:0x40289540 ad:0x40289580 ad:0x402895C0 ad:0x40289600 ad:0x40289640 ad:0x40289680 ad:0x402896C0 ad:0x40289700 ad:0x40289740 ad:0x40289780 ad:0x402897C0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F)(list ad:0x40289800 ad:0x40289840 ad:0x40289880 ad:0x402898C0 ad:0x40289900 ad:0x40289940 ad:0x40289980 ad:0x402899C0 ad:0x40289A00 ad:0x40289A40 ad:0x40289A80 ad:0x40289AC0 ad:0x40289B00 ad:0x40289B40 ad:0x40289B80 ad:0x40289BC0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F)(list ad:0x40289C00 ad:0x40289C40 ad:0x40289C80 ad:0x40289CC0 ad:0x40289D00 ad:0x40289D40 ad:0x40289D80 ad:0x40289DC0 ad:0x40289E00 ad:0x40289E40 ad:0x40289E80 ad:0x40289EC0 ad:0x40289F00 ad:0x40289F40 ad:0x40289F80 ad:0x40289FC0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 15. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E)(list ad:0x4028A000 ad:0x4028A040 ad:0x4028A080 ad:0x4028A0C0 ad:0x4028A100 ad:0x4028A140 ad:0x4028A180 ad:0x4028A1C0 ad:0x4028A200 ad:0x4028A240 ad:0x4028A280 ad:0x4028A2C0 ad:0x4028A300 ad:0x4028A340 ad:0x4028A380)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "DW1"
|
|
base ad:0x40290000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "ENABLED,IP enable:" "0,1"
|
|
bitfld.long 0x0 1. "ECC_INJ_EN,Enable parity injection for SRAM." "0,1"
|
|
bitfld.long 0x0 0. "ECC_EN,Enable ECC checking:" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Status"
|
|
bitfld.long 0x0 31. "ACTIVE,Active channel present:" "0,1"
|
|
bitfld.long 0x0 28.--30. "STATE,State of the DW controller." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 16.--24. 1. "CH_IDX,Active channel index."
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Active channel preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Active channel priority." "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Active channel protection context."
|
|
newline
|
|
bitfld.long 0x0 2. "B,Active channel non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Active channel secure/non-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,Active channel user/privileged access control:" "0,1"
|
|
rgroup.long 0x20++0xB
|
|
line.long 0x0 "ACT_DESCR_CTL,Active descriptor control"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "ACT_DESCR_SRC,Active descriptor source"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Copy of DESCR_SRC of the currently active descriptor."
|
|
line.long 0x8 "ACT_DESCR_DST,Active descriptor destination"
|
|
hexmask.long 0x8 0.--31. 1. "DATA,Copy of DESCR_DST of the currently active descriptor."
|
|
rgroup.long 0x30++0xB
|
|
line.long 0x0 "ACT_DESCR_X_CTL,Active descriptor X loop control"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Copy of DESCR_X_CTL of the currently active descriptor."
|
|
line.long 0x4 "ACT_DESCR_Y_CTL,Active descriptor Y loop control"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Copy of DESCR_Y_CTL of the currently active descriptor."
|
|
line.long 0x8 "ACT_DESCR_NEXT_PTR,Active descriptor next pointer"
|
|
hexmask.long 0x8 2.--31. 1. "ADDR,Copy of DESCR_NEXT_PTR of the currently active descriptor."
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x0 "ACT_SRC,Active source"
|
|
hexmask.long 0x0 0.--31. 1. "SRC_ADDR,Current address of source location."
|
|
line.long 0x4 "ACT_DST,Active destination"
|
|
hexmask.long 0x4 0.--31. 1. "DST_ADDR,Current address of destination location."
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x0 25.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR."
|
|
hexmask.long.word 0x0 0.--9. 1. "WORD_ADDR,Specifies the word address where an error will be injected."
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "CRC_CTL,CRC control"
|
|
bitfld.long 0x0 8. "REM_REVERSE,Specifies whether the remainder is bit reversed (reversal is performed after XORing):" "0,1"
|
|
bitfld.long 0x0 0. "DATA_REVERSE,Specifies the bit order in which a data Byte is processed (reversal is performed after XORing):" "0,1"
|
|
group.long 0x110++0x3
|
|
line.long 0x0 "CRC_DATA_CTL,CRC data control"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA_XOR,Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal."
|
|
group.long 0x120++0x3
|
|
line.long 0x0 "CRC_POL_CTL,CRC polynomial control"
|
|
hexmask.long 0x0 0.--31. 1. "POLYNOMIAL,CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less.."
|
|
group.long 0x130++0x3
|
|
line.long 0x0 "CRC_LFSR_CTL,CRC LFSR control"
|
|
hexmask.long 0x0 0.--31. 1. "LFSR32,State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC. This register needs to be initialized by SW to provide the CRC seed value."
|
|
group.long 0x140++0x3
|
|
line.long 0x0 "CRC_REM_CTL,CRC remainder control"
|
|
hexmask.long 0x0 0.--31. 1. "REM_XOR,Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal."
|
|
rgroup.long 0x148++0x3
|
|
line.long 0x0 "CRC_REM_RESULT,CRC remainder result"
|
|
hexmask.long 0x0 0.--31. 1. "REM,Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE:"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40298000 ad:0x40298040 ad:0x40298080 ad:0x402980C0 ad:0x40298100 ad:0x40298140 ad:0x40298180 ad:0x402981C0 ad:0x40298200 ad:0x40298240 ad:0x40298280 ad:0x402982C0 ad:0x40298300 ad:0x40298340 ad:0x40298380 ad:0x402983C0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x40298400 ad:0x40298440 ad:0x40298480 ad:0x402984C0 ad:0x40298500 ad:0x40298540 ad:0x40298580 ad:0x402985C0 ad:0x40298600 ad:0x40298640 ad:0x40298680 ad:0x402986C0 ad:0x40298700 ad:0x40298740 ad:0x40298780 ad:0x402987C0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F)(list ad:0x40298800 ad:0x40298840 ad:0x40298880 ad:0x402988C0 ad:0x40298900 ad:0x40298940 ad:0x40298980 ad:0x402989C0 ad:0x40298A00 ad:0x40298A40 ad:0x40298A80 ad:0x40298AC0 ad:0x40298B00 ad:0x40298B40 ad:0x40298B80 ad:0x40298BC0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F)(list ad:0x40298C00 ad:0x40298C40 ad:0x40298C80 ad:0x40298CC0 ad:0x40298D00 ad:0x40298D40 ad:0x40298D80 ad:0x40298DC0 ad:0x40298E00 ad:0x40298E40 ad:0x40298E80 ad:0x40298EC0 ad:0x40298F00 ad:0x40298F40 ad:0x40298F80 ad:0x40298FC0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F)(list ad:0x40299000 ad:0x40299040 ad:0x40299080 ad:0x402990C0 ad:0x40299100 ad:0x40299140 ad:0x40299180 ad:0x402991C0 ad:0x40299200 ad:0x40299240 ad:0x40299280 ad:0x402992C0 ad:0x40299300 ad:0x40299340 ad:0x40299380 ad:0x402993C0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F)(list ad:0x40299400 ad:0x40299440 ad:0x40299480 ad:0x402994C0 ad:0x40299500 ad:0x40299540 ad:0x40299580 ad:0x402995C0 ad:0x40299600 ad:0x40299640 ad:0x40299680 ad:0x402996C0 ad:0x40299700 ad:0x40299740 ad:0x40299780 ad:0x402997C0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F)(list ad:0x40299800 ad:0x40299840 ad:0x40299880 ad:0x402998C0 ad:0x40299900 ad:0x40299940 ad:0x40299980 ad:0x402999C0 ad:0x40299A00 ad:0x40299A40 ad:0x40299A80 ad:0x40299AC0 ad:0x40299B00 ad:0x40299B40 ad:0x40299B80 ad:0x40299BC0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F)(list ad:0x40299C00 ad:0x40299C40 ad:0x40299C80 ad:0x40299CC0 ad:0x40299D00 ad:0x40299D40 ad:0x40299D80 ad:0x40299DC0 ad:0x40299E00 ad:0x40299E40 ad:0x40299E80 ad:0x40299EC0 ad:0x40299F00 ad:0x40299F40 ad:0x40299F80 ad:0x40299FC0)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 15. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E)(list ad:0x4029A000 ad:0x4029A040 ad:0x4029A080 ad:0x4029A0C0 ad:0x4029A100 ad:0x4029A140 ad:0x4029A180 ad:0x4029A1C0 ad:0x4029A200 ad:0x4029A240 ad:0x4029A280 ad:0x4029A2C0 ad:0x4029A300 ad:0x4029A340 ad:0x4029A380)
|
|
tree "CH_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CH_CTL,Channel control"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 11. "PREEMPTABLE,Specifies if the channel is preemptable." "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Channel priority:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,Protection context."
|
|
bitfld.long 0x0 2. "B,Non-bufferable/bufferable access control:" "0,1"
|
|
bitfld.long 0x0 1. "NS,Secure/on-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CH_STATUS,Channel status"
|
|
bitfld.long 0x0 31. "PENDING,Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s))." "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTR_CAUSE,Specifies the source of the interrupt cause:"
|
|
group.long ($2+0x8)++0x13
|
|
line.long 0x0 "CH_IDX,Channel current indices"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Y_IDX,Specifies the Y loop index with X_COUNT taken from the current descriptor."
|
|
hexmask.long.byte 0x0 0.--7. 1. "X_IDX,Specifies the X loop index. In the range of [0 X_COUNT] with X_COUNT taken from the current descriptor."
|
|
line.long 0x4 "CH_CURR_PTR,Channel current descriptor pointer"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR,Address of current descriptor. When this field is '0' there is no valid descriptor."
|
|
line.long 0x8 "INTR,Interrupt"
|
|
bitfld.long 0x8 0. "CH,Set to '1' when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1' to clear bit. Write INTR_SET.CH field with '1' to set bit." "0,1"
|
|
line.long 0xC "INTR_SET,Interrupt set"
|
|
bitfld.long 0xC 0. "CH,Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x10 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x10 0. "CH,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "CH,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
group.long ($2+0x20)++0xB
|
|
line.long 0x0 "SRAM_DATA0,SRAM data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,N/A"
|
|
line.long 0x4 "SRAM_DATA1,SRAM data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,N/A"
|
|
line.long 0x8 "TR_CMD,Channel software trigger"
|
|
bitfld.long 0x8 0. "ACTIVATE,Software trigger. When written with '1' a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree.end
|
|
tree "EFUSE (OTP eFuse Memory)"
|
|
base ad:0x0
|
|
tree "EFUSE_DATA"
|
|
base ad:0x402C0800
|
|
group.long 0x2C++0x17
|
|
line.long 0x0 "SECURE_HASH_WORD0,Secure 128 bits HASH word 0 that is used for authentication in SECURE protection state."
|
|
hexmask.long 0x0 0.--31. 1. "HASH_WORD0,Secure 128 bits HASH word 0 that is used for authentication in SECURE protection state."
|
|
line.long 0x4 "SECURE_HASH_WORD1,Secure 128 bits HASH word 1 that is used for authentication in SECURE protection state."
|
|
hexmask.long 0x4 0.--31. 1. "HASH_WORD1,Secure 128 bits HASH word 1 that is used for authentication in SECURE protection state."
|
|
line.long 0x8 "SECURE_HASH_WORD2,Secure 128 bits HASH word 2 that is used for authentication in SECURE protection state."
|
|
hexmask.long 0x8 0.--31. 1. "HASH_WORD2,Secure 128 bits HASH word 2 that is used for authentication in SECURE protection state."
|
|
line.long 0xC "SECURE_HASH_WORD3,Secure 128 bits HASH word 3 that is used for authentication in SECURE protection state."
|
|
hexmask.long 0xC 0.--31. 1. "HASH_WORD3,Secure 128 bits HASH word 3 that is used for authentication in SECURE protection state."
|
|
line.long 0x10 "SECURE_ACCESS_RESTRICT,Access restrictions for SECURE protection state in SECURE lifecycle stage"
|
|
hexmask.long.word 0x10 21.--31. 1. "RESEREVED,N/A"
|
|
bitfld.long 0x10 20. "SMIF_XIP_ENABLE,goes to SYS DAP MPU" "0,1"
|
|
bitfld.long 0x10 18.--19. "MMIO_ALLOWED,goes to SYS DAP MPU" "0,1,2,3"
|
|
bitfld.long 0x10 16.--17. "SFLASH_ALLOWED,goes to SYS DAP MPU" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 14.--15. "WORK_FLASH_ALLOWED,goes to SYS DAP MPU" "0,1,2,3"
|
|
bitfld.long 0x10 11.--13. "SRAM_ALLOWED,goes to SYS DAP MPU" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 8.--10. "FLASH_ALLOWED,goes to SYS DAP MPU" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 7. "DIRECT_EXECUTE_DISABLE,used by ROM boot" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. "SYS_AP_MPU_ENABLE,goes to SYS DAP MPU" "0,1"
|
|
bitfld.long 0x10 4.--5. "AP_CTL_SYS_DISABLE,goes to CPUSS.AP_CTL" "0,1,2,3"
|
|
bitfld.long 0x10 2.--3. "AP_CTL_CMX_DISABLE,goes to CPUSS.AP_CTL" "0,1,2,3"
|
|
bitfld.long 0x10 0.--1. "AP_CTL_CM0_DISABLE,goes to CPUSS.AP_CTL" "0,1,2,3"
|
|
line.long 0x14 "SECURE_DEAD_ACCESS_RESTRICT_ZEROS,Access restrictions for DEAD protection state in SECURE lifecycle stage and number of zeros for Secure fuse group"
|
|
hexmask.long.byte 0x14 24.--31. 1. "SECURE_GROUP_ZEROS,number of zeros for Secure fuse group covers secure hash secure access restriction secure hash zeros secure dead access restriction"
|
|
bitfld.long 0x14 20. "SMIF_XIP_ENABLE,goes to SYS DAP MPU" "0,1"
|
|
bitfld.long 0x14 18.--19. "MMIO_ALLOWED,goes to SYS DAP MPU" "0,1,2,3"
|
|
bitfld.long 0x14 16.--17. "SFLASH_ALLOWED,goes to SYS DAP MPU" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 14.--15. "WORK_FLASH_ALLOWED,goes to SYS DAP MPU" "0,1,2,3"
|
|
bitfld.long 0x14 11.--13. "SRAM_ALLOWED,goes to SYS DAP MPU" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 8.--10. "FLASH_ALLOWED,goes to SYS DAP MPU" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 7. "DIRECT_EXECUTE_DISABLE,used by ROM boot" "0,1"
|
|
newline
|
|
bitfld.long 0x14 6. "SYS_AP_MPU_ENABLE,goes to SYS DAP MPU" "0,1"
|
|
bitfld.long 0x14 4.--5. "AP_CTL_SYS_DISABLE,goes to CPUSS.AP_CTL" "0,1,2,3"
|
|
bitfld.long 0x14 2.--3. "AP_CTL_CMX_DISABLE,goes to CPUSS.AP_CTL" "0,1,2,3"
|
|
bitfld.long 0x14 0.--1. "AP_CTL_CM0_DISABLE,goes to CPUSS.AP_CTL" "0,1,2,3"
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x68)++0x3
|
|
line.long 0x0 "CUSTOMER_DATA[$1],Available EFUSE bits for customer usage.They can be programmed in NORMAL protection state via CMx/DAP and in SECURE protection state via CMx."
|
|
hexmask.long 0x0 0.--31. 1. "DATA_BYTE,Available EFUSE bits for customer usage.They can be programmed in NORMAL protection state via CMx/DAP and in SECURE protection state via CMx."
|
|
repeat.end
|
|
tree.end
|
|
tree "EFUSE_MXS40"
|
|
base ad:0x402C0000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "ENABLED,IP enable:" "0,1"
|
|
line.long 0x4 "TEST,Test"
|
|
bitfld.long 0x4 0.--1. "MARG_READ,Margin Read" "0: Low Resistance: -50 percent from nominal,1: Nominal resistance (Default read condition),2: High Resistance: +50 percent from nominal,3: Higher Resistance: +100 percent from nominal"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "CMD,Command"
|
|
bitfld.long 0x0 31. "START,FW sets this field to '1' to start a program operation. HW sets this field to '0' to indicate that the operation has completed." "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "MACRO_ADDR,Macro address. This field specifies an eFUSE macro."
|
|
hexmask.long.byte 0x0 8.--12. 1. "BYTE_ADDR,Byte address. This field specifies a Byte within a eFUSE macro (each macro has 32 B)."
|
|
bitfld.long 0x0 4.--6. "BIT_ADDR,Bit address. This field specifies a bit within a Byte." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0. "BIT_DATA,Bit data. This field specifies the bit value that is to be programmed into the eFUSE macro array. The address of the bit is specified by the BIT_ADDR BYTE_ADDR and MACRO_ADDR fields. This bit is a don't care for the MXS40 Macro." "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SEQ_DEFAULT,Sequencer Default value"
|
|
bitfld.long 0x0 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x0 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x0 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x0 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
bitfld.long 0x0 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x0 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
group.long 0x40++0x17
|
|
line.long 0x0 "SEQ_READ_CTL_0,Sequencer read control 0"
|
|
bitfld.long 0x0 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x0 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x0 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x0 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x0 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x0 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x0 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
hexmask.long.word 0x0 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x4 "SEQ_READ_CTL_1,Sequencer read control 1"
|
|
bitfld.long 0x4 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x4 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x4 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x4 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x4 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x4 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x4 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x8 "SEQ_READ_CTL_2,Sequencer read control 2"
|
|
bitfld.long 0x8 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x8 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x8 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x8 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x8 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x8 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x8 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x8 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
hexmask.long.word 0x8 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0xC "SEQ_READ_CTL_3,Sequencer read control 3"
|
|
bitfld.long 0xC 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0xC 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0xC 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0xC 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0xC 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0xC 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0xC 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0xC 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
hexmask.long.word 0xC 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x10 "SEQ_READ_CTL_4,Sequencer read control 4"
|
|
bitfld.long 0x10 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x10 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x10 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x10 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x10 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x10 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x10 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x10 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
hexmask.long.word 0x10 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x14 "SEQ_READ_CTL_5,Sequencer read control 5"
|
|
bitfld.long 0x14 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x14 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x14 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x14 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x14 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x14 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x14 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x14 16. "STROBE_A,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
hexmask.long.word 0x14 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
group.long 0x60++0x17
|
|
line.long 0x0 "SEQ_PROGRAM_CTL_0,Sequencer program control 0"
|
|
bitfld.long 0x0 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x0 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x0 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x0 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x0 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x0 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x0 16. "STROBE_A,Specifies value of eFUSE control signal strobe_a" "0,1"
|
|
hexmask.long.word 0x0 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x4 "SEQ_PROGRAM_CTL_1,Sequencer program control 1"
|
|
bitfld.long 0x4 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x4 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x4 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x4 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x4 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x4 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x4 16. "STROBE_A,Specifies value of eFUSE control signal strobe_a" "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x8 "SEQ_PROGRAM_CTL_2,Sequencer program control 2"
|
|
bitfld.long 0x8 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x8 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x8 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x8 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x8 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x8 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x8 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x8 16. "STROBE_A,Specifies value of eFUSE control signal strobe_a" "0,1"
|
|
hexmask.long.word 0x8 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0xC "SEQ_PROGRAM_CTL_3,Sequencer program control 3"
|
|
bitfld.long 0xC 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0xC 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0xC 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0xC 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0xC 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0xC 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0xC 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0xC 16. "STROBE_A,Specifies value of eFUSE control signal strobe_a" "0,1"
|
|
hexmask.long.word 0xC 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x10 "SEQ_PROGRAM_CTL_4,Sequencer program control 4"
|
|
bitfld.long 0x10 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x10 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x10 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x10 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x10 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x10 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x10 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x10 16. "STROBE_A,Specifies value of eFUSE control signal strobe_a" "0,1"
|
|
hexmask.long.word 0x10 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
line.long 0x14 "SEQ_PROGRAM_CTL_5,Sequencer program control 5"
|
|
bitfld.long 0x14 31. "DONE,When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0." "0,1"
|
|
bitfld.long 0x14 22. "STROBE_G,Specifies value of eFUSE control signal strobe_g" "0,1"
|
|
bitfld.long 0x14 21. "STROBE_F,Specifies value of eFUSE control signal strobe_f" "0,1"
|
|
bitfld.long 0x14 20. "STROBE_E,Specifies value of eFUSE control signal strobe_e" "0,1"
|
|
bitfld.long 0x14 19. "STROBE_D,Specifies value of eFUSE control signal strobe_d" "0,1"
|
|
newline
|
|
bitfld.long 0x14 18. "STROBE_C,Specifies value of eFUSE control signal strobe_c" "0,1"
|
|
bitfld.long 0x14 17. "STROBE_B,Specifies value of eFUSEcontrol signal strobe_b" "0,1"
|
|
bitfld.long 0x14 16. "STROBE_A,Specifies value of eFUSE control signal strobe_a" "0,1"
|
|
hexmask.long.word 0x14 0.--9. 1. "CYCLES,Number of IP clock cycles (minus 1). This field is in the range of [0 1023] allowing for a time of [1 1024] IP clock cycles."
|
|
tree.end
|
|
tree.end
|
|
tree "ETH (Ethernet Interface)"
|
|
base ad:0x0
|
|
tree "ETH0"
|
|
base ad:0x40480000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,MXETH Control Register"
|
|
bitfld.long 0x0 31. "ENABLED,MXETH enable:" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "REFCLK_DIV,Specify the ref_clk divider. Integer division by (1+REFCLK_DIV). Allows for integer divisions in the range [1 256]."
|
|
newline
|
|
bitfld.long 0x0 2. "REFCLK_SRC_SEL,Select the source for ref_clk." "0: Ref_clk comes from REF_CLK_IN input port,1: Ref_clk comes from REF_CLK_INT_IN input port"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "ETH_MODE,Set ethernet mode. The speed of 10M/100M/1G is selected by programming network_config after IP is enabled." "0: MII mode (10/100MHz speed is determined by..,1: GMII mode (network_config[10] must be set to..,2: RGMII mode (10M/100M/1G speed is determined by..,3: RMII mode (10M/100M speed is determined by.."
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,MXETH Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "RX_PFC_PAUSED,Each bit corresponds to a priority indicated within the PFC priority based pause frame."
|
|
newline
|
|
bitfld.long 0x0 0. "PFC_NEGOTIATE,Identifies that PFC priority based pause flow control" "0: No PFC priority based pause frames have yet,1: At least one PFC priority based pause frames"
|
|
group.long 0x1000++0x7
|
|
line.long 0x0 "NETWORK_CONTROL,The network control register contains general MAC control functions for both receiver and transmitter."
|
|
rbitfld.long 0x0 31. "EXT_RXQ_RSVD_31,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "IFG_EATS_QAV_CREDIT,Setting this bit high modifies the CBS algorithm so the" "0,1"
|
|
newline
|
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bitfld.long 0x0 29. "TWO_PT_FIVE_GIG,2.5G operation selected - setting this bit high drives" "0,1"
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bitfld.long 0x0 28. "SEL_MII_ON_RGMII,If the RGMII interface being used set this bit high to" "0,1"
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bitfld.long 0x0 27. "OSS_CORRECTION_FIELD,1588 One Step Correction Field Update. Set this bit" "0,1"
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bitfld.long 0x0 26. "EXT_RXQ_SEL_EN,Enable external selection of receive queue. When this bit is high the ext_match1 ext_match2 ext_match3 and ext_match4 inputs will determine which receive queue a frame is routed to. This will be the case regardless of the state of the.." "0,1"
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bitfld.long 0x0 25. "PFC_CTRL,'Enable multiple PFC pause quantums one per pause priority'" "0,1"
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bitfld.long 0x0 24. "ONE_STEP_SYNC_MODE,1588 One Step Sync Mode. Write 1 to enable. Replace timestamp field in the 1588 header for TX Sync Frames with current TSU timer value." "0,1"
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rbitfld.long 0x0 23. "EXT_TSU_PORT_ENABLE,Write ignore read 0" "0,1"
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bitfld.long 0x0 22. "STORE_UDP_OFFSET,N/A" "0,1"
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bitfld.long 0x0 21. "ALT_SGMII_MODE,Alternative sgmii mode. If asserted with sgmii_mode in the network control register the ACK bit is driven before ability detect during transfer of status information from the PHY to the MAC." "0,1"
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bitfld.long 0x0 20. "PTP_UNICAST_ENA,Enable detection of unicast PTP unicast frames." "0,1"
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bitfld.long 0x0 19. "TX_LPI_EN,Enable LPI transmission when set LPI (low power idle) is immediately transmitted. LPI is transmitted even if bit 3 transmit enable is disabled. Setting this bit also sends a pause signal to the transmit datapath." "0,1"
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bitfld.long 0x0 18. "FLUSH_RX_PKT_PCLK,Flush the next packet from the external RX DPRAM. Writing one to this bit will only have an effect if the DMA is not currently writing a packet already stored in the DPRAM to memory. Self clearing register." "0,1"
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bitfld.long 0x0 17. "TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME,Write a one to transmit PFC priority based pause frame. Takes the values stored in the Transmit PFC Pause Register. Self clearing register." "0,1"
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bitfld.long 0x0 16. "PFC_ENABLE,Enable PFC Priority Based Pause Reception capabilities. Setting this bit will enable PFC negotiation and recognition of priority based pause frames." "0,1"
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bitfld.long 0x0 15. "STORE_RX_TS,Store receive time stamp to memory. Setting this bit to one will cause the CRC of every received frame to be replaced with the value of the nanoseconds field of the 1588 timer that was captured as the receive frame passed the message time.." "0,1"
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rbitfld.long 0x0 14. "REMOVED_14,Write ignore read 0" "0,1"
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rbitfld.long 0x0 13. "REMOVED_13,Write ignore read 0" "0,1"
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bitfld.long 0x0 12. "TX_PAUSE_FRAME_ZERO,Transmit zero quantum pause frame - writing one to this bit causes a pause frame with zero quantum to be transmitted." "0,1"
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bitfld.long 0x0 11. "TX_PAUSE_FRAME_REQ,Transmit pause frame - writing one to this bit causes a pause frame to be transmitted. Self clearing register." "0,1"
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bitfld.long 0x0 10. "TX_HALT_PCLK,Transmit halt - writing one to this bit halts transmission as soon as any ongoing frame transmission ends." "0,1"
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bitfld.long 0x0 9. "TX_START_PCLK,Start transmission - writing one to this bit starts transmission." "0,1"
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bitfld.long 0x0 8. "BACK_PRESSURE,Back pressure if set in 10M or 100M half duplex mode will force collisions on all received frames. Ignored in gigabit half duplex mode." "0,1"
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bitfld.long 0x0 7. "STATS_WRITE_EN,Write enable for statistics registers - setting this bit to one means the statistics registers can be written for functional test purposes." "0,1"
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bitfld.long 0x0 6. "INC_ALL_STATS_REGS,Incremental statistics registers - this bit is write only. Writing a one increments all the statistics registers by one for test purposes. Self clearing register." "0,1"
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bitfld.long 0x0 5. "CLEAR_ALL_STATS_REGS,Clear statistics registers - this bit is write only. Writing a one clears the statistics registers. Self clearing register." "0,1"
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bitfld.long 0x0 4. "MAN_PORT_EN,Management port enable - set to one to enable the management port. When zero forces mdio to high impedance state and mdc low." "0,1"
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bitfld.long 0x0 3. "ENABLE_TRANSMIT,Transmit enable - when set it enables the GEM transmitter to send data. When reset transmission will stop immediately the transmit pipeline and control registers will be cleared and the transmit queue pointer register will reset to.." "0,1"
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bitfld.long 0x0 2. "ENABLE_RECEIVE,Receive enable - when set it enables the GEM to receive data. When reset frame reception will stop immediately and the receive pipeline will be cleared. The receive queue pointer register is unaffected." "0,1"
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bitfld.long 0x0 1. "LOOPBACK_LOCAL,Loopback local - asserts the loopback_local signal to the system clock generator. Also connects txd to rxd tx_en to rx_dv and forces full duplex mode. Bit 11 of the network configuration register must be set low to disable TBI mode when.." "0,1"
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bitfld.long 0x0 0. "LOOPBACK,Loopback - controls the loopback output pin." "0,1"
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line.long 0x4 "NETWORK_CONFIG,The network configuration register contains functions for setting the mode of operation for the Gigabit Ethernet MAC."
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bitfld.long 0x4 31. "RSVD_31,N/A" "0,1"
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bitfld.long 0x4 30. "IGNORE_IPG_RX_ER,Ignore IPG rx_er. When set rx_er has no effect on the GEMs operation when rx_dv is low. Set this when using the RGMII wrapper in half-duplex mode." "0,1"
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bitfld.long 0x4 29. "NSP_CHANGE,Receive bad preamble. When set frames with non-standard preamble are not rejected." "0,1"
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bitfld.long 0x4 28. "IPG_STRETCH_ENABLE,IPG stretch enable - when set the transmit IPG can be increased above 96 bit times depending on the previous frame length using the IPG stretch register." "0,1"
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bitfld.long 0x4 27. "SGMII_MODE_ENABLE,SGMII mode enable - changes behaviour of the auto-negotiation advertisement and link partner ability registers to meet the requirements of SGMII and reduces the duration of the link timer from 10 ms to 1.6 ms." "0,1"
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bitfld.long 0x4 26. "IGNORE_RX_FCS,Ignore RX FCS - when set frames with FCS/CRC errors will not be rejected. FCS error statistics will still be collected for frames with bad FCS and FCS status will be recorded in frame's DMA descriptor. For normal operation this bit must be.." "0,1"
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bitfld.long 0x4 25. "EN_HALF_DUPLEX_RX,Enable frames to be received in half-duplex mode while transmitting." "0,1"
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bitfld.long 0x4 24. "RECEIVE_CHECKSUM_OFFLOAD_ENABLE,Receive checksum offload enable - when set the receive checksum engine is enabled. Frames with bad IP TCP or UDP checksums are discarded." "0,1"
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bitfld.long 0x4 23. "DISABLE_COPY_OF_PAUSE_FRAMES,Disable copy of pause frames - set to one to prevent pause frames being copied to memory. When set neither control frames with type id 8808 nor pause frames with destination address 010000c28001 are copied to memory this.." "0,1"
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bitfld.long 0x4 21.--22. "DATA_BUS_WIDTH,Data bus width - set according to AMBA (AXI/AHB) or external FIFO data bus width. The reset value for this can be changed by defining a new value for gem_dma_bus_width_def in gem_defs. Only valid bus widths may be written if the system is.." "0,1,2,3"
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bitfld.long 0x4 18.--20. "MDC_CLOCK_DIVISION,MDC clock division - set according to pclk speed. These three bits determine the number pclk will be divided by to generate MDC. For conformance with the 802.3 specification MDC must not exceed 2.5 MHz (MDC is only active during MDIO.." "0: divide pclk by 8,1: divide pclk by 16,?,?,?,?,?,?"
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bitfld.long 0x4 17. "FCS_REMOVE,FCS remove - setting this bit will cause received frames to be written to memory without their frame check sequence (last 4 bytes). The frame length indicated will be reduced by four bytes in this mode." "0,1"
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bitfld.long 0x4 16. "LENGTH_FIELD_ERROR_FRAME_DISCARD,Length field error frame discard - setting this bit causes frames with a measured length shorter than the extracted length field (as indicated by bytes 13 and 14 in a non-VLAN tagged frame) to be discarded. This only.." "0,1"
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bitfld.long 0x4 14.--15. "RECEIVE_BUFFER_OFFSET,Receive buffer offset - indicates the number of bytes by which the received data is offset from the start of the receive buffer." "0,1,2,3"
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bitfld.long 0x4 13. "PAUSE_ENABLE,Pause enable - when set transmission will pause if a non zero 802.3 classic pause frame is received and PFC has not been negotiated." "0,1"
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bitfld.long 0x4 12. "RETRY_TEST,Retry test - must be set to zero for normal operation. If set to one the backoff between collisions will always be one slot time. Setting this bit to one helps test the too many retries condition. Also used in the pause frame tests to reduce.." "0,1"
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bitfld.long 0x4 11. "PCS_SELECT,PCS select - selects between MII/GMII and TBI" "0,1"
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bitfld.long 0x4 10. "GIGABIT_MODE_ENABLE,Gigabit mode enable - setting this bit configures the GEM for 1000 Mbps operation." "?,1: Gigabit operation using GMI interface"
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bitfld.long 0x4 9. "EXTERNAL_ADDRESS_MATCH_ENABLE,External address match enable - when set the external address match interface can be used to copy frames to memory." "0,1"
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bitfld.long 0x4 8. "RECEIVE_1536_BYTE_FRAMES,Receive 1536 byte frames - setting this bit means the GEM will accept frames up to 1536 bytes in length. Normally the GEM would reject any frame above 1518 bytes." "0,1"
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bitfld.long 0x4 7. "UNICAST_HASH_ENABLE,Unicast hash enable - when set unicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register." "0,1"
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bitfld.long 0x4 6. "MULTICAST_HASH_ENABLE,Multicast hash enable - when set multicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register." "0,1"
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bitfld.long 0x4 5. "NO_BROADCAST,No broadcast - when set to logic one frames addressed to the broadcast address of all ones will not be accepted." "0,1"
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bitfld.long 0x4 4. "COPY_ALL_FRAMES,Copy all frames - when set to logic one all valid frames will be accepted." "0,1"
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bitfld.long 0x4 3. "JUMBO_FRAMES,Jumbo frames - set to one to enable jumbo frames up to `gem_jumbo_max_length bytes to be accepted. The default length is 10 240 bytes." "0,1"
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bitfld.long 0x4 2. "DISCARD_NON_VLAN_FRAMES,Discard non-VLAN frames - when set only VLAN tagged frames will be passed to the address matching logic." "0,1"
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bitfld.long 0x4 1. "FULL_DUPLEX,Full duplex - if set to logic one the transmit block ignores the state of collision and carrier sense and allows receive while transmitting. Also controls the half_duplex pin." "0,1"
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bitfld.long 0x4 0. "SPEED,Speed - set to logic one to indicate 100Mbps operation logic zero for 10Mbps." "0,1"
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rgroup.long 0x1008++0x7
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line.long 0x0 "NETWORK_STATUS,The network status register returns status information with respect to the PHY management interface."
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bitfld.long 0x0 7. "LPI_INDICATE_PCLK,LPI Indication - Low power idle has been detected on receive. This bit is set when LPI is detected and reset when normal idle is detected. An interrupt is generated when the state of this bit changes." "0,1"
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bitfld.long 0x0 6. "PFC_NEGOTIATE_PCLK,Set when PFC Priority Based Pause has been negotiated." "0,1"
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bitfld.long 0x0 4.--5. "REMOVED_5_4,N/A" "0,1,2,3"
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bitfld.long 0x0 3. "MAC_FULL_DUPLEX,PCS auto-negotiation duplex resolution. Set to one if the resolution function determines that both devices are capable of full duplex operation. If zero half-duplex operation is possible as long as bit 0 (PCS link state) is also one." "0,1"
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bitfld.long 0x0 2. "MAN_DONE,The PHY management logic is idle (i.e. has completed)." "0,1"
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bitfld.long 0x0 1. "MDIO_IN,Returns status of the mdio_in pin." "0,1"
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bitfld.long 0x0 0. "PCS_LINK_STATE,Returns status of PCS link state. If auto-negotiation is disabled this returns the synchronisation status. If auto-negotiation is enabled it is set in the LINK_OK state as long as a compatible duplex mode is resolved." "0,1"
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line.long 0x4 "USER_IO_REGISTER,Not presents. Access to the register will return AHB error."
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hexmask.long 0x4 0.--31. 1. "RSVD_31_0,Write ignore read 0"
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group.long 0x1010++0x17
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line.long 0x0 "DMA_CONFIG,DMA Configuration Register"
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bitfld.long 0x0 30. "DMA_ADDR_BUS_WIDTH_1,DMA address bus width. 0 = 32b 1 = 64b. MXETH only supports 32b DMA address bus width so must set it 0." "0,1"
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bitfld.long 0x0 29. "TX_BD_EXTENDED_MODE_EN,Enable TX extended BD mode. See TX BD control register definition for description of feature." "0,1"
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bitfld.long 0x0 28. "RX_BD_EXTENDED_MODE_EN,Enable RX extended BD mode. See RX BD control register definition for description of feature." "0,1"
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bitfld.long 0x0 26. "FORCE_MAX_AMBA_BURST_TX,Force max length bursts on TX. Force the TX DMA to always issue max length bursts on EOP(end of packet) or EOB(end of buffer) transfers as defined by bits 4:0 of this register even when there is less that max burst data bytes to.." "0,1"
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bitfld.long 0x0 25. "FORCE_MAX_AMBA_BURST_RX,Force max length bursts on RX. Force the RX DMA to always issue max length bursts on EOP(end of packet) or EOB(end of buffer)transfers even if there is less than max burst real packet data required to write. Any extra bytes of.." "0,1"
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bitfld.long 0x0 24. "FORCE_DISCARD_ON_ERR,Auto Discard RX pkts during lack of resource. When set the GEM DMA will automatically discard receive packets from the receiver packet buffer memory when no AMBA (AXI/AHB) resource is available. When low then received packets will.." "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "RX_BUF_SIZE,DMA receive buffer size in external AMBA (AXI/AHB) system memory. The value defined by these bits determines the size of buffer to use in main system memory when writing received data. The value is defined in multiples of 64 bytes."
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bitfld.long 0x0 13. "CRC_ERROR_REPORT,When the bit is set bit 16 of the receive buffer descriptor will represent FCS/CRC error (only if frames with FCS are copied to memory as enabled by bit 26 in the network config register). When this bit is clear bit 16 of the receive.." "0,1"
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bitfld.long 0x0 12. "INFINITE_LAST_DBUF_SIZE_EN,Forces the DMA to consider the data buffer pointed to by last descriptor in the descriptor list to be of infinite size." "0,1"
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bitfld.long 0x0 11. "TX_PBUF_TCP_EN,N/A" "0,1"
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bitfld.long 0x0 10. "TX_PBUF_SIZE,N/A" "0,1"
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bitfld.long 0x0 8.--9. "RX_PBUF_SIZE,N/A" "0,1,2,3"
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bitfld.long 0x0 7. "ENDIAN_SWAP_PACKET,endian swap mode enable for packet data accesses. When set selects swapped endianism for AMBA (AXI/AHB) transfers. When clear selects little endian mode. Note the default value of this bit equals to `gem_endian_swap_def which is.." "0,1"
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bitfld.long 0x0 6. "ENDIAN_SWAP_MANAGEMENT,endian swap mode enable for management descriptor accesses. When set selects swapped endianism for AMBA (AXI/AHB) transfers. When clear selects little endian mode. Note the default value of this bit equals to.." "0,1"
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bitfld.long 0x0 5. "HDR_DATA_SPLITTING_EN,Enable header data Splitting. When set receive frames will be forwarded to main memory using a minimum of two DMA data buffers. The first X data buffers will contain the frame header consisting of the Ethernet VLAN (IPv4 or.." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "AMBA_BURST_LENGTH,Selects the burst length to use on the AMBA (AHB/AXI) when transferring frame data. Not used for DMA management operations and only used where space and data size allow and respecting AXI/AHB burst boundary rules. One-hot priority.."
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line.long 0x4 "TRANSMIT_STATUS,This register. when read. provides details of the status of a transmit. Once read. individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register."
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bitfld.long 0x4 8. "RESP_NOT_OK123,bresp/hresp not OK - set when the DMA block sees bresp/hresp not OK. Cleared by writing a one to this bit." "0,1"
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bitfld.long 0x4 7. "LATE_COLLISION_OCCURRED,Late collision occurred - only set if the condition occurs in gigabit mode as retry is not attempted. Cleared by writing a one to this bit." "0,1"
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bitfld.long 0x4 6. "TRANSMIT_UNDER_RUN123,Transmit under run - this bit is set if the transmitter was forced to terminate a frame that it had already began transmitting due to further data being unavailable. This bit is set if a transmitter status write back has not.." "0,1"
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bitfld.long 0x4 5. "TRANSMIT_COMPLETE123,Transmit complete - set when a frame has been transmitted. Cleared by writing a one to this bit." "0,1"
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bitfld.long 0x4 4. "AMBA_ERROR123,Transmit frame corruption due to AMBA (AXI/AHB) errors. Set if an error occurs whilst midway through reading transmit frame from external memory including RRESP or BRESP errors and buffers exhausted mid frame (if the buffers run out during.." "0,1"
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rbitfld.long 0x4 3. "TRANSMIT_GO,Transmit go - if high transmit is active. When using the exposed FIFO interface this bit represents bit 3 of the network control register. When using the DMA interface this bit represents the tx_go variable as specified in the transmit.." "0,1"
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bitfld.long 0x4 2. "RETRY_LIMIT_EXCEEDED,Retry limit exceeded - cleared by writing a one to this bit." "0,1"
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bitfld.long 0x4 1. "COLLISION_OCCURRED,Collision occurred - set by the assertion of collision. Cleared by writing a one to this bit. When operating in 10/100 mode this status indicates either a collision or a late collision. In gigabit mode this status is not set for a.." "0,1"
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bitfld.long 0x4 0. "USED_BIT_READ,Used bit read - set when a transmit buffer descriptor is read with its used bit set. Cleared by writing a one to this bit." "0,1"
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line.long 0x8 "RECEIVE_Q_PTR,This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once.."
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hexmask.long 0x8 2.--31. 1. "DMA_RX_Q_PTR,Receive buffer queue base address - written with the address of the start of the receive queue."
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bitfld.long 0x8 0. "DMA_RX_DIS_Q,Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while receive is not enabled." "0,1"
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line.long 0xC "TRANSMIT_Q_PTR,This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control.."
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hexmask.long 0xC 2.--31. 1. "DMA_TX_Q_PTR,Transmit buffer queue base address - written with the address of the start of the transmit queue."
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bitfld.long 0xC 0. "DMA_TX_DIS_Q,Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while transmit is not enabled." "0,1"
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line.long 0x10 "RECEIVE_STATUS,This register. when read provides details of the status of a receive. Once read. individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register."
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bitfld.long 0x10 3. "RESP_NOT_OK1234,bresp not OK - set when the DMA block sees bresp/hresp not OK. Cleared by writing a one to this bit." "0,1"
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bitfld.long 0x10 2. "RECEIVE_OVERRUN123,Receive overrun - this bit is set if either the gem_dma RX FIFO or external RX FIFO were unable to store the receive frame due to a FIFO overflow or if the receive status reported by the gem_rx module to the gem_dma was not taken at.." "0,1"
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bitfld.long 0x10 1. "FRAME_RECEIVED,Frame received - one or more frames have been received and placed in memory. Cleared by writing a one to this bit." "0,1"
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bitfld.long 0x10 0. "BUFFER_NOT_AVAILABLE,Buffer not available - an attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA will reread the pointer each time an end of frame is received until a valid pointer is found. This.." "0,1"
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line.long 0x14 "INT_STATUS,If not configured for priority queueing. the GEM generates a single interrupt. This register indicates the source of this interrupt. The corresponding bit in the mask register must be clear for a bit to be set. If any bit is set in this.."
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bitfld.long 0x14 29. "TSU_TIMER_COMPARISON_INTERRUPT,TSU timer comparison interrupt. Indicates when TSU timer count value is equal to programmed value." "0,1"
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rbitfld.long 0x14 28. "REMOVED_28,Write ignore read 0" "0,1"
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bitfld.long 0x14 27. "RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE,Receive LPI indication status bit change" "0,1"
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bitfld.long 0x14 26. "TSU_SECONDS_REGISTER_INCREMENT,TSU seconds register increment indicates the register has incremented. Cleared on read." "0,1"
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bitfld.long 0x14 25. "PTP_PDELAY_RESP_FRAME_TRANSMITTED,PTP pdelay_resp frame transmitted indicates a PTP pdelay_resp frame has been transmitted. Cleared on read." "0,1"
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bitfld.long 0x14 24. "PTP_PDELAY_REQ_FRAME_TRANSMITTED,PTP pdelay_req frame transmitted indicates a PTP pdelay_req frame has been transmitted. Cleared on read." "0,1"
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bitfld.long 0x14 23. "PTP_PDELAY_RESP_FRAME_RECEIVED,PTP pdelay_resp frame received indicates a PTP pdelay_resp frame has been received. Cleared on read." "0,1"
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bitfld.long 0x14 22. "PTP_PDELAY_REQ_FRAME_RECEIVED,PTP pdelay_req frame received indicates a PTP pdelay_req frame has been received. Cleared on read." "0,1"
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bitfld.long 0x14 21. "PTP_SYNC_FRAME_TRANSMITTED,PTP sync frame transmitted indicates a PTP sync frame has been transmitted. Cleared on read." "0,1"
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bitfld.long 0x14 20. "PTP_DELAY_REQ_FRAME_TRANSMITTED,PTP delay_req frame transmitted indicates a PTP delay_req frame has been transmitted. Cleared on read." "0,1"
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bitfld.long 0x14 19. "PTP_SYNC_FRAME_RECEIVED,PTP sync frame received indicates a PTP sync frame has been received. Cleared on read." "0,1"
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bitfld.long 0x14 18. "PTP_DELAY_REQ_FRAME_RECEIVED,PTP delay_req frame received indicates a PTP delay_req frame has been received. Cleared on read." "0,1"
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rbitfld.long 0x14 17. "REMOVED_17,Write ignore read 0" "0,1"
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rbitfld.long 0x14 16. "REMOVED_16,Write ignore read 0" "0,1"
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rbitfld.long 0x14 15. "REMOVED_15,Write ignore read 0" "0,1"
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bitfld.long 0x14 14. "PAUSE_FRAME_TRANSMITTED,Pause frame transmitted - indicates a pause frame has been successfully transmitted after being initiated from the network control register or from the tx_pause control pin. Cleared on read." "0,1"
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bitfld.long 0x14 13. "PAUSE_TIME_ELAPSED,Pause Time elapsed. set when either the pause time register at address 0x38 decrements to zero or when a valid pause frame is received with a zero pause quantum field. Cleared on read." "0,1"
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bitfld.long 0x14 12. "PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED,Pause frame with non-zero pause quantum received - indicates a valid pause has been received that has a non-zero pause quantum field. Cleared on read." "0,1"
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bitfld.long 0x14 11. "RESP_NOT_OK,bresp not OK - set when the DMA block sees bresp not OK. Cleared on read." "0,1"
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bitfld.long 0x14 10. "RECEIVE_OVERRUN,Receive overrun - set when the receive overrun status bit gets set. Cleared on read." "0,1"
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rbitfld.long 0x14 9. "REMOVED_9,Write ignore read 0" "0,1"
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bitfld.long 0x14 7. "TRANSMIT_COMPLETE,Transmit complete - set when a frame has been transmitted. Cleared on read." "0,1"
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bitfld.long 0x14 6. "AMBA_ERROR,Transmit frame corruption due to AMBA (AXI/AHB) error. Set if an error occurs whilst midway through reading transmit frame from external system memory including HRESP (AHB) RRESP or BRESP(AXI) errors and buffers exhausted mid frame (if the.." "0,1"
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bitfld.long 0x14 5. "RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION,Retry limit exceeded or late collision - transmit error. Late collision will only cause this status bit to be set in gigabit mode (as a retry is not attempted). Cleared on read." "0,1"
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bitfld.long 0x14 4. "TRANSMIT_UNDER_RUN,Transmit under run - this interrupt is set if the transmitter was forced to terminate a frame that it has already began transmitting due to further data being unavailable. If an under run occurs the transmitter will force bad crc and.." "0,1"
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bitfld.long 0x14 3. "TX_USED_BIT_READ,TX used bit read - set when a transmit buffer descriptor is read with its used bit set. Cleared on read." "0,1"
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bitfld.long 0x14 2. "RX_USED_BIT_READ,RX used bit read - set when a receive buffer descriptor is read with its used bit set. Cleared on read." "0,1"
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bitfld.long 0x14 1. "RECEIVE_COMPLETE,Receive complete - a frame has been stored in memory. Cleared on read." "0,1"
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bitfld.long 0x14 0. "MANAGEMENT_FRAME_SENT,Management frame sent - the PHY maintenance register has completed its operation. Cleared on read." "0,1"
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wgroup.long 0x1028++0x3
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line.long 0x0 "INT_ENABLE,At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero."
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bitfld.long 0x0 29. "ENABLE_TSU_TIMER_COMPARISON_INTERRUPT,Enable TSU timer comparison interrupt." "0,1"
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bitfld.long 0x0 28. "UNUSED_28,Not used" "0,1"
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bitfld.long 0x0 27. "ENABLE_RX_LPI_INDICATION_INTERRUPT,Enable RX LPI indication interrupt" "0,1"
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bitfld.long 0x0 26. "ENABLE_TSU_SECONDS_REGISTER_INCREMENT,Enable TSU seconds register increment" "0,1"
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bitfld.long 0x0 25. "ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED,Enable PTP pdelay_resp frame transmitted" "0,1"
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bitfld.long 0x0 24. "ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED,Enable PTP pdelay_req frame transmitted" "0,1"
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bitfld.long 0x0 23. "ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED,Enable PTP pdelay_resp frame received" "0,1"
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bitfld.long 0x0 22. "ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED,Enable PTP pdelay_req frame received" "0,1"
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bitfld.long 0x0 21. "ENABLE_PTP_SYNC_FRAME_TRANSMITTED,Enable PTP sync frame transmitted" "0,1"
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bitfld.long 0x0 20. "ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED,Enable PTP delay_req frame transmitted" "0,1"
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bitfld.long 0x0 19. "ENABLE_PTP_SYNC_FRAME_RECEIVED,Enable PTP sync frame received" "0,1"
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bitfld.long 0x0 18. "ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED,Enable PTP delay_req frame received" "0,1"
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bitfld.long 0x0 17. "UNUSED_17,Not used" "0,1"
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bitfld.long 0x0 16. "UNUSED_16,Not used" "0,1"
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bitfld.long 0x0 15. "UNUSED_15,Not used" "0,1"
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bitfld.long 0x0 14. "ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT,Enable pause frame transmitted interrupt" "0,1"
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bitfld.long 0x0 13. "ENABLE_PAUSE_TIME_ZERO_INTERRUPT,Enable pause time zero interrupt" "0,1"
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bitfld.long 0x0 12. "ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT,Enable pause frame with non-zero pause quantum interrupt" "0,1"
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bitfld.long 0x0 11. "ENABLE_RESP_NOT_OK_INTERRUPT,Enable bresp not OK interrupt" "0,1"
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bitfld.long 0x0 10. "ENABLE_RECEIVE_OVERRUN_INTERRUPT,Enable receive overrun interrupt" "0,1"
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bitfld.long 0x0 9. "UNUSED_9,Not used" "0,1"
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bitfld.long 0x0 8. "UNUSED_8,Not used" "0,1"
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bitfld.long 0x0 7. "ENABLE_TRANSMIT_COMPLETE_INTERRUPT,Enable transmit complete interrupt" "0,1"
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bitfld.long 0x0 6. "ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT,Enable transmit frame corruption due to AMBA (AXI/AHB) error interrupt" "0,1"
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bitfld.long 0x0 5. "ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT,Enable retry limit exceeded or late collision interrupt" "0,1"
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bitfld.long 0x0 4. "ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT,Enable transmit buffer under run interrupt" "0,1"
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bitfld.long 0x0 3. "ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT,Enable transmit used bit read interrupt" "0,1"
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bitfld.long 0x0 2. "ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT,Enable receive used bit read interrupt" "0,1"
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bitfld.long 0x0 1. "ENABLE_RECEIVE_COMPLETE_INTERRUPT,Enable receive complete interrupt" "0,1"
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bitfld.long 0x0 0. "ENABLE_MANAGEMENT_DONE_INTERRUPT,Enable management done interrupt" "0,1"
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group.long 0x102C++0x3
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line.long 0x0 "INT_DISABLE,Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero."
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rbitfld.long 0x0 31. "RSVD_31_31,N/A" "0,1"
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rbitfld.long 0x0 30. "RSVD_30_30,N/A" "0,1"
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bitfld.long 0x0 29. "DISABLE_TSU_TIMER_COMPARISON_INTERRUPT,'Disable TSU timer comparison interrupt.'" "0,1"
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bitfld.long 0x0 28. "UNUSED_28,Not used" "0,1"
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bitfld.long 0x0 27. "DISABLE_RX_LPI_INDICATION_INTERRUPT,'Disable RX LPI indication interrupt'" "0,1"
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bitfld.long 0x0 26. "DISABLE_TSU_SECONDS_REGISTER_INCREMENT,'Disable TSU seconds register increment'" "0,1"
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bitfld.long 0x0 25. "DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED,'Disable PTP pdelay_resp frame transmitted'" "0,1"
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bitfld.long 0x0 24. "DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED,'Disable PTP pdelay_req frame transmitted'" "0,1"
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bitfld.long 0x0 23. "DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED,'Disable PTP pdelay_resp frame received'" "0,1"
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bitfld.long 0x0 22. "DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED,'Disable PTP pdelay_req frame received'" "0,1"
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bitfld.long 0x0 21. "DISABLE_PTP_SYNC_FRAME_TRANSMITTED,'Disable PTP sync frame transmitted '" "0,1"
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bitfld.long 0x0 20. "DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED,'Disable PTP delay_req frame transmitted '" "0,1"
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bitfld.long 0x0 19. "DISABLE_PTP_SYNC_FRAME_RECEIVED,'Disable PTP sync frame received'" "0,1"
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bitfld.long 0x0 18. "DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED,'Disable PTP delay_req frame received'" "0,1"
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bitfld.long 0x0 17. "UNUSED_17,Not used" "0,1"
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bitfld.long 0x0 16. "UNUSED_16,Not used" "0,1"
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bitfld.long 0x0 15. "UNUSED_15,Not used" "0,1"
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bitfld.long 0x0 14. "DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT,'Disable pause frame transmitted interrupt'" "0,1"
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bitfld.long 0x0 13. "DISABLE_PAUSE_TIME_ZERO_INTERRUPT,'Disable pause time zero interrupt'" "0,1"
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bitfld.long 0x0 12. "DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT,'Disable pause frame with non-zero pause quantum interrupt'" "0,1"
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bitfld.long 0x0 11. "DISABLE_RESP_NOT_OK_INTERRUPT,'Disable bresp/hresp not OK interrupt'" "0,1"
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bitfld.long 0x0 10. "DISABLE_RECEIVE_OVERRUN_INTERRUPT,'Disable receive overrun interrupt'" "0,1"
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bitfld.long 0x0 9. "UNUSED_9,Not used" "0,1"
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bitfld.long 0x0 8. "UNUSED_8,Not used" "0,1"
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bitfld.long 0x0 7. "DISABLE_TRANSMIT_COMPLETE_INTERRUPT,'Disable transmit complete interrupt'" "0,1"
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bitfld.long 0x0 6. "DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT,'Disable transmit frame corruption due to AMBA (AHB/AXI) error interrupt'" "0,1"
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bitfld.long 0x0 5. "DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT,'Disable retry limit exceeded or late collision interrupt'" "0,1"
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bitfld.long 0x0 4. "DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT,'Disable transmit buffer under run interrupt'" "0,1"
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bitfld.long 0x0 3. "DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT,'Disable transmit used bit read interrupt'" "0,1"
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bitfld.long 0x0 2. "DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT,'Disable receive used bit read interrupt'" "0,1"
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bitfld.long 0x0 1. "DISABLE_RECEIVE_COMPLETE_INTERRUPT,'Disable receive complete interrupt'" "0,1"
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bitfld.long 0x0 0. "DISABLE_MANAGEMENT_DONE_INTERRUPT,'Disable management done interrupt'" "0,1"
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rgroup.long 0x1030++0x3
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line.long 0x0 "INT_MASK,The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt.."
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bitfld.long 0x0 29. "TSU_TIMER_COMPARISON_MASK,Enable TSU timer comparison interrupt mask." "0,1"
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bitfld.long 0x0 28. "UNUSED_28,unused" "0,1"
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bitfld.long 0x0 27. "RX_LPI_INDICATION_MASK,A read of this register returns the value of the RX LPI indication mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 26. "TSU_SECONDS_REGISTER_INCREMENT_MASK,A read of this register returns the value of the TSU seconds register increment mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 25. "PTP_PDELAY_RESP_FRAME_TRANSMITTED_MASK,A read of this register returns the value of the PTP pdelay_resp frame transmitted mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 24. "PTP_PDELAY_REQ_FRAME_TRANSMITTED_MASK,A read of this register returns the value of the PTP pdelay_req frame transmitted mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 23. "PTP_PDELAY_RESP_FRAME_RECEIVED_MASK,A read of this register returns the value of the PTP pdelay_resp frame received mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 22. "PTP_PDELAY_REQ_FRAME_RECEIVED_MASK,A read of this register returns the value of the PTP pdelay_req frame received mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 21. "PTP_SYNC_FRAME_TRANSMITTED_MASK,A read of this register returns the value of the PTP sync frame transmitted mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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newline
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bitfld.long 0x0 20. "PTP_DELAY_REQ_FRAME_TRANSMITTED_MASK,A read of this register returns the value of the PTP delay_req frame transmitted mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 19. "PTP_SYNC_FRAME_RECEIVED_MASK,A read of this register returns the value of the PTP sync frame received mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 18. "PTP_DELAY_REQ_FRAME_RECEIVED_MASK,A read of this register returns the value of the PTP delay_req frame received mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 17. "UNUSED_17,Not used" "0,1"
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bitfld.long 0x0 16. "UNUSED_16,Not used" "0,1"
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bitfld.long 0x0 15. "UNUSED_15,Not used" "0,1"
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bitfld.long 0x0 14. "PAUSE_FRAME_TRANSMITTED_INTERRUPT_MASK,pause frame transmitted interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 13. "PAUSE_TIME_ZERO_INTERRUPT_MASK,pause time zero interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 12. "PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_MASK,pause frame with non-zero pause quantum interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 11. "RESP_NOT_OK_INTERRUPT_MASK,bresp not OK interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 10. "RECEIVE_OVERRUN_INTERRUPT_MASK,receive overrun interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 9. "UNUSED_9,Not used" "0,1"
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bitfld.long 0x0 8. "UNUSED_8,Not used" "0,1"
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bitfld.long 0x0 7. "TRANSMIT_COMPLETE_INTERRUPT_MASK,transmit complete interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 6. "AMBA_ERROR_INTERRUPT_MASK,transmit frame corruption due to AMBA (AXI) error interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 5. "RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_MASK,A read of this register returns the value of the retry limit exceeded or late collision (gigabit mode only) interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 4. "TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_MASK,transmit buffer under run interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 3. "TRANSMIT_USED_BIT_READ_INTERRUPT_MASK,transmit used bit read interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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|
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bitfld.long 0x0 2. "RECEIVE_USED_BIT_READ_INTERRUPT_MASK,receive used bit read interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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newline
|
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bitfld.long 0x0 1. "RECEIVE_COMPLETE_INTERRUPT_MASK,receive complete interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 0. "MANAGEMENT_DONE_INTERRUPT_MASK,management done interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
|
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group.long 0x1034++0x3
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line.long 0x0 "PHY_MANAGEMENT,The PHY maintenance register is implemented as a shift register. Writing to the register starts a shift operation which is signalled as complete when bit-2 is set in the network status register. It takes about 2000 pclk cycles to complete..."
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bitfld.long 0x0 31. "WRITE0,Must be written with 0." "0,1"
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bitfld.long 0x0 30. "WRITE1,Must be written to 1 for a valid Clause 22 frame and to 0 for a valid Clause 45 frame." "0,1"
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bitfld.long 0x0 28.--29. "OPERATION,Operation. For a Clause 45 frame: 00 is an addr 01 is a write 10 is a post read increment 11 is a read frame. For a Clause 22 frame: 10 is a read 01 is a write." "0,1,2,3"
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hexmask.long.byte 0x0 23.--27. 1. "PHY_ADDRESS,PHY address."
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hexmask.long.byte 0x0 18.--22. 1. "REGISTER_ADDRESS,Register address - specifies the register in the PHY to access."
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bitfld.long 0x0 16.--17. "WRITE10,Must be written with 10." "0,1,2,3"
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hexmask.long.word 0x0 0.--15. 1. "PHY_WRITE_READ_DATA,For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY."
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rgroup.long 0x1038++0x3
|
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line.long 0x0 "PAUSE_TIME,Received Pause Quantum Register"
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hexmask.long.word 0x0 0.--15. 1. "QUANTUM,Received pause quantum - stores the current value of the received pause quantum register which is decremented every 512 bit times."
|
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group.long 0x103C++0xF
|
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line.long 0x0 "TX_PAUSE_QUANTUM,Transmit Pause Quantum Register"
|
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hexmask.long.word 0x0 16.--31. 1. "QUANTUM_P1,Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 1."
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|
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hexmask.long.word 0x0 0.--15. 1. "QUANTUM,Transmit pause quantum - written with the pause quantum value for pause frame transmission."
|
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line.long 0x4 "PBUF_TXCUTTHRU,Partial store and forward is only applicable when using the DMA configured in SRAM based packet buffer mode. It is also not available when using multi buffer frames. TX Partial Store and Forward"
|
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bitfld.long 0x4 31. "DMA_TX_CUTTHRU,Enable TX partial store and forward operation" "0,1"
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hexmask.long.word 0x4 0.--8. 1. "DMA_TX_CUTTHRU_THRESHOLD,Watermark value. This value must be >= 0x9. The reset value depends on the value of the configuration option `gem_tx_pbuf_addr which is defined in the verilog defs configuration file. The value chosen for the generation of the.."
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line.long 0x8 "PBUF_RXCUTTHRU,RX Partial Store and Forward"
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bitfld.long 0x8 31. "DMA_RX_CUTTHRU,Enable RX partial store and forward operation" "0,1"
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hexmask.long.byte 0x8 0.--7. 1. "DMA_RX_CUTTHRU_THRESHOLD,Watermark value. The reset value depends on the value of the configuration option `gem_rx_pbuf_addr which is defined in the verilog defs configuration file. The value chosen for the generation of the userguide was.."
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line.long 0xC "JUMBO_MAX_LENGTH,Maximum Jumbo Frame Size."
|
|
hexmask.long.word 0xC 0.--13. 1. "JUMBO_MAX_LENGTH,Maximum Jumbo Frame Size - resets to the gem_jumbo_max_length define value."
|
|
rgroup.long 0x104C++0x3
|
|
line.long 0x0 "EXTERNAL_FIFO_INTERFACE,Not presents."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
group.long 0x1054++0x3
|
|
line.long 0x0 "AXI_MAX_PIPELINE,Used to set the maximum amount of outstanding transactions on the AXI bus between AR / R channels and AW / W channels. Cannot be more than the depth of the configured AXI pipeline FIFO (defined in verilog defs.v)"
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|
bitfld.long 0x0 16. "USE_AW2B_FILL,For the write issuing capability as defined in bits 15:8 of this register select whether the max number of transactions operates between the AW to W AXI channel or the AW to B channel. Set to 0 to operate between the AW and W channels. Set.." "0,1"
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|
newline
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|
hexmask.long.byte 0x0 8.--15. 1. "AW2W_MAX_PIPELINE,Defines the maximum number of outstanding AXI write requests that can be issued by the DMA via the AW channel."
|
|
newline
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hexmask.long.byte 0x0 0.--7. 1. "AR2R_MAX_PIPELINE,Defines the maximum number of outstanding AXI read requests that can be issued by the DMA via the AR channel."
|
|
rgroup.long 0x1058++0x3
|
|
line.long 0x0 "RSC_CONTROL,Not presents. Access to the register will return AHB error."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
group.long 0x105C++0x7
|
|
line.long 0x0 "INT_MODERATION,Used to moderate the number of transmit and receive complete interrupts issued. With interrupt moderation enabled receive and transmit interrupts are not generated immediately a frame is transmitted or received. Instead when a receive or.."
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|
hexmask.long.byte 0x0 16.--23. 1. "TX_INT_MODERATION,Count of 800ns periods before bit 7 is set in the interrupt status register after a frame is transmitted. A non-zero value indicates transmit interrupt moderation will be performed."
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|
newline
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hexmask.long.byte 0x0 0.--7. 1. "RX_INT_MODERATION,Count of 800ns periods before bit 1 is set in the interrupt status register after a frame is received. A non-zero value indicates receive interrupt moderation will be performed."
|
|
line.long 0x4 "SYS_WAKE_TIME,Used to pause transmission after deassertion of tx_lpi_en. Each unit in this register corresponds to 64ns in gigabit mode. 320ns in 100M mode and 3200ns at 10M. After tx_lpi_en is deasserted transmission will pause for the set time."
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|
hexmask.long.word 0x4 0.--15. 1. "SYS_WAKE_TIME,Count of 64ns 320ns or 3200ns intervals before transmission starts after deassertion of tx_lpi_en (each interval is equivalent to eight tx_clk periods and so varies with data rate)."
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|
group.long 0x1080++0x67
|
|
line.long 0x0 "HASH_BOTTOM,The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames. Hash Register Bottom (31 to 0 bits)"
|
|
hexmask.long 0x0 0.--31. 1. "ADDRESS_HASH_B,The first 32 bits of the hash address register."
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|
line.long 0x4 "HASH_TOP,Hash Register Top (63 to 32 bits)"
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|
hexmask.long 0x4 0.--31. 1. "ADDRESS_HASH_T,The remaining 32 bits of the hash address register."
|
|
line.long 0x8 "SPEC_ADD1_BOTTOM,The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written."
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|
hexmask.long 0x8 0.--31. 1. "ADDRESS_ADD1_B,'Least significant 32 bits of the destination address that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.'"
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|
line.long 0xC "SPEC_ADD1_TOP,Specific Address Top"
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|
bitfld.long 0xC 16. "FILTER_TYPE,This control bit selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame. When set to zero the filter is a destination address filter. When set to one the filter.." "0,1"
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|
newline
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|
hexmask.long.word 0xC 0.--15. 1. "ADDRESS_TOP,Specific address 1. The most significant bits of the destination/source address that is to be compared that is bits 47:32."
|
|
line.long 0x10 "SPEC_ADD2_BOTTOM,The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written."
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|
hexmask.long 0x10 0.--31. 1. "ADDRESS_BOTTOM,Least significant 32 bits of the destination address that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received."
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|
line.long 0x14 "SPEC_ADD2_TOP,Specific Address Top"
|
|
hexmask.long.byte 0x14 24.--29. 1. "FILTER_BYTE_MASK,When high the associated byte of the specific address will not be compared. Bit 24 controls whether the first byte received should be compared. Bit 29 controls whether the last byte received should be compared."
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|
newline
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bitfld.long 0x14 16. "FILTER_TYPE,This control bit selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame. When set to zero the filter is a destination address filter. When set to one the filter.." "0,1"
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|
newline
|
|
hexmask.long.word 0x14 0.--15. 1. "ADDRESS_TOP,Specific address 1. The most significant bits of the destination/source address that is to be compared that is bits 47:32."
|
|
line.long 0x18 "SPEC_ADD3_BOTTOM,The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written."
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|
hexmask.long 0x18 0.--31. 1. "ADDRESS_BOTTOM,Least significant 32 bits of the destination address that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received."
|
|
line.long 0x1C "SPEC_ADD3_TOP,Specific Address Top"
|
|
hexmask.long.byte 0x1C 24.--29. 1. "FILTER_BYTE_MASK,When high the associated byte of the specific address will not be compared. Bit 24 controls whether the first byte received should be compared. Bit 29 controls whether the last byte received should be compared."
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|
newline
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bitfld.long 0x1C 16. "FILTER_TYPE,This control bit selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame. When set to zero the filter is a destination address filter. When set to one the filter.." "0,1"
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|
newline
|
|
hexmask.long.word 0x1C 0.--15. 1. "ADDRESS_TOP,Specific address 1. The most significant bits of the destination/source address that is to be compared that is bits 47:32."
|
|
line.long 0x20 "SPEC_ADD4_BOTTOM,The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written."
|
|
hexmask.long 0x20 0.--31. 1. "ADDRESS_BOTTOM,Least significant 32 bits of the destination address that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received."
|
|
line.long 0x24 "SPEC_ADD4_TOP,Specific Address Top"
|
|
hexmask.long.byte 0x24 24.--29. 1. "FILTER_BYTE_MASK,When high the associated byte of the specific address will not be compared. Bit 24 controls whether the first byte received should be compared. Bit 29 controls whether the last byte received should be compared."
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|
newline
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bitfld.long 0x24 16. "FILTER_TYPE,This control bit selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame. When set to zero the filter is a destination address filter. When set to one the filter.." "0,1"
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|
newline
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|
hexmask.long.word 0x24 0.--15. 1. "ADDRESS_TOP,Specific address 1. The most significant bits of the destination/source address that is to be compared that is bits 47:32."
|
|
line.long 0x28 "SPEC_TYPE1,Type ID Match 1"
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|
bitfld.long 0x28 31. "ENABLE_COPY,Enable copying of type ID match 1 matched frames." "0,1"
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|
newline
|
|
hexmask.long.word 0x28 0.--15. 1. "MATCH,Type ID match 1. For use in comparisons with received frames type ID/length field."
|
|
line.long 0x2C "SPEC_TYPE2,Type ID Match 2"
|
|
bitfld.long 0x2C 31. "ENABLE_COPY,Enable copying of type ID match 2 matched frames." "0,1"
|
|
newline
|
|
hexmask.long.word 0x2C 0.--15. 1. "MATCH,Type ID match 2. For use in comparisons with received frames type ID/length field."
|
|
line.long 0x30 "SPEC_TYPE3,Type ID Match 3"
|
|
bitfld.long 0x30 31. "ENABLE_COPY,Enable copying of type ID match 3 matched frames." "0,1"
|
|
newline
|
|
hexmask.long.word 0x30 0.--15. 1. "MATCH,Type ID match 3. For use in comparisons with received frames type ID/length field."
|
|
line.long 0x34 "SPEC_TYPE4,Type ID Match 4"
|
|
bitfld.long 0x34 31. "ENABLE_COPY,Enable copying of type ID match 4 matched frames." "0,1"
|
|
newline
|
|
hexmask.long.word 0x34 0.--15. 1. "MATCH,Type ID match 4. For use in comparisons with received frames type ID/length field."
|
|
line.long 0x38 "WOL_REGISTER,Wake on LAN Register. Presents in design. but feature is not supported."
|
|
bitfld.long 0x38 19. "WOL_MASK_3,Wake on LAN multicast hash event enable. When set multicast hash events will cause the wol output to be asserted." "0,1"
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|
newline
|
|
bitfld.long 0x38 18. "WOL_MASK_2,Wake on LAN specific address register 1 event enable. When set specific address 1 events will cause the wol output to be asserted." "0,1"
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|
newline
|
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bitfld.long 0x38 17. "WOL_MASK_1,Wake on LAN ARP request event enable. When set ARP request events will cause the wol output to be asserted." "0,1"
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|
newline
|
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bitfld.long 0x38 16. "WOL_MASK_0,Wake on LAN magic packet event enable. When set magic packet events will cause the wol output to be asserted." "0,1"
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|
newline
|
|
hexmask.long.word 0x38 0.--15. 1. "ADDR,Wake on LAN ARP request IP address. Written to define the least significant 16 bits of the target IP address that is matched to generate a Wake on LAN event. A value of zero will not generate an event even if this is matched by the received frame."
|
|
line.long 0x3C "STRETCH_RATIO,IPG stretch register"
|
|
hexmask.long.word 0x3C 0.--15. 1. "IPG_STRETCH,IPG Stretch. Bits 7:0 are multiplied with the previously transmitted frame length (including preamble) bits 15:8 +1 divide the frame length. If the resulting number is greater than 96 and bit 28 is set in the network configuration register.."
|
|
line.long 0x40 "STACKED_VLAN,Stacked VLAN Register"
|
|
bitfld.long 0x40 31. "ENABLE_PROCESSING,Enable stacked VLAN processing mode" "0,1"
|
|
newline
|
|
hexmask.long.word 0x40 0.--15. 1. "MATCH,User defined VLAN_TYPE field. When Stacked VLAN is enabled the first VLAN tag in a received frame will only be accepted if the VLAN type field is equal to this user defined VLAN_TYPE OR equal to the standard VLAN type (0x8100). Note that the.."
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line.long 0x44 "TX_PFC_PAUSE,Transmit PFC Pause Register"
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hexmask.long.byte 0x44 8.--15. 1. "VECTOR,Priority Vector Pause Size. If bit 17 of the network control register is written with a one then for each entry equal to zero in the Transmit PFC Pause Register[15:8] the PFC pause frame's pause quantum field associated with that entry will be.."
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|
newline
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hexmask.long.byte 0x44 0.--7. 1. "VECTOR_ENABLE,Priority Vector Enable. If bit 17 of the network control register is written with a one then the priority enable vector of the PFC priority based pause frame will be set equal to the value stored in this register [7:0]."
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|
line.long 0x48 "MASK_ADD1_BOTTOM,Specific Address Mask 1 Bottom (31 to 0 bits)"
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|
hexmask.long 0x48 0.--31. 1. "ADDRESS_MASK_BOTTOM,Specific Address Mask. Setting a bit to one masks the corresponding bit in the specific address 1 register (31 to 0 bits)"
|
|
line.long 0x4C "MASK_ADD1_TOP,Specific Address Mask 1 Top (47 to 32 bits)"
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hexmask.long.word 0x4C 0.--15. 1. "ADDRESS_MASK_TOP,Specific Address Mask. Setting a bit to one masks the corresponding bit in the specific address 1 register (47 to 32 bits)."
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|
line.long 0x50 "DMA_ADDR_OR_MASK,Receive DMA Data Buffer Address Mask"
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hexmask.long.byte 0x50 28.--31. 1. "MASK_VALUE_DA,Data Buffer Address Mask Value. Values used to force bits 31:28 of the receive data buffer AHB address to a particular value when the associated enable bits stored in this register [3:0] are set. Any changes to this register will be ignored.."
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newline
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hexmask.long.byte 0x50 0.--3. 1. "MASK_ENABLE,Data Buffer Address Mask Enable. These bits are associated directly with bits[31:28].When bit 0 is set the AXI/AHB address bit 28 used for accessing the receive data buffers will be forced to the value stored in bit 28 of this register. When.."
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|
line.long 0x54 "RX_PTP_UNICAST,PTP RX unicast IP destination address"
|
|
hexmask.long 0x54 0.--31. 1. "ADDRESS_UNICAST,Unicast IP destination address. Used for detection of PTP frames on receive path."
|
|
line.long 0x58 "TX_PTP_UNICAST,PTP TX unicast IP destination address"
|
|
hexmask.long 0x58 0.--31. 1. "ADDRESS_UNICAST,Unicast IP destination address. Used for detection of PTP frames on transmit path."
|
|
line.long 0x5C "TSU_NSEC_CMP,TSU timer comparison value nanoseconds"
|
|
hexmask.long.tbyte 0x5C 0.--21. 1. "COMPARISON_NSEC,TSU timer comparison value (ns). Value is compared to the bits[45:24] of the TSU timer count value (upper 22 bits of nanosecond value)."
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line.long 0x60 "TSU_SEC_CMP,TSU timer comparison value seconds (31 to 0 bits)"
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hexmask.long 0x60 0.--31. 1. "COMPARISON_SEC,TSU timer comparison value (s). Value is compared to seconds value bits [31:0] of the TSU timer count value."
|
|
line.long 0x64 "TSU_MSB_SEC_CMP,TSU timer comparison value seconds (47 to 32 bits)"
|
|
hexmask.long.word 0x64 0.--15. 1. "COMPARISON_MSB_SEC,TSU timer comparison value (s). Value is compared to the top 16 bits (most significant 16-bits {47:32] of seconds value) of the TSU timer count value."
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|
rgroup.long 0x10E8++0xF
|
|
line.long 0x0 "TSU_PTP_TX_MSB_SEC,PTP Event Frame Transmitted Seconds Register (47 to 32 bits)"
|
|
hexmask.long.word 0x0 0.--15. 1. "TIMER_SECONDS,PTP Event Frame TX Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame.."
|
|
line.long 0x4 "TSU_PTP_RX_MSB_SEC,PTP Event Frame Received Seconds Register (47 to 32 bits)"
|
|
hexmask.long.word 0x4 0.--15. 1. "TIMER_SECONDS,PTP Event Frame TX Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP receive primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame.."
|
|
line.long 0x8 "TSU_PEER_TX_MSB_SEC,PTP Peer Event Frame Transmitted Seconds Register (47 to 32 bits)"
|
|
hexmask.long.word 0x8 0.--15. 1. "TIMER_SECONDS,PTP Peer Event Frame TX Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit peer event crosses the MII interface. The actual update occurs when the GEM recognizes the.."
|
|
line.long 0xC "TSU_PEER_RX_MSB_SEC,PTP Peer Event Frame Received Seconds Register (47 to 32 bits)"
|
|
hexmask.long.word 0xC 0.--15. 1. "TIMER_SECONDS,PTP Peer Event Frame RX Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP receive peer event crosses the MII interface. The actual update occurs when the GEM recognizes the frame.."
|
|
group.long 0x10F8++0x3
|
|
line.long 0x0 "DPRAM_FILL_DBG,The fill levels for the TX & RX packet buffers can be read using this register. including the fill level for each queue in the TX direction."
|
|
hexmask.long.word 0x0 16.--31. 1. "DMA_TX_RX_FILL_LEVEL,Fill Level - TX or RX packet buffer fill level selected by the tx_q_fill_level_select and tx_rx_fill_level_select registers. Read this register to determine the fill level."
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "DMA_TX_Q_FILL_LEVEL_SELECT,TX queue fill level select - select what TX queue to report fill levels for."
|
|
newline
|
|
bitfld.long 0x0 0. "DMA_TX_RX_FILL_LEVEL_SELECT,TX/RX Fill Level select - report the fill level for the TX or RX packet buffer." "0,1"
|
|
rgroup.long 0x10FC++0xBB
|
|
line.long 0x0 "REVISION_REG,This register indicates a Cadence module identification number and module revision. The value of this register is read only as defined by `gem_revision_reg_value"
|
|
hexmask.long.byte 0x0 28.--31. 1. "FIX_NUMBER,Fix number - incremented for fix releases."
|
|
newline
|
|
hexmask.long.word 0x0 16.--27. 1. "MODULE_IDENTIFICATION_NUMBER,Module identification number - for the GEM this value is fixed."
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "MODULE_REVISION,Module revision - fixed value specific to the revision of the design which is incremented for each non-fix release of the IP."
|
|
line.long 0x4 "OCTETS_TXED_BOTTOM,Octets Transmitted lower bits (31 to 0 bits)"
|
|
hexmask.long 0x4 0.--31. 1. "COUNT_BOTTOM,Transmitted octets in frame without errors [31:0]. The number of octets transmitted in valid frames of any type. This counter is 48-bits and is read through two registers. This count does not include octets from automatically generated.."
|
|
line.long 0x8 "OCTETS_TXED_TOP,Octets Transmitted higher bits (47 to 32 bits)"
|
|
hexmask.long.word 0x8 0.--15. 1. "COUNT_TOP,Transmitted octets in frame without errors [47:32]. The number of octets transmitted in valid frames of any type. This counter is 48-bits and is read through two registers. This count does not include octets from automatically generated pause.."
|
|
line.long 0xC "FRAMES_TXED_OK,Frames Transmitted"
|
|
hexmask.long 0xC 0.--31. 1. "COUNT_OK,Frames transmitted without error. A 32 bit register counting the number of frames successfully transmitted i.e. no under run and not too many retries. Excludes pause frames."
|
|
line.long 0x10 "BROADCAST_TXED,Broadcast Frames Transmitted"
|
|
hexmask.long 0x10 0.--31. 1. "COUNT_BROADCAST,Broadcast frames transmitted without error. A 32 bit register counting the number of broadcast frames successfully transmitted without error i.e. no under run and not too many retries. Excludes pause frames."
|
|
line.long 0x14 "MULTICAST_TXED,Multicast Frames Transmitted"
|
|
hexmask.long 0x14 0.--31. 1. "COUNT_MULTICAST,Multicast frames transmitted without error. A 32 bit register counting the number of multicast frames successfully transmitted without error i.e. no under run and not too many retries. Excludes pause frames."
|
|
line.long 0x18 "PAUSE_FRAMES_TXED,Pause Frames Transmitted"
|
|
hexmask.long.word 0x18 0.--15. 1. "COUNT_PAUSE,Transmitted pause frames - a 16 bit register counting the number of pause frames transmitted. Only pause frames triggered by the register interface or through the external pause pins are counted as pause frames. Pause frames received through.."
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|
line.long 0x1C "FRAMES_TXED_64,64 Byte Frames Transmitted"
|
|
hexmask.long 0x1C 0.--31. 1. "COUNT_64,64 byte frames transmitted without error. A 32 bit register counting the number of 64 byte frames successfully transmitted without error i.e. no under run and not too many retries. Excludes pause frames."
|
|
line.long 0x20 "FRAMES_TXED_65,65 to 127 Byte Frames Transmitted"
|
|
hexmask.long 0x20 0.--31. 1. "COUNT_65,65 to127 byte frames transmitted without error. A 32 bit register counting the number of 65 to127 byte frames successfully transmitted without error i.e. no under run and not too many retries."
|
|
line.long 0x24 "FRAMES_TXED_128,128 to 255 Byte Frames Transmitted"
|
|
hexmask.long 0x24 0.--31. 1. "COUNT_128,128 to 255 byte frames transmitted without error. A 32 bit register counting the number of 128 to 255 byte frames successfully transmitted without error i.e. no under run and not too many retries."
|
|
line.long 0x28 "FRAMES_TXED_256,256 to 511 Byte Frames Transmitted"
|
|
hexmask.long 0x28 0.--31. 1. "COUNT_256,256 to 511 byte frames transmitted without error. A 32 bit register counting the number of 256 to 511 byte frames successfully transmitted without error i.e. no under run and not too many retries."
|
|
line.long 0x2C "FRAMES_TXED_512,512 to 1023 Byte Frames Transmitted"
|
|
hexmask.long 0x2C 0.--31. 1. "COUNT_512,512 to 1023 byte frames transmitted without error. A 32 bit register counting the number of 512 to 1023 byte frames successfully transmitted without error i.e. no under run and not too many retries."
|
|
line.long 0x30 "FRAMES_TXED_1024,1024 to 1518 Byte Frames Transmitted"
|
|
hexmask.long 0x30 0.--31. 1. "COUNT_1024,1024 to 1518 byte frames transmitted without error. A 32 bit register counting the number of 1024 to 1518 byte frames successfully transmitted without error i.e. no under run and not too many retries."
|
|
line.long 0x34 "FRAMES_TXED_1519,Greater Than 1518 Byte Frames Transmitted"
|
|
hexmask.long 0x34 0.--31. 1. "COUNT_1519,Greater than 1518 byte frames transmitted without error. A 32 bit register counting the number of 1518 or above byte frames successfully transmitted without error i.e. no under run and not too many retries."
|
|
line.long 0x38 "TX_UNDERRUNS,Transmit Under Runs"
|
|
hexmask.long.word 0x38 0.--9. 1. "COUNT_UN,Transmit under runs - a 10 bit register counting the number of frames not transmitted due to a transmit under run. If this register is incremented then no other statistics register is incremented."
|
|
line.long 0x3C "SINGLE_COLLISIONS,Single Collision Frames. Presents in design but not support."
|
|
hexmask.long.tbyte 0x3C 0.--17. 1. "COUNT14,Single collision frames - an 18 bit register counting the number of frames experiencing a single collision before being successfully transmitted i.e. no under run."
|
|
line.long 0x40 "MULTIPLE_COLLISIONS,Multiple Collision Frames. Presents in design but not support."
|
|
hexmask.long.tbyte 0x40 0.--17. 1. "COUNT15,Multiple collision frames - an 18 bit register counting the number of frames experiencing between two and fifteen collisions prior to being successfully transmitted i.e. no under run and not too many retries."
|
|
line.long 0x44 "EXCESSIVE_COLLISIONS,Excessive Collisions. Presents in design but not support."
|
|
hexmask.long.word 0x44 0.--9. 1. "COUNT16,Excessive collisions - a 10 bit register counting the number of frames that failed to be transmitted because they experienced 16 collisions."
|
|
line.long 0x48 "LATE_COLLISIONS,Late Collisions. Presents in design but not support."
|
|
hexmask.long.word 0x48 0.--9. 1. "COUNT17,Late collisions - a 10 bit register counting the number of late collision occurring after the slot time (512 bits) has expired. In 10/100 mode late collisions are counted twice i.e. both as a collision and a late collision. In gigabit mode a.."
|
|
line.long 0x4C "DEFERRED_FRAMES,Deferred Transmission Frames. Presents in design but not support."
|
|
hexmask.long.tbyte 0x4C 0.--17. 1. "COUNT18,Deferred transmission frames - an 18 bit register counting the number of frames experiencing deferral due to carrier sense being active on their first attempt at transmission. Frames involved in any collision are not counted nor are frames that.."
|
|
line.long 0x50 "CRS_ERRORS,Carrier Sense Errors. Presents in design but not support."
|
|
hexmask.long.word 0x50 0.--9. 1. "COUNT19,Carrier sense errors - a 10 bit register counting the number of frames transmitted where carrier sense was not seen during transmission or where carrier sense was deasserted after being asserted in a transmit frame without collision (no under.."
|
|
line.long 0x54 "OCTETS_RXED_BOTTOM,Octets Received (31 to 0 bits)"
|
|
hexmask.long 0x54 0.--31. 1. "COUNT_BOTTOM,Received octets in frame without errors [31:0]. The number of octets received in valid frames of any type. This counter is 48-bits and is read through two registers. This count does not include octets from pause frames and is only.."
|
|
line.long 0x58 "OCTETS_RXED_TOP,Octets Received (47 to 32 bits)"
|
|
hexmask.long.word 0x58 0.--15. 1. "COUNT_TOP,Received octets in frame without errors [47:32]. The number of octets received in valid frames of any type. This counter is 48-bits and is read through two registers. This count does not include octets from pause frames and is only incremented.."
|
|
line.long 0x5C "FRAMES_RXED_OK,Frames Received"
|
|
hexmask.long 0x5C 0.--31. 1. "COUNT_OK,Frames received without error. A 32 bit register counting the number of frames successfully received. Excludes pause frames and is only incremented if the frame is successfully filtered."
|
|
line.long 0x60 "BROADCAST_RXED,Broadcast Frames Received"
|
|
hexmask.long 0x60 0.--31. 1. "COUNT_BROADCAST,Broadcast frames received without error. A 32 bit register counting the number of broadcast frames successfully received without error. Excludes pause frames and is only incremented if the frame is successfully filtered."
|
|
line.long 0x64 "MULTICAST_RXED,Multicast Frames Received"
|
|
hexmask.long 0x64 0.--31. 1. "COUNT_MULTICAST,Multicast frames received without error. A 32 bit register counting the number of multicast frames successfully received without error. Excludes pause frames and is only incremented if the frame is successfully filtered."
|
|
line.long 0x68 "PAUSE_FRAMES_RXED,Pause Frames Received"
|
|
hexmask.long.word 0x68 0.--15. 1. "COUNT_PAUSE,Received pause frames - a 16 bit register counting the number of pause frames received without error."
|
|
line.long 0x6C "FRAMES_RXED_64,64 Byte Frames Received"
|
|
hexmask.long 0x6C 0.--31. 1. "COUNT_64,64 byte frames received without error. A 32 bit register counting the number of 64 byte frames successfully received without error. Excludes pause frames and is only incremented if the frame is successfully filtered."
|
|
line.long 0x70 "FRAMES_RXED_65,65 to 127 Byte Frames Received"
|
|
hexmask.long 0x70 0.--31. 1. "COUNT_65,65 to 127 byte frames received without error. A 32 bit register counting the number of 65 to 127 byte frames successfully received without error. Excludes pause frames and is only incremented if the frame is successfully filtered."
|
|
line.long 0x74 "FRAMES_RXED_128,128 to 255 Byte Frames Received"
|
|
hexmask.long 0x74 0.--31. 1. "COUNT_128,128 to 255 byte frames received without error. A 32 bit register counting the number of 128 to 255 byte frames successfully received without error. Excludes pause frames and is only incremented if the frame is successfully filtered."
|
|
line.long 0x78 "FRAMES_RXED_256,256 to 511 Byte Frames Received"
|
|
hexmask.long 0x78 0.--31. 1. "COUNT_256,256 to 511 byte frames received without error. A 32 bit register counting the number of 256 to 511 byte frames successfully transmitted without error. Excludes pause frames and is only incremented if the frame is successfully filtered."
|
|
line.long 0x7C "FRAMES_RXED_512,512 to 1023 Byte Frames Received"
|
|
hexmask.long 0x7C 0.--31. 1. "COUNT_512,512 to 1023 byte frames received without error. A 32 bit register counting the number of 512 to 1023 byte frames successfully received without error. Excludes pause frames and is only incremented if the frame is successfully filtered."
|
|
line.long 0x80 "FRAMES_RXED_1024,1024 to 1518 Byte Frames Received"
|
|
hexmask.long 0x80 0.--31. 1. "COUNT_1024,1024 to 1518 byte frames received without error. A 32 bit register counting the number of 1024 to 1518 byte frames successfully received without error. Excludes pause frames and is only incremented if the frame is successfully filtered."
|
|
line.long 0x84 "FRAMES_RXED_1519,1519 to maximum Byte Frames Received"
|
|
hexmask.long 0x84 0.--31. 1. "COUNT_1519,1519 to maximum byte frames received without error. A 32 bit register counting the number of 1519 byte or above frames successfully received without error. Maximum frame size is determined by the network configuration register bit 8 (1536.."
|
|
line.long 0x88 "UNDERSIZE_FRAMES,Undersized Frames Received"
|
|
hexmask.long.word 0x88 0.--9. 1. "COUNT_UNDERSIZE,Undersize frames received - a 10 bit register counting the number of frames received less than 64 bytes in length (10/100 mode or gigabit mode full duplex) that do not have either a CRC error or an alignment error. In gigabit mode half.."
|
|
line.long 0x8C "EXCESSIVE_RX_LENGTH,Oversize Frames Received"
|
|
hexmask.long.word 0x8C 0.--9. 1. "COUNT_OVERSIZE,Oversize frames received - a 10 bit register counting the number of frames received exceeding 1518 bytes (1536 bytes if bit 8 is set in network configuration register 10 240 bytes if bit 3 is set in the network configuration register) in.."
|
|
line.long 0x90 "RX_JABBERS,Jabbers Received"
|
|
hexmask.long.word 0x90 0.--9. 1. "COUNT_JABBERS,Jabbers received - a 10 bit register counting the number of frames received exceeding 1518 bytes (1536 if bit 8 set in network configuration register 10 240 bytes if bit 3 is set in the network configuration register) in length and have.."
|
|
line.long 0x94 "FCS_ERRORS,Frame Check Sequence Errors"
|
|
hexmask.long.word 0x94 0.--9. 1. "COUNT_FCS_ERR,Frame check sequence errors - a 10 bit register counting frames that are an integral number of bytes have bad CRC and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register 10 240 bytes if bit 3 is.."
|
|
line.long 0x98 "RX_LENGTH_ERRORS,Length Field Frame Errors"
|
|
hexmask.long.word 0x98 0.--9. 1. "COUNT_LENGTH_ERR,Length field frame errors - this 10-bit register counts the number of frames received that have a measured length shorter than that extracted from the length field (bytes 13 and 14). This condition is only counted if the value of the.."
|
|
line.long 0x9C "RX_SYMBOL_ERRORS,Receive Symbol Errors"
|
|
hexmask.long.word 0x9C 0.--9. 1. "COUNT_SYMBOL_ERR,Receive symbol errors - a 10-bit register counting the number of frames that had rx_er asserted during reception. For 10/100 mode symbol errors are counted regardless of frame length checks. For gigabit mode the frame must satisfy slot.."
|
|
line.long 0xA0 "ALIGNMENT_ERRORS,Alignment Errors"
|
|
hexmask.long.word 0xA0 0.--9. 1. "COUNT_ALIGNMENT_ERROR,Alignment errors - a 10 bit register counting frames that are not an integral number of bytes long and have bad CRC when their length is truncated to an integral number of bytes and are between 64 and 1518 bytes in length (1536 if.."
|
|
line.long 0xA4 "RX_RESOURCE_ERRORS,Receive Resource Errors"
|
|
hexmask.long.tbyte 0xA4 0.--17. 1. "COUNT_RESOURCE_ERR,Receive resource errors - an 18 bit register counting the number of frames that were successfully received by the MAC (correct address matched frame and adequate slot time) but could not be copied to memory because no receive buffer.."
|
|
line.long 0xA8 "RX_OVERRUNS,Receive Overruns"
|
|
hexmask.long.word 0xA8 0.--9. 1. "COUNT_OVERRUN,Receive overruns - a 10 bit register counting the number of frames that are address recognized but were not copied to memory due to a receive overrun."
|
|
line.long 0xAC "RX_IP_CK_ERRORS,IP Header Checksum Errors"
|
|
hexmask.long.byte 0xAC 0.--7. 1. "COUNT_IPCK_ERR,IP header checksum errors - an 8-bit register counting the number of frames discarded due to an incorrect IP header checksum but are between 64 and 1518 bytes (1536 bytes if bit 8 is set in the network configuration register or 10240.."
|
|
line.long 0xB0 "RX_TCP_CK_ERRORS,TCP Checksum Errors"
|
|
hexmask.long.byte 0xB0 0.--7. 1. "COUNT_TCPCK_ERR,TCP checksum errors - an 8-bit register counting the number of frames discarded due to an incorrect TCP checksum but are between 64 and 1518 bytes (1536 bytes if bit 8 is set in the network configuration register or 10240 bytes if bit 3.."
|
|
line.long 0xB4 "RX_UDP_CK_ERRORS,UDP Checksum Errors"
|
|
hexmask.long.byte 0xB4 0.--7. 1. "COUNT_UDPCK_ERR,UDP checksum errors - an 8-bit register counting the number of frames discarded due to an incorrect UDP checksum but are between 64 and 1518 bytes (1536 bytes if bit 8 is set in the network configuration register or 10240 bytes if bit 3.."
|
|
line.long 0xB8 "AUTO_FLUSHED_PKTS,Receive DMA Flushed Packets"
|
|
hexmask.long.word 0xB8 0.--15. 1. "COUNT_FLUSHED,Flushed RX packets counter. A 16 bit register counting the number of frames that have been flushed from the receive SRAM based packet buffer due to one of the following reasons .1. When partial store and forward mode is enabled or bit 24 of.."
|
|
group.long 0x11BC++0x7
|
|
line.long 0x0 "TSU_TIMER_INCR_SUB_NSEC,1588 Timer Increment Register sub nsec"
|
|
hexmask.long.byte 0x0 24.--31. 1. "SUB_NS_INCR_LSB,These are the least significant bits [7:0] of the sub-ns value by which the 1588 timer will be incremented each clock cycle."
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "SUB_NS_INCR,These are the most significant bits [23:8] of the sub-ns value by which the 1588 timer will be incremented each clock cycle. 24 bits of sub nanosecond precision gives resolution of approximately 5.86E-17 seconds (16 bits gives 15.2.."
|
|
line.long 0x4 "TSU_TIMER_MSB_SEC,1588 Timer Seconds Register (47 to 32 bits)"
|
|
hexmask.long.word 0x4 0.--15. 1. "TIMER_MSB_SEC,TSU timer value (s). Most significant 16 bits of seconds timer count. The register is writeable. The 48-bit counter increments by one when the 1588 nanoseconds counter counts to one second. It may also be incremented or decremented when the.."
|
|
rgroup.long 0x11C4++0xB
|
|
line.long 0x0 "TSU_STROBE_MSB_SEC,1588 Timer Sync Strobe Seconds Register (47 to 32 bits)"
|
|
hexmask.long.word 0x0 0.--15. 1. "STROBE_MSB_SEC,1588 Timer Sync Strobe Seconds. The most significant 16-bit value of the Timer Seconds register captured when gem_tsu_ms and gem_tsu_inc_ctrl are zero."
|
|
line.long 0x4 "TSU_STROBE_SEC,1588 Timer Sync Strobe Seconds Register (31 to 0 bits)"
|
|
hexmask.long 0x4 0.--31. 1. "STROBE_SEC,1588 Timer Sync Strobe Seconds. The lowest significant 32-bit value of the Timer Seconds register captured when gem_tsu_ms and gem_tsu_inc_ctrl are zero."
|
|
line.long 0x8 "TSU_STROBE_NSEC,1588 Timer Sync Strobe Nanoseconds Register"
|
|
hexmask.long 0x8 0.--29. 1. "STROBE_NSEC,1588 Timer Sync Strobe Nanoseconds. The value of the Timer Nanoseconds register captured when gem_tsu_ms and gem_tsu_inc_ctrl are zero."
|
|
group.long 0x11D0++0x7
|
|
line.long 0x0 "TSU_TIMER_SEC,1588 Timer Seconds Register (31 to 0 bits)"
|
|
hexmask.long 0x0 0.--31. 1. "TIMER_SEC,1588 Timer Seconds Register. TSU timer value (s). Least significant 32 bits of seconds timer count. This register is writeable. The 48-bit counter increments by one when the 1588 nanoseconds counter counts to one second. It may also be.."
|
|
line.long 0x4 "TSU_TIMER_NSEC,1588 Timer Nanoseconds Register"
|
|
hexmask.long 0x4 0.--29. 1. "TIMER_NSEC,Timer count in nanoseconds. This register is writeable. It can also be adjusted by writes to the 1588 timer adjust register. It increments by the value of the 1588 timer increment register each clock cycle (if this register is close to zero.."
|
|
wgroup.long 0x11D8++0x3
|
|
line.long 0x0 "TSU_TIMER_ADJUST,This register is used to adjust the value of the timer in the TSU. It allows an integral number of nanoseconds to be added or subtracted from the timer in a one-off operation. This register returns all zeroes when read."
|
|
bitfld.long 0x0 31. "ADD_SUBTRACT,Write as one to subtract from the 1588 timer. Write as zero to add to it." "0,1"
|
|
newline
|
|
hexmask.long 0x0 0.--29. 1. "INCREMENT_VALUE,Timer increment value. The number of nanoseconds to increment or decrement the 1588 timer nanoseconds register. If necessary the 1588 seconds register will be incremented or decremented."
|
|
group.long 0x11DC++0x3
|
|
line.long 0x0 "TSU_TIMER_INCR,1588 Timer Increment Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "NUM_INCS,Number of incs before alt inc. The number of increments after which the alternative increment is used."
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "ALT_NS_INCR,Alternative nanoseconds count. Alternative count of nanoseconds by which the 1588 timer nanoseconds register will be incremented each clock cycle."
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "NS_INCREMENT,A count of nanoseconds by which the 1588 timer nanoseconds register will be incremented each clock cycle. These are the most significant 8 bits of the 32 bit timer_increment counter. The tsu_timer_incr_sub_nsec register holds the least.."
|
|
rgroup.long 0x11E0++0x27
|
|
line.long 0x0 "TSU_PTP_TX_SEC,PTP Event Frame Transmitted Seconds Register (31 to 0 bits)"
|
|
hexmask.long 0x0 0.--31. 1. "TIMER_PTP_SEC,PTP Event Frame Transmitted Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit primary event crosses the MII interface. The actual update occurs when the GEM recognizes.."
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|
line.long 0x4 "TSU_PTP_TX_NSEC,PTP Event Frame Transmitted Nanoseconds Register"
|
|
hexmask.long 0x4 0.--29. 1. "TIMER_PTP_NSEC,PTP Event Frame Transmitted Nanoseconds. The register is updated with the value that the 1588 timer nanoseconds register held when the SFD of a PTP transmit primary event crosses the MII interface. The actual update occurs when the GEM.."
|
|
line.long 0x8 "TSU_PTP_RX_SEC,PTP Event Frame Received Seconds Register (31 to 0 bits)"
|
|
hexmask.long 0x8 0.--31. 1. "TIMER_PTP_SEC,PTP Event Frame Received Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP receive primary event crosses the MII interface. The actual update occurs when the GEM recognizes the.."
|
|
line.long 0xC "TSU_PTP_RX_NSEC,PTP Event Frame Received Nanoseconds Register"
|
|
hexmask.long 0xC 0.--29. 1. "TIMER_PTP_NSEC,PTP Event Frame Received Nanoseconds. The register is updated with the value that the 1588 timer nanoseconds register held when the SFD of a PTP receive primary event crosses the MII interface. The actual update occurs when the GEM.."
|
|
line.long 0x10 "TSU_PEER_TX_SEC,PTP Peer Event Frame Transmitted Seconds Register (31 to 0 bits)"
|
|
hexmask.long 0x10 0.--31. 1. "TIMER_PEER_SEC,PTP Peer Event Frame Received Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit peer event crosses the MII interface. The actual update occurs when the GEM recognizes.."
|
|
line.long 0x14 "TSU_PEER_TX_NSEC,PTP Peer Event Frame Transmitted Nanoseconds Register"
|
|
hexmask.long 0x14 0.--29. 1. "TIMER_PEER_NSEC,PTP Peer Event Frame Transmitted Nanoseconds. The register is updated with the value that the 1588 timer nanoseconds register held when the SFD of a PTP transmit peer event crosses the MII interface. The actual update occurs when the GEM.."
|
|
line.long 0x18 "TSU_PEER_RX_SEC,PTP Peer Event Frame Received Seconds Register (31 to 0 bits)"
|
|
hexmask.long 0x18 0.--31. 1. "TIMER_PEER_SEC,PTP Peer Event Frame Received Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP receive peer event crosses the MII interface. The actual update occurs when the GEM recognizes.."
|
|
line.long 0x1C "TSU_PEER_RX_NSEC,PTP Peer Event Frame Received Nanoseconds Register"
|
|
hexmask.long 0x1C 0.--29. 1. "TIMER_PEER_NSEC,PTP Peer Event Frame Received Nanoseconds. The register is updated with the value that the 1588 timer nanoseconds register held when the SFD of a PTP receive peer event crosses the MII interface. The actual update occurs when the GEM.."
|
|
line.long 0x20 "PCS_CONTROL,Not presents. Access to the register returns AHB error."
|
|
hexmask.long 0x20 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
line.long 0x24 "PCS_STATUS,Not presents. Access to the register returns AHB error."
|
|
hexmask.long 0x24 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x1210++0x13
|
|
line.long 0x0 "PCS_AN_ADV,Not presents. Access to the register returns AHB error."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
line.long 0x4 "PCS_AN_LP_BASE,Not presents. Access to the register returns AHB error."
|
|
hexmask.long 0x4 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
line.long 0x8 "PCS_AN_EXP,Not presents. Access to the register returns AHB error."
|
|
hexmask.long 0x8 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
line.long 0xC "PCS_AN_NP_TX,Not presents. Access to the register returns AHB error."
|
|
hexmask.long 0xC 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
line.long 0x10 "PCS_AN_LP_NP,Not presents. Access to the register returns AHB error."
|
|
hexmask.long 0x10 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x123C++0x3
|
|
line.long 0x0 "PCS_AN_EXT_STATUS,Not presents. Access to the register returns AHB error."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
group.long 0x1260++0xB
|
|
line.long 0x0 "TX_PAUSE_QUANTUM1,Transmit Pause Quantum Register 1"
|
|
hexmask.long.word 0x0 16.--31. 1. "QUANTUM_P3,Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 3."
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "QUANTUM_P2,Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 2."
|
|
line.long 0x4 "TX_PAUSE_QUANTUM2,Transmit Pause Quantum Register 2"
|
|
hexmask.long.word 0x4 16.--31. 1. "QUANTUM_P5,Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 5."
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "QUANTUM_P4,Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 4."
|
|
line.long 0x8 "TX_PAUSE_QUANTUM3,Transmit Pause Quantum Register 3"
|
|
hexmask.long.word 0x8 16.--31. 1. "QUANTUM_P7,Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 7."
|
|
newline
|
|
hexmask.long.word 0x8 0.--15. 1. "QUANTUM_P6,Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 6."
|
|
rgroup.long 0x1270++0x37
|
|
line.long 0x0 "RX_LPI,Received LPI transitions"
|
|
hexmask.long.word 0x0 0.--15. 1. "COUNT_LPI,Count of RX LPI transitions. A count of the number of times there is a transition from receiving normal idle to receiving low power idle. Cleared on read."
|
|
line.long 0x4 "RX_LPI_TIME,Received LPI time"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "LPI_TIME,Time in LPI. This register increments once every 16 pclk cycles when the LPI indication bit 20 is set in the receive configuration register. Cleared on read."
|
|
line.long 0x8 "TX_LPI,Transmit LPI transitions"
|
|
hexmask.long.word 0x8 0.--15. 1. "COUNT_LPI,Count of LPI transmissions. A count of the number of times the enable LPI transmission bit 20 goes from low to high in the transmit control register."
|
|
line.long 0xC "TX_LPI_TIME,Transmit LPI time"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "LPI_TIME,Time in LPI. This register increments once every 16 pclk cycles when the enable LPI transmission bit 20 is set in the transmit control register. Cleared on read."
|
|
line.long 0x10 "DESIGNCFG_DEBUG1,The GEM_GXL(3PIP) has many parameterisation options to configure the IP during compilation stage. This is achieved using Verilog define compiler directives in an include file called mxeth_defs.v."
|
|
hexmask.long.byte 0x10 28.--31. 1. "AXI_CACHE_VALUE,Takes the value of the `gem_axi_cache_value DEFINE"
|
|
newline
|
|
bitfld.long 0x10 25.--27. "DMA_BUS_WIDTH,Takes the value of bits 7:5 of the `gem_dma_bus_width DEFINE. So if the define is set to decimal 64 this will return binary 010." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 24. "EXCLUDE_CBS,Takes the value of the `gem_exclude_cbs DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x10 23. "IRQ_READ_CLEAR,Takes the value of the `gem_irq_read_clear DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x10 22. "NO_SNAPSHOT,Takes the value of the `gem_no_snapshot DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x10 21. "NO_STATS,Takes the value of the `gem_no_stats DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x10 20. "RSVD_20,N/A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 15.--19. 1. "USER_IN_WIDTH,Takes the value of the `gem_user_in_width DEFINE `gem_user_io."
|
|
newline
|
|
hexmask.long.byte 0x10 10.--14. 1. "USER_OUT_WIDTH,Takes the value of the `gem_user_out_width DEFINE if `gem_user_io is set."
|
|
newline
|
|
bitfld.long 0x10 9. "USER_IO,Takes the value of the `gem_user_io DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "RSVD_8,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "RSVD_7,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. "EXT_FIFO_INTERFACE,Takes the value of the `gem_ext_fifo_interface DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "RSVD_5,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "INT_LOOPBACK,Takes the value of the `gem_int_loopback DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2.--3. "RSVD_2,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 1. "EXCLUDE_QBV,Takes the value of the `gem_exclude_qbv DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "NO_PCS,Takes the value of the `gem_no_pcs DEFINE" "0,1"
|
|
line.long 0x14 "DESIGNCFG_DEBUG2,Design Configuration Register 2"
|
|
bitfld.long 0x14 31. "SPRAM,Takes the value of the `gem_spram DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x14 30. "AXI,Takes the value of the `gem_axi DEFINE" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x14 26.--29. 1. "TX_PBUF_ADDR,Takes the value of the `gem_tx_pbuf_addr DEFINE"
|
|
newline
|
|
hexmask.long.byte 0x14 22.--25. 1. "RX_PBUF_ADDR,Takes the value of the `gem_rx_pbuf_addr DEFINE"
|
|
newline
|
|
bitfld.long 0x14 21. "TX_PKT_BUFFER,Takes the value of the `gem_tx_pkt_buffer DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x14 20. "RX_PKT_BUFFER,Takes the value of the `gem_rx_pkt_buffer DEFINE" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x14 16.--19. 1. "HPROT_VALUE,Takes the value of the `gem_hprot_value DEFINE"
|
|
newline
|
|
hexmask.long.word 0x14 0.--13. 1. "JUMBO_MAX_LENGTH,Takes the value of the `gem_jumbo_max_length DEFINE"
|
|
line.long 0x18 "DESIGNCFG_DEBUG3,Design Configuration Register 3"
|
|
hexmask.long.byte 0x18 24.--29. 1. "NUM_SPEC_ADD_FILTERS,Takes the value of the `num_spec_add_filters DEFINE"
|
|
line.long 0x1C "DESIGNCFG_DEBUG4,Design Configuration Register 4"
|
|
hexmask.long 0x1C 0.--31. 1. "RSVD_31_0,N/A"
|
|
line.long 0x20 "DESIGNCFG_DEBUG5,Design Configuration Register 5"
|
|
bitfld.long 0x20 29.--31. "AXI_PROT_VALUE,Takes the value of the `gem_axi_prot_value DEFINE" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x20 28. "TSU_CLK,Takes the value of the `gem_tsu_clk DEFINE" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x20 20.--27. 1. "RX_BUFFER_LENGTH_DEF,Takes the value of the `gem_rx_buffer_length_def DEFINE"
|
|
newline
|
|
bitfld.long 0x20 19. "TX_PBUF_SIZE_DEF,Takes the value of the `gem_tx_pbuf_size_def DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x20 17.--18. "RX_PBUF_SIZE_DEF,Takes the value of the `gem_rx_pbuf_size_def DEFINE" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x20 15.--16. "ENDIAN_SWAP_DEF,Takes the value of the `gem_endian_swap_def DEFINE" "0,1,2,3"
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|
newline
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bitfld.long 0x20 12.--14. "MDC_CLOCK_DIV,Takes the value of the `gem_mdc_clock_div DEFINE" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x20 10.--11. "DMA_BUS_WIDTH_DEF,Takes the value of the `gem_dma_bus_width_def DEFINE" "0,1,2,3"
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newline
|
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bitfld.long 0x20 9. "PHY_IDENT,Takes the value of the `gem_phy_ident DEFINE" "0,1"
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|
newline
|
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bitfld.long 0x20 8. "TSU,Takes the value of the `gem_tsu DEFINE" "0,1"
|
|
newline
|
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hexmask.long.byte 0x20 4.--7. 1. "TX_FIFO_CNT_WIDTH,Takes the value of the `gem_tx_fifo_cnt_width DEFINE"
|
|
newline
|
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hexmask.long.byte 0x20 0.--3. 1. "RX_FIFO_CNT_WIDTH,Takes the value of the `gem_rx_fifo_cnt_width DEFINE"
|
|
line.long 0x24 "DESIGNCFG_DEBUG6,Design Configuration Register 6"
|
|
bitfld.long 0x24 27. "PBUF_LSO,Takes the value of the `gem_pbuf_lso DEFINE" "0,1"
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newline
|
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bitfld.long 0x24 26. "PBUF_RSC,Takes the value of the `gem_pbuf_rsc DEFINE" "0,1"
|
|
newline
|
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bitfld.long 0x24 25. "PBUF_CUTTHRU,Takes the value of the `gem_pbuf_cutthru DEFINE" "0,1"
|
|
newline
|
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bitfld.long 0x24 24. "PFC_MULTI_QUANTUM,Takes the value of the `gem_pfc_multi_quantum DEFINE" "0,1"
|
|
newline
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bitfld.long 0x24 23. "DMA_ADDR_WIDTH_IS_64B,Takes the value of the `gem_dma_addr_width_is_64b DEFINE" "0,1"
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|
newline
|
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bitfld.long 0x24 22. "HOST_IF_SOFT_SELECT,Takes the value of the `gem_host_if_soft_select DEFINE" "0,1"
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|
newline
|
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bitfld.long 0x24 21. "TX_ADD_FIFO_IF,Takes the value of the `gem_tx_add_fifo_if DEFINE" "0,1"
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|
newline
|
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bitfld.long 0x24 20. "EXT_TSU_TIMER,Takes the value of the `gem_ext_tsu_timer DEFINE" "0,1"
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|
newline
|
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hexmask.long.byte 0x24 16.--19. 1. "TX_PBUF_QUEUE_SEGMENT_SIZE,Takes the value of the `gem_tx_pbuf_queue_segment_size DEFINE"
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|
newline
|
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bitfld.long 0x24 15. "DMA_PRIORITY_QUEUE15,Takes the value of the `dma_priority_queue15 DEFINE" "0,1"
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|
newline
|
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bitfld.long 0x24 14. "DMA_PRIORITY_QUEUE14,Takes the value of the `dma_priority_queue14 DEFINE" "0,1"
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|
newline
|
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bitfld.long 0x24 13. "DMA_PRIORITY_QUEUE13,Takes the value of the `dma_priority_queue13 DEFINE" "0,1"
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|
newline
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bitfld.long 0x24 12. "DMA_PRIORITY_QUEUE12,Takes the value of the `dma_priority_queue12 DEFINE" "0,1"
|
|
newline
|
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bitfld.long 0x24 11. "DMA_PRIORITY_QUEUE11,Takes the value of the `dma_priority_queue11 DEFINE" "0,1"
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|
newline
|
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bitfld.long 0x24 10. "DMA_PRIORITY_QUEUE10,Takes the value of the `dma_priority_queue10 DEFINE" "0,1"
|
|
newline
|
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bitfld.long 0x24 9. "DMA_PRIORITY_QUEUE9,Takes the value of the `dma_priority_queue9 DEFINE" "0,1"
|
|
newline
|
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bitfld.long 0x24 8. "DMA_PRIORITY_QUEUE8,Takes the value of the `dma_priority_queue8 DEFINE" "0,1"
|
|
newline
|
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bitfld.long 0x24 7. "DMA_PRIORITY_QUEUE7,Takes the value of the `dma_priority_queue7 DEFINE" "0,1"
|
|
newline
|
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bitfld.long 0x24 6. "DMA_PRIORITY_QUEUE6,Takes the value of the `dma_priority_queue6 DEFINE" "0,1"
|
|
newline
|
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bitfld.long 0x24 5. "DMA_PRIORITY_QUEUE5,Takes the value of the `dma_priority_queue5 DEFINE" "0,1"
|
|
newline
|
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bitfld.long 0x24 4. "DMA_PRIORITY_QUEUE4,Takes the value of the `dma_priority_queue4 DEFINE" "0,1"
|
|
newline
|
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bitfld.long 0x24 3. "DMA_PRIORITY_QUEUE3,Takes the value of the `dma_priority_queue3 DEFINE" "0,1"
|
|
newline
|
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bitfld.long 0x24 2. "DMA_PRIORITY_QUEUE2,Takes the value of the `dma_priority_queue2 DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x24 1. "DMA_PRIORITY_QUEUE1,Takes the value of the `dma_priority_queue1 DEFINE" "0,1"
|
|
line.long 0x28 "DESIGNCFG_DEBUG7,Design Configuration Register 7"
|
|
hexmask.long.byte 0x28 28.--31. 1. "X_PBUF_NUM_SEGMENTS_Q7,Takes the value of the `gem_tx_pbuf_num_segments_q7 DEFINE"
|
|
newline
|
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hexmask.long.byte 0x28 24.--27. 1. "X_PBUF_NUM_SEGMENTS_Q6,Takes the value of the `gem_tx_pbuf_num_segments_q6 DEFINE"
|
|
newline
|
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hexmask.long.byte 0x28 20.--23. 1. "X_PBUF_NUM_SEGMENTS_Q5,Takes the value of the `gem_tx_pbuf_num_segments_q5 DEFINE"
|
|
newline
|
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hexmask.long.byte 0x28 16.--19. 1. "X_PBUF_NUM_SEGMENTS_Q4,Takes the value of the `gem_tx_pbuf_num_segments_q4 DEFINE"
|
|
newline
|
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hexmask.long.byte 0x28 12.--15. 1. "X_PBUF_NUM_SEGMENTS_Q3,Takes the value of the `gem_tx_pbuf_num_segments_q3 DEFINE"
|
|
newline
|
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hexmask.long.byte 0x28 8.--11. 1. "X_PBUF_NUM_SEGMENTS_Q2,Takes the value of the `gem_tx_pbuf_num_segments_q2 DEFINE"
|
|
newline
|
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hexmask.long.byte 0x28 4.--7. 1. "X_PBUF_NUM_SEGMENTS_Q1,Takes the value of the `gem_tx_pbuf_num_segments_q1 DEFINE"
|
|
newline
|
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hexmask.long.byte 0x28 0.--3. 1. "X_PBUF_NUM_SEGMENTS_Q0,Takes the value of the `gem_tx_pbuf_num_segments_q0 DEFINE"
|
|
line.long 0x2C "DESIGNCFG_DEBUG8,Design Configuration Register 8"
|
|
hexmask.long.byte 0x2C 24.--31. 1. "NUM_TYPE1_SCREENERS,Takes the value of the `num_type1_screeners DEFINE"
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|
newline
|
|
hexmask.long.byte 0x2C 16.--23. 1. "NUM_TYPE2_SCREENERS,Takes the value of the `num_type2_screeners DEFINE"
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|
newline
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hexmask.long.byte 0x2C 8.--15. 1. "NUM_SCR2_ETHTYPE_REGS,Takes the value of the `num_scr2_ethtype_regs DEFINE"
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newline
|
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hexmask.long.byte 0x2C 0.--7. 1. "NUM_SCR2_COMPARE_REGS,Takes the value of the `num_scr2_compare_regs DEFINE"
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|
line.long 0x30 "DESIGNCFG_DEBUG9,Design Configuration Register 9"
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hexmask.long.byte 0x30 28.--31. 1. "TX_PBUF_NUM_SEGMENTS_Q15,Takes the value of the `gem_tx_pbuf_num_segments_q15 DEFINE"
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newline
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hexmask.long.byte 0x30 24.--27. 1. "TX_PBUF_NUM_SEGMENTS_Q14,Takes the value of the `gem_tx_pbuf_num_segments_q14 DEFINE"
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newline
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hexmask.long.byte 0x30 20.--23. 1. "TX_PBUF_NUM_SEGMENTS_Q13,Takes the value of the `gem_tx_pbuf_num_segments_q13 DEFINE"
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|
newline
|
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hexmask.long.byte 0x30 16.--19. 1. "TX_PBUF_NUM_SEGMENTS_Q12,Takes the value of the `gem_tx_pbuf_num_segments_q12 DEFINE"
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|
newline
|
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hexmask.long.byte 0x30 12.--15. 1. "TX_PBUF_NUM_SEGMENTS_Q11,Takes the value of the `gem_tx_pbuf_num_segments_q11 DEFINE"
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newline
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hexmask.long.byte 0x30 8.--11. 1. "TX_PBUF_NUM_SEGMENTS_Q10,Takes the value of the `gem_tx_pbuf_num_segments_q10 DEFINE"
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newline
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hexmask.long.byte 0x30 4.--7. 1. "TX_PBUF_NUM_SEGMENTS_Q9,Takes the value of the `gem_tx_pbuf_num_segments_q9 DEFINE"
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|
newline
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hexmask.long.byte 0x30 0.--3. 1. "TX_PBUF_NUM_SEGMENTS_Q8,Takes the value of the `gem_tx_pbuf_num_segments_q8 DEFINE"
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|
line.long 0x34 "DESIGNCFG_DEBUG10,Design Configuration Register 10"
|
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hexmask.long.byte 0x34 28.--31. 1. "EMAC_BUS_WIDTH,Takes the value of the `gem_emac_bus_width DEFINE. 1 - The MAC has a datawidth of 32bits. 2 - The MAC has a datawidth of 64bits. 4 - The MAC has a datawidth of 128bits"
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newline
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hexmask.long.byte 0x34 24.--27. 1. "TX_PBUF_DATA,Takes the value of the `gem_tx_pbuf_data DEFINE. 1 - The TX DPRAM has a datawidth of 32bits. 2 - The TX DPRAM has a datawidth of 64bits. 4 - The TX DPRAM has a datawidth of 128bits"
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newline
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hexmask.long.byte 0x34 20.--23. 1. "RX_PBUF_DATA,Takes the value of the `gem_rx_pbuf_data DEFINE. 1 - The RX DPRAM has a datawidth of 32bits. 2 - The RX DPRAM has a datawidth of 64bits. 4 - RX The DPRAM has a datawidth of 128bits"
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newline
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hexmask.long.byte 0x34 16.--19. 1. "AXI_ACCESS_PIPELINE_BITS,Takes the value of the `gem_axi_access_pipeline_bits DEFINE"
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newline
|
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hexmask.long.byte 0x34 12.--15. 1. "AXI_TX_DESCR_RD_BUFF_BITS,Takes the value of the `gem_axi_tx_descr_rd_buff_bits DEFINE"
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|
newline
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hexmask.long.byte 0x34 8.--11. 1. "AXI_RX_DESCR_RD_BUFF_BITS,Takes the value of the `gem_axi_rx_descr_rd_buff_bits DEFINE"
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newline
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hexmask.long.byte 0x34 4.--7. 1. "AXI_TX_DESCR_WR_BUFF_BITS,Takes the value of the `gem_axi_tx_descr_wr_buff_bits DEFINE"
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newline
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hexmask.long.byte 0x34 0.--3. 1. "AXI_RX_DESCR_WR_BUFF_BITS,Takes the value of the `gem_axi_rx_descr_wr_buff_bits DEFINE"
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rgroup.long 0x1300++0x7
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line.long 0x0 "SPEC_ADD5_BOTTOM,Specific address registers 5 ~ 36 doesn't present. Access to the register returns AHB error."
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hexmask.long 0x0 0.--31. 1. "RSVD_31_0,Write ignore read 0"
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line.long 0x4 "SPEC_ADD5_TOP,Specific address registers 5 ~ 36 doesn't present. Access to the register returns AHB error."
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hexmask.long 0x4 0.--31. 1. "RSVD_31_0,Write ignore read 0"
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rgroup.long 0x13F8++0x13
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line.long 0x0 "SPEC_ADD36_BOTTOM,Not presents."
|
|
hexmask.long 0x0 0.--31. 1. "RSVD_31_0,Write ignore read 0"
|
|
line.long 0x4 "SPEC_ADD36_TOP,Not presents."
|
|
hexmask.long 0x4 0.--31. 1. "RSVD_31_0,Write ignore read 0"
|
|
line.long 0x8 "INT_Q1_STATUS,Priority queue Interrupt Status Register"
|
|
bitfld.long 0x8 11. "RESP_NOT_OK,bresp not OK" "0,1"
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newline
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bitfld.long 0x8 7. "TRANSMIT_COMPLETE,Transmit complete" "0,1"
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|
newline
|
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bitfld.long 0x8 6. "AMBA_ERROR,Transmit frame corruption due to AMBA (AXI/AHB) error set if an error occurs whilst midway through reading transmit frame from the external memory including HRESP (AHB) RRESP and BRESP errors (AXI) and buffers exhausted mid frame" "0,1"
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newline
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bitfld.long 0x8 5. "RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION,Retry limit exceeded or late collision" "0,1"
|
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newline
|
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bitfld.long 0x8 2. "RX_USED_BIT_READ,RX used bit read" "0,1"
|
|
newline
|
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bitfld.long 0x8 1. "RECEIVE_COMPLETE,Receive complete" "0,1"
|
|
line.long 0xC "INT_Q2_STATUS,Priority queue Interrupt Status Register"
|
|
bitfld.long 0xC 11. "RESP_NOT_OK,bresp not OK" "0,1"
|
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newline
|
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bitfld.long 0xC 7. "TRANSMIT_COMPLETE,Transmit complete" "0,1"
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|
newline
|
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bitfld.long 0xC 6. "AMBA_ERROR,Transmit frame corruption due to AMBA (AXI/AHB) error set if an error occurs whilst midway through reading transmit frame from the external memory including HRESP(AHB) RRESP and BRESP errors (AXI) and buffers exhausted mid frame" "0,1"
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newline
|
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bitfld.long 0xC 5. "RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION,Retry limit exceeded or late collision" "0,1"
|
|
newline
|
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bitfld.long 0xC 2. "RX_USED_BIT_READ,RX used bit read" "0,1"
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|
newline
|
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bitfld.long 0xC 1. "RECEIVE_COMPLETE,Receive complete" "0,1"
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line.long 0x10 "INT_Q3_STATUS,int_q3_status to int_q15_status doesn't present. Access to the register returns AHB error."
|
|
hexmask.long 0x10 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
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|
rgroup.long 0x1438++0x3
|
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line.long 0x0 "INT_Q15_STATUS,Not presents."
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|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
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group.long 0x1440++0x7
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line.long 0x0 "TRANSMIT_Q1_PTR,This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control.."
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hexmask.long 0x0 2.--31. 1. "DMA_TX_Q_PTR,This register holds the start address of the transmit buffer queue (transmit buffers"
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newline
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bitfld.long 0x0 0. "DMA_TX_DIS_Q,Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while transmit is not enabled." "0,1"
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line.long 0x4 "TRANSMIT_Q2_PTR,This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control.."
|
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hexmask.long 0x4 2.--31. 1. "DMA_TX_Q_PTR,This register holds the start address of the transmit buffer queue (transmit buffers"
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newline
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bitfld.long 0x4 0. "DMA_TX_DIS_Q,Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while transmit is not enabled." "0,1"
|
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rgroup.long 0x1448++0x3
|
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line.long 0x0 "TRANSMIT_Q3_PTR,transmit_q3_ptr to transmit_q15_ptr doesn't present. Access to the register returns AHB error."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while transmit is not enabled."
|
|
rgroup.long 0x1478++0x3
|
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line.long 0x0 "TRANSMIT_Q15_PTR,Not presents."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
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group.long 0x1480++0x7
|
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line.long 0x0 "RECEIVE_Q1_PTR,This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control.."
|
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hexmask.long 0x0 2.--31. 1. "DMA_RX_Q_PTR,Receive buffer queue base address - written with the address of the start of the receive queue."
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newline
|
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bitfld.long 0x0 0. "DMA_RX_DIS_Q,Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while receive is not enabled." "0,1"
|
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line.long 0x4 "RECEIVE_Q2_PTR,This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control.."
|
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hexmask.long 0x4 2.--31. 1. "DMA_RX_Q_PTR,Receive buffer queue base address - written with the address of the start of the receive queue."
|
|
newline
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bitfld.long 0x4 0. "DMA_RX_DIS_Q,Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while receive is not enabled." "0,1"
|
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rgroup.long 0x1488++0x3
|
|
line.long 0x0 "RECEIVE_Q3_PTR,Not presents. Start address register doesn't present for queue3 ~ queue7."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x1498++0x3
|
|
line.long 0x0 "RECEIVE_Q7_PTR,Not presents."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
group.long 0x14A0++0x7
|
|
line.long 0x0 "DMA_RXBUF_SIZE_Q1,Receive Buffer queue 1 Size"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DMA_RX_Q_BUF_SIZE,DMA receive buffer size in system memory. The value defined by these bits determines the size of buffer to use in main system memory when writing received data. The value is defined in multiples of 64 bytes."
|
|
line.long 0x4 "DMA_RXBUF_SIZE_Q2,Receive Buffer queue 2 Size"
|
|
hexmask.long.byte 0x4 0.--7. 1. "DMA_RX_Q_BUF_SIZE,DMA receive buffer size in system memory. The value defined by these bits determines the size of buffer to use in main system memory when writing received data. The value is defined in multiples of 64 bytes."
|
|
rgroup.long 0x14A8++0x3
|
|
line.long 0x0 "DMA_RXBUF_SIZE_Q3,dma_rxbuf_size_q3 to dma_rxbuf_size_q7 doesn't present."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,DMA receive buffer size in system memory. The value defined by these bits determines the size of buffer to use in main system memory when writing received data. The value is defined in multiples of 64 bytes."
|
|
rgroup.long 0x14B8++0x3
|
|
line.long 0x0 "DMA_RXBUF_SIZE_Q7,Not presents."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
group.long 0x14BC++0x1B
|
|
line.long 0x0 "CBS_CONTROL,The IdleSlope value is defined as the rate of change of credit when a packet is waiting to be sent. This must not exceed the portTransmitRate which is dependent on the speed of operation. eg. portTranmsitRate. 1Gb/s = 32'h07735940 (125.."
|
|
bitfld.long 0x0 1. "CBS_ENABLE_QUEUE_B,Enable Credit-Based shaping on the 2nd highest priority queue (queue B). Write 1 to enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CBS_ENABLE_QUEUE_A,Enable Credit-Based Shaping on the highest priority queue (queue A). Write 1 to enable" "0,1"
|
|
line.long 0x4 "CBS_IDLESLOPE_Q_A,queue A is the highest priority queue. This would be queue 8 in an 8 queue configuration."
|
|
hexmask.long 0x4 0.--31. 1. "IDLESLOPE_A,IdleSlope value for queue A in bytes/sec for gigabit operation and nibbles/sec for 10/100 operation"
|
|
line.long 0x8 "CBS_IDLESLOPE_Q_B,queue B is the 2nd highest priority queue. This would be queue 7 in an 8 queue configuration."
|
|
hexmask.long 0x8 0.--31. 1. "IDLESLOPE_B,IdleSlope value for queue B in bytes/sec for gigabit operation and nibbles/sec for 10/100 operation"
|
|
line.long 0xC "UPPER_TX_Q_BASE_ADDR,Upper 32 bits of transmit buffer descriptor queue base address."
|
|
hexmask.long 0xC 0.--31. 1. "UPPER_TX_Q_BASE_ADDR,Upper 32 bits of transmit buffer descriptor queue base address. Used when 64 bit addressing is enabled. (In releases earlier to 1p06f2 this register also affected the receive descriptor queue.)"
|
|
line.long 0x10 "TX_BD_CONTROL,TX BD control register"
|
|
bitfld.long 0x10 4.--5. "TX_BD_TS_MODE,TX Descriptor Timestamp Insertion mode 00: TS insertion disable 01: TS inserted for PTP Event Frames only 10: TS inserted for All PTP Frames only 11: TS insertion for All Frames" "0: TS insertion disable,1: TS inserted for PTP Event Frames only,?,?"
|
|
line.long 0x14 "RX_BD_CONTROL,RX BD control register"
|
|
bitfld.long 0x14 4.--5. "RX_BD_TS_MODE,RX Descriptor Timestamp Insertion mode 00: TS insertion disable 01: TS inserted for PTP Event Frames only 10: TS inserted for All PTP Frames only 11: TS insertion for All Frames" "0: TS insertion disable,1: TS inserted for PTP Event Frames only,?,?"
|
|
line.long 0x18 "UPPER_RX_Q_BASE_ADDR,Upper 32 bits of receive buffer descriptor queue base address."
|
|
hexmask.long 0x18 0.--31. 1. "UPPER_RX_Q_BASE_ADDR,Upper 32 bits of receive buffer descriptor queue base address. Used when 64 bit addressing is enabled."
|
|
group.long 0x14E0++0xF
|
|
line.long 0x0 "HIDDEN_REG0,Hidden registers defined in edma_defs.v '`define gem_cbs_port_tx_rate_10m 12'h4e0 // 10M Port TX Rate *** HIDDEN Register ***'. Default value of cbs related hidden registers (0x14E0~0x14E8) are depicted in cbs_control register."
|
|
hexmask.long 0x0 0.--31. 1. "HIDDEN0_FIELD,default value is defined per description of register cbs_control."
|
|
line.long 0x4 "HIDDEN_REG1,Hidden registers defined in edma_defs.v '`define gem_cbs_port_tx_rate_100m 12'h4e4 // 100M Port TX Rate *** HIDDEN Register ***'"
|
|
hexmask.long 0x4 0.--31. 1. "HIDDEN1_FIELD,default value is defined per description of register cbs_control."
|
|
line.long 0x8 "HIDDEN_REG2,Hidden registers defined in edma_defs.v '`define gem_cbs_port_tx_rate_1g 12'h4e8 // 1G Port TX Rate *** HIDDEN Register ***'"
|
|
hexmask.long 0x8 0.--31. 1. "HIDDEN2_FIELD,default value is defined per description of register cbs_control."
|
|
line.long 0xC "HIDDEN_REG3,Hidden registers defined in edma_defs.v '`define gem_wd_counter 12'h4ec // *** HIDDEN Register ***'."
|
|
hexmask.long.byte 0xC 0.--3. 1. "HIDDEN3_FIELD,default value is defined per description of register cbs_control."
|
|
group.long 0x14F8++0x8B
|
|
line.long 0x0 "HIDDEN_REG4,Hidden registers defined in edma_defs.v '`define gem_axi_tx_full_threshold0 12'h4f8 // AXI full threshold setting *** HIDDEN Register ***'. Note. When using AXI mode with a single port ram ( gem_spram == 1) mode and a 32b dma bus width (.."
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hexmask.long.word 0x0 16.--24. 1. "HIDDEN4_FIELD_H,The valid bits is defined by `gem_tx_pbuf_addr."
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "HIDDEN4_FIELD_L,The valid bits is defined by `gem_tx_pbuf_addr."
|
|
line.long 0x4 "HIDDEN_REG5,Hidden registers defined in edma_defs.v '`define gem_axi_tx_full_threshold1 12'h4fc // AXI full threshold setting *** HIDDEN Register ***'."
|
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hexmask.long.word 0x4 16.--24. 1. "HIDDEN5_FIELD_H,The valid bits is defined by `gem_tx_pbuf_addr."
|
|
newline
|
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hexmask.long.word 0x4 0.--8. 1. "HIDDEN5_FIELD_L,The valid bits is defined by `gem_tx_pbuf_addr."
|
|
line.long 0x8 "SCREENING_TYPE_1_REGISTER_0,Screening type 1 registers are used to allocate up to 16 priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly. when DS/TC match enable is set (bit 28). the DS (Differentiated.."
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bitfld.long 0x8 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
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|
newline
|
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bitfld.long 0x8 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
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newline
|
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hexmask.long.word 0x8 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
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newline
|
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hexmask.long.byte 0x8 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
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hexmask.long.byte 0x8 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
|
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line.long 0xC "SCREENING_TYPE_1_REGISTER_1,screening type 1 register 1. same as screening_type_1_register_0"
|
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bitfld.long 0xC 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
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newline
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bitfld.long 0xC 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
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newline
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hexmask.long.word 0xC 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
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newline
|
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hexmask.long.byte 0xC 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
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hexmask.long.byte 0xC 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
|
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line.long 0x10 "SCREENING_TYPE_1_REGISTER_2,screening type 1 register 2. same as screening_type_1_register_0"
|
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bitfld.long 0x10 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
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newline
|
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bitfld.long 0x10 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
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newline
|
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hexmask.long.word 0x10 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
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newline
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hexmask.long.byte 0x10 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
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newline
|
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hexmask.long.byte 0x10 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
|
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line.long 0x14 "SCREENING_TYPE_1_REGISTER_3,screening type 1 register 3. same as screening_type_1_register_0"
|
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bitfld.long 0x14 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
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newline
|
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bitfld.long 0x14 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
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newline
|
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hexmask.long.word 0x14 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
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newline
|
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hexmask.long.byte 0x14 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
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hexmask.long.byte 0x14 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
|
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line.long 0x18 "SCREENING_TYPE_1_REGISTER_4,screening type 1 register 4. same as screening_type_1_register_0"
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bitfld.long 0x18 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
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newline
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bitfld.long 0x18 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
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newline
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hexmask.long.word 0x18 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
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newline
|
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hexmask.long.byte 0x18 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
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hexmask.long.byte 0x18 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
|
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line.long 0x1C "SCREENING_TYPE_1_REGISTER_5,screening type 1 register 5. same as screening_type_1_register_0"
|
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bitfld.long 0x1C 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
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newline
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bitfld.long 0x1C 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
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newline
|
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hexmask.long.word 0x1C 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
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newline
|
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hexmask.long.byte 0x1C 4.--11. 1. "DSTC_MATCH,DS/TC Match"
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newline
|
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hexmask.long.byte 0x1C 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
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line.long 0x20 "SCREENING_TYPE_1_REGISTER_6,screening type 1 register 6. same as screening_type_1_register_0"
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bitfld.long 0x20 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
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newline
|
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bitfld.long 0x20 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
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newline
|
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hexmask.long.word 0x20 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
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newline
|
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hexmask.long.byte 0x20 4.--11. 1. "DSTC_MATCH,DS/TC Match"
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newline
|
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hexmask.long.byte 0x20 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
|
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line.long 0x24 "SCREENING_TYPE_1_REGISTER_7,screening type 1 register 7. same as screening_type_1_register_0"
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bitfld.long 0x24 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
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newline
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bitfld.long 0x24 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
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newline
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hexmask.long.word 0x24 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
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newline
|
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hexmask.long.byte 0x24 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
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newline
|
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hexmask.long.byte 0x24 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
|
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line.long 0x28 "SCREENING_TYPE_1_REGISTER_8,screening type 1 register 8. same as screening_type_1_register_0"
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bitfld.long 0x28 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
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newline
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bitfld.long 0x28 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
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newline
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hexmask.long.word 0x28 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
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newline
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hexmask.long.byte 0x28 4.--11. 1. "DSTC_MATCH,DS/TC Match"
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|
newline
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hexmask.long.byte 0x28 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
|
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line.long 0x2C "SCREENING_TYPE_1_REGISTER_9,screening type 1 register 9. same as screening_type_1_register_0"
|
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bitfld.long 0x2C 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
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newline
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bitfld.long 0x2C 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
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newline
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hexmask.long.word 0x2C 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
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newline
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hexmask.long.byte 0x2C 4.--11. 1. "DSTC_MATCH,DS/TC Match"
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newline
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hexmask.long.byte 0x2C 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
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line.long 0x30 "SCREENING_TYPE_1_REGISTER_10,screening type 1 register 10. same as screening_type_1_register_0"
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bitfld.long 0x30 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
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newline
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bitfld.long 0x30 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
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newline
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hexmask.long.word 0x30 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
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newline
|
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hexmask.long.byte 0x30 4.--11. 1. "DSTC_MATCH,DS/TC Match"
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newline
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hexmask.long.byte 0x30 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
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line.long 0x34 "SCREENING_TYPE_1_REGISTER_11,screening type 1 register 11. same as screening_type_1_register_0"
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bitfld.long 0x34 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
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newline
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bitfld.long 0x34 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
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newline
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hexmask.long.word 0x34 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
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newline
|
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hexmask.long.byte 0x34 4.--11. 1. "DSTC_MATCH,DS/TC Match"
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newline
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hexmask.long.byte 0x34 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
|
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line.long 0x38 "SCREENING_TYPE_1_REGISTER_12,screening type 1 register 12. same as screening_type_1_register_0"
|
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bitfld.long 0x38 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
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newline
|
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bitfld.long 0x38 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
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newline
|
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hexmask.long.word 0x38 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
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newline
|
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hexmask.long.byte 0x38 4.--11. 1. "DSTC_MATCH,DS/TC Match"
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newline
|
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hexmask.long.byte 0x38 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
|
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line.long 0x3C "SCREENING_TYPE_1_REGISTER_13,screening type 1 register 13. same as screening_type_1_register_0"
|
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bitfld.long 0x3C 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
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newline
|
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bitfld.long 0x3C 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
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|
newline
|
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hexmask.long.word 0x3C 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
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newline
|
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hexmask.long.byte 0x3C 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
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newline
|
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hexmask.long.byte 0x3C 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
|
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line.long 0x40 "SCREENING_TYPE_1_REGISTER_14,screening type 1 register 14. same as screening_type_1_register_0"
|
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bitfld.long 0x40 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
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newline
|
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bitfld.long 0x40 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
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newline
|
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hexmask.long.word 0x40 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
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newline
|
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hexmask.long.byte 0x40 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
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newline
|
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hexmask.long.byte 0x40 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
|
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line.long 0x44 "SCREENING_TYPE_1_REGISTER_15,screening type 1 register 15. same as screening_type_1_register_0"
|
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bitfld.long 0x44 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
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newline
|
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bitfld.long 0x44 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
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newline
|
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hexmask.long.word 0x44 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
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newline
|
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hexmask.long.byte 0x44 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
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newline
|
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hexmask.long.byte 0x44 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
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line.long 0x48 "SCREENING_TYPE_2_REGISTER_0,Screener Type 2 match registers operate independently of screener type 1 registers and offer additional match capabilities. extending the capabilities into vendor specific protocols."
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rbitfld.long 0x48 31. "RSVD_31,N/A" "0,1"
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newline
|
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bitfld.long 0x48 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
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newline
|
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hexmask.long.byte 0x48 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
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newline
|
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bitfld.long 0x48 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
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newline
|
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hexmask.long.byte 0x48 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
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newline
|
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bitfld.long 0x48 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
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|
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hexmask.long.byte 0x48 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
|
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newline
|
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bitfld.long 0x48 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
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newline
|
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bitfld.long 0x48 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
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newline
|
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bitfld.long 0x48 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
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|
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bitfld.long 0x48 7. "RSVD_7,N/A" "0,1"
|
|
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|
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bitfld.long 0x48 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
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newline
|
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hexmask.long.byte 0x48 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
|
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line.long 0x4C "SCREENING_TYPE_2_REGISTER_1,screening type 2 register 1. same as screening_type_2_register_0"
|
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rbitfld.long 0x4C 31. "RSVD_31,N/A" "0,1"
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|
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bitfld.long 0x4C 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
|
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|
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hexmask.long.byte 0x4C 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
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newline
|
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bitfld.long 0x4C 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
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|
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hexmask.long.byte 0x4C 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
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newline
|
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bitfld.long 0x4C 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
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newline
|
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hexmask.long.byte 0x4C 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
|
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newline
|
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bitfld.long 0x4C 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
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newline
|
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bitfld.long 0x4C 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
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newline
|
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bitfld.long 0x4C 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
|
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|
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bitfld.long 0x4C 7. "RSVD_7,N/A" "0,1"
|
|
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|
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bitfld.long 0x4C 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
|
newline
|
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hexmask.long.byte 0x4C 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
|
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line.long 0x50 "SCREENING_TYPE_2_REGISTER_2,screening type 2 register 2. same as screening_type_2_register_0"
|
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rbitfld.long 0x50 31. "RSVD_31,N/A" "0,1"
|
|
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|
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bitfld.long 0x50 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
|
newline
|
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hexmask.long.byte 0x50 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
|
|
newline
|
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bitfld.long 0x50 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
|
newline
|
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hexmask.long.byte 0x50 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
|
|
newline
|
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bitfld.long 0x50 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
|
|
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|
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hexmask.long.byte 0x50 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
|
|
newline
|
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bitfld.long 0x50 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
|
newline
|
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bitfld.long 0x50 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x50 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
|
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|
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bitfld.long 0x50 7. "RSVD_7,N/A" "0,1"
|
|
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|
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bitfld.long 0x50 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
|
newline
|
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hexmask.long.byte 0x50 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
|
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line.long 0x54 "SCREENING_TYPE_2_REGISTER_3,screening type 2 register 3. same as screening_type_2_register_0"
|
|
rbitfld.long 0x54 31. "RSVD_31,N/A" "0,1"
|
|
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|
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bitfld.long 0x54 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
|
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|
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hexmask.long.byte 0x54 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
|
|
newline
|
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bitfld.long 0x54 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
|
newline
|
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hexmask.long.byte 0x54 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
|
|
newline
|
|
bitfld.long 0x54 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
|
|
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|
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hexmask.long.byte 0x54 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
|
|
newline
|
|
bitfld.long 0x54 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
|
newline
|
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bitfld.long 0x54 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x54 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
|
newline
|
|
bitfld.long 0x54 7. "RSVD_7,N/A" "0,1"
|
|
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|
|
bitfld.long 0x54 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
|
newline
|
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hexmask.long.byte 0x54 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
|
|
line.long 0x58 "SCREENING_TYPE_2_REGISTER_4,screening type 2 register 4. same as screening_type_2_register_0"
|
|
rbitfld.long 0x58 31. "RSVD_31,N/A" "0,1"
|
|
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|
|
bitfld.long 0x58 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x58 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
|
|
newline
|
|
bitfld.long 0x58 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x58 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
|
|
newline
|
|
bitfld.long 0x58 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x58 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
|
|
newline
|
|
bitfld.long 0x58 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
|
newline
|
|
bitfld.long 0x58 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x58 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
|
newline
|
|
bitfld.long 0x58 7. "RSVD_7,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x58 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x58 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
|
|
line.long 0x5C "SCREENING_TYPE_2_REGISTER_5,screening type 2 register 5. same as screening_type_2_register_0"
|
|
rbitfld.long 0x5C 31. "RSVD_31,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x5C 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
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|
newline
|
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hexmask.long.byte 0x5C 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
|
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newline
|
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bitfld.long 0x5C 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
|
newline
|
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hexmask.long.byte 0x5C 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
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newline
|
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bitfld.long 0x5C 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
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newline
|
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hexmask.long.byte 0x5C 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
|
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newline
|
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bitfld.long 0x5C 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
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newline
|
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bitfld.long 0x5C 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
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newline
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bitfld.long 0x5C 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
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newline
|
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bitfld.long 0x5C 7. "RSVD_7,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x5C 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
|
newline
|
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hexmask.long.byte 0x5C 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
|
|
line.long 0x60 "SCREENING_TYPE_2_REGISTER_6,screening type 2 register 6. same as screening_type_2_register_0"
|
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rbitfld.long 0x60 31. "RSVD_31,N/A" "0,1"
|
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newline
|
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bitfld.long 0x60 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
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newline
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hexmask.long.byte 0x60 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
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newline
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bitfld.long 0x60 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
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newline
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hexmask.long.byte 0x60 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
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newline
|
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bitfld.long 0x60 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
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newline
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hexmask.long.byte 0x60 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
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newline
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bitfld.long 0x60 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
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newline
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bitfld.long 0x60 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x60 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
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newline
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bitfld.long 0x60 7. "RSVD_7,N/A" "0,1"
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newline
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bitfld.long 0x60 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
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newline
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hexmask.long.byte 0x60 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
|
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line.long 0x64 "SCREENING_TYPE_2_REGISTER_7,screening type 2 register 7. same as screening_type_2_register_0"
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rbitfld.long 0x64 31. "RSVD_31,N/A" "0,1"
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bitfld.long 0x64 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
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hexmask.long.byte 0x64 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
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newline
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bitfld.long 0x64 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
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newline
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hexmask.long.byte 0x64 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
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newline
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bitfld.long 0x64 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
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newline
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hexmask.long.byte 0x64 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
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newline
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bitfld.long 0x64 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
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newline
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bitfld.long 0x64 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x64 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
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bitfld.long 0x64 7. "RSVD_7,N/A" "0,1"
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bitfld.long 0x64 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x64 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
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line.long 0x68 "SCREENING_TYPE_2_REGISTER_8,screening type 2 register 8. same as screening_type_2_register_0"
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rbitfld.long 0x68 31. "RSVD_31,N/A" "0,1"
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newline
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bitfld.long 0x68 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
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hexmask.long.byte 0x68 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
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newline
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bitfld.long 0x68 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
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newline
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hexmask.long.byte 0x68 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
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newline
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bitfld.long 0x68 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
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newline
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hexmask.long.byte 0x68 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
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newline
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bitfld.long 0x68 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
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newline
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bitfld.long 0x68 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x68 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
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newline
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bitfld.long 0x68 7. "RSVD_7,N/A" "0,1"
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bitfld.long 0x68 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x68 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
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line.long 0x6C "SCREENING_TYPE_2_REGISTER_9,screening type 2 register 9. same as screening_type_2_register_0"
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rbitfld.long 0x6C 31. "RSVD_31,N/A" "0,1"
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newline
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bitfld.long 0x6C 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
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newline
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hexmask.long.byte 0x6C 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
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newline
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bitfld.long 0x6C 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
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newline
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hexmask.long.byte 0x6C 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
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newline
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bitfld.long 0x6C 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
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newline
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hexmask.long.byte 0x6C 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
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newline
|
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bitfld.long 0x6C 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
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newline
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bitfld.long 0x6C 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x6C 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
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bitfld.long 0x6C 7. "RSVD_7,N/A" "0,1"
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bitfld.long 0x6C 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
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newline
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hexmask.long.byte 0x6C 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
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line.long 0x70 "SCREENING_TYPE_2_REGISTER_10,screening type 2 register 10. same as screening_type_2_register_0"
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rbitfld.long 0x70 31. "RSVD_31,N/A" "0,1"
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newline
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bitfld.long 0x70 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
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newline
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hexmask.long.byte 0x70 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
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newline
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bitfld.long 0x70 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
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newline
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hexmask.long.byte 0x70 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
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newline
|
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bitfld.long 0x70 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
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newline
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hexmask.long.byte 0x70 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
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newline
|
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bitfld.long 0x70 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
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newline
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bitfld.long 0x70 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x70 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
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newline
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bitfld.long 0x70 7. "RSVD_7,N/A" "0,1"
|
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|
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bitfld.long 0x70 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
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newline
|
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hexmask.long.byte 0x70 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
|
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line.long 0x74 "SCREENING_TYPE_2_REGISTER_11,screening type 2 register 11. same as screening_type_2_register_0"
|
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rbitfld.long 0x74 31. "RSVD_31,N/A" "0,1"
|
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newline
|
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bitfld.long 0x74 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
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newline
|
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hexmask.long.byte 0x74 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
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newline
|
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bitfld.long 0x74 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
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newline
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hexmask.long.byte 0x74 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
|
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newline
|
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bitfld.long 0x74 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
|
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newline
|
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hexmask.long.byte 0x74 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
|
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newline
|
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bitfld.long 0x74 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
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newline
|
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bitfld.long 0x74 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
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newline
|
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bitfld.long 0x74 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
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newline
|
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bitfld.long 0x74 7. "RSVD_7,N/A" "0,1"
|
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newline
|
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bitfld.long 0x74 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
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newline
|
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hexmask.long.byte 0x74 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
|
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line.long 0x78 "SCREENING_TYPE_2_REGISTER_12,screening type 2 register 12. same as screening_type_2_register_0"
|
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rbitfld.long 0x78 31. "RSVD_31,N/A" "0,1"
|
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newline
|
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bitfld.long 0x78 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
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newline
|
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hexmask.long.byte 0x78 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
|
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newline
|
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bitfld.long 0x78 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
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newline
|
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hexmask.long.byte 0x78 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
|
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newline
|
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bitfld.long 0x78 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
|
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newline
|
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hexmask.long.byte 0x78 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
|
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newline
|
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bitfld.long 0x78 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
|
newline
|
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bitfld.long 0x78 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
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newline
|
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bitfld.long 0x78 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
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newline
|
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bitfld.long 0x78 7. "RSVD_7,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x78 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
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newline
|
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hexmask.long.byte 0x78 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
|
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line.long 0x7C "SCREENING_TYPE_2_REGISTER_13,screening type 2 register 13. same as screening_type_2_register_0"
|
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rbitfld.long 0x7C 31. "RSVD_31,N/A" "0,1"
|
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newline
|
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bitfld.long 0x7C 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
|
newline
|
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hexmask.long.byte 0x7C 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
|
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newline
|
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bitfld.long 0x7C 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
|
newline
|
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hexmask.long.byte 0x7C 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
|
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newline
|
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bitfld.long 0x7C 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
|
|
newline
|
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hexmask.long.byte 0x7C 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
|
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newline
|
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bitfld.long 0x7C 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
|
newline
|
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bitfld.long 0x7C 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
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newline
|
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bitfld.long 0x7C 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
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newline
|
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bitfld.long 0x7C 7. "RSVD_7,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x7C 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
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newline
|
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hexmask.long.byte 0x7C 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
|
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line.long 0x80 "SCREENING_TYPE_2_REGISTER_14,screening type 2 register 14. same as screening_type_2_register_0"
|
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rbitfld.long 0x80 31. "RSVD_31,N/A" "0,1"
|
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newline
|
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bitfld.long 0x80 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
|
newline
|
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hexmask.long.byte 0x80 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
|
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newline
|
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bitfld.long 0x80 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
|
newline
|
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hexmask.long.byte 0x80 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
|
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newline
|
|
bitfld.long 0x80 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
|
|
newline
|
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hexmask.long.byte 0x80 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
|
|
newline
|
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bitfld.long 0x80 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
|
newline
|
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bitfld.long 0x80 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
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newline
|
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bitfld.long 0x80 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
|
newline
|
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bitfld.long 0x80 7. "RSVD_7,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x80 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
|
newline
|
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hexmask.long.byte 0x80 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
|
|
line.long 0x84 "SCREENING_TYPE_2_REGISTER_15,screening type 2 register 15. same as screening_type_2_register_0"
|
|
rbitfld.long 0x84 31. "RSVD_31,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x84 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
|
newline
|
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hexmask.long.byte 0x84 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
|
|
newline
|
|
bitfld.long 0x84 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
|
newline
|
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hexmask.long.byte 0x84 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
|
|
newline
|
|
bitfld.long 0x84 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
|
|
newline
|
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hexmask.long.byte 0x84 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
|
|
newline
|
|
bitfld.long 0x84 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
|
newline
|
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bitfld.long 0x84 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x84 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
|
newline
|
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bitfld.long 0x84 7. "RSVD_7,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x84 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
|
newline
|
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hexmask.long.byte 0x84 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
|
|
line.long 0x88 "TX_SCHED_CTRL,This register controls the transmit scheduling algorithm the user can select for each active transmit queue. By default all queues are initialized to fixed priority. with the top indexed queue having overall priority"
|
|
hexmask.long.tbyte 0x88 8.--31. 1. "REMOVED_31_8,Write ignore read 0"
|
|
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|
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rbitfld.long 0x88 6.--7. "TX_SCHED_Q3,Write ignore read 0" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x88 4.--5. "TX_SCHED_Q2,'Queue 2 selection." "0: Fixed Priority,1: CBS Enabled only valid for top two enabled..,?,?"
|
|
newline
|
|
bitfld.long 0x88 2.--3. "TX_SCHED_Q1,'Queue 1 selection." "0: Fixed Priority,1: CBS Enabled only valid for top two enabled..,?,?"
|
|
newline
|
|
bitfld.long 0x88 0.--1. "TX_SCHED_Q0,'Queue 0 selection." "0: Fixed Priority,1: CBS Enabled only valid for top two enabled..,?,?"
|
|
group.long 0x1590++0x7
|
|
line.long 0x0 "BW_RATE_LIMIT_Q0TO3,This register holds the DWRR weighting value or the ETS bandwidth percentage value used by the transmit scheduler for queues 0 to 3."
|
|
hexmask.long.byte 0x0 24.--31. 1. "DWRR_ETS_WEIGHT_Q3,Write ignore read 0"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DWRR_ETS_WEIGHT_Q2,'DWRR Weighting / ETS Bandwidth Allocation for queue 2'"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "DWRR_ETS_WEIGHT_Q1,'DWRR Weighting / ETS Bandwidth Allocation for queue 1'"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DWRR_ETS_WEIGHT_Q0,'DWRR Weighting / ETS Bandwidth Allocation for queue 0'"
|
|
line.long 0x4 "BW_RATE_LIMIT_Q4TO7,Not presents. MXETH has only 3 queues. Access to the register returns AHB error."
|
|
hexmask.long 0x4 0.--31. 1. "REMOVED_31_0,'DWRR Weighting / ETS Bandwidth Allocation for queue 0'"
|
|
rgroup.long 0x1598++0x7
|
|
line.long 0x0 "BW_RATE_LIMIT_Q8TO11,Not presents. MXETH has only 3 queues. Access to the register returns AHB error."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
line.long 0x4 "BW_RATE_LIMIT_Q12TO15,Not presents. MXETH has only 3 queues. Access to the register returns AHB error."
|
|
hexmask.long 0x4 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
group.long 0x15A0++0x3
|
|
line.long 0x0 "TX_Q_SEG_ALLOC_Q0TO7,This register allows the user to distribute the Transmit SRAM used by the DMA across the priority queues. for queues 0 to 7. The SRAM itself is split into a number of evenly sized segments (this is defined in the verilog.."
|
|
rbitfld.long 0x0 31. "RSVD_31_31,Write ignore read 0" "0,1"
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|
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rbitfld.long 0x0 28.--30. "REMOVED_30_28,Write ignore read 0" "0,1,2,3,4,5,6,7"
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|
newline
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rbitfld.long 0x0 27. "RSVD_27_27,Write ignore read 0" "0,1"
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|
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rbitfld.long 0x0 24.--26. "REMOVED_26_24,Write ignore read 0" "0,1,2,3,4,5,6,7"
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newline
|
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rbitfld.long 0x0 23. "RSVD_23,Write ignore read 0" "0,1"
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|
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|
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rbitfld.long 0x0 20.--22. "REMOVED_22_20,Write ignore read 0" "0,1,2,3,4,5,6,7"
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|
newline
|
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rbitfld.long 0x0 19. "RSVD_19_19,Write ignore read 0" "0,1"
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|
newline
|
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rbitfld.long 0x0 16.--18. "REMOVED_18_16,Write ignore read 0" "0,1,2,3,4,5,6,7"
|
|
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|
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rbitfld.long 0x0 15. "RSVD_15_15,Write ignore read 0" "0,1"
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|
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|
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rbitfld.long 0x0 12.--14. "REMOVED_14_12,Write ignore read 0" "0,1,2,3,4,5,6,7"
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|
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|
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rbitfld.long 0x0 11. "RSVD_11_11,Write ignore read 0" "0,1"
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|
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|
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bitfld.long 0x0 8.--10. "SEGMENT_ALLOC_Q2,Number of segments allocated to q2. This should be entered as a log 2 for example entering a value of 2 would grant 4 segments. A maximum of 32 segments can be granted" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x0 7. "RSVD_7_7,N/A" "0,1"
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|
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|
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bitfld.long 0x0 4.--6. "SEGMENT_ALLOC_Q1,Number of segments allocated to q1. This should be entered as a log 2 for example entering a value of 2 would grant 4 segments. A maximum of 32 segments can be granted" "0,1,2,3,4,5,6,7"
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|
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|
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rbitfld.long 0x0 3. "RSVD_3_3,N/A" "0,1"
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|
|
bitfld.long 0x0 0.--2. "SEGMENT_ALLOC_Q0,Number of segments allocated to q0. This should be entered as a log 2 for example entering a value of 2 would grant 4 segments. A maximum of 32 segments can be granted. The default value is determined by `gem_tx_pbuf_num_segments_q0" "0,1,2,3,4,5,6,7"
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|
rgroup.long 0x15A4++0x3
|
|
line.long 0x0 "TX_Q_SEG_ALLOC_Q8TO15,Not presents. Access to the register returns AHB error."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x15C0++0x3
|
|
line.long 0x0 "RECEIVE_Q8_PTR,receive_q8_ptr to receive_q15_ptr doesn't present. Access to the register returns AHB error."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x15DC++0x7
|
|
line.long 0x0 "RECEIVE_Q15_PTR,Not presents."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
line.long 0x4 "DMA_RXBUF_SIZE_Q8,dma_rxbuf_size_q8 to dma_rxbuf_size_q15 doesn't present. Access to the register returns AHB error."
|
|
hexmask.long 0x4 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x15FC++0x3
|
|
line.long 0x0 "DMA_RXBUF_SIZE_Q15,Not presents."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
wgroup.long 0x1600++0x7
|
|
line.long 0x0 "INT_Q1_ENABLE,At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero."
|
|
bitfld.long 0x0 11. "ENABLE_RESP_NOT_OK_INTERRUPT,Enable bresp not OK interrupt" "0,1"
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bitfld.long 0x0 7. "ENABLE_TRANSMIT_COMPLETE_INTERRUPT,Enable Transmit complete interrupt" "0,1"
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|
newline
|
|
bitfld.long 0x0 6. "ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT,Enable Transmit frame corruption due to AMBA (AXI/AHB) error interrupt" "0,1"
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newline
|
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bitfld.long 0x0 5. "ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT,Enable Retry limit exceeded or late collision interrupt" "0,1"
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bitfld.long 0x0 2. "ENABLE_RX_USED_BIT_READ_INTERRUPT,Enable RX used bit read interrupt" "0,1"
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newline
|
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bitfld.long 0x0 1. "ENABLE_RECEIVE_COMPLETE_INTERRUPT,Enable Receive complete interrupt" "0,1"
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line.long 0x4 "INT_Q2_ENABLE,At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero."
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|
bitfld.long 0x4 11. "ENABLE_RESP_NOT_OK_INTERRUPT,Enable bresp not OK interrupt" "0,1"
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newline
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bitfld.long 0x4 7. "ENABLE_TRANSMIT_COMPLETE_INTERRUPT,Enable Transmit complete interrupt" "0,1"
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|
newline
|
|
bitfld.long 0x4 6. "ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT,Enable Transmit frame corruption due to AMBA (AXI/AHB) error interrupt" "0,1"
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newline
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bitfld.long 0x4 5. "ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT,Enable Retry limit exceeded or late collision interrupt" "0,1"
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|
newline
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bitfld.long 0x4 2. "ENABLE_RX_USED_BIT_READ_INTERRUPT,Enable RX used bit read interrupt" "0,1"
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newline
|
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bitfld.long 0x4 1. "ENABLE_RECEIVE_COMPLETE_INTERRUPT,Enable Receive complete interrupt" "0,1"
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|
rgroup.long 0x1608++0x3
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line.long 0x0 "INT_Q3_ENABLE,int_q3_enable to int_q7_enable doesn't present. Access to the register returns AHB error."
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|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x1618++0x3
|
|
line.long 0x0 "INT_Q7_ENABLE,Not presents."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
wgroup.long 0x1620++0x7
|
|
line.long 0x0 "INT_Q1_DISABLE,Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero."
|
|
bitfld.long 0x0 11. "DISABLE_RESP_NOT_OK_INTERRUPT,Disable bresp not OK interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "DISABLE_TRANSMIT_COMPLETE_INTERRUPT,Disable Transmit complete interrupt" "0,1"
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|
newline
|
|
bitfld.long 0x0 6. "DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT,Disable Transmit frame corruption due to AMBA (AXI/AHB) error interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT,Disable Retry limit exceeded or late collision interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DISABLE_RX_USED_BIT_READ_INTERRUPT,Disable RX used bit read interrupt" "0,1"
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|
newline
|
|
bitfld.long 0x0 1. "DISABLE_RECEIVE_COMPLETE_INTERRUPT,Disable Receive complete interrupt" "0,1"
|
|
line.long 0x4 "INT_Q2_DISABLE,Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero."
|
|
bitfld.long 0x4 11. "DISABLE_RESP_NOT_OK_INTERRUPT,Disable bresp not OK interrupt" "0,1"
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|
newline
|
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bitfld.long 0x4 7. "DISABLE_TRANSMIT_COMPLETE_INTERRUPT,Disable Transmit complete interrupt" "0,1"
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|
newline
|
|
bitfld.long 0x4 6. "DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT,Disable Transmit frame corruption due to AMBA (AXI/AHB) error interrupt" "0,1"
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|
newline
|
|
bitfld.long 0x4 5. "DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT,Disable Retry limit exceeded or late collision interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DISABLE_RX_USED_BIT_READ_INTERRUPT,Disable RX used bit read interrupt" "0,1"
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|
newline
|
|
bitfld.long 0x4 1. "DISABLE_RECEIVE_COMPLETE_INTERRUPT,Disable Receive complete interrupt" "0,1"
|
|
rgroup.long 0x1628++0x3
|
|
line.long 0x0 "INT_Q3_DISABLE,int_q3_disable to int_q7_disable doesn't present. Access to the register returns AHB error."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
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|
rgroup.long 0x1638++0x3
|
|
line.long 0x0 "INT_Q7_DISABLE,Not presents."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x1640++0xB
|
|
line.long 0x0 "INT_Q1_MASK,The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt.."
|
|
bitfld.long 0x0 11. "RESP_NOT_OK_INTERRUPT_MASK,bresp not OK interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
newline
|
|
bitfld.long 0x0 7. "TRANSMIT_COMPLETE_INTERRUPT_MASK,transmit complete interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
newline
|
|
bitfld.long 0x0 6. "AMBA_ERROR_INTERRUPT_MASK,A read of this register returns the value of the AMBA (AXI/AHB) error interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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|
newline
|
|
bitfld.long 0x0 5. "RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK,retry limit exceeded or late collision interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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|
newline
|
|
bitfld.long 0x0 2. "RX_USED_INTERRUPT_MASK,A read of this register returns the value of the RX Used interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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|
newline
|
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bitfld.long 0x0 1. "RECEIVE_COMPLETE_INTERRUPT_MASK,receive complete interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
line.long 0x4 "INT_Q2_MASK,The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt.."
|
|
bitfld.long 0x4 11. "RESP_NOT_OK_INTERRUPT_MASK,bresp not OK interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
newline
|
|
bitfld.long 0x4 7. "TRANSMIT_COMPLETE_INTERRUPT_MASK,transmit complete interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
newline
|
|
bitfld.long 0x4 6. "AMBA_ERROR_INTERRUPT_MASK,A read of this register returns the value of the AMBA (AXI/AHB) error interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
newline
|
|
bitfld.long 0x4 5. "RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK,retry limit exceeded or late collision interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
newline
|
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bitfld.long 0x4 2. "RX_USED_INTERRUPT_MASK,A read of this register returns the value of the RX Used interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
newline
|
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bitfld.long 0x4 1. "RECEIVE_COMPLETE_INTERRUPT_MASK,receive complete interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
line.long 0x8 "INT_Q3_MASK,int_q3_mask to int_q7_mask doesn't present. Access to the register returns AHB error."
|
|
hexmask.long 0x8 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x1658++0x3
|
|
line.long 0x0 "INT_Q7_MASK,Not presents."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x1660++0x3
|
|
line.long 0x0 "INT_Q8_ENABLE,int_q8_enable to int_q15_enable doesn't present. Access to the register returns AHB error."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x167C++0x7
|
|
line.long 0x0 "INT_Q15_ENABLE,Not presents."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
line.long 0x4 "INT_Q8_DISABLE,int_q8_disable to int_q15_disable doesn't present. Access to the register returns AHB error."
|
|
hexmask.long 0x4 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x169C++0x7
|
|
line.long 0x0 "INT_Q15_DISABLE,Not presents."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
line.long 0x4 "INT_Q8_MASK,int_q8_mask to int_q15_mask doesn't present. Access to the register returns AHB error."
|
|
hexmask.long 0x4 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x16BC++0x3
|
|
line.long 0x0 "INT_Q15_MASK,Not presents."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
group.long 0x16E0++0x11F
|
|
line.long 0x0 "SCREENING_TYPE_2_ETHERTYPE_REG_0,Ethertype Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RSVD_31_16,N/A"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "COMPARE_VALUE,'EtherType compare value'"
|
|
line.long 0x4 "SCREENING_TYPE_2_ETHERTYPE_REG_1,Ethertype Register"
|
|
hexmask.long.word 0x4 16.--31. 1. "RSVD_31_16,N/A"
|
|
newline
|
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hexmask.long.word 0x4 0.--15. 1. "COMPARE_VALUE,'EtherType compare value'"
|
|
line.long 0x8 "SCREENING_TYPE_2_ETHERTYPE_REG_2,Ethertype Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "RSVD_31_16,N/A"
|
|
newline
|
|
hexmask.long.word 0x8 0.--15. 1. "COMPARE_VALUE,'EtherType compare value'"
|
|
line.long 0xC "SCREENING_TYPE_2_ETHERTYPE_REG_3,Ethertype Register"
|
|
hexmask.long.word 0xC 16.--31. 1. "RSVD_31_16,N/A"
|
|
newline
|
|
hexmask.long.word 0xC 0.--15. 1. "COMPARE_VALUE,'EtherType compare value'"
|
|
line.long 0x10 "SCREENING_TYPE_2_ETHERTYPE_REG_4,Ethertype Register"
|
|
hexmask.long.word 0x10 16.--31. 1. "RSVD_31_16,N/A"
|
|
newline
|
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hexmask.long.word 0x10 0.--15. 1. "COMPARE_VALUE,'EtherType compare value'"
|
|
line.long 0x14 "SCREENING_TYPE_2_ETHERTYPE_REG_5,Ethertype Register"
|
|
hexmask.long.word 0x14 16.--31. 1. "RSVD_31_16,N/A"
|
|
newline
|
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hexmask.long.word 0x14 0.--15. 1. "COMPARE_VALUE,'EtherType compare value'"
|
|
line.long 0x18 "SCREENING_TYPE_2_ETHERTYPE_REG_6,Ethertype Register"
|
|
hexmask.long.word 0x18 16.--31. 1. "RSVD_31_16,N/A"
|
|
newline
|
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hexmask.long.word 0x18 0.--15. 1. "COMPARE_VALUE,'EtherType compare value'"
|
|
line.long 0x1C "SCREENING_TYPE_2_ETHERTYPE_REG_7,Ethertype Register"
|
|
hexmask.long.word 0x1C 16.--31. 1. "RSVD_31_16,N/A"
|
|
newline
|
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hexmask.long.word 0x1C 0.--15. 1. "COMPARE_VALUE,'EtherType compare value'"
|
|
line.long 0x20 "TYPE2_COMPARE_0_WORD_0,'Compare A. B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame. ANDed with the MASK Value if the mask.."
|
|
hexmask.long.word 0x20 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
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|
newline
|
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hexmask.long.word 0x20 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x24 "TYPE2_COMPARE_0_WORD_1,'Type2 Compare Word 1'"
|
|
hexmask.long.tbyte 0x24 10.--31. 1. "RSVD_31_10,N/A"
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newline
|
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bitfld.long 0x24 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
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|
newline
|
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bitfld.long 0x24 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
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hexmask.long.byte 0x24 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x28 "TYPE2_COMPARE_1_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x28 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
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hexmask.long.word 0x28 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x2C "TYPE2_COMPARE_1_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x2C 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
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bitfld.long 0x2C 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
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bitfld.long 0x2C 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
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hexmask.long.byte 0x2C 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x30 "TYPE2_COMPARE_2_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x30 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
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hexmask.long.word 0x30 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x34 "TYPE2_COMPARE_2_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x34 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x34 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x34 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x34 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x38 "TYPE2_COMPARE_3_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x38 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x38 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x3C "TYPE2_COMPARE_3_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x3C 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x3C 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x3C 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x3C 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x40 "TYPE2_COMPARE_4_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x40 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x40 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x44 "TYPE2_COMPARE_4_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x44 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x44 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x44 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x44 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x48 "TYPE2_COMPARE_5_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x48 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x48 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x4C "TYPE2_COMPARE_5_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x4C 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x4C 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x4C 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x4C 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x50 "TYPE2_COMPARE_6_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x50 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x50 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x54 "TYPE2_COMPARE_6_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x54 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x54 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x54 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x54 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x58 "TYPE2_COMPARE_7_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x58 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x58 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x5C "TYPE2_COMPARE_7_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x5C 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x5C 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x5C 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x5C 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x60 "TYPE2_COMPARE_8_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x60 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x60 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x64 "TYPE2_COMPARE_8_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x64 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x64 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x64 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x64 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x68 "TYPE2_COMPARE_9_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x68 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x68 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x6C "TYPE2_COMPARE_9_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x6C 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x6C 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x6C 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x6C 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x70 "TYPE2_COMPARE_10_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x70 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x70 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x74 "TYPE2_COMPARE_10_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x74 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x74 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x74 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x74 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x78 "TYPE2_COMPARE_11_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x78 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x78 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x7C "TYPE2_COMPARE_11_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x7C 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x7C 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x7C 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x7C 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x80 "TYPE2_COMPARE_12_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x80 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x80 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x84 "TYPE2_COMPARE_12_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x84 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x84 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x84 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x84 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x88 "TYPE2_COMPARE_13_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x88 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x88 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x8C "TYPE2_COMPARE_13_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x8C 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x8C 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x8C 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x8C 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x90 "TYPE2_COMPARE_14_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x90 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x90 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x94 "TYPE2_COMPARE_14_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x94 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x94 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x94 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x94 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x98 "TYPE2_COMPARE_15_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x98 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x98 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x9C "TYPE2_COMPARE_15_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x9C 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x9C 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x9C 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x9C 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0xA0 "TYPE2_COMPARE_16_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0xA0 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0xA0 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0xA4 "TYPE2_COMPARE_16_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0xA4 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0xA4 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0xA4 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0xA4 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0xA8 "TYPE2_COMPARE_17_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0xA8 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0xA8 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0xAC "TYPE2_COMPARE_17_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0xAC 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0xAC 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0xAC 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0xAC 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0xB0 "TYPE2_COMPARE_18_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0xB0 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0xB0 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0xB4 "TYPE2_COMPARE_18_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0xB4 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0xB4 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0xB4 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0xB4 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0xB8 "TYPE2_COMPARE_19_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0xB8 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0xB8 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0xBC "TYPE2_COMPARE_19_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0xBC 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0xBC 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0xBC 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0xBC 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0xC0 "TYPE2_COMPARE_20_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0xC0 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0xC0 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0xC4 "TYPE2_COMPARE_20_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0xC4 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0xC4 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0xC4 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0xC4 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0xC8 "TYPE2_COMPARE_21_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0xC8 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0xC8 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0xCC "TYPE2_COMPARE_21_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0xCC 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0xCC 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0xCC 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0xCC 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0xD0 "TYPE2_COMPARE_22_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0xD0 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0xD0 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0xD4 "TYPE2_COMPARE_22_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0xD4 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0xD4 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0xD4 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0xD4 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0xD8 "TYPE2_COMPARE_23_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0xD8 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0xD8 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0xDC "TYPE2_COMPARE_23_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0xDC 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0xDC 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0xDC 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0xDC 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0xE0 "TYPE2_COMPARE_24_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0xE0 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0xE0 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0xE4 "TYPE2_COMPARE_24_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0xE4 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0xE4 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0xE4 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0xE4 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0xE8 "TYPE2_COMPARE_25_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0xE8 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0xE8 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0xEC "TYPE2_COMPARE_25_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0xEC 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0xEC 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0xEC 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0xEC 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0xF0 "TYPE2_COMPARE_26_WORD_0,same as type2_compare_0_word_0"
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hexmask.long.word 0xF0 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
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hexmask.long.word 0xF0 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
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line.long 0xF4 "TYPE2_COMPARE_26_WORD_1,same as type2_compare_0_word_1"
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hexmask.long.tbyte 0xF4 10.--31. 1. "RSVD_31_10,N/A"
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bitfld.long 0xF4 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
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bitfld.long 0xF4 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
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hexmask.long.byte 0xF4 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
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line.long 0xF8 "TYPE2_COMPARE_27_WORD_0,same as type2_compare_0_word_0"
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hexmask.long.word 0xF8 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
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hexmask.long.word 0xF8 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
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line.long 0xFC "TYPE2_COMPARE_27_WORD_1,same as type2_compare_0_word_1"
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hexmask.long.tbyte 0xFC 10.--31. 1. "RSVD_31_10,N/A"
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bitfld.long 0xFC 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
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bitfld.long 0xFC 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
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hexmask.long.byte 0xFC 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
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line.long 0x100 "TYPE2_COMPARE_28_WORD_0,same as type2_compare_0_word_0"
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hexmask.long.word 0x100 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
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hexmask.long.word 0x100 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
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line.long 0x104 "TYPE2_COMPARE_28_WORD_1,same as type2_compare_0_word_1"
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hexmask.long.tbyte 0x104 10.--31. 1. "RSVD_31_10,N/A"
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bitfld.long 0x104 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
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bitfld.long 0x104 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
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hexmask.long.byte 0x104 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
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line.long 0x108 "TYPE2_COMPARE_29_WORD_0,same as type2_compare_0_word_0"
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hexmask.long.word 0x108 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
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hexmask.long.word 0x108 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
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line.long 0x10C "TYPE2_COMPARE_29_WORD_1,same as type2_compare_0_word_1"
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hexmask.long.tbyte 0x10C 10.--31. 1. "RSVD_31_10,N/A"
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bitfld.long 0x10C 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
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bitfld.long 0x10C 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
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hexmask.long.byte 0x10C 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
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line.long 0x110 "TYPE2_COMPARE_30_WORD_0,same as type2_compare_0_word_0"
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hexmask.long.word 0x110 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
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hexmask.long.word 0x110 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
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line.long 0x114 "TYPE2_COMPARE_30_WORD_1,same as type2_compare_0_word_1"
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hexmask.long.tbyte 0x114 10.--31. 1. "RSVD_31_10,N/A"
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bitfld.long 0x114 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
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bitfld.long 0x114 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
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hexmask.long.byte 0x114 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
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line.long 0x118 "TYPE2_COMPARE_31_WORD_0,same as type2_compare_0_word_0"
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hexmask.long.word 0x118 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
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hexmask.long.word 0x118 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
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line.long 0x11C "TYPE2_COMPARE_31_WORD_1,same as type2_compare_0_word_1"
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hexmask.long.tbyte 0x11C 10.--31. 1. "RSVD_31_10,N/A"
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bitfld.long 0x11C 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
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bitfld.long 0x11C 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
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hexmask.long.byte 0x11C 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
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tree.end
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tree "ETH1"
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base ad:0x40490000
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group.long 0x0++0x3
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line.long 0x0 "CTL,MXETH Control Register"
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bitfld.long 0x0 31. "ENABLED,MXETH enable:" "0,1"
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hexmask.long.byte 0x0 8.--15. 1. "REFCLK_DIV,Specify the ref_clk divider. Integer division by (1+REFCLK_DIV). Allows for integer divisions in the range [1 256]."
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bitfld.long 0x0 2. "REFCLK_SRC_SEL,Select the source for ref_clk." "0: Ref_clk comes from REF_CLK_IN input port,1: Ref_clk comes from REF_CLK_INT_IN input port"
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bitfld.long 0x0 0.--1. "ETH_MODE,Set ethernet mode. The speed of 10M/100M/1G is selected by programming network_config after IP is enabled." "0: MII mode (10/100MHz speed is determined by..,1: GMII mode (network_config[10] must be set to..,2: RGMII mode (10M/100M/1G speed is determined by..,3: RMII mode (10M/100M speed is determined by.."
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rgroup.long 0x4++0x3
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line.long 0x0 "STATUS,MXETH Status Register"
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hexmask.long.byte 0x0 8.--15. 1. "RX_PFC_PAUSED,Each bit corresponds to a priority indicated within the PFC priority based pause frame."
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bitfld.long 0x0 0. "PFC_NEGOTIATE,Identifies that PFC priority based pause flow control" "0: No PFC priority based pause frames have yet,1: At least one PFC priority based pause frames"
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group.long 0x1000++0x7
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line.long 0x0 "NETWORK_CONTROL,The network control register contains general MAC control functions for both receiver and transmitter."
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rbitfld.long 0x0 31. "EXT_RXQ_RSVD_31,N/A" "0,1"
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bitfld.long 0x0 30. "IFG_EATS_QAV_CREDIT,Setting this bit high modifies the CBS algorithm so the" "0,1"
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bitfld.long 0x0 29. "TWO_PT_FIVE_GIG,2.5G operation selected - setting this bit high drives" "0,1"
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bitfld.long 0x0 28. "SEL_MII_ON_RGMII,If the RGMII interface being used set this bit high to" "0,1"
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bitfld.long 0x0 27. "OSS_CORRECTION_FIELD,1588 One Step Correction Field Update. Set this bit" "0,1"
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bitfld.long 0x0 26. "EXT_RXQ_SEL_EN,Enable external selection of receive queue. When this bit is high the ext_match1 ext_match2 ext_match3 and ext_match4 inputs will determine which receive queue a frame is routed to. This will be the case regardless of the state of the.." "0,1"
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bitfld.long 0x0 25. "PFC_CTRL,'Enable multiple PFC pause quantums one per pause priority'" "0,1"
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bitfld.long 0x0 24. "ONE_STEP_SYNC_MODE,1588 One Step Sync Mode. Write 1 to enable. Replace timestamp field in the 1588 header for TX Sync Frames with current TSU timer value." "0,1"
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rbitfld.long 0x0 23. "EXT_TSU_PORT_ENABLE,Write ignore read 0" "0,1"
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bitfld.long 0x0 22. "STORE_UDP_OFFSET,N/A" "0,1"
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bitfld.long 0x0 21. "ALT_SGMII_MODE,Alternative sgmii mode. If asserted with sgmii_mode in the network control register the ACK bit is driven before ability detect during transfer of status information from the PHY to the MAC." "0,1"
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bitfld.long 0x0 20. "PTP_UNICAST_ENA,Enable detection of unicast PTP unicast frames." "0,1"
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bitfld.long 0x0 19. "TX_LPI_EN,Enable LPI transmission when set LPI (low power idle) is immediately transmitted. LPI is transmitted even if bit 3 transmit enable is disabled. Setting this bit also sends a pause signal to the transmit datapath." "0,1"
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bitfld.long 0x0 18. "FLUSH_RX_PKT_PCLK,Flush the next packet from the external RX DPRAM. Writing one to this bit will only have an effect if the DMA is not currently writing a packet already stored in the DPRAM to memory. Self clearing register." "0,1"
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bitfld.long 0x0 17. "TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME,Write a one to transmit PFC priority based pause frame. Takes the values stored in the Transmit PFC Pause Register. Self clearing register." "0,1"
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bitfld.long 0x0 16. "PFC_ENABLE,Enable PFC Priority Based Pause Reception capabilities. Setting this bit will enable PFC negotiation and recognition of priority based pause frames." "0,1"
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bitfld.long 0x0 15. "STORE_RX_TS,Store receive time stamp to memory. Setting this bit to one will cause the CRC of every received frame to be replaced with the value of the nanoseconds field of the 1588 timer that was captured as the receive frame passed the message time.." "0,1"
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rbitfld.long 0x0 14. "REMOVED_14,Write ignore read 0" "0,1"
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rbitfld.long 0x0 13. "REMOVED_13,Write ignore read 0" "0,1"
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bitfld.long 0x0 12. "TX_PAUSE_FRAME_ZERO,Transmit zero quantum pause frame - writing one to this bit causes a pause frame with zero quantum to be transmitted." "0,1"
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newline
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bitfld.long 0x0 11. "TX_PAUSE_FRAME_REQ,Transmit pause frame - writing one to this bit causes a pause frame to be transmitted. Self clearing register." "0,1"
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newline
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bitfld.long 0x0 10. "TX_HALT_PCLK,Transmit halt - writing one to this bit halts transmission as soon as any ongoing frame transmission ends." "0,1"
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bitfld.long 0x0 9. "TX_START_PCLK,Start transmission - writing one to this bit starts transmission." "0,1"
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bitfld.long 0x0 8. "BACK_PRESSURE,Back pressure if set in 10M or 100M half duplex mode will force collisions on all received frames. Ignored in gigabit half duplex mode." "0,1"
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bitfld.long 0x0 7. "STATS_WRITE_EN,Write enable for statistics registers - setting this bit to one means the statistics registers can be written for functional test purposes." "0,1"
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bitfld.long 0x0 6. "INC_ALL_STATS_REGS,Incremental statistics registers - this bit is write only. Writing a one increments all the statistics registers by one for test purposes. Self clearing register." "0,1"
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bitfld.long 0x0 5. "CLEAR_ALL_STATS_REGS,Clear statistics registers - this bit is write only. Writing a one clears the statistics registers. Self clearing register." "0,1"
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newline
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bitfld.long 0x0 4. "MAN_PORT_EN,Management port enable - set to one to enable the management port. When zero forces mdio to high impedance state and mdc low." "0,1"
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bitfld.long 0x0 3. "ENABLE_TRANSMIT,Transmit enable - when set it enables the GEM transmitter to send data. When reset transmission will stop immediately the transmit pipeline and control registers will be cleared and the transmit queue pointer register will reset to.." "0,1"
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bitfld.long 0x0 2. "ENABLE_RECEIVE,Receive enable - when set it enables the GEM to receive data. When reset frame reception will stop immediately and the receive pipeline will be cleared. The receive queue pointer register is unaffected." "0,1"
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newline
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bitfld.long 0x0 1. "LOOPBACK_LOCAL,Loopback local - asserts the loopback_local signal to the system clock generator. Also connects txd to rxd tx_en to rx_dv and forces full duplex mode. Bit 11 of the network configuration register must be set low to disable TBI mode when.." "0,1"
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newline
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bitfld.long 0x0 0. "LOOPBACK,Loopback - controls the loopback output pin." "0,1"
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line.long 0x4 "NETWORK_CONFIG,The network configuration register contains functions for setting the mode of operation for the Gigabit Ethernet MAC."
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bitfld.long 0x4 31. "RSVD_31,N/A" "0,1"
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bitfld.long 0x4 30. "IGNORE_IPG_RX_ER,Ignore IPG rx_er. When set rx_er has no effect on the GEMs operation when rx_dv is low. Set this when using the RGMII wrapper in half-duplex mode." "0,1"
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bitfld.long 0x4 29. "NSP_CHANGE,Receive bad preamble. When set frames with non-standard preamble are not rejected." "0,1"
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bitfld.long 0x4 28. "IPG_STRETCH_ENABLE,IPG stretch enable - when set the transmit IPG can be increased above 96 bit times depending on the previous frame length using the IPG stretch register." "0,1"
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newline
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bitfld.long 0x4 27. "SGMII_MODE_ENABLE,SGMII mode enable - changes behaviour of the auto-negotiation advertisement and link partner ability registers to meet the requirements of SGMII and reduces the duration of the link timer from 10 ms to 1.6 ms." "0,1"
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bitfld.long 0x4 26. "IGNORE_RX_FCS,Ignore RX FCS - when set frames with FCS/CRC errors will not be rejected. FCS error statistics will still be collected for frames with bad FCS and FCS status will be recorded in frame's DMA descriptor. For normal operation this bit must be.." "0,1"
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bitfld.long 0x4 25. "EN_HALF_DUPLEX_RX,Enable frames to be received in half-duplex mode while transmitting." "0,1"
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bitfld.long 0x4 24. "RECEIVE_CHECKSUM_OFFLOAD_ENABLE,Receive checksum offload enable - when set the receive checksum engine is enabled. Frames with bad IP TCP or UDP checksums are discarded." "0,1"
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bitfld.long 0x4 23. "DISABLE_COPY_OF_PAUSE_FRAMES,Disable copy of pause frames - set to one to prevent pause frames being copied to memory. When set neither control frames with type id 8808 nor pause frames with destination address 010000c28001 are copied to memory this.." "0,1"
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bitfld.long 0x4 21.--22. "DATA_BUS_WIDTH,Data bus width - set according to AMBA (AXI/AHB) or external FIFO data bus width. The reset value for this can be changed by defining a new value for gem_dma_bus_width_def in gem_defs. Only valid bus widths may be written if the system is.." "0,1,2,3"
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bitfld.long 0x4 18.--20. "MDC_CLOCK_DIVISION,MDC clock division - set according to pclk speed. These three bits determine the number pclk will be divided by to generate MDC. For conformance with the 802.3 specification MDC must not exceed 2.5 MHz (MDC is only active during MDIO.." "0: divide pclk by 8,1: divide pclk by 16,?,?,?,?,?,?"
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bitfld.long 0x4 17. "FCS_REMOVE,FCS remove - setting this bit will cause received frames to be written to memory without their frame check sequence (last 4 bytes). The frame length indicated will be reduced by four bytes in this mode." "0,1"
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bitfld.long 0x4 16. "LENGTH_FIELD_ERROR_FRAME_DISCARD,Length field error frame discard - setting this bit causes frames with a measured length shorter than the extracted length field (as indicated by bytes 13 and 14 in a non-VLAN tagged frame) to be discarded. This only.." "0,1"
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bitfld.long 0x4 14.--15. "RECEIVE_BUFFER_OFFSET,Receive buffer offset - indicates the number of bytes by which the received data is offset from the start of the receive buffer." "0,1,2,3"
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bitfld.long 0x4 13. "PAUSE_ENABLE,Pause enable - when set transmission will pause if a non zero 802.3 classic pause frame is received and PFC has not been negotiated." "0,1"
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bitfld.long 0x4 12. "RETRY_TEST,Retry test - must be set to zero for normal operation. If set to one the backoff between collisions will always be one slot time. Setting this bit to one helps test the too many retries condition. Also used in the pause frame tests to reduce.." "0,1"
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bitfld.long 0x4 11. "PCS_SELECT,PCS select - selects between MII/GMII and TBI" "0,1"
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newline
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bitfld.long 0x4 10. "GIGABIT_MODE_ENABLE,Gigabit mode enable - setting this bit configures the GEM for 1000 Mbps operation." "?,1: Gigabit operation using GMI interface"
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newline
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bitfld.long 0x4 9. "EXTERNAL_ADDRESS_MATCH_ENABLE,External address match enable - when set the external address match interface can be used to copy frames to memory." "0,1"
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newline
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bitfld.long 0x4 8. "RECEIVE_1536_BYTE_FRAMES,Receive 1536 byte frames - setting this bit means the GEM will accept frames up to 1536 bytes in length. Normally the GEM would reject any frame above 1518 bytes." "0,1"
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bitfld.long 0x4 7. "UNICAST_HASH_ENABLE,Unicast hash enable - when set unicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register." "0,1"
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bitfld.long 0x4 6. "MULTICAST_HASH_ENABLE,Multicast hash enable - when set multicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the hash register." "0,1"
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bitfld.long 0x4 5. "NO_BROADCAST,No broadcast - when set to logic one frames addressed to the broadcast address of all ones will not be accepted." "0,1"
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bitfld.long 0x4 4. "COPY_ALL_FRAMES,Copy all frames - when set to logic one all valid frames will be accepted." "0,1"
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bitfld.long 0x4 3. "JUMBO_FRAMES,Jumbo frames - set to one to enable jumbo frames up to `gem_jumbo_max_length bytes to be accepted. The default length is 10 240 bytes." "0,1"
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newline
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bitfld.long 0x4 2. "DISCARD_NON_VLAN_FRAMES,Discard non-VLAN frames - when set only VLAN tagged frames will be passed to the address matching logic." "0,1"
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newline
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bitfld.long 0x4 1. "FULL_DUPLEX,Full duplex - if set to logic one the transmit block ignores the state of collision and carrier sense and allows receive while transmitting. Also controls the half_duplex pin." "0,1"
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newline
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bitfld.long 0x4 0. "SPEED,Speed - set to logic one to indicate 100Mbps operation logic zero for 10Mbps." "0,1"
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rgroup.long 0x1008++0x7
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line.long 0x0 "NETWORK_STATUS,The network status register returns status information with respect to the PHY management interface."
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bitfld.long 0x0 7. "LPI_INDICATE_PCLK,LPI Indication - Low power idle has been detected on receive. This bit is set when LPI is detected and reset when normal idle is detected. An interrupt is generated when the state of this bit changes." "0,1"
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newline
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bitfld.long 0x0 6. "PFC_NEGOTIATE_PCLK,Set when PFC Priority Based Pause has been negotiated." "0,1"
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newline
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bitfld.long 0x0 4.--5. "REMOVED_5_4,N/A" "0,1,2,3"
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newline
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bitfld.long 0x0 3. "MAC_FULL_DUPLEX,PCS auto-negotiation duplex resolution. Set to one if the resolution function determines that both devices are capable of full duplex operation. If zero half-duplex operation is possible as long as bit 0 (PCS link state) is also one." "0,1"
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newline
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bitfld.long 0x0 2. "MAN_DONE,The PHY management logic is idle (i.e. has completed)." "0,1"
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newline
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bitfld.long 0x0 1. "MDIO_IN,Returns status of the mdio_in pin." "0,1"
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newline
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bitfld.long 0x0 0. "PCS_LINK_STATE,Returns status of PCS link state. If auto-negotiation is disabled this returns the synchronisation status. If auto-negotiation is enabled it is set in the LINK_OK state as long as a compatible duplex mode is resolved." "0,1"
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line.long 0x4 "USER_IO_REGISTER,Not presents. Access to the register will return AHB error."
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hexmask.long 0x4 0.--31. 1. "RSVD_31_0,Write ignore read 0"
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group.long 0x1010++0x17
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line.long 0x0 "DMA_CONFIG,DMA Configuration Register"
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bitfld.long 0x0 30. "DMA_ADDR_BUS_WIDTH_1,DMA address bus width. 0 = 32b 1 = 64b. MXETH only supports 32b DMA address bus width so must set it 0." "0,1"
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newline
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bitfld.long 0x0 29. "TX_BD_EXTENDED_MODE_EN,Enable TX extended BD mode. See TX BD control register definition for description of feature." "0,1"
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newline
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bitfld.long 0x0 28. "RX_BD_EXTENDED_MODE_EN,Enable RX extended BD mode. See RX BD control register definition for description of feature." "0,1"
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bitfld.long 0x0 26. "FORCE_MAX_AMBA_BURST_TX,Force max length bursts on TX. Force the TX DMA to always issue max length bursts on EOP(end of packet) or EOB(end of buffer) transfers as defined by bits 4:0 of this register even when there is less that max burst data bytes to.." "0,1"
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bitfld.long 0x0 25. "FORCE_MAX_AMBA_BURST_RX,Force max length bursts on RX. Force the RX DMA to always issue max length bursts on EOP(end of packet) or EOB(end of buffer)transfers even if there is less than max burst real packet data required to write. Any extra bytes of.." "0,1"
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bitfld.long 0x0 24. "FORCE_DISCARD_ON_ERR,Auto Discard RX pkts during lack of resource. When set the GEM DMA will automatically discard receive packets from the receiver packet buffer memory when no AMBA (AXI/AHB) resource is available. When low then received packets will.." "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "RX_BUF_SIZE,DMA receive buffer size in external AMBA (AXI/AHB) system memory. The value defined by these bits determines the size of buffer to use in main system memory when writing received data. The value is defined in multiples of 64 bytes."
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bitfld.long 0x0 13. "CRC_ERROR_REPORT,When the bit is set bit 16 of the receive buffer descriptor will represent FCS/CRC error (only if frames with FCS are copied to memory as enabled by bit 26 in the network config register). When this bit is clear bit 16 of the receive.." "0,1"
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bitfld.long 0x0 12. "INFINITE_LAST_DBUF_SIZE_EN,Forces the DMA to consider the data buffer pointed to by last descriptor in the descriptor list to be of infinite size." "0,1"
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bitfld.long 0x0 11. "TX_PBUF_TCP_EN,N/A" "0,1"
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bitfld.long 0x0 10. "TX_PBUF_SIZE,N/A" "0,1"
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bitfld.long 0x0 8.--9. "RX_PBUF_SIZE,N/A" "0,1,2,3"
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bitfld.long 0x0 7. "ENDIAN_SWAP_PACKET,endian swap mode enable for packet data accesses. When set selects swapped endianism for AMBA (AXI/AHB) transfers. When clear selects little endian mode. Note the default value of this bit equals to `gem_endian_swap_def which is.." "0,1"
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bitfld.long 0x0 6. "ENDIAN_SWAP_MANAGEMENT,endian swap mode enable for management descriptor accesses. When set selects swapped endianism for AMBA (AXI/AHB) transfers. When clear selects little endian mode. Note the default value of this bit equals to.." "0,1"
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bitfld.long 0x0 5. "HDR_DATA_SPLITTING_EN,Enable header data Splitting. When set receive frames will be forwarded to main memory using a minimum of two DMA data buffers. The first X data buffers will contain the frame header consisting of the Ethernet VLAN (IPv4 or.." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "AMBA_BURST_LENGTH,Selects the burst length to use on the AMBA (AHB/AXI) when transferring frame data. Not used for DMA management operations and only used where space and data size allow and respecting AXI/AHB burst boundary rules. One-hot priority.."
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line.long 0x4 "TRANSMIT_STATUS,This register. when read. provides details of the status of a transmit. Once read. individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register."
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bitfld.long 0x4 8. "RESP_NOT_OK123,bresp/hresp not OK - set when the DMA block sees bresp/hresp not OK. Cleared by writing a one to this bit." "0,1"
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bitfld.long 0x4 7. "LATE_COLLISION_OCCURRED,Late collision occurred - only set if the condition occurs in gigabit mode as retry is not attempted. Cleared by writing a one to this bit." "0,1"
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bitfld.long 0x4 6. "TRANSMIT_UNDER_RUN123,Transmit under run - this bit is set if the transmitter was forced to terminate a frame that it had already began transmitting due to further data being unavailable. This bit is set if a transmitter status write back has not.." "0,1"
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bitfld.long 0x4 5. "TRANSMIT_COMPLETE123,Transmit complete - set when a frame has been transmitted. Cleared by writing a one to this bit." "0,1"
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bitfld.long 0x4 4. "AMBA_ERROR123,Transmit frame corruption due to AMBA (AXI/AHB) errors. Set if an error occurs whilst midway through reading transmit frame from external memory including RRESP or BRESP errors and buffers exhausted mid frame (if the buffers run out during.." "0,1"
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rbitfld.long 0x4 3. "TRANSMIT_GO,Transmit go - if high transmit is active. When using the exposed FIFO interface this bit represents bit 3 of the network control register. When using the DMA interface this bit represents the tx_go variable as specified in the transmit.." "0,1"
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bitfld.long 0x4 2. "RETRY_LIMIT_EXCEEDED,Retry limit exceeded - cleared by writing a one to this bit." "0,1"
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bitfld.long 0x4 1. "COLLISION_OCCURRED,Collision occurred - set by the assertion of collision. Cleared by writing a one to this bit. When operating in 10/100 mode this status indicates either a collision or a late collision. In gigabit mode this status is not set for a.." "0,1"
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bitfld.long 0x4 0. "USED_BIT_READ,Used bit read - set when a transmit buffer descriptor is read with its used bit set. Cleared by writing a one to this bit." "0,1"
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line.long 0x8 "RECEIVE_Q_PTR,This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once.."
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hexmask.long 0x8 2.--31. 1. "DMA_RX_Q_PTR,Receive buffer queue base address - written with the address of the start of the receive queue."
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bitfld.long 0x8 0. "DMA_RX_DIS_Q,Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while receive is not enabled." "0,1"
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line.long 0xC "TRANSMIT_Q_PTR,This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control.."
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hexmask.long 0xC 2.--31. 1. "DMA_TX_Q_PTR,Transmit buffer queue base address - written with the address of the start of the transmit queue."
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bitfld.long 0xC 0. "DMA_TX_DIS_Q,Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while transmit is not enabled." "0,1"
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line.long 0x10 "RECEIVE_STATUS,This register. when read provides details of the status of a receive. Once read. individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register."
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bitfld.long 0x10 3. "RESP_NOT_OK1234,bresp not OK - set when the DMA block sees bresp/hresp not OK. Cleared by writing a one to this bit." "0,1"
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bitfld.long 0x10 2. "RECEIVE_OVERRUN123,Receive overrun - this bit is set if either the gem_dma RX FIFO or external RX FIFO were unable to store the receive frame due to a FIFO overflow or if the receive status reported by the gem_rx module to the gem_dma was not taken at.." "0,1"
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bitfld.long 0x10 1. "FRAME_RECEIVED,Frame received - one or more frames have been received and placed in memory. Cleared by writing a one to this bit." "0,1"
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bitfld.long 0x10 0. "BUFFER_NOT_AVAILABLE,Buffer not available - an attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA will reread the pointer each time an end of frame is received until a valid pointer is found. This.." "0,1"
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line.long 0x14 "INT_STATUS,If not configured for priority queueing. the GEM generates a single interrupt. This register indicates the source of this interrupt. The corresponding bit in the mask register must be clear for a bit to be set. If any bit is set in this.."
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bitfld.long 0x14 29. "TSU_TIMER_COMPARISON_INTERRUPT,TSU timer comparison interrupt. Indicates when TSU timer count value is equal to programmed value." "0,1"
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rbitfld.long 0x14 28. "REMOVED_28,Write ignore read 0" "0,1"
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bitfld.long 0x14 27. "RECEIVE_LPI_INDICATION_STATUS_BIT_CHANGE,Receive LPI indication status bit change" "0,1"
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bitfld.long 0x14 26. "TSU_SECONDS_REGISTER_INCREMENT,TSU seconds register increment indicates the register has incremented. Cleared on read." "0,1"
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bitfld.long 0x14 25. "PTP_PDELAY_RESP_FRAME_TRANSMITTED,PTP pdelay_resp frame transmitted indicates a PTP pdelay_resp frame has been transmitted. Cleared on read." "0,1"
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bitfld.long 0x14 24. "PTP_PDELAY_REQ_FRAME_TRANSMITTED,PTP pdelay_req frame transmitted indicates a PTP pdelay_req frame has been transmitted. Cleared on read." "0,1"
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bitfld.long 0x14 23. "PTP_PDELAY_RESP_FRAME_RECEIVED,PTP pdelay_resp frame received indicates a PTP pdelay_resp frame has been received. Cleared on read." "0,1"
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bitfld.long 0x14 22. "PTP_PDELAY_REQ_FRAME_RECEIVED,PTP pdelay_req frame received indicates a PTP pdelay_req frame has been received. Cleared on read." "0,1"
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bitfld.long 0x14 21. "PTP_SYNC_FRAME_TRANSMITTED,PTP sync frame transmitted indicates a PTP sync frame has been transmitted. Cleared on read." "0,1"
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bitfld.long 0x14 20. "PTP_DELAY_REQ_FRAME_TRANSMITTED,PTP delay_req frame transmitted indicates a PTP delay_req frame has been transmitted. Cleared on read." "0,1"
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bitfld.long 0x14 19. "PTP_SYNC_FRAME_RECEIVED,PTP sync frame received indicates a PTP sync frame has been received. Cleared on read." "0,1"
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bitfld.long 0x14 18. "PTP_DELAY_REQ_FRAME_RECEIVED,PTP delay_req frame received indicates a PTP delay_req frame has been received. Cleared on read." "0,1"
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rbitfld.long 0x14 17. "REMOVED_17,Write ignore read 0" "0,1"
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rbitfld.long 0x14 16. "REMOVED_16,Write ignore read 0" "0,1"
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rbitfld.long 0x14 15. "REMOVED_15,Write ignore read 0" "0,1"
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bitfld.long 0x14 14. "PAUSE_FRAME_TRANSMITTED,Pause frame transmitted - indicates a pause frame has been successfully transmitted after being initiated from the network control register or from the tx_pause control pin. Cleared on read." "0,1"
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bitfld.long 0x14 13. "PAUSE_TIME_ELAPSED,Pause Time elapsed. set when either the pause time register at address 0x38 decrements to zero or when a valid pause frame is received with a zero pause quantum field. Cleared on read." "0,1"
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bitfld.long 0x14 12. "PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_RECEIVED,Pause frame with non-zero pause quantum received - indicates a valid pause has been received that has a non-zero pause quantum field. Cleared on read." "0,1"
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bitfld.long 0x14 11. "RESP_NOT_OK,bresp not OK - set when the DMA block sees bresp not OK. Cleared on read." "0,1"
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bitfld.long 0x14 10. "RECEIVE_OVERRUN,Receive overrun - set when the receive overrun status bit gets set. Cleared on read." "0,1"
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rbitfld.long 0x14 9. "REMOVED_9,Write ignore read 0" "0,1"
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bitfld.long 0x14 7. "TRANSMIT_COMPLETE,Transmit complete - set when a frame has been transmitted. Cleared on read." "0,1"
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bitfld.long 0x14 6. "AMBA_ERROR,Transmit frame corruption due to AMBA (AXI/AHB) error. Set if an error occurs whilst midway through reading transmit frame from external system memory including HRESP (AHB) RRESP or BRESP(AXI) errors and buffers exhausted mid frame (if the.." "0,1"
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bitfld.long 0x14 5. "RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION,Retry limit exceeded or late collision - transmit error. Late collision will only cause this status bit to be set in gigabit mode (as a retry is not attempted). Cleared on read." "0,1"
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bitfld.long 0x14 4. "TRANSMIT_UNDER_RUN,Transmit under run - this interrupt is set if the transmitter was forced to terminate a frame that it has already began transmitting due to further data being unavailable. If an under run occurs the transmitter will force bad crc and.." "0,1"
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bitfld.long 0x14 3. "TX_USED_BIT_READ,TX used bit read - set when a transmit buffer descriptor is read with its used bit set. Cleared on read." "0,1"
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bitfld.long 0x14 2. "RX_USED_BIT_READ,RX used bit read - set when a receive buffer descriptor is read with its used bit set. Cleared on read." "0,1"
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bitfld.long 0x14 1. "RECEIVE_COMPLETE,Receive complete - a frame has been stored in memory. Cleared on read." "0,1"
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bitfld.long 0x14 0. "MANAGEMENT_FRAME_SENT,Management frame sent - the PHY maintenance register has completed its operation. Cleared on read." "0,1"
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wgroup.long 0x1028++0x3
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line.long 0x0 "INT_ENABLE,At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero."
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bitfld.long 0x0 29. "ENABLE_TSU_TIMER_COMPARISON_INTERRUPT,Enable TSU timer comparison interrupt." "0,1"
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bitfld.long 0x0 28. "UNUSED_28,Not used" "0,1"
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bitfld.long 0x0 27. "ENABLE_RX_LPI_INDICATION_INTERRUPT,Enable RX LPI indication interrupt" "0,1"
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bitfld.long 0x0 26. "ENABLE_TSU_SECONDS_REGISTER_INCREMENT,Enable TSU seconds register increment" "0,1"
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bitfld.long 0x0 25. "ENABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED,Enable PTP pdelay_resp frame transmitted" "0,1"
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bitfld.long 0x0 24. "ENABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED,Enable PTP pdelay_req frame transmitted" "0,1"
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bitfld.long 0x0 23. "ENABLE_PTP_PDELAY_RESP_FRAME_RECEIVED,Enable PTP pdelay_resp frame received" "0,1"
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bitfld.long 0x0 22. "ENABLE_PTP_PDELAY_REQ_FRAME_RECEIVED,Enable PTP pdelay_req frame received" "0,1"
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bitfld.long 0x0 21. "ENABLE_PTP_SYNC_FRAME_TRANSMITTED,Enable PTP sync frame transmitted" "0,1"
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bitfld.long 0x0 20. "ENABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED,Enable PTP delay_req frame transmitted" "0,1"
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bitfld.long 0x0 19. "ENABLE_PTP_SYNC_FRAME_RECEIVED,Enable PTP sync frame received" "0,1"
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bitfld.long 0x0 18. "ENABLE_PTP_DELAY_REQ_FRAME_RECEIVED,Enable PTP delay_req frame received" "0,1"
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bitfld.long 0x0 17. "UNUSED_17,Not used" "0,1"
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bitfld.long 0x0 16. "UNUSED_16,Not used" "0,1"
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bitfld.long 0x0 15. "UNUSED_15,Not used" "0,1"
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bitfld.long 0x0 14. "ENABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT,Enable pause frame transmitted interrupt" "0,1"
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bitfld.long 0x0 13. "ENABLE_PAUSE_TIME_ZERO_INTERRUPT,Enable pause time zero interrupt" "0,1"
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bitfld.long 0x0 12. "ENABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT,Enable pause frame with non-zero pause quantum interrupt" "0,1"
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bitfld.long 0x0 11. "ENABLE_RESP_NOT_OK_INTERRUPT,Enable bresp not OK interrupt" "0,1"
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bitfld.long 0x0 10. "ENABLE_RECEIVE_OVERRUN_INTERRUPT,Enable receive overrun interrupt" "0,1"
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bitfld.long 0x0 9. "UNUSED_9,Not used" "0,1"
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bitfld.long 0x0 8. "UNUSED_8,Not used" "0,1"
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bitfld.long 0x0 7. "ENABLE_TRANSMIT_COMPLETE_INTERRUPT,Enable transmit complete interrupt" "0,1"
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bitfld.long 0x0 6. "ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT,Enable transmit frame corruption due to AMBA (AXI/AHB) error interrupt" "0,1"
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bitfld.long 0x0 5. "ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT,Enable retry limit exceeded or late collision interrupt" "0,1"
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bitfld.long 0x0 4. "ENABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT,Enable transmit buffer under run interrupt" "0,1"
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bitfld.long 0x0 3. "ENABLE_TRANSMIT_USED_BIT_READ_INTERRUPT,Enable transmit used bit read interrupt" "0,1"
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bitfld.long 0x0 2. "ENABLE_RECEIVE_USED_BIT_READ_INTERRUPT,Enable receive used bit read interrupt" "0,1"
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bitfld.long 0x0 1. "ENABLE_RECEIVE_COMPLETE_INTERRUPT,Enable receive complete interrupt" "0,1"
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bitfld.long 0x0 0. "ENABLE_MANAGEMENT_DONE_INTERRUPT,Enable management done interrupt" "0,1"
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group.long 0x102C++0x3
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line.long 0x0 "INT_DISABLE,Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero."
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rbitfld.long 0x0 31. "RSVD_31_31,N/A" "0,1"
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rbitfld.long 0x0 30. "RSVD_30_30,N/A" "0,1"
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bitfld.long 0x0 29. "DISABLE_TSU_TIMER_COMPARISON_INTERRUPT,'Disable TSU timer comparison interrupt.'" "0,1"
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bitfld.long 0x0 28. "UNUSED_28,Not used" "0,1"
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bitfld.long 0x0 27. "DISABLE_RX_LPI_INDICATION_INTERRUPT,'Disable RX LPI indication interrupt'" "0,1"
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bitfld.long 0x0 26. "DISABLE_TSU_SECONDS_REGISTER_INCREMENT,'Disable TSU seconds register increment'" "0,1"
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bitfld.long 0x0 25. "DISABLE_PTP_PDELAY_RESP_FRAME_TRANSMITTED,'Disable PTP pdelay_resp frame transmitted'" "0,1"
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bitfld.long 0x0 24. "DISABLE_PTP_PDELAY_REQ_FRAME_TRANSMITTED,'Disable PTP pdelay_req frame transmitted'" "0,1"
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bitfld.long 0x0 23. "DISABLE_PTP_PDELAY_RESP_FRAME_RECEIVED,'Disable PTP pdelay_resp frame received'" "0,1"
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bitfld.long 0x0 22. "DISABLE_PTP_PDELAY_REQ_FRAME_RECEIVED,'Disable PTP pdelay_req frame received'" "0,1"
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bitfld.long 0x0 21. "DISABLE_PTP_SYNC_FRAME_TRANSMITTED,'Disable PTP sync frame transmitted '" "0,1"
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bitfld.long 0x0 20. "DISABLE_PTP_DELAY_REQ_FRAME_TRANSMITTED,'Disable PTP delay_req frame transmitted '" "0,1"
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bitfld.long 0x0 19. "DISABLE_PTP_SYNC_FRAME_RECEIVED,'Disable PTP sync frame received'" "0,1"
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bitfld.long 0x0 18. "DISABLE_PTP_DELAY_REQ_FRAME_RECEIVED,'Disable PTP delay_req frame received'" "0,1"
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bitfld.long 0x0 17. "UNUSED_17,Not used" "0,1"
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bitfld.long 0x0 16. "UNUSED_16,Not used" "0,1"
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bitfld.long 0x0 15. "UNUSED_15,Not used" "0,1"
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bitfld.long 0x0 14. "DISABLE_PAUSE_FRAME_TRANSMITTED_INTERRUPT,'Disable pause frame transmitted interrupt'" "0,1"
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bitfld.long 0x0 13. "DISABLE_PAUSE_TIME_ZERO_INTERRUPT,'Disable pause time zero interrupt'" "0,1"
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bitfld.long 0x0 12. "DISABLE_PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT,'Disable pause frame with non-zero pause quantum interrupt'" "0,1"
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bitfld.long 0x0 11. "DISABLE_RESP_NOT_OK_INTERRUPT,'Disable bresp/hresp not OK interrupt'" "0,1"
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bitfld.long 0x0 10. "DISABLE_RECEIVE_OVERRUN_INTERRUPT,'Disable receive overrun interrupt'" "0,1"
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bitfld.long 0x0 9. "UNUSED_9,Not used" "0,1"
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bitfld.long 0x0 8. "UNUSED_8,Not used" "0,1"
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bitfld.long 0x0 7. "DISABLE_TRANSMIT_COMPLETE_INTERRUPT,'Disable transmit complete interrupt'" "0,1"
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bitfld.long 0x0 6. "DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT,'Disable transmit frame corruption due to AMBA (AHB/AXI) error interrupt'" "0,1"
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bitfld.long 0x0 5. "DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT,'Disable retry limit exceeded or late collision interrupt'" "0,1"
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bitfld.long 0x0 4. "DISABLE_TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT,'Disable transmit buffer under run interrupt'" "0,1"
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bitfld.long 0x0 3. "DISABLE_TRANSMIT_USED_BIT_READ_INTERRUPT,'Disable transmit used bit read interrupt'" "0,1"
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bitfld.long 0x0 2. "DISABLE_RECEIVE_USED_BIT_READ_INTERRUPT,'Disable receive used bit read interrupt'" "0,1"
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bitfld.long 0x0 1. "DISABLE_RECEIVE_COMPLETE_INTERRUPT,'Disable receive complete interrupt'" "0,1"
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bitfld.long 0x0 0. "DISABLE_MANAGEMENT_DONE_INTERRUPT,'Disable management done interrupt'" "0,1"
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rgroup.long 0x1030++0x3
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line.long 0x0 "INT_MASK,The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt.."
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bitfld.long 0x0 29. "TSU_TIMER_COMPARISON_MASK,Enable TSU timer comparison interrupt mask." "0,1"
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bitfld.long 0x0 28. "UNUSED_28,unused" "0,1"
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bitfld.long 0x0 27. "RX_LPI_INDICATION_MASK,A read of this register returns the value of the RX LPI indication mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 26. "TSU_SECONDS_REGISTER_INCREMENT_MASK,A read of this register returns the value of the TSU seconds register increment mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 25. "PTP_PDELAY_RESP_FRAME_TRANSMITTED_MASK,A read of this register returns the value of the PTP pdelay_resp frame transmitted mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 24. "PTP_PDELAY_REQ_FRAME_TRANSMITTED_MASK,A read of this register returns the value of the PTP pdelay_req frame transmitted mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 23. "PTP_PDELAY_RESP_FRAME_RECEIVED_MASK,A read of this register returns the value of the PTP pdelay_resp frame received mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 22. "PTP_PDELAY_REQ_FRAME_RECEIVED_MASK,A read of this register returns the value of the PTP pdelay_req frame received mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 21. "PTP_SYNC_FRAME_TRANSMITTED_MASK,A read of this register returns the value of the PTP sync frame transmitted mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 20. "PTP_DELAY_REQ_FRAME_TRANSMITTED_MASK,A read of this register returns the value of the PTP delay_req frame transmitted mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 19. "PTP_SYNC_FRAME_RECEIVED_MASK,A read of this register returns the value of the PTP sync frame received mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 18. "PTP_DELAY_REQ_FRAME_RECEIVED_MASK,A read of this register returns the value of the PTP delay_req frame received mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 17. "UNUSED_17,Not used" "0,1"
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bitfld.long 0x0 16. "UNUSED_16,Not used" "0,1"
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bitfld.long 0x0 15. "UNUSED_15,Not used" "0,1"
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bitfld.long 0x0 14. "PAUSE_FRAME_TRANSMITTED_INTERRUPT_MASK,pause frame transmitted interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 13. "PAUSE_TIME_ZERO_INTERRUPT_MASK,pause time zero interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 12. "PAUSE_FRAME_WITH_NON_ZERO_PAUSE_QUANTUM_INTERRUPT_MASK,pause frame with non-zero pause quantum interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 11. "RESP_NOT_OK_INTERRUPT_MASK,bresp not OK interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 10. "RECEIVE_OVERRUN_INTERRUPT_MASK,receive overrun interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 9. "UNUSED_9,Not used" "0,1"
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bitfld.long 0x0 8. "UNUSED_8,Not used" "0,1"
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bitfld.long 0x0 7. "TRANSMIT_COMPLETE_INTERRUPT_MASK,transmit complete interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 6. "AMBA_ERROR_INTERRUPT_MASK,transmit frame corruption due to AMBA (AXI) error interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 5. "RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_MASK,A read of this register returns the value of the retry limit exceeded or late collision (gigabit mode only) interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 4. "TRANSMIT_BUFFER_UNDER_RUN_INTERRUPT_MASK,transmit buffer under run interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 3. "TRANSMIT_USED_BIT_READ_INTERRUPT_MASK,transmit used bit read interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 2. "RECEIVE_USED_BIT_READ_INTERRUPT_MASK,receive used bit read interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 1. "RECEIVE_COMPLETE_INTERRUPT_MASK,receive complete interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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bitfld.long 0x0 0. "MANAGEMENT_DONE_INTERRUPT_MASK,management done interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
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group.long 0x1034++0x3
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line.long 0x0 "PHY_MANAGEMENT,The PHY maintenance register is implemented as a shift register. Writing to the register starts a shift operation which is signalled as complete when bit-2 is set in the network status register. It takes about 2000 pclk cycles to complete..."
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bitfld.long 0x0 31. "WRITE0,Must be written with 0." "0,1"
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bitfld.long 0x0 30. "WRITE1,Must be written to 1 for a valid Clause 22 frame and to 0 for a valid Clause 45 frame." "0,1"
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bitfld.long 0x0 28.--29. "OPERATION,Operation. For a Clause 45 frame: 00 is an addr 01 is a write 10 is a post read increment 11 is a read frame. For a Clause 22 frame: 10 is a read 01 is a write." "0,1,2,3"
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hexmask.long.byte 0x0 23.--27. 1. "PHY_ADDRESS,PHY address."
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hexmask.long.byte 0x0 18.--22. 1. "REGISTER_ADDRESS,Register address - specifies the register in the PHY to access."
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bitfld.long 0x0 16.--17. "WRITE10,Must be written with 10." "0,1,2,3"
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hexmask.long.word 0x0 0.--15. 1. "PHY_WRITE_READ_DATA,For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY."
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rgroup.long 0x1038++0x3
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line.long 0x0 "PAUSE_TIME,Received Pause Quantum Register"
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hexmask.long.word 0x0 0.--15. 1. "QUANTUM,Received pause quantum - stores the current value of the received pause quantum register which is decremented every 512 bit times."
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group.long 0x103C++0xF
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line.long 0x0 "TX_PAUSE_QUANTUM,Transmit Pause Quantum Register"
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hexmask.long.word 0x0 16.--31. 1. "QUANTUM_P1,Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 1."
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hexmask.long.word 0x0 0.--15. 1. "QUANTUM,Transmit pause quantum - written with the pause quantum value for pause frame transmission."
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line.long 0x4 "PBUF_TXCUTTHRU,Partial store and forward is only applicable when using the DMA configured in SRAM based packet buffer mode. It is also not available when using multi buffer frames. TX Partial Store and Forward"
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bitfld.long 0x4 31. "DMA_TX_CUTTHRU,Enable TX partial store and forward operation" "0,1"
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hexmask.long.word 0x4 0.--8. 1. "DMA_TX_CUTTHRU_THRESHOLD,Watermark value. This value must be >= 0x9. The reset value depends on the value of the configuration option `gem_tx_pbuf_addr which is defined in the verilog defs configuration file. The value chosen for the generation of the.."
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line.long 0x8 "PBUF_RXCUTTHRU,RX Partial Store and Forward"
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bitfld.long 0x8 31. "DMA_RX_CUTTHRU,Enable RX partial store and forward operation" "0,1"
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hexmask.long.byte 0x8 0.--7. 1. "DMA_RX_CUTTHRU_THRESHOLD,Watermark value. The reset value depends on the value of the configuration option `gem_rx_pbuf_addr which is defined in the verilog defs configuration file. The value chosen for the generation of the userguide was.."
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line.long 0xC "JUMBO_MAX_LENGTH,Maximum Jumbo Frame Size."
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hexmask.long.word 0xC 0.--13. 1. "JUMBO_MAX_LENGTH,Maximum Jumbo Frame Size - resets to the gem_jumbo_max_length define value."
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rgroup.long 0x104C++0x3
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line.long 0x0 "EXTERNAL_FIFO_INTERFACE,Not presents."
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hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
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group.long 0x1054++0x3
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line.long 0x0 "AXI_MAX_PIPELINE,Used to set the maximum amount of outstanding transactions on the AXI bus between AR / R channels and AW / W channels. Cannot be more than the depth of the configured AXI pipeline FIFO (defined in verilog defs.v)"
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bitfld.long 0x0 16. "USE_AW2B_FILL,For the write issuing capability as defined in bits 15:8 of this register select whether the max number of transactions operates between the AW to W AXI channel or the AW to B channel. Set to 0 to operate between the AW and W channels. Set.." "0,1"
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hexmask.long.byte 0x0 8.--15. 1. "AW2W_MAX_PIPELINE,Defines the maximum number of outstanding AXI write requests that can be issued by the DMA via the AW channel."
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hexmask.long.byte 0x0 0.--7. 1. "AR2R_MAX_PIPELINE,Defines the maximum number of outstanding AXI read requests that can be issued by the DMA via the AR channel."
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rgroup.long 0x1058++0x3
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line.long 0x0 "RSC_CONTROL,Not presents. Access to the register will return AHB error."
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hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
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group.long 0x105C++0x7
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line.long 0x0 "INT_MODERATION,Used to moderate the number of transmit and receive complete interrupts issued. With interrupt moderation enabled receive and transmit interrupts are not generated immediately a frame is transmitted or received. Instead when a receive or.."
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hexmask.long.byte 0x0 16.--23. 1. "TX_INT_MODERATION,Count of 800ns periods before bit 7 is set in the interrupt status register after a frame is transmitted. A non-zero value indicates transmit interrupt moderation will be performed."
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hexmask.long.byte 0x0 0.--7. 1. "RX_INT_MODERATION,Count of 800ns periods before bit 1 is set in the interrupt status register after a frame is received. A non-zero value indicates receive interrupt moderation will be performed."
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line.long 0x4 "SYS_WAKE_TIME,Used to pause transmission after deassertion of tx_lpi_en. Each unit in this register corresponds to 64ns in gigabit mode. 320ns in 100M mode and 3200ns at 10M. After tx_lpi_en is deasserted transmission will pause for the set time."
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hexmask.long.word 0x4 0.--15. 1. "SYS_WAKE_TIME,Count of 64ns 320ns or 3200ns intervals before transmission starts after deassertion of tx_lpi_en (each interval is equivalent to eight tx_clk periods and so varies with data rate)."
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group.long 0x1080++0x67
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line.long 0x0 "HASH_BOTTOM,The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames. Hash Register Bottom (31 to 0 bits)"
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hexmask.long 0x0 0.--31. 1. "ADDRESS_HASH_B,The first 32 bits of the hash address register."
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line.long 0x4 "HASH_TOP,Hash Register Top (63 to 32 bits)"
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hexmask.long 0x4 0.--31. 1. "ADDRESS_HASH_T,The remaining 32 bits of the hash address register."
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line.long 0x8 "SPEC_ADD1_BOTTOM,The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written."
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hexmask.long 0x8 0.--31. 1. "ADDRESS_ADD1_B,'Least significant 32 bits of the destination address that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.'"
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line.long 0xC "SPEC_ADD1_TOP,Specific Address Top"
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bitfld.long 0xC 16. "FILTER_TYPE,This control bit selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame. When set to zero the filter is a destination address filter. When set to one the filter.." "0,1"
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hexmask.long.word 0xC 0.--15. 1. "ADDRESS_TOP,Specific address 1. The most significant bits of the destination/source address that is to be compared that is bits 47:32."
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line.long 0x10 "SPEC_ADD2_BOTTOM,The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written."
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hexmask.long 0x10 0.--31. 1. "ADDRESS_BOTTOM,Least significant 32 bits of the destination address that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received."
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line.long 0x14 "SPEC_ADD2_TOP,Specific Address Top"
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hexmask.long.byte 0x14 24.--29. 1. "FILTER_BYTE_MASK,When high the associated byte of the specific address will not be compared. Bit 24 controls whether the first byte received should be compared. Bit 29 controls whether the last byte received should be compared."
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bitfld.long 0x14 16. "FILTER_TYPE,This control bit selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame. When set to zero the filter is a destination address filter. When set to one the filter.." "0,1"
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hexmask.long.word 0x14 0.--15. 1. "ADDRESS_TOP,Specific address 1. The most significant bits of the destination/source address that is to be compared that is bits 47:32."
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line.long 0x18 "SPEC_ADD3_BOTTOM,The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written."
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hexmask.long 0x18 0.--31. 1. "ADDRESS_BOTTOM,Least significant 32 bits of the destination address that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received."
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line.long 0x1C "SPEC_ADD3_TOP,Specific Address Top"
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hexmask.long.byte 0x1C 24.--29. 1. "FILTER_BYTE_MASK,When high the associated byte of the specific address will not be compared. Bit 24 controls whether the first byte received should be compared. Bit 29 controls whether the last byte received should be compared."
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bitfld.long 0x1C 16. "FILTER_TYPE,This control bit selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame. When set to zero the filter is a destination address filter. When set to one the filter.." "0,1"
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hexmask.long.word 0x1C 0.--15. 1. "ADDRESS_TOP,Specific address 1. The most significant bits of the destination/source address that is to be compared that is bits 47:32."
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line.long 0x20 "SPEC_ADD4_BOTTOM,The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written."
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hexmask.long 0x20 0.--31. 1. "ADDRESS_BOTTOM,Least significant 32 bits of the destination address that is bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received."
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line.long 0x24 "SPEC_ADD4_TOP,Specific Address Top"
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hexmask.long.byte 0x24 24.--29. 1. "FILTER_BYTE_MASK,When high the associated byte of the specific address will not be compared. Bit 24 controls whether the first byte received should be compared. Bit 29 controls whether the last byte received should be compared."
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bitfld.long 0x24 16. "FILTER_TYPE,This control bit selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame. When set to zero the filter is a destination address filter. When set to one the filter.." "0,1"
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hexmask.long.word 0x24 0.--15. 1. "ADDRESS_TOP,Specific address 1. The most significant bits of the destination/source address that is to be compared that is bits 47:32."
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line.long 0x28 "SPEC_TYPE1,Type ID Match 1"
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bitfld.long 0x28 31. "ENABLE_COPY,Enable copying of type ID match 1 matched frames." "0,1"
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hexmask.long.word 0x28 0.--15. 1. "MATCH,Type ID match 1. For use in comparisons with received frames type ID/length field."
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line.long 0x2C "SPEC_TYPE2,Type ID Match 2"
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bitfld.long 0x2C 31. "ENABLE_COPY,Enable copying of type ID match 2 matched frames." "0,1"
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hexmask.long.word 0x2C 0.--15. 1. "MATCH,Type ID match 2. For use in comparisons with received frames type ID/length field."
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line.long 0x30 "SPEC_TYPE3,Type ID Match 3"
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bitfld.long 0x30 31. "ENABLE_COPY,Enable copying of type ID match 3 matched frames." "0,1"
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hexmask.long.word 0x30 0.--15. 1. "MATCH,Type ID match 3. For use in comparisons with received frames type ID/length field."
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line.long 0x34 "SPEC_TYPE4,Type ID Match 4"
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bitfld.long 0x34 31. "ENABLE_COPY,Enable copying of type ID match 4 matched frames." "0,1"
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newline
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hexmask.long.word 0x34 0.--15. 1. "MATCH,Type ID match 4. For use in comparisons with received frames type ID/length field."
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line.long 0x38 "WOL_REGISTER,Wake on LAN Register. Presents in design. but feature is not supported."
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bitfld.long 0x38 19. "WOL_MASK_3,Wake on LAN multicast hash event enable. When set multicast hash events will cause the wol output to be asserted." "0,1"
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bitfld.long 0x38 18. "WOL_MASK_2,Wake on LAN specific address register 1 event enable. When set specific address 1 events will cause the wol output to be asserted." "0,1"
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bitfld.long 0x38 17. "WOL_MASK_1,Wake on LAN ARP request event enable. When set ARP request events will cause the wol output to be asserted." "0,1"
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newline
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bitfld.long 0x38 16. "WOL_MASK_0,Wake on LAN magic packet event enable. When set magic packet events will cause the wol output to be asserted." "0,1"
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hexmask.long.word 0x38 0.--15. 1. "ADDR,Wake on LAN ARP request IP address. Written to define the least significant 16 bits of the target IP address that is matched to generate a Wake on LAN event. A value of zero will not generate an event even if this is matched by the received frame."
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line.long 0x3C "STRETCH_RATIO,IPG stretch register"
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hexmask.long.word 0x3C 0.--15. 1. "IPG_STRETCH,IPG Stretch. Bits 7:0 are multiplied with the previously transmitted frame length (including preamble) bits 15:8 +1 divide the frame length. If the resulting number is greater than 96 and bit 28 is set in the network configuration register.."
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line.long 0x40 "STACKED_VLAN,Stacked VLAN Register"
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bitfld.long 0x40 31. "ENABLE_PROCESSING,Enable stacked VLAN processing mode" "0,1"
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hexmask.long.word 0x40 0.--15. 1. "MATCH,User defined VLAN_TYPE field. When Stacked VLAN is enabled the first VLAN tag in a received frame will only be accepted if the VLAN type field is equal to this user defined VLAN_TYPE OR equal to the standard VLAN type (0x8100). Note that the.."
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line.long 0x44 "TX_PFC_PAUSE,Transmit PFC Pause Register"
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hexmask.long.byte 0x44 8.--15. 1. "VECTOR,Priority Vector Pause Size. If bit 17 of the network control register is written with a one then for each entry equal to zero in the Transmit PFC Pause Register[15:8] the PFC pause frame's pause quantum field associated with that entry will be.."
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hexmask.long.byte 0x44 0.--7. 1. "VECTOR_ENABLE,Priority Vector Enable. If bit 17 of the network control register is written with a one then the priority enable vector of the PFC priority based pause frame will be set equal to the value stored in this register [7:0]."
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line.long 0x48 "MASK_ADD1_BOTTOM,Specific Address Mask 1 Bottom (31 to 0 bits)"
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hexmask.long 0x48 0.--31. 1. "ADDRESS_MASK_BOTTOM,Specific Address Mask. Setting a bit to one masks the corresponding bit in the specific address 1 register (31 to 0 bits)"
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line.long 0x4C "MASK_ADD1_TOP,Specific Address Mask 1 Top (47 to 32 bits)"
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hexmask.long.word 0x4C 0.--15. 1. "ADDRESS_MASK_TOP,Specific Address Mask. Setting a bit to one masks the corresponding bit in the specific address 1 register (47 to 32 bits)."
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line.long 0x50 "DMA_ADDR_OR_MASK,Receive DMA Data Buffer Address Mask"
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hexmask.long.byte 0x50 28.--31. 1. "MASK_VALUE_DA,Data Buffer Address Mask Value. Values used to force bits 31:28 of the receive data buffer AHB address to a particular value when the associated enable bits stored in this register [3:0] are set. Any changes to this register will be ignored.."
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hexmask.long.byte 0x50 0.--3. 1. "MASK_ENABLE,Data Buffer Address Mask Enable. These bits are associated directly with bits[31:28].When bit 0 is set the AXI/AHB address bit 28 used for accessing the receive data buffers will be forced to the value stored in bit 28 of this register. When.."
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line.long 0x54 "RX_PTP_UNICAST,PTP RX unicast IP destination address"
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hexmask.long 0x54 0.--31. 1. "ADDRESS_UNICAST,Unicast IP destination address. Used for detection of PTP frames on receive path."
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line.long 0x58 "TX_PTP_UNICAST,PTP TX unicast IP destination address"
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hexmask.long 0x58 0.--31. 1. "ADDRESS_UNICAST,Unicast IP destination address. Used for detection of PTP frames on transmit path."
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line.long 0x5C "TSU_NSEC_CMP,TSU timer comparison value nanoseconds"
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hexmask.long.tbyte 0x5C 0.--21. 1. "COMPARISON_NSEC,TSU timer comparison value (ns). Value is compared to the bits[45:24] of the TSU timer count value (upper 22 bits of nanosecond value)."
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line.long 0x60 "TSU_SEC_CMP,TSU timer comparison value seconds (31 to 0 bits)"
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hexmask.long 0x60 0.--31. 1. "COMPARISON_SEC,TSU timer comparison value (s). Value is compared to seconds value bits [31:0] of the TSU timer count value."
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line.long 0x64 "TSU_MSB_SEC_CMP,TSU timer comparison value seconds (47 to 32 bits)"
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hexmask.long.word 0x64 0.--15. 1. "COMPARISON_MSB_SEC,TSU timer comparison value (s). Value is compared to the top 16 bits (most significant 16-bits {47:32] of seconds value) of the TSU timer count value."
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rgroup.long 0x10E8++0xF
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line.long 0x0 "TSU_PTP_TX_MSB_SEC,PTP Event Frame Transmitted Seconds Register (47 to 32 bits)"
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hexmask.long.word 0x0 0.--15. 1. "TIMER_SECONDS,PTP Event Frame TX Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame.."
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line.long 0x4 "TSU_PTP_RX_MSB_SEC,PTP Event Frame Received Seconds Register (47 to 32 bits)"
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hexmask.long.word 0x4 0.--15. 1. "TIMER_SECONDS,PTP Event Frame TX Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP receive primary event crosses the MII interface. The actual update occurs when the GEM recognizes the frame.."
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line.long 0x8 "TSU_PEER_TX_MSB_SEC,PTP Peer Event Frame Transmitted Seconds Register (47 to 32 bits)"
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hexmask.long.word 0x8 0.--15. 1. "TIMER_SECONDS,PTP Peer Event Frame TX Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit peer event crosses the MII interface. The actual update occurs when the GEM recognizes the.."
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line.long 0xC "TSU_PEER_RX_MSB_SEC,PTP Peer Event Frame Received Seconds Register (47 to 32 bits)"
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hexmask.long.word 0xC 0.--15. 1. "TIMER_SECONDS,PTP Peer Event Frame RX Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP receive peer event crosses the MII interface. The actual update occurs when the GEM recognizes the frame.."
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group.long 0x10F8++0x3
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line.long 0x0 "DPRAM_FILL_DBG,The fill levels for the TX & RX packet buffers can be read using this register. including the fill level for each queue in the TX direction."
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hexmask.long.word 0x0 16.--31. 1. "DMA_TX_RX_FILL_LEVEL,Fill Level - TX or RX packet buffer fill level selected by the tx_q_fill_level_select and tx_rx_fill_level_select registers. Read this register to determine the fill level."
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newline
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hexmask.long.byte 0x0 4.--7. 1. "DMA_TX_Q_FILL_LEVEL_SELECT,TX queue fill level select - select what TX queue to report fill levels for."
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newline
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bitfld.long 0x0 0. "DMA_TX_RX_FILL_LEVEL_SELECT,TX/RX Fill Level select - report the fill level for the TX or RX packet buffer." "0,1"
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rgroup.long 0x10FC++0xBB
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line.long 0x0 "REVISION_REG,This register indicates a Cadence module identification number and module revision. The value of this register is read only as defined by `gem_revision_reg_value"
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hexmask.long.byte 0x0 28.--31. 1. "FIX_NUMBER,Fix number - incremented for fix releases."
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newline
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hexmask.long.word 0x0 16.--27. 1. "MODULE_IDENTIFICATION_NUMBER,Module identification number - for the GEM this value is fixed."
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newline
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hexmask.long.word 0x0 0.--15. 1. "MODULE_REVISION,Module revision - fixed value specific to the revision of the design which is incremented for each non-fix release of the IP."
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line.long 0x4 "OCTETS_TXED_BOTTOM,Octets Transmitted lower bits (31 to 0 bits)"
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hexmask.long 0x4 0.--31. 1. "COUNT_BOTTOM,Transmitted octets in frame without errors [31:0]. The number of octets transmitted in valid frames of any type. This counter is 48-bits and is read through two registers. This count does not include octets from automatically generated.."
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line.long 0x8 "OCTETS_TXED_TOP,Octets Transmitted higher bits (47 to 32 bits)"
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hexmask.long.word 0x8 0.--15. 1. "COUNT_TOP,Transmitted octets in frame without errors [47:32]. The number of octets transmitted in valid frames of any type. This counter is 48-bits and is read through two registers. This count does not include octets from automatically generated pause.."
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line.long 0xC "FRAMES_TXED_OK,Frames Transmitted"
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hexmask.long 0xC 0.--31. 1. "COUNT_OK,Frames transmitted without error. A 32 bit register counting the number of frames successfully transmitted i.e. no under run and not too many retries. Excludes pause frames."
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line.long 0x10 "BROADCAST_TXED,Broadcast Frames Transmitted"
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hexmask.long 0x10 0.--31. 1. "COUNT_BROADCAST,Broadcast frames transmitted without error. A 32 bit register counting the number of broadcast frames successfully transmitted without error i.e. no under run and not too many retries. Excludes pause frames."
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line.long 0x14 "MULTICAST_TXED,Multicast Frames Transmitted"
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hexmask.long 0x14 0.--31. 1. "COUNT_MULTICAST,Multicast frames transmitted without error. A 32 bit register counting the number of multicast frames successfully transmitted without error i.e. no under run and not too many retries. Excludes pause frames."
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line.long 0x18 "PAUSE_FRAMES_TXED,Pause Frames Transmitted"
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hexmask.long.word 0x18 0.--15. 1. "COUNT_PAUSE,Transmitted pause frames - a 16 bit register counting the number of pause frames transmitted. Only pause frames triggered by the register interface or through the external pause pins are counted as pause frames. Pause frames received through.."
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line.long 0x1C "FRAMES_TXED_64,64 Byte Frames Transmitted"
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hexmask.long 0x1C 0.--31. 1. "COUNT_64,64 byte frames transmitted without error. A 32 bit register counting the number of 64 byte frames successfully transmitted without error i.e. no under run and not too many retries. Excludes pause frames."
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line.long 0x20 "FRAMES_TXED_65,65 to 127 Byte Frames Transmitted"
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hexmask.long 0x20 0.--31. 1. "COUNT_65,65 to127 byte frames transmitted without error. A 32 bit register counting the number of 65 to127 byte frames successfully transmitted without error i.e. no under run and not too many retries."
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line.long 0x24 "FRAMES_TXED_128,128 to 255 Byte Frames Transmitted"
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hexmask.long 0x24 0.--31. 1. "COUNT_128,128 to 255 byte frames transmitted without error. A 32 bit register counting the number of 128 to 255 byte frames successfully transmitted without error i.e. no under run and not too many retries."
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line.long 0x28 "FRAMES_TXED_256,256 to 511 Byte Frames Transmitted"
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hexmask.long 0x28 0.--31. 1. "COUNT_256,256 to 511 byte frames transmitted without error. A 32 bit register counting the number of 256 to 511 byte frames successfully transmitted without error i.e. no under run and not too many retries."
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line.long 0x2C "FRAMES_TXED_512,512 to 1023 Byte Frames Transmitted"
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hexmask.long 0x2C 0.--31. 1. "COUNT_512,512 to 1023 byte frames transmitted without error. A 32 bit register counting the number of 512 to 1023 byte frames successfully transmitted without error i.e. no under run and not too many retries."
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line.long 0x30 "FRAMES_TXED_1024,1024 to 1518 Byte Frames Transmitted"
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hexmask.long 0x30 0.--31. 1. "COUNT_1024,1024 to 1518 byte frames transmitted without error. A 32 bit register counting the number of 1024 to 1518 byte frames successfully transmitted without error i.e. no under run and not too many retries."
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line.long 0x34 "FRAMES_TXED_1519,Greater Than 1518 Byte Frames Transmitted"
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hexmask.long 0x34 0.--31. 1. "COUNT_1519,Greater than 1518 byte frames transmitted without error. A 32 bit register counting the number of 1518 or above byte frames successfully transmitted without error i.e. no under run and not too many retries."
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line.long 0x38 "TX_UNDERRUNS,Transmit Under Runs"
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hexmask.long.word 0x38 0.--9. 1. "COUNT_UN,Transmit under runs - a 10 bit register counting the number of frames not transmitted due to a transmit under run. If this register is incremented then no other statistics register is incremented."
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line.long 0x3C "SINGLE_COLLISIONS,Single Collision Frames. Presents in design but not support."
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hexmask.long.tbyte 0x3C 0.--17. 1. "COUNT14,Single collision frames - an 18 bit register counting the number of frames experiencing a single collision before being successfully transmitted i.e. no under run."
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line.long 0x40 "MULTIPLE_COLLISIONS,Multiple Collision Frames. Presents in design but not support."
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hexmask.long.tbyte 0x40 0.--17. 1. "COUNT15,Multiple collision frames - an 18 bit register counting the number of frames experiencing between two and fifteen collisions prior to being successfully transmitted i.e. no under run and not too many retries."
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line.long 0x44 "EXCESSIVE_COLLISIONS,Excessive Collisions. Presents in design but not support."
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hexmask.long.word 0x44 0.--9. 1. "COUNT16,Excessive collisions - a 10 bit register counting the number of frames that failed to be transmitted because they experienced 16 collisions."
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line.long 0x48 "LATE_COLLISIONS,Late Collisions. Presents in design but not support."
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hexmask.long.word 0x48 0.--9. 1. "COUNT17,Late collisions - a 10 bit register counting the number of late collision occurring after the slot time (512 bits) has expired. In 10/100 mode late collisions are counted twice i.e. both as a collision and a late collision. In gigabit mode a.."
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line.long 0x4C "DEFERRED_FRAMES,Deferred Transmission Frames. Presents in design but not support."
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hexmask.long.tbyte 0x4C 0.--17. 1. "COUNT18,Deferred transmission frames - an 18 bit register counting the number of frames experiencing deferral due to carrier sense being active on their first attempt at transmission. Frames involved in any collision are not counted nor are frames that.."
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line.long 0x50 "CRS_ERRORS,Carrier Sense Errors. Presents in design but not support."
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hexmask.long.word 0x50 0.--9. 1. "COUNT19,Carrier sense errors - a 10 bit register counting the number of frames transmitted where carrier sense was not seen during transmission or where carrier sense was deasserted after being asserted in a transmit frame without collision (no under.."
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line.long 0x54 "OCTETS_RXED_BOTTOM,Octets Received (31 to 0 bits)"
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hexmask.long 0x54 0.--31. 1. "COUNT_BOTTOM,Received octets in frame without errors [31:0]. The number of octets received in valid frames of any type. This counter is 48-bits and is read through two registers. This count does not include octets from pause frames and is only.."
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|
line.long 0x58 "OCTETS_RXED_TOP,Octets Received (47 to 32 bits)"
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hexmask.long.word 0x58 0.--15. 1. "COUNT_TOP,Received octets in frame without errors [47:32]. The number of octets received in valid frames of any type. This counter is 48-bits and is read through two registers. This count does not include octets from pause frames and is only incremented.."
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line.long 0x5C "FRAMES_RXED_OK,Frames Received"
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hexmask.long 0x5C 0.--31. 1. "COUNT_OK,Frames received without error. A 32 bit register counting the number of frames successfully received. Excludes pause frames and is only incremented if the frame is successfully filtered."
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line.long 0x60 "BROADCAST_RXED,Broadcast Frames Received"
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hexmask.long 0x60 0.--31. 1. "COUNT_BROADCAST,Broadcast frames received without error. A 32 bit register counting the number of broadcast frames successfully received without error. Excludes pause frames and is only incremented if the frame is successfully filtered."
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line.long 0x64 "MULTICAST_RXED,Multicast Frames Received"
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hexmask.long 0x64 0.--31. 1. "COUNT_MULTICAST,Multicast frames received without error. A 32 bit register counting the number of multicast frames successfully received without error. Excludes pause frames and is only incremented if the frame is successfully filtered."
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line.long 0x68 "PAUSE_FRAMES_RXED,Pause Frames Received"
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hexmask.long.word 0x68 0.--15. 1. "COUNT_PAUSE,Received pause frames - a 16 bit register counting the number of pause frames received without error."
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line.long 0x6C "FRAMES_RXED_64,64 Byte Frames Received"
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hexmask.long 0x6C 0.--31. 1. "COUNT_64,64 byte frames received without error. A 32 bit register counting the number of 64 byte frames successfully received without error. Excludes pause frames and is only incremented if the frame is successfully filtered."
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line.long 0x70 "FRAMES_RXED_65,65 to 127 Byte Frames Received"
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hexmask.long 0x70 0.--31. 1. "COUNT_65,65 to 127 byte frames received without error. A 32 bit register counting the number of 65 to 127 byte frames successfully received without error. Excludes pause frames and is only incremented if the frame is successfully filtered."
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line.long 0x74 "FRAMES_RXED_128,128 to 255 Byte Frames Received"
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hexmask.long 0x74 0.--31. 1. "COUNT_128,128 to 255 byte frames received without error. A 32 bit register counting the number of 128 to 255 byte frames successfully received without error. Excludes pause frames and is only incremented if the frame is successfully filtered."
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line.long 0x78 "FRAMES_RXED_256,256 to 511 Byte Frames Received"
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hexmask.long 0x78 0.--31. 1. "COUNT_256,256 to 511 byte frames received without error. A 32 bit register counting the number of 256 to 511 byte frames successfully transmitted without error. Excludes pause frames and is only incremented if the frame is successfully filtered."
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line.long 0x7C "FRAMES_RXED_512,512 to 1023 Byte Frames Received"
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hexmask.long 0x7C 0.--31. 1. "COUNT_512,512 to 1023 byte frames received without error. A 32 bit register counting the number of 512 to 1023 byte frames successfully received without error. Excludes pause frames and is only incremented if the frame is successfully filtered."
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line.long 0x80 "FRAMES_RXED_1024,1024 to 1518 Byte Frames Received"
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hexmask.long 0x80 0.--31. 1. "COUNT_1024,1024 to 1518 byte frames received without error. A 32 bit register counting the number of 1024 to 1518 byte frames successfully received without error. Excludes pause frames and is only incremented if the frame is successfully filtered."
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line.long 0x84 "FRAMES_RXED_1519,1519 to maximum Byte Frames Received"
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hexmask.long 0x84 0.--31. 1. "COUNT_1519,1519 to maximum byte frames received without error. A 32 bit register counting the number of 1519 byte or above frames successfully received without error. Maximum frame size is determined by the network configuration register bit 8 (1536.."
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line.long 0x88 "UNDERSIZE_FRAMES,Undersized Frames Received"
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hexmask.long.word 0x88 0.--9. 1. "COUNT_UNDERSIZE,Undersize frames received - a 10 bit register counting the number of frames received less than 64 bytes in length (10/100 mode or gigabit mode full duplex) that do not have either a CRC error or an alignment error. In gigabit mode half.."
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line.long 0x8C "EXCESSIVE_RX_LENGTH,Oversize Frames Received"
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hexmask.long.word 0x8C 0.--9. 1. "COUNT_OVERSIZE,Oversize frames received - a 10 bit register counting the number of frames received exceeding 1518 bytes (1536 bytes if bit 8 is set in network configuration register 10 240 bytes if bit 3 is set in the network configuration register) in.."
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line.long 0x90 "RX_JABBERS,Jabbers Received"
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hexmask.long.word 0x90 0.--9. 1. "COUNT_JABBERS,Jabbers received - a 10 bit register counting the number of frames received exceeding 1518 bytes (1536 if bit 8 set in network configuration register 10 240 bytes if bit 3 is set in the network configuration register) in length and have.."
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line.long 0x94 "FCS_ERRORS,Frame Check Sequence Errors"
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hexmask.long.word 0x94 0.--9. 1. "COUNT_FCS_ERR,Frame check sequence errors - a 10 bit register counting frames that are an integral number of bytes have bad CRC and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register 10 240 bytes if bit 3 is.."
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line.long 0x98 "RX_LENGTH_ERRORS,Length Field Frame Errors"
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hexmask.long.word 0x98 0.--9. 1. "COUNT_LENGTH_ERR,Length field frame errors - this 10-bit register counts the number of frames received that have a measured length shorter than that extracted from the length field (bytes 13 and 14). This condition is only counted if the value of the.."
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line.long 0x9C "RX_SYMBOL_ERRORS,Receive Symbol Errors"
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hexmask.long.word 0x9C 0.--9. 1. "COUNT_SYMBOL_ERR,Receive symbol errors - a 10-bit register counting the number of frames that had rx_er asserted during reception. For 10/100 mode symbol errors are counted regardless of frame length checks. For gigabit mode the frame must satisfy slot.."
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line.long 0xA0 "ALIGNMENT_ERRORS,Alignment Errors"
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hexmask.long.word 0xA0 0.--9. 1. "COUNT_ALIGNMENT_ERROR,Alignment errors - a 10 bit register counting frames that are not an integral number of bytes long and have bad CRC when their length is truncated to an integral number of bytes and are between 64 and 1518 bytes in length (1536 if.."
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line.long 0xA4 "RX_RESOURCE_ERRORS,Receive Resource Errors"
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hexmask.long.tbyte 0xA4 0.--17. 1. "COUNT_RESOURCE_ERR,Receive resource errors - an 18 bit register counting the number of frames that were successfully received by the MAC (correct address matched frame and adequate slot time) but could not be copied to memory because no receive buffer.."
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line.long 0xA8 "RX_OVERRUNS,Receive Overruns"
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hexmask.long.word 0xA8 0.--9. 1. "COUNT_OVERRUN,Receive overruns - a 10 bit register counting the number of frames that are address recognized but were not copied to memory due to a receive overrun."
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line.long 0xAC "RX_IP_CK_ERRORS,IP Header Checksum Errors"
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hexmask.long.byte 0xAC 0.--7. 1. "COUNT_IPCK_ERR,IP header checksum errors - an 8-bit register counting the number of frames discarded due to an incorrect IP header checksum but are between 64 and 1518 bytes (1536 bytes if bit 8 is set in the network configuration register or 10240.."
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line.long 0xB0 "RX_TCP_CK_ERRORS,TCP Checksum Errors"
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hexmask.long.byte 0xB0 0.--7. 1. "COUNT_TCPCK_ERR,TCP checksum errors - an 8-bit register counting the number of frames discarded due to an incorrect TCP checksum but are between 64 and 1518 bytes (1536 bytes if bit 8 is set in the network configuration register or 10240 bytes if bit 3.."
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line.long 0xB4 "RX_UDP_CK_ERRORS,UDP Checksum Errors"
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hexmask.long.byte 0xB4 0.--7. 1. "COUNT_UDPCK_ERR,UDP checksum errors - an 8-bit register counting the number of frames discarded due to an incorrect UDP checksum but are between 64 and 1518 bytes (1536 bytes if bit 8 is set in the network configuration register or 10240 bytes if bit 3.."
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line.long 0xB8 "AUTO_FLUSHED_PKTS,Receive DMA Flushed Packets"
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hexmask.long.word 0xB8 0.--15. 1. "COUNT_FLUSHED,Flushed RX packets counter. A 16 bit register counting the number of frames that have been flushed from the receive SRAM based packet buffer due to one of the following reasons .1. When partial store and forward mode is enabled or bit 24 of.."
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group.long 0x11BC++0x7
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line.long 0x0 "TSU_TIMER_INCR_SUB_NSEC,1588 Timer Increment Register sub nsec"
|
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hexmask.long.byte 0x0 24.--31. 1. "SUB_NS_INCR_LSB,These are the least significant bits [7:0] of the sub-ns value by which the 1588 timer will be incremented each clock cycle."
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newline
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hexmask.long.word 0x0 0.--15. 1. "SUB_NS_INCR,These are the most significant bits [23:8] of the sub-ns value by which the 1588 timer will be incremented each clock cycle. 24 bits of sub nanosecond precision gives resolution of approximately 5.86E-17 seconds (16 bits gives 15.2.."
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line.long 0x4 "TSU_TIMER_MSB_SEC,1588 Timer Seconds Register (47 to 32 bits)"
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hexmask.long.word 0x4 0.--15. 1. "TIMER_MSB_SEC,TSU timer value (s). Most significant 16 bits of seconds timer count. The register is writeable. The 48-bit counter increments by one when the 1588 nanoseconds counter counts to one second. It may also be incremented or decremented when the.."
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rgroup.long 0x11C4++0xB
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line.long 0x0 "TSU_STROBE_MSB_SEC,1588 Timer Sync Strobe Seconds Register (47 to 32 bits)"
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hexmask.long.word 0x0 0.--15. 1. "STROBE_MSB_SEC,1588 Timer Sync Strobe Seconds. The most significant 16-bit value of the Timer Seconds register captured when gem_tsu_ms and gem_tsu_inc_ctrl are zero."
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line.long 0x4 "TSU_STROBE_SEC,1588 Timer Sync Strobe Seconds Register (31 to 0 bits)"
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hexmask.long 0x4 0.--31. 1. "STROBE_SEC,1588 Timer Sync Strobe Seconds. The lowest significant 32-bit value of the Timer Seconds register captured when gem_tsu_ms and gem_tsu_inc_ctrl are zero."
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line.long 0x8 "TSU_STROBE_NSEC,1588 Timer Sync Strobe Nanoseconds Register"
|
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hexmask.long 0x8 0.--29. 1. "STROBE_NSEC,1588 Timer Sync Strobe Nanoseconds. The value of the Timer Nanoseconds register captured when gem_tsu_ms and gem_tsu_inc_ctrl are zero."
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group.long 0x11D0++0x7
|
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line.long 0x0 "TSU_TIMER_SEC,1588 Timer Seconds Register (31 to 0 bits)"
|
|
hexmask.long 0x0 0.--31. 1. "TIMER_SEC,1588 Timer Seconds Register. TSU timer value (s). Least significant 32 bits of seconds timer count. This register is writeable. The 48-bit counter increments by one when the 1588 nanoseconds counter counts to one second. It may also be.."
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line.long 0x4 "TSU_TIMER_NSEC,1588 Timer Nanoseconds Register"
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hexmask.long 0x4 0.--29. 1. "TIMER_NSEC,Timer count in nanoseconds. This register is writeable. It can also be adjusted by writes to the 1588 timer adjust register. It increments by the value of the 1588 timer increment register each clock cycle (if this register is close to zero.."
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wgroup.long 0x11D8++0x3
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line.long 0x0 "TSU_TIMER_ADJUST,This register is used to adjust the value of the timer in the TSU. It allows an integral number of nanoseconds to be added or subtracted from the timer in a one-off operation. This register returns all zeroes when read."
|
|
bitfld.long 0x0 31. "ADD_SUBTRACT,Write as one to subtract from the 1588 timer. Write as zero to add to it." "0,1"
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|
newline
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hexmask.long 0x0 0.--29. 1. "INCREMENT_VALUE,Timer increment value. The number of nanoseconds to increment or decrement the 1588 timer nanoseconds register. If necessary the 1588 seconds register will be incremented or decremented."
|
|
group.long 0x11DC++0x3
|
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line.long 0x0 "TSU_TIMER_INCR,1588 Timer Increment Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "NUM_INCS,Number of incs before alt inc. The number of increments after which the alternative increment is used."
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|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "ALT_NS_INCR,Alternative nanoseconds count. Alternative count of nanoseconds by which the 1588 timer nanoseconds register will be incremented each clock cycle."
|
|
newline
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hexmask.long.byte 0x0 0.--7. 1. "NS_INCREMENT,A count of nanoseconds by which the 1588 timer nanoseconds register will be incremented each clock cycle. These are the most significant 8 bits of the 32 bit timer_increment counter. The tsu_timer_incr_sub_nsec register holds the least.."
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rgroup.long 0x11E0++0x27
|
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line.long 0x0 "TSU_PTP_TX_SEC,PTP Event Frame Transmitted Seconds Register (31 to 0 bits)"
|
|
hexmask.long 0x0 0.--31. 1. "TIMER_PTP_SEC,PTP Event Frame Transmitted Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit primary event crosses the MII interface. The actual update occurs when the GEM recognizes.."
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line.long 0x4 "TSU_PTP_TX_NSEC,PTP Event Frame Transmitted Nanoseconds Register"
|
|
hexmask.long 0x4 0.--29. 1. "TIMER_PTP_NSEC,PTP Event Frame Transmitted Nanoseconds. The register is updated with the value that the 1588 timer nanoseconds register held when the SFD of a PTP transmit primary event crosses the MII interface. The actual update occurs when the GEM.."
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line.long 0x8 "TSU_PTP_RX_SEC,PTP Event Frame Received Seconds Register (31 to 0 bits)"
|
|
hexmask.long 0x8 0.--31. 1. "TIMER_PTP_SEC,PTP Event Frame Received Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP receive primary event crosses the MII interface. The actual update occurs when the GEM recognizes the.."
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line.long 0xC "TSU_PTP_RX_NSEC,PTP Event Frame Received Nanoseconds Register"
|
|
hexmask.long 0xC 0.--29. 1. "TIMER_PTP_NSEC,PTP Event Frame Received Nanoseconds. The register is updated with the value that the 1588 timer nanoseconds register held when the SFD of a PTP receive primary event crosses the MII interface. The actual update occurs when the GEM.."
|
|
line.long 0x10 "TSU_PEER_TX_SEC,PTP Peer Event Frame Transmitted Seconds Register (31 to 0 bits)"
|
|
hexmask.long 0x10 0.--31. 1. "TIMER_PEER_SEC,PTP Peer Event Frame Received Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit peer event crosses the MII interface. The actual update occurs when the GEM recognizes.."
|
|
line.long 0x14 "TSU_PEER_TX_NSEC,PTP Peer Event Frame Transmitted Nanoseconds Register"
|
|
hexmask.long 0x14 0.--29. 1. "TIMER_PEER_NSEC,PTP Peer Event Frame Transmitted Nanoseconds. The register is updated with the value that the 1588 timer nanoseconds register held when the SFD of a PTP transmit peer event crosses the MII interface. The actual update occurs when the GEM.."
|
|
line.long 0x18 "TSU_PEER_RX_SEC,PTP Peer Event Frame Received Seconds Register (31 to 0 bits)"
|
|
hexmask.long 0x18 0.--31. 1. "TIMER_PEER_SEC,PTP Peer Event Frame Received Seconds. The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP receive peer event crosses the MII interface. The actual update occurs when the GEM recognizes.."
|
|
line.long 0x1C "TSU_PEER_RX_NSEC,PTP Peer Event Frame Received Nanoseconds Register"
|
|
hexmask.long 0x1C 0.--29. 1. "TIMER_PEER_NSEC,PTP Peer Event Frame Received Nanoseconds. The register is updated with the value that the 1588 timer nanoseconds register held when the SFD of a PTP receive peer event crosses the MII interface. The actual update occurs when the GEM.."
|
|
line.long 0x20 "PCS_CONTROL,Not presents. Access to the register returns AHB error."
|
|
hexmask.long 0x20 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
line.long 0x24 "PCS_STATUS,Not presents. Access to the register returns AHB error."
|
|
hexmask.long 0x24 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x1210++0x13
|
|
line.long 0x0 "PCS_AN_ADV,Not presents. Access to the register returns AHB error."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
line.long 0x4 "PCS_AN_LP_BASE,Not presents. Access to the register returns AHB error."
|
|
hexmask.long 0x4 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
line.long 0x8 "PCS_AN_EXP,Not presents. Access to the register returns AHB error."
|
|
hexmask.long 0x8 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
line.long 0xC "PCS_AN_NP_TX,Not presents. Access to the register returns AHB error."
|
|
hexmask.long 0xC 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
line.long 0x10 "PCS_AN_LP_NP,Not presents. Access to the register returns AHB error."
|
|
hexmask.long 0x10 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x123C++0x3
|
|
line.long 0x0 "PCS_AN_EXT_STATUS,Not presents. Access to the register returns AHB error."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
group.long 0x1260++0xB
|
|
line.long 0x0 "TX_PAUSE_QUANTUM1,Transmit Pause Quantum Register 1"
|
|
hexmask.long.word 0x0 16.--31. 1. "QUANTUM_P3,Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 3."
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "QUANTUM_P2,Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 2."
|
|
line.long 0x4 "TX_PAUSE_QUANTUM2,Transmit Pause Quantum Register 2"
|
|
hexmask.long.word 0x4 16.--31. 1. "QUANTUM_P5,Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 5."
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "QUANTUM_P4,Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 4."
|
|
line.long 0x8 "TX_PAUSE_QUANTUM3,Transmit Pause Quantum Register 3"
|
|
hexmask.long.word 0x8 16.--31. 1. "QUANTUM_P7,Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 7."
|
|
newline
|
|
hexmask.long.word 0x8 0.--15. 1. "QUANTUM_P6,Transmit pause quantum - written with the pause quantum value for pause frame transmission of priority 6."
|
|
rgroup.long 0x1270++0x37
|
|
line.long 0x0 "RX_LPI,Received LPI transitions"
|
|
hexmask.long.word 0x0 0.--15. 1. "COUNT_LPI,Count of RX LPI transitions. A count of the number of times there is a transition from receiving normal idle to receiving low power idle. Cleared on read."
|
|
line.long 0x4 "RX_LPI_TIME,Received LPI time"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "LPI_TIME,Time in LPI. This register increments once every 16 pclk cycles when the LPI indication bit 20 is set in the receive configuration register. Cleared on read."
|
|
line.long 0x8 "TX_LPI,Transmit LPI transitions"
|
|
hexmask.long.word 0x8 0.--15. 1. "COUNT_LPI,Count of LPI transmissions. A count of the number of times the enable LPI transmission bit 20 goes from low to high in the transmit control register."
|
|
line.long 0xC "TX_LPI_TIME,Transmit LPI time"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "LPI_TIME,Time in LPI. This register increments once every 16 pclk cycles when the enable LPI transmission bit 20 is set in the transmit control register. Cleared on read."
|
|
line.long 0x10 "DESIGNCFG_DEBUG1,The GEM_GXL(3PIP) has many parameterisation options to configure the IP during compilation stage. This is achieved using Verilog define compiler directives in an include file called mxeth_defs.v."
|
|
hexmask.long.byte 0x10 28.--31. 1. "AXI_CACHE_VALUE,Takes the value of the `gem_axi_cache_value DEFINE"
|
|
newline
|
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bitfld.long 0x10 25.--27. "DMA_BUS_WIDTH,Takes the value of bits 7:5 of the `gem_dma_bus_width DEFINE. So if the define is set to decimal 64 this will return binary 010." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 24. "EXCLUDE_CBS,Takes the value of the `gem_exclude_cbs DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x10 23. "IRQ_READ_CLEAR,Takes the value of the `gem_irq_read_clear DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x10 22. "NO_SNAPSHOT,Takes the value of the `gem_no_snapshot DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x10 21. "NO_STATS,Takes the value of the `gem_no_stats DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x10 20. "RSVD_20,N/A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 15.--19. 1. "USER_IN_WIDTH,Takes the value of the `gem_user_in_width DEFINE `gem_user_io."
|
|
newline
|
|
hexmask.long.byte 0x10 10.--14. 1. "USER_OUT_WIDTH,Takes the value of the `gem_user_out_width DEFINE if `gem_user_io is set."
|
|
newline
|
|
bitfld.long 0x10 9. "USER_IO,Takes the value of the `gem_user_io DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "RSVD_8,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "RSVD_7,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. "EXT_FIFO_INTERFACE,Takes the value of the `gem_ext_fifo_interface DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "RSVD_5,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "INT_LOOPBACK,Takes the value of the `gem_int_loopback DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2.--3. "RSVD_2,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 1. "EXCLUDE_QBV,Takes the value of the `gem_exclude_qbv DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "NO_PCS,Takes the value of the `gem_no_pcs DEFINE" "0,1"
|
|
line.long 0x14 "DESIGNCFG_DEBUG2,Design Configuration Register 2"
|
|
bitfld.long 0x14 31. "SPRAM,Takes the value of the `gem_spram DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x14 30. "AXI,Takes the value of the `gem_axi DEFINE" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x14 26.--29. 1. "TX_PBUF_ADDR,Takes the value of the `gem_tx_pbuf_addr DEFINE"
|
|
newline
|
|
hexmask.long.byte 0x14 22.--25. 1. "RX_PBUF_ADDR,Takes the value of the `gem_rx_pbuf_addr DEFINE"
|
|
newline
|
|
bitfld.long 0x14 21. "TX_PKT_BUFFER,Takes the value of the `gem_tx_pkt_buffer DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x14 20. "RX_PKT_BUFFER,Takes the value of the `gem_rx_pkt_buffer DEFINE" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x14 16.--19. 1. "HPROT_VALUE,Takes the value of the `gem_hprot_value DEFINE"
|
|
newline
|
|
hexmask.long.word 0x14 0.--13. 1. "JUMBO_MAX_LENGTH,Takes the value of the `gem_jumbo_max_length DEFINE"
|
|
line.long 0x18 "DESIGNCFG_DEBUG3,Design Configuration Register 3"
|
|
hexmask.long.byte 0x18 24.--29. 1. "NUM_SPEC_ADD_FILTERS,Takes the value of the `num_spec_add_filters DEFINE"
|
|
line.long 0x1C "DESIGNCFG_DEBUG4,Design Configuration Register 4"
|
|
hexmask.long 0x1C 0.--31. 1. "RSVD_31_0,N/A"
|
|
line.long 0x20 "DESIGNCFG_DEBUG5,Design Configuration Register 5"
|
|
bitfld.long 0x20 29.--31. "AXI_PROT_VALUE,Takes the value of the `gem_axi_prot_value DEFINE" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x20 28. "TSU_CLK,Takes the value of the `gem_tsu_clk DEFINE" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x20 20.--27. 1. "RX_BUFFER_LENGTH_DEF,Takes the value of the `gem_rx_buffer_length_def DEFINE"
|
|
newline
|
|
bitfld.long 0x20 19. "TX_PBUF_SIZE_DEF,Takes the value of the `gem_tx_pbuf_size_def DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x20 17.--18. "RX_PBUF_SIZE_DEF,Takes the value of the `gem_rx_pbuf_size_def DEFINE" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x20 15.--16. "ENDIAN_SWAP_DEF,Takes the value of the `gem_endian_swap_def DEFINE" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x20 12.--14. "MDC_CLOCK_DIV,Takes the value of the `gem_mdc_clock_div DEFINE" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x20 10.--11. "DMA_BUS_WIDTH_DEF,Takes the value of the `gem_dma_bus_width_def DEFINE" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x20 9. "PHY_IDENT,Takes the value of the `gem_phy_ident DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x20 8. "TSU,Takes the value of the `gem_tsu DEFINE" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x20 4.--7. 1. "TX_FIFO_CNT_WIDTH,Takes the value of the `gem_tx_fifo_cnt_width DEFINE"
|
|
newline
|
|
hexmask.long.byte 0x20 0.--3. 1. "RX_FIFO_CNT_WIDTH,Takes the value of the `gem_rx_fifo_cnt_width DEFINE"
|
|
line.long 0x24 "DESIGNCFG_DEBUG6,Design Configuration Register 6"
|
|
bitfld.long 0x24 27. "PBUF_LSO,Takes the value of the `gem_pbuf_lso DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x24 26. "PBUF_RSC,Takes the value of the `gem_pbuf_rsc DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x24 25. "PBUF_CUTTHRU,Takes the value of the `gem_pbuf_cutthru DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x24 24. "PFC_MULTI_QUANTUM,Takes the value of the `gem_pfc_multi_quantum DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x24 23. "DMA_ADDR_WIDTH_IS_64B,Takes the value of the `gem_dma_addr_width_is_64b DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x24 22. "HOST_IF_SOFT_SELECT,Takes the value of the `gem_host_if_soft_select DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x24 21. "TX_ADD_FIFO_IF,Takes the value of the `gem_tx_add_fifo_if DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x24 20. "EXT_TSU_TIMER,Takes the value of the `gem_ext_tsu_timer DEFINE" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x24 16.--19. 1. "TX_PBUF_QUEUE_SEGMENT_SIZE,Takes the value of the `gem_tx_pbuf_queue_segment_size DEFINE"
|
|
newline
|
|
bitfld.long 0x24 15. "DMA_PRIORITY_QUEUE15,Takes the value of the `dma_priority_queue15 DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x24 14. "DMA_PRIORITY_QUEUE14,Takes the value of the `dma_priority_queue14 DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x24 13. "DMA_PRIORITY_QUEUE13,Takes the value of the `dma_priority_queue13 DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x24 12. "DMA_PRIORITY_QUEUE12,Takes the value of the `dma_priority_queue12 DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x24 11. "DMA_PRIORITY_QUEUE11,Takes the value of the `dma_priority_queue11 DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x24 10. "DMA_PRIORITY_QUEUE10,Takes the value of the `dma_priority_queue10 DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x24 9. "DMA_PRIORITY_QUEUE9,Takes the value of the `dma_priority_queue9 DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x24 8. "DMA_PRIORITY_QUEUE8,Takes the value of the `dma_priority_queue8 DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x24 7. "DMA_PRIORITY_QUEUE7,Takes the value of the `dma_priority_queue7 DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x24 6. "DMA_PRIORITY_QUEUE6,Takes the value of the `dma_priority_queue6 DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x24 5. "DMA_PRIORITY_QUEUE5,Takes the value of the `dma_priority_queue5 DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x24 4. "DMA_PRIORITY_QUEUE4,Takes the value of the `dma_priority_queue4 DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x24 3. "DMA_PRIORITY_QUEUE3,Takes the value of the `dma_priority_queue3 DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x24 2. "DMA_PRIORITY_QUEUE2,Takes the value of the `dma_priority_queue2 DEFINE" "0,1"
|
|
newline
|
|
bitfld.long 0x24 1. "DMA_PRIORITY_QUEUE1,Takes the value of the `dma_priority_queue1 DEFINE" "0,1"
|
|
line.long 0x28 "DESIGNCFG_DEBUG7,Design Configuration Register 7"
|
|
hexmask.long.byte 0x28 28.--31. 1. "X_PBUF_NUM_SEGMENTS_Q7,Takes the value of the `gem_tx_pbuf_num_segments_q7 DEFINE"
|
|
newline
|
|
hexmask.long.byte 0x28 24.--27. 1. "X_PBUF_NUM_SEGMENTS_Q6,Takes the value of the `gem_tx_pbuf_num_segments_q6 DEFINE"
|
|
newline
|
|
hexmask.long.byte 0x28 20.--23. 1. "X_PBUF_NUM_SEGMENTS_Q5,Takes the value of the `gem_tx_pbuf_num_segments_q5 DEFINE"
|
|
newline
|
|
hexmask.long.byte 0x28 16.--19. 1. "X_PBUF_NUM_SEGMENTS_Q4,Takes the value of the `gem_tx_pbuf_num_segments_q4 DEFINE"
|
|
newline
|
|
hexmask.long.byte 0x28 12.--15. 1. "X_PBUF_NUM_SEGMENTS_Q3,Takes the value of the `gem_tx_pbuf_num_segments_q3 DEFINE"
|
|
newline
|
|
hexmask.long.byte 0x28 8.--11. 1. "X_PBUF_NUM_SEGMENTS_Q2,Takes the value of the `gem_tx_pbuf_num_segments_q2 DEFINE"
|
|
newline
|
|
hexmask.long.byte 0x28 4.--7. 1. "X_PBUF_NUM_SEGMENTS_Q1,Takes the value of the `gem_tx_pbuf_num_segments_q1 DEFINE"
|
|
newline
|
|
hexmask.long.byte 0x28 0.--3. 1. "X_PBUF_NUM_SEGMENTS_Q0,Takes the value of the `gem_tx_pbuf_num_segments_q0 DEFINE"
|
|
line.long 0x2C "DESIGNCFG_DEBUG8,Design Configuration Register 8"
|
|
hexmask.long.byte 0x2C 24.--31. 1. "NUM_TYPE1_SCREENERS,Takes the value of the `num_type1_screeners DEFINE"
|
|
newline
|
|
hexmask.long.byte 0x2C 16.--23. 1. "NUM_TYPE2_SCREENERS,Takes the value of the `num_type2_screeners DEFINE"
|
|
newline
|
|
hexmask.long.byte 0x2C 8.--15. 1. "NUM_SCR2_ETHTYPE_REGS,Takes the value of the `num_scr2_ethtype_regs DEFINE"
|
|
newline
|
|
hexmask.long.byte 0x2C 0.--7. 1. "NUM_SCR2_COMPARE_REGS,Takes the value of the `num_scr2_compare_regs DEFINE"
|
|
line.long 0x30 "DESIGNCFG_DEBUG9,Design Configuration Register 9"
|
|
hexmask.long.byte 0x30 28.--31. 1. "TX_PBUF_NUM_SEGMENTS_Q15,Takes the value of the `gem_tx_pbuf_num_segments_q15 DEFINE"
|
|
newline
|
|
hexmask.long.byte 0x30 24.--27. 1. "TX_PBUF_NUM_SEGMENTS_Q14,Takes the value of the `gem_tx_pbuf_num_segments_q14 DEFINE"
|
|
newline
|
|
hexmask.long.byte 0x30 20.--23. 1. "TX_PBUF_NUM_SEGMENTS_Q13,Takes the value of the `gem_tx_pbuf_num_segments_q13 DEFINE"
|
|
newline
|
|
hexmask.long.byte 0x30 16.--19. 1. "TX_PBUF_NUM_SEGMENTS_Q12,Takes the value of the `gem_tx_pbuf_num_segments_q12 DEFINE"
|
|
newline
|
|
hexmask.long.byte 0x30 12.--15. 1. "TX_PBUF_NUM_SEGMENTS_Q11,Takes the value of the `gem_tx_pbuf_num_segments_q11 DEFINE"
|
|
newline
|
|
hexmask.long.byte 0x30 8.--11. 1. "TX_PBUF_NUM_SEGMENTS_Q10,Takes the value of the `gem_tx_pbuf_num_segments_q10 DEFINE"
|
|
newline
|
|
hexmask.long.byte 0x30 4.--7. 1. "TX_PBUF_NUM_SEGMENTS_Q9,Takes the value of the `gem_tx_pbuf_num_segments_q9 DEFINE"
|
|
newline
|
|
hexmask.long.byte 0x30 0.--3. 1. "TX_PBUF_NUM_SEGMENTS_Q8,Takes the value of the `gem_tx_pbuf_num_segments_q8 DEFINE"
|
|
line.long 0x34 "DESIGNCFG_DEBUG10,Design Configuration Register 10"
|
|
hexmask.long.byte 0x34 28.--31. 1. "EMAC_BUS_WIDTH,Takes the value of the `gem_emac_bus_width DEFINE. 1 - The MAC has a datawidth of 32bits. 2 - The MAC has a datawidth of 64bits. 4 - The MAC has a datawidth of 128bits"
|
|
newline
|
|
hexmask.long.byte 0x34 24.--27. 1. "TX_PBUF_DATA,Takes the value of the `gem_tx_pbuf_data DEFINE. 1 - The TX DPRAM has a datawidth of 32bits. 2 - The TX DPRAM has a datawidth of 64bits. 4 - The TX DPRAM has a datawidth of 128bits"
|
|
newline
|
|
hexmask.long.byte 0x34 20.--23. 1. "RX_PBUF_DATA,Takes the value of the `gem_rx_pbuf_data DEFINE. 1 - The RX DPRAM has a datawidth of 32bits. 2 - The RX DPRAM has a datawidth of 64bits. 4 - RX The DPRAM has a datawidth of 128bits"
|
|
newline
|
|
hexmask.long.byte 0x34 16.--19. 1. "AXI_ACCESS_PIPELINE_BITS,Takes the value of the `gem_axi_access_pipeline_bits DEFINE"
|
|
newline
|
|
hexmask.long.byte 0x34 12.--15. 1. "AXI_TX_DESCR_RD_BUFF_BITS,Takes the value of the `gem_axi_tx_descr_rd_buff_bits DEFINE"
|
|
newline
|
|
hexmask.long.byte 0x34 8.--11. 1. "AXI_RX_DESCR_RD_BUFF_BITS,Takes the value of the `gem_axi_rx_descr_rd_buff_bits DEFINE"
|
|
newline
|
|
hexmask.long.byte 0x34 4.--7. 1. "AXI_TX_DESCR_WR_BUFF_BITS,Takes the value of the `gem_axi_tx_descr_wr_buff_bits DEFINE"
|
|
newline
|
|
hexmask.long.byte 0x34 0.--3. 1. "AXI_RX_DESCR_WR_BUFF_BITS,Takes the value of the `gem_axi_rx_descr_wr_buff_bits DEFINE"
|
|
rgroup.long 0x1300++0x7
|
|
line.long 0x0 "SPEC_ADD5_BOTTOM,Specific address registers 5 ~ 36 doesn't present. Access to the register returns AHB error."
|
|
hexmask.long 0x0 0.--31. 1. "RSVD_31_0,Write ignore read 0"
|
|
line.long 0x4 "SPEC_ADD5_TOP,Specific address registers 5 ~ 36 doesn't present. Access to the register returns AHB error."
|
|
hexmask.long 0x4 0.--31. 1. "RSVD_31_0,Write ignore read 0"
|
|
rgroup.long 0x13F8++0x13
|
|
line.long 0x0 "SPEC_ADD36_BOTTOM,Not presents."
|
|
hexmask.long 0x0 0.--31. 1. "RSVD_31_0,Write ignore read 0"
|
|
line.long 0x4 "SPEC_ADD36_TOP,Not presents."
|
|
hexmask.long 0x4 0.--31. 1. "RSVD_31_0,Write ignore read 0"
|
|
line.long 0x8 "INT_Q1_STATUS,Priority queue Interrupt Status Register"
|
|
bitfld.long 0x8 11. "RESP_NOT_OK,bresp not OK" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "TRANSMIT_COMPLETE,Transmit complete" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "AMBA_ERROR,Transmit frame corruption due to AMBA (AXI/AHB) error set if an error occurs whilst midway through reading transmit frame from the external memory including HRESP (AHB) RRESP and BRESP errors (AXI) and buffers exhausted mid frame" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION,Retry limit exceeded or late collision" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "RX_USED_BIT_READ,RX used bit read" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "RECEIVE_COMPLETE,Receive complete" "0,1"
|
|
line.long 0xC "INT_Q2_STATUS,Priority queue Interrupt Status Register"
|
|
bitfld.long 0xC 11. "RESP_NOT_OK,bresp not OK" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "TRANSMIT_COMPLETE,Transmit complete" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "AMBA_ERROR,Transmit frame corruption due to AMBA (AXI/AHB) error set if an error occurs whilst midway through reading transmit frame from the external memory including HRESP(AHB) RRESP and BRESP errors (AXI) and buffers exhausted mid frame" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION,Retry limit exceeded or late collision" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "RX_USED_BIT_READ,RX used bit read" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "RECEIVE_COMPLETE,Receive complete" "0,1"
|
|
line.long 0x10 "INT_Q3_STATUS,int_q3_status to int_q15_status doesn't present. Access to the register returns AHB error."
|
|
hexmask.long 0x10 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x1438++0x3
|
|
line.long 0x0 "INT_Q15_STATUS,Not presents."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
group.long 0x1440++0x7
|
|
line.long 0x0 "TRANSMIT_Q1_PTR,This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control.."
|
|
hexmask.long 0x0 2.--31. 1. "DMA_TX_Q_PTR,This register holds the start address of the transmit buffer queue (transmit buffers"
|
|
newline
|
|
bitfld.long 0x0 0. "DMA_TX_DIS_Q,Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while transmit is not enabled." "0,1"
|
|
line.long 0x4 "TRANSMIT_Q2_PTR,This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control.."
|
|
hexmask.long 0x4 2.--31. 1. "DMA_TX_Q_PTR,This register holds the start address of the transmit buffer queue (transmit buffers"
|
|
newline
|
|
bitfld.long 0x4 0. "DMA_TX_DIS_Q,Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while transmit is not enabled." "0,1"
|
|
rgroup.long 0x1448++0x3
|
|
line.long 0x0 "TRANSMIT_Q3_PTR,transmit_q3_ptr to transmit_q15_ptr doesn't present. Access to the register returns AHB error."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while transmit is not enabled."
|
|
rgroup.long 0x1478++0x3
|
|
line.long 0x0 "TRANSMIT_Q15_PTR,Not presents."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
group.long 0x1480++0x7
|
|
line.long 0x0 "RECEIVE_Q1_PTR,This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control.."
|
|
hexmask.long 0x0 2.--31. 1. "DMA_RX_Q_PTR,Receive buffer queue base address - written with the address of the start of the receive queue."
|
|
newline
|
|
bitfld.long 0x0 0. "DMA_RX_DIS_Q,Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while receive is not enabled." "0,1"
|
|
line.long 0x4 "RECEIVE_Q2_PTR,This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control.."
|
|
hexmask.long 0x4 2.--31. 1. "DMA_RX_Q_PTR,Receive buffer queue base address - written with the address of the start of the receive queue."
|
|
newline
|
|
bitfld.long 0x4 0. "DMA_RX_DIS_Q,Disable queue if set to 1. This can be used to reduce the number of active queues and should only be changed while receive is not enabled." "0,1"
|
|
rgroup.long 0x1488++0x3
|
|
line.long 0x0 "RECEIVE_Q3_PTR,Not presents. Start address register doesn't present for queue3 ~ queue7."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x1498++0x3
|
|
line.long 0x0 "RECEIVE_Q7_PTR,Not presents."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
group.long 0x14A0++0x7
|
|
line.long 0x0 "DMA_RXBUF_SIZE_Q1,Receive Buffer queue 1 Size"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DMA_RX_Q_BUF_SIZE,DMA receive buffer size in system memory. The value defined by these bits determines the size of buffer to use in main system memory when writing received data. The value is defined in multiples of 64 bytes."
|
|
line.long 0x4 "DMA_RXBUF_SIZE_Q2,Receive Buffer queue 2 Size"
|
|
hexmask.long.byte 0x4 0.--7. 1. "DMA_RX_Q_BUF_SIZE,DMA receive buffer size in system memory. The value defined by these bits determines the size of buffer to use in main system memory when writing received data. The value is defined in multiples of 64 bytes."
|
|
rgroup.long 0x14A8++0x3
|
|
line.long 0x0 "DMA_RXBUF_SIZE_Q3,dma_rxbuf_size_q3 to dma_rxbuf_size_q7 doesn't present."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,DMA receive buffer size in system memory. The value defined by these bits determines the size of buffer to use in main system memory when writing received data. The value is defined in multiples of 64 bytes."
|
|
rgroup.long 0x14B8++0x3
|
|
line.long 0x0 "DMA_RXBUF_SIZE_Q7,Not presents."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
group.long 0x14BC++0x1B
|
|
line.long 0x0 "CBS_CONTROL,The IdleSlope value is defined as the rate of change of credit when a packet is waiting to be sent. This must not exceed the portTransmitRate which is dependent on the speed of operation. eg. portTranmsitRate. 1Gb/s = 32'h07735940 (125.."
|
|
bitfld.long 0x0 1. "CBS_ENABLE_QUEUE_B,Enable Credit-Based shaping on the 2nd highest priority queue (queue B). Write 1 to enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CBS_ENABLE_QUEUE_A,Enable Credit-Based Shaping on the highest priority queue (queue A). Write 1 to enable" "0,1"
|
|
line.long 0x4 "CBS_IDLESLOPE_Q_A,queue A is the highest priority queue. This would be queue 8 in an 8 queue configuration."
|
|
hexmask.long 0x4 0.--31. 1. "IDLESLOPE_A,IdleSlope value for queue A in bytes/sec for gigabit operation and nibbles/sec for 10/100 operation"
|
|
line.long 0x8 "CBS_IDLESLOPE_Q_B,queue B is the 2nd highest priority queue. This would be queue 7 in an 8 queue configuration."
|
|
hexmask.long 0x8 0.--31. 1. "IDLESLOPE_B,IdleSlope value for queue B in bytes/sec for gigabit operation and nibbles/sec for 10/100 operation"
|
|
line.long 0xC "UPPER_TX_Q_BASE_ADDR,Upper 32 bits of transmit buffer descriptor queue base address."
|
|
hexmask.long 0xC 0.--31. 1. "UPPER_TX_Q_BASE_ADDR,Upper 32 bits of transmit buffer descriptor queue base address. Used when 64 bit addressing is enabled. (In releases earlier to 1p06f2 this register also affected the receive descriptor queue.)"
|
|
line.long 0x10 "TX_BD_CONTROL,TX BD control register"
|
|
bitfld.long 0x10 4.--5. "TX_BD_TS_MODE,TX Descriptor Timestamp Insertion mode 00: TS insertion disable 01: TS inserted for PTP Event Frames only 10: TS inserted for All PTP Frames only 11: TS insertion for All Frames" "0: TS insertion disable,1: TS inserted for PTP Event Frames only,?,?"
|
|
line.long 0x14 "RX_BD_CONTROL,RX BD control register"
|
|
bitfld.long 0x14 4.--5. "RX_BD_TS_MODE,RX Descriptor Timestamp Insertion mode 00: TS insertion disable 01: TS inserted for PTP Event Frames only 10: TS inserted for All PTP Frames only 11: TS insertion for All Frames" "0: TS insertion disable,1: TS inserted for PTP Event Frames only,?,?"
|
|
line.long 0x18 "UPPER_RX_Q_BASE_ADDR,Upper 32 bits of receive buffer descriptor queue base address."
|
|
hexmask.long 0x18 0.--31. 1. "UPPER_RX_Q_BASE_ADDR,Upper 32 bits of receive buffer descriptor queue base address. Used when 64 bit addressing is enabled."
|
|
group.long 0x14E0++0xF
|
|
line.long 0x0 "HIDDEN_REG0,Hidden registers defined in edma_defs.v '`define gem_cbs_port_tx_rate_10m 12'h4e0 // 10M Port TX Rate *** HIDDEN Register ***'. Default value of cbs related hidden registers (0x14E0~0x14E8) are depicted in cbs_control register."
|
|
hexmask.long 0x0 0.--31. 1. "HIDDEN0_FIELD,default value is defined per description of register cbs_control."
|
|
line.long 0x4 "HIDDEN_REG1,Hidden registers defined in edma_defs.v '`define gem_cbs_port_tx_rate_100m 12'h4e4 // 100M Port TX Rate *** HIDDEN Register ***'"
|
|
hexmask.long 0x4 0.--31. 1. "HIDDEN1_FIELD,default value is defined per description of register cbs_control."
|
|
line.long 0x8 "HIDDEN_REG2,Hidden registers defined in edma_defs.v '`define gem_cbs_port_tx_rate_1g 12'h4e8 // 1G Port TX Rate *** HIDDEN Register ***'"
|
|
hexmask.long 0x8 0.--31. 1. "HIDDEN2_FIELD,default value is defined per description of register cbs_control."
|
|
line.long 0xC "HIDDEN_REG3,Hidden registers defined in edma_defs.v '`define gem_wd_counter 12'h4ec // *** HIDDEN Register ***'."
|
|
hexmask.long.byte 0xC 0.--3. 1. "HIDDEN3_FIELD,default value is defined per description of register cbs_control."
|
|
group.long 0x14F8++0x8B
|
|
line.long 0x0 "HIDDEN_REG4,Hidden registers defined in edma_defs.v '`define gem_axi_tx_full_threshold0 12'h4f8 // AXI full threshold setting *** HIDDEN Register ***'. Note. When using AXI mode with a single port ram ( gem_spram == 1) mode and a 32b dma bus width (.."
|
|
hexmask.long.word 0x0 16.--24. 1. "HIDDEN4_FIELD_H,The valid bits is defined by `gem_tx_pbuf_addr."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "HIDDEN4_FIELD_L,The valid bits is defined by `gem_tx_pbuf_addr."
|
|
line.long 0x4 "HIDDEN_REG5,Hidden registers defined in edma_defs.v '`define gem_axi_tx_full_threshold1 12'h4fc // AXI full threshold setting *** HIDDEN Register ***'."
|
|
hexmask.long.word 0x4 16.--24. 1. "HIDDEN5_FIELD_H,The valid bits is defined by `gem_tx_pbuf_addr."
|
|
newline
|
|
hexmask.long.word 0x4 0.--8. 1. "HIDDEN5_FIELD_L,The valid bits is defined by `gem_tx_pbuf_addr."
|
|
line.long 0x8 "SCREENING_TYPE_1_REGISTER_0,Screening type 1 registers are used to allocate up to 16 priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly. when DS/TC match enable is set (bit 28). the DS (Differentiated.."
|
|
bitfld.long 0x8 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x8 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
|
|
line.long 0xC "SCREENING_TYPE_1_REGISTER_1,screening type 1 register 1. same as screening_type_1_register_0"
|
|
bitfld.long 0xC 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0xC 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
|
newline
|
|
hexmask.long.byte 0xC 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
|
|
line.long 0x10 "SCREENING_TYPE_1_REGISTER_2,screening type 1 register 2. same as screening_type_1_register_0"
|
|
bitfld.long 0x10 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x10 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
|
newline
|
|
hexmask.long.byte 0x10 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
|
|
line.long 0x14 "SCREENING_TYPE_1_REGISTER_3,screening type 1 register 3. same as screening_type_1_register_0"
|
|
bitfld.long 0x14 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
|
newline
|
|
bitfld.long 0x14 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x14 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
|
newline
|
|
hexmask.long.byte 0x14 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
|
|
line.long 0x18 "SCREENING_TYPE_1_REGISTER_4,screening type 1 register 4. same as screening_type_1_register_0"
|
|
bitfld.long 0x18 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x18 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
|
newline
|
|
hexmask.long.byte 0x18 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
|
|
line.long 0x1C "SCREENING_TYPE_1_REGISTER_5,screening type 1 register 5. same as screening_type_1_register_0"
|
|
bitfld.long 0x1C 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x1C 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
|
newline
|
|
hexmask.long.byte 0x1C 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
|
|
line.long 0x20 "SCREENING_TYPE_1_REGISTER_6,screening type 1 register 6. same as screening_type_1_register_0"
|
|
bitfld.long 0x20 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
|
newline
|
|
bitfld.long 0x20 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x20 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
|
newline
|
|
hexmask.long.byte 0x20 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
|
hexmask.long.byte 0x20 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
|
|
line.long 0x24 "SCREENING_TYPE_1_REGISTER_7,screening type 1 register 7. same as screening_type_1_register_0"
|
|
bitfld.long 0x24 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
|
newline
|
|
bitfld.long 0x24 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x24 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
|
newline
|
|
hexmask.long.byte 0x24 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
|
hexmask.long.byte 0x24 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
|
|
line.long 0x28 "SCREENING_TYPE_1_REGISTER_8,screening type 1 register 8. same as screening_type_1_register_0"
|
|
bitfld.long 0x28 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
|
newline
|
|
bitfld.long 0x28 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x28 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
|
newline
|
|
hexmask.long.byte 0x28 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
|
hexmask.long.byte 0x28 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
|
|
line.long 0x2C "SCREENING_TYPE_1_REGISTER_9,screening type 1 register 9. same as screening_type_1_register_0"
|
|
bitfld.long 0x2C 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x2C 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
|
newline
|
|
hexmask.long.byte 0x2C 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
|
hexmask.long.byte 0x2C 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
|
|
line.long 0x30 "SCREENING_TYPE_1_REGISTER_10,screening type 1 register 10. same as screening_type_1_register_0"
|
|
bitfld.long 0x30 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
|
newline
|
|
bitfld.long 0x30 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x30 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
|
newline
|
|
hexmask.long.byte 0x30 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
|
hexmask.long.byte 0x30 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
|
|
line.long 0x34 "SCREENING_TYPE_1_REGISTER_11,screening type 1 register 11. same as screening_type_1_register_0"
|
|
bitfld.long 0x34 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
|
newline
|
|
bitfld.long 0x34 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x34 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
|
newline
|
|
hexmask.long.byte 0x34 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
|
hexmask.long.byte 0x34 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
|
|
line.long 0x38 "SCREENING_TYPE_1_REGISTER_12,screening type 1 register 12. same as screening_type_1_register_0"
|
|
bitfld.long 0x38 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
|
newline
|
|
bitfld.long 0x38 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x38 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
|
newline
|
|
hexmask.long.byte 0x38 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
|
hexmask.long.byte 0x38 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
|
|
line.long 0x3C "SCREENING_TYPE_1_REGISTER_13,screening type 1 register 13. same as screening_type_1_register_0"
|
|
bitfld.long 0x3C 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
|
newline
|
|
bitfld.long 0x3C 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x3C 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
|
newline
|
|
hexmask.long.byte 0x3C 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
|
hexmask.long.byte 0x3C 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
|
|
line.long 0x40 "SCREENING_TYPE_1_REGISTER_14,screening type 1 register 14. same as screening_type_1_register_0"
|
|
bitfld.long 0x40 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
|
newline
|
|
bitfld.long 0x40 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x40 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
|
newline
|
|
hexmask.long.byte 0x40 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
|
hexmask.long.byte 0x40 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
|
|
line.long 0x44 "SCREENING_TYPE_1_REGISTER_15,screening type 1 register 15. same as screening_type_1_register_0"
|
|
bitfld.long 0x44 29. "UDP_PORT_MATCH_ENABLE,UDP port match enable" "0,1"
|
|
newline
|
|
bitfld.long 0x44 28. "DSTC_ENABLE,DS/TC Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x44 12.--27. 1. "UDP_PORT_MATCH,UDP Port Match"
|
|
newline
|
|
hexmask.long.byte 0x44 4.--11. 1. "DSTC_MATCH,DS/TC Match"
|
|
newline
|
|
hexmask.long.byte 0x44 0.--3. 1. "QUEUE_NUMBER,Queue Number (0 to 15)"
|
|
line.long 0x48 "SCREENING_TYPE_2_REGISTER_0,Screener Type 2 match registers operate independently of screener type 1 registers and offer additional match capabilities. extending the capabilities into vendor specific protocols."
|
|
rbitfld.long 0x48 31. "RSVD_31,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x48 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x48 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
|
|
newline
|
|
bitfld.long 0x48 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x48 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
|
|
newline
|
|
bitfld.long 0x48 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
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hexmask.long.byte 0x48 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
|
|
newline
|
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bitfld.long 0x48 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
|
newline
|
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bitfld.long 0x48 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x48 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
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newline
|
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bitfld.long 0x48 7. "RSVD_7,N/A" "0,1"
|
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newline
|
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bitfld.long 0x48 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
|
newline
|
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hexmask.long.byte 0x48 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
|
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line.long 0x4C "SCREENING_TYPE_2_REGISTER_1,screening type 2 register 1. same as screening_type_2_register_0"
|
|
rbitfld.long 0x4C 31. "RSVD_31,N/A" "0,1"
|
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newline
|
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bitfld.long 0x4C 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
|
newline
|
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hexmask.long.byte 0x4C 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
|
|
newline
|
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bitfld.long 0x4C 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
|
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|
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hexmask.long.byte 0x4C 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
|
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newline
|
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bitfld.long 0x4C 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
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newline
|
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hexmask.long.byte 0x4C 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
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newline
|
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bitfld.long 0x4C 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
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newline
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bitfld.long 0x4C 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x4C 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
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bitfld.long 0x4C 7. "RSVD_7,N/A" "0,1"
|
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newline
|
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bitfld.long 0x4C 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.byte 0x4C 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
|
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line.long 0x50 "SCREENING_TYPE_2_REGISTER_2,screening type 2 register 2. same as screening_type_2_register_0"
|
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rbitfld.long 0x50 31. "RSVD_31,N/A" "0,1"
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bitfld.long 0x50 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
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hexmask.long.byte 0x50 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
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newline
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bitfld.long 0x50 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
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hexmask.long.byte 0x50 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
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newline
|
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bitfld.long 0x50 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
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newline
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hexmask.long.byte 0x50 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
|
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newline
|
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bitfld.long 0x50 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
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newline
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bitfld.long 0x50 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x50 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
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bitfld.long 0x50 7. "RSVD_7,N/A" "0,1"
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|
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bitfld.long 0x50 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.byte 0x50 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
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line.long 0x54 "SCREENING_TYPE_2_REGISTER_3,screening type 2 register 3. same as screening_type_2_register_0"
|
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rbitfld.long 0x54 31. "RSVD_31,N/A" "0,1"
|
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|
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bitfld.long 0x54 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
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hexmask.long.byte 0x54 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
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newline
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bitfld.long 0x54 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
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hexmask.long.byte 0x54 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
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newline
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bitfld.long 0x54 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
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hexmask.long.byte 0x54 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
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newline
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bitfld.long 0x54 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
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newline
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bitfld.long 0x54 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x54 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
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bitfld.long 0x54 7. "RSVD_7,N/A" "0,1"
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bitfld.long 0x54 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x54 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
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line.long 0x58 "SCREENING_TYPE_2_REGISTER_4,screening type 2 register 4. same as screening_type_2_register_0"
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rbitfld.long 0x58 31. "RSVD_31,N/A" "0,1"
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newline
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bitfld.long 0x58 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
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hexmask.long.byte 0x58 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
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newline
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bitfld.long 0x58 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
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newline
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hexmask.long.byte 0x58 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
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newline
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bitfld.long 0x58 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
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newline
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hexmask.long.byte 0x58 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
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newline
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bitfld.long 0x58 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
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newline
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bitfld.long 0x58 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x58 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
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bitfld.long 0x58 7. "RSVD_7,N/A" "0,1"
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newline
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bitfld.long 0x58 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
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newline
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hexmask.long.byte 0x58 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
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line.long 0x5C "SCREENING_TYPE_2_REGISTER_5,screening type 2 register 5. same as screening_type_2_register_0"
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rbitfld.long 0x5C 31. "RSVD_31,N/A" "0,1"
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newline
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bitfld.long 0x5C 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
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newline
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hexmask.long.byte 0x5C 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
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newline
|
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bitfld.long 0x5C 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
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newline
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hexmask.long.byte 0x5C 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
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newline
|
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bitfld.long 0x5C 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
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newline
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hexmask.long.byte 0x5C 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
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newline
|
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bitfld.long 0x5C 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
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newline
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bitfld.long 0x5C 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
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newline
|
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bitfld.long 0x5C 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
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newline
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bitfld.long 0x5C 7. "RSVD_7,N/A" "0,1"
|
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newline
|
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bitfld.long 0x5C 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
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newline
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hexmask.long.byte 0x5C 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
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line.long 0x60 "SCREENING_TYPE_2_REGISTER_6,screening type 2 register 6. same as screening_type_2_register_0"
|
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rbitfld.long 0x60 31. "RSVD_31,N/A" "0,1"
|
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newline
|
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bitfld.long 0x60 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
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newline
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hexmask.long.byte 0x60 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
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newline
|
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bitfld.long 0x60 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
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newline
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hexmask.long.byte 0x60 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
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newline
|
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bitfld.long 0x60 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
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newline
|
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hexmask.long.byte 0x60 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
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newline
|
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bitfld.long 0x60 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
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newline
|
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bitfld.long 0x60 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
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newline
|
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bitfld.long 0x60 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
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newline
|
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bitfld.long 0x60 7. "RSVD_7,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x60 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
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newline
|
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hexmask.long.byte 0x60 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
|
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line.long 0x64 "SCREENING_TYPE_2_REGISTER_7,screening type 2 register 7. same as screening_type_2_register_0"
|
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rbitfld.long 0x64 31. "RSVD_31,N/A" "0,1"
|
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newline
|
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bitfld.long 0x64 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
|
newline
|
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hexmask.long.byte 0x64 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
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newline
|
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bitfld.long 0x64 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
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newline
|
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hexmask.long.byte 0x64 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
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newline
|
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bitfld.long 0x64 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
|
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newline
|
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hexmask.long.byte 0x64 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
|
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newline
|
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bitfld.long 0x64 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
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newline
|
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bitfld.long 0x64 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
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newline
|
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bitfld.long 0x64 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
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newline
|
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bitfld.long 0x64 7. "RSVD_7,N/A" "0,1"
|
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newline
|
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bitfld.long 0x64 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
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newline
|
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hexmask.long.byte 0x64 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
|
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line.long 0x68 "SCREENING_TYPE_2_REGISTER_8,screening type 2 register 8. same as screening_type_2_register_0"
|
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rbitfld.long 0x68 31. "RSVD_31,N/A" "0,1"
|
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newline
|
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bitfld.long 0x68 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
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newline
|
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hexmask.long.byte 0x68 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
|
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newline
|
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bitfld.long 0x68 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
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|
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hexmask.long.byte 0x68 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
|
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newline
|
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bitfld.long 0x68 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
|
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newline
|
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hexmask.long.byte 0x68 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
|
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newline
|
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bitfld.long 0x68 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
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newline
|
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bitfld.long 0x68 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
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newline
|
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bitfld.long 0x68 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
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newline
|
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bitfld.long 0x68 7. "RSVD_7,N/A" "0,1"
|
|
newline
|
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bitfld.long 0x68 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
|
newline
|
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hexmask.long.byte 0x68 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
|
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line.long 0x6C "SCREENING_TYPE_2_REGISTER_9,screening type 2 register 9. same as screening_type_2_register_0"
|
|
rbitfld.long 0x6C 31. "RSVD_31,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x6C 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
|
newline
|
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hexmask.long.byte 0x6C 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
|
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newline
|
|
bitfld.long 0x6C 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
|
newline
|
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hexmask.long.byte 0x6C 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
|
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newline
|
|
bitfld.long 0x6C 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
|
|
newline
|
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hexmask.long.byte 0x6C 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
|
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newline
|
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bitfld.long 0x6C 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
|
newline
|
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bitfld.long 0x6C 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x6C 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
|
newline
|
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bitfld.long 0x6C 7. "RSVD_7,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x6C 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
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newline
|
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hexmask.long.byte 0x6C 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
|
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line.long 0x70 "SCREENING_TYPE_2_REGISTER_10,screening type 2 register 10. same as screening_type_2_register_0"
|
|
rbitfld.long 0x70 31. "RSVD_31,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x70 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x70 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
|
|
newline
|
|
bitfld.long 0x70 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x70 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
|
|
newline
|
|
bitfld.long 0x70 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x70 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
|
|
newline
|
|
bitfld.long 0x70 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
|
newline
|
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bitfld.long 0x70 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x70 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
|
newline
|
|
bitfld.long 0x70 7. "RSVD_7,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x70 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
|
newline
|
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hexmask.long.byte 0x70 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
|
|
line.long 0x74 "SCREENING_TYPE_2_REGISTER_11,screening type 2 register 11. same as screening_type_2_register_0"
|
|
rbitfld.long 0x74 31. "RSVD_31,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x74 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x74 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
|
|
newline
|
|
bitfld.long 0x74 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x74 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
|
|
newline
|
|
bitfld.long 0x74 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x74 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
|
|
newline
|
|
bitfld.long 0x74 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
|
newline
|
|
bitfld.long 0x74 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x74 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
|
|
newline
|
|
bitfld.long 0x74 7. "RSVD_7,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x74 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x74 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
|
|
line.long 0x78 "SCREENING_TYPE_2_REGISTER_12,screening type 2 register 12. same as screening_type_2_register_0"
|
|
rbitfld.long 0x78 31. "RSVD_31,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x78 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x78 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
|
|
newline
|
|
bitfld.long 0x78 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x78 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
|
|
newline
|
|
bitfld.long 0x78 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x78 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
|
|
newline
|
|
bitfld.long 0x78 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
|
|
newline
|
|
bitfld.long 0x78 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
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bitfld.long 0x78 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
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bitfld.long 0x78 7. "RSVD_7,N/A" "0,1"
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bitfld.long 0x78 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
|
|
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hexmask.long.byte 0x78 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
|
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line.long 0x7C "SCREENING_TYPE_2_REGISTER_13,screening type 2 register 13. same as screening_type_2_register_0"
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rbitfld.long 0x7C 31. "RSVD_31,N/A" "0,1"
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bitfld.long 0x7C 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
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hexmask.long.byte 0x7C 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
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bitfld.long 0x7C 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
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hexmask.long.byte 0x7C 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
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bitfld.long 0x7C 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
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hexmask.long.byte 0x7C 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
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bitfld.long 0x7C 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
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bitfld.long 0x7C 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
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bitfld.long 0x7C 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
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bitfld.long 0x7C 7. "RSVD_7,N/A" "0,1"
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bitfld.long 0x7C 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x7C 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
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line.long 0x80 "SCREENING_TYPE_2_REGISTER_14,screening type 2 register 14. same as screening_type_2_register_0"
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rbitfld.long 0x80 31. "RSVD_31,N/A" "0,1"
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bitfld.long 0x80 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
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hexmask.long.byte 0x80 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
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bitfld.long 0x80 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
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hexmask.long.byte 0x80 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
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bitfld.long 0x80 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
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hexmask.long.byte 0x80 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
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bitfld.long 0x80 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
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bitfld.long 0x80 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
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bitfld.long 0x80 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
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bitfld.long 0x80 7. "RSVD_7,N/A" "0,1"
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bitfld.long 0x80 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x80 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
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line.long 0x84 "SCREENING_TYPE_2_REGISTER_15,screening type 2 register 15. same as screening_type_2_register_0"
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rbitfld.long 0x84 31. "RSVD_31,N/A" "0,1"
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bitfld.long 0x84 30. "COMPARE_C_ENABLE,'Compare C Enable'" "0,1"
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hexmask.long.byte 0x84 25.--29. 1. "COMPARE_C,'Compare C - Index to screener type 2 Compare register'"
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bitfld.long 0x84 24. "COMPARE_B_ENABLE,'Compare B Enable'" "0,1"
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hexmask.long.byte 0x84 19.--23. 1. "COMPARE_B,'Compare B - Index to screener type 2 Compare register'"
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bitfld.long 0x84 18. "COMPARE_A_ENABLE,'Compare A Enable'" "0,1"
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hexmask.long.byte 0x84 13.--17. 1. "COMPARE_A,'Compare A - Index to screener type 2 Compare register '"
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newline
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bitfld.long 0x84 12. "ETHERTYPE_ENABLE,'EtherType Enable'" "0,1"
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bitfld.long 0x84 9.--11. "INDEX,'Index to screener type 2 EtherType register'" "0,1,2,3,4,5,6,7"
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bitfld.long 0x84 8. "VLAN_ENABLE,'VLAN Enable'" "0,1"
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bitfld.long 0x84 7. "RSVD_7,N/A" "0,1"
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bitfld.long 0x84 4.--6. "VLAN_PRIORITY,'VLAN Priority'" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x84 0.--3. 1. "QUEUE_NUMBER,'Queue Number (0 to 15)'"
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line.long 0x88 "TX_SCHED_CTRL,This register controls the transmit scheduling algorithm the user can select for each active transmit queue. By default all queues are initialized to fixed priority. with the top indexed queue having overall priority"
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hexmask.long.tbyte 0x88 8.--31. 1. "REMOVED_31_8,Write ignore read 0"
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rbitfld.long 0x88 6.--7. "TX_SCHED_Q3,Write ignore read 0" "0,1,2,3"
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bitfld.long 0x88 4.--5. "TX_SCHED_Q2,'Queue 2 selection." "0: Fixed Priority,1: CBS Enabled only valid for top two enabled..,?,?"
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bitfld.long 0x88 2.--3. "TX_SCHED_Q1,'Queue 1 selection." "0: Fixed Priority,1: CBS Enabled only valid for top two enabled..,?,?"
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bitfld.long 0x88 0.--1. "TX_SCHED_Q0,'Queue 0 selection." "0: Fixed Priority,1: CBS Enabled only valid for top two enabled..,?,?"
|
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group.long 0x1590++0x7
|
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line.long 0x0 "BW_RATE_LIMIT_Q0TO3,This register holds the DWRR weighting value or the ETS bandwidth percentage value used by the transmit scheduler for queues 0 to 3."
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hexmask.long.byte 0x0 24.--31. 1. "DWRR_ETS_WEIGHT_Q3,Write ignore read 0"
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hexmask.long.byte 0x0 16.--23. 1. "DWRR_ETS_WEIGHT_Q2,'DWRR Weighting / ETS Bandwidth Allocation for queue 2'"
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hexmask.long.byte 0x0 8.--15. 1. "DWRR_ETS_WEIGHT_Q1,'DWRR Weighting / ETS Bandwidth Allocation for queue 1'"
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hexmask.long.byte 0x0 0.--7. 1. "DWRR_ETS_WEIGHT_Q0,'DWRR Weighting / ETS Bandwidth Allocation for queue 0'"
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line.long 0x4 "BW_RATE_LIMIT_Q4TO7,Not presents. MXETH has only 3 queues. Access to the register returns AHB error."
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hexmask.long 0x4 0.--31. 1. "REMOVED_31_0,'DWRR Weighting / ETS Bandwidth Allocation for queue 0'"
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rgroup.long 0x1598++0x7
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line.long 0x0 "BW_RATE_LIMIT_Q8TO11,Not presents. MXETH has only 3 queues. Access to the register returns AHB error."
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hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
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line.long 0x4 "BW_RATE_LIMIT_Q12TO15,Not presents. MXETH has only 3 queues. Access to the register returns AHB error."
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hexmask.long 0x4 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
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group.long 0x15A0++0x3
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line.long 0x0 "TX_Q_SEG_ALLOC_Q0TO7,This register allows the user to distribute the Transmit SRAM used by the DMA across the priority queues. for queues 0 to 7. The SRAM itself is split into a number of evenly sized segments (this is defined in the verilog.."
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rbitfld.long 0x0 31. "RSVD_31_31,Write ignore read 0" "0,1"
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rbitfld.long 0x0 28.--30. "REMOVED_30_28,Write ignore read 0" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x0 27. "RSVD_27_27,Write ignore read 0" "0,1"
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rbitfld.long 0x0 24.--26. "REMOVED_26_24,Write ignore read 0" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x0 23. "RSVD_23,Write ignore read 0" "0,1"
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rbitfld.long 0x0 20.--22. "REMOVED_22_20,Write ignore read 0" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x0 19. "RSVD_19_19,Write ignore read 0" "0,1"
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rbitfld.long 0x0 16.--18. "REMOVED_18_16,Write ignore read 0" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x0 15. "RSVD_15_15,Write ignore read 0" "0,1"
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rbitfld.long 0x0 12.--14. "REMOVED_14_12,Write ignore read 0" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x0 11. "RSVD_11_11,Write ignore read 0" "0,1"
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bitfld.long 0x0 8.--10. "SEGMENT_ALLOC_Q2,Number of segments allocated to q2. This should be entered as a log 2 for example entering a value of 2 would grant 4 segments. A maximum of 32 segments can be granted" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x0 7. "RSVD_7_7,N/A" "0,1"
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bitfld.long 0x0 4.--6. "SEGMENT_ALLOC_Q1,Number of segments allocated to q1. This should be entered as a log 2 for example entering a value of 2 would grant 4 segments. A maximum of 32 segments can be granted" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x0 3. "RSVD_3_3,N/A" "0,1"
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bitfld.long 0x0 0.--2. "SEGMENT_ALLOC_Q0,Number of segments allocated to q0. This should be entered as a log 2 for example entering a value of 2 would grant 4 segments. A maximum of 32 segments can be granted. The default value is determined by `gem_tx_pbuf_num_segments_q0" "0,1,2,3,4,5,6,7"
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rgroup.long 0x15A4++0x3
|
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line.long 0x0 "TX_Q_SEG_ALLOC_Q8TO15,Not presents. Access to the register returns AHB error."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
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rgroup.long 0x15C0++0x3
|
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line.long 0x0 "RECEIVE_Q8_PTR,receive_q8_ptr to receive_q15_ptr doesn't present. Access to the register returns AHB error."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
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rgroup.long 0x15DC++0x7
|
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line.long 0x0 "RECEIVE_Q15_PTR,Not presents."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
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line.long 0x4 "DMA_RXBUF_SIZE_Q8,dma_rxbuf_size_q8 to dma_rxbuf_size_q15 doesn't present. Access to the register returns AHB error."
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hexmask.long 0x4 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
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rgroup.long 0x15FC++0x3
|
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line.long 0x0 "DMA_RXBUF_SIZE_Q15,Not presents."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
wgroup.long 0x1600++0x7
|
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line.long 0x0 "INT_Q1_ENABLE,At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero."
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|
bitfld.long 0x0 11. "ENABLE_RESP_NOT_OK_INTERRUPT,Enable bresp not OK interrupt" "0,1"
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|
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bitfld.long 0x0 7. "ENABLE_TRANSMIT_COMPLETE_INTERRUPT,Enable Transmit complete interrupt" "0,1"
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newline
|
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bitfld.long 0x0 6. "ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT,Enable Transmit frame corruption due to AMBA (AXI/AHB) error interrupt" "0,1"
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newline
|
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bitfld.long 0x0 5. "ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT,Enable Retry limit exceeded or late collision interrupt" "0,1"
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|
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bitfld.long 0x0 2. "ENABLE_RX_USED_BIT_READ_INTERRUPT,Enable RX used bit read interrupt" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "ENABLE_RECEIVE_COMPLETE_INTERRUPT,Enable Receive complete interrupt" "0,1"
|
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line.long 0x4 "INT_Q2_ENABLE,At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero."
|
|
bitfld.long 0x4 11. "ENABLE_RESP_NOT_OK_INTERRUPT,Enable bresp not OK interrupt" "0,1"
|
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newline
|
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bitfld.long 0x4 7. "ENABLE_TRANSMIT_COMPLETE_INTERRUPT,Enable Transmit complete interrupt" "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "ENABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT,Enable Transmit frame corruption due to AMBA (AXI/AHB) error interrupt" "0,1"
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newline
|
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bitfld.long 0x4 5. "ENABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT,Enable Retry limit exceeded or late collision interrupt" "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "ENABLE_RX_USED_BIT_READ_INTERRUPT,Enable RX used bit read interrupt" "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "ENABLE_RECEIVE_COMPLETE_INTERRUPT,Enable Receive complete interrupt" "0,1"
|
|
rgroup.long 0x1608++0x3
|
|
line.long 0x0 "INT_Q3_ENABLE,int_q3_enable to int_q7_enable doesn't present. Access to the register returns AHB error."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x1618++0x3
|
|
line.long 0x0 "INT_Q7_ENABLE,Not presents."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
wgroup.long 0x1620++0x7
|
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line.long 0x0 "INT_Q1_DISABLE,Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero."
|
|
bitfld.long 0x0 11. "DISABLE_RESP_NOT_OK_INTERRUPT,Disable bresp not OK interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "DISABLE_TRANSMIT_COMPLETE_INTERRUPT,Disable Transmit complete interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT,Disable Transmit frame corruption due to AMBA (AXI/AHB) error interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT,Disable Retry limit exceeded or late collision interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DISABLE_RX_USED_BIT_READ_INTERRUPT,Disable RX used bit read interrupt" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "DISABLE_RECEIVE_COMPLETE_INTERRUPT,Disable Receive complete interrupt" "0,1"
|
|
line.long 0x4 "INT_Q2_DISABLE,Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero."
|
|
bitfld.long 0x4 11. "DISABLE_RESP_NOT_OK_INTERRUPT,Disable bresp not OK interrupt" "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "DISABLE_TRANSMIT_COMPLETE_INTERRUPT,Disable Transmit complete interrupt" "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "DISABLE_TRANSMIT_FRAME_CORRUPTION_DUE_TO_AMBA_ERROR_INTERRUPT,Disable Transmit frame corruption due to AMBA (AXI/AHB) error interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DISABLE_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT,Disable Retry limit exceeded or late collision interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DISABLE_RX_USED_BIT_READ_INTERRUPT,Disable RX used bit read interrupt" "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "DISABLE_RECEIVE_COMPLETE_INTERRUPT,Disable Receive complete interrupt" "0,1"
|
|
rgroup.long 0x1628++0x3
|
|
line.long 0x0 "INT_Q3_DISABLE,int_q3_disable to int_q7_disable doesn't present. Access to the register returns AHB error."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x1638++0x3
|
|
line.long 0x0 "INT_Q7_DISABLE,Not presents."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x1640++0xB
|
|
line.long 0x0 "INT_Q1_MASK,The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt.."
|
|
bitfld.long 0x0 11. "RESP_NOT_OK_INTERRUPT_MASK,bresp not OK interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
newline
|
|
bitfld.long 0x0 7. "TRANSMIT_COMPLETE_INTERRUPT_MASK,transmit complete interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
newline
|
|
bitfld.long 0x0 6. "AMBA_ERROR_INTERRUPT_MASK,A read of this register returns the value of the AMBA (AXI/AHB) error interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
newline
|
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bitfld.long 0x0 5. "RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK,retry limit exceeded or late collision interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
newline
|
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bitfld.long 0x0 2. "RX_USED_INTERRUPT_MASK,A read of this register returns the value of the RX Used interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
newline
|
|
bitfld.long 0x0 1. "RECEIVE_COMPLETE_INTERRUPT_MASK,receive complete interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
line.long 0x4 "INT_Q2_MASK,The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt.."
|
|
bitfld.long 0x4 11. "RESP_NOT_OK_INTERRUPT_MASK,bresp not OK interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
newline
|
|
bitfld.long 0x4 7. "TRANSMIT_COMPLETE_INTERRUPT_MASK,transmit complete interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
newline
|
|
bitfld.long 0x4 6. "AMBA_ERROR_INTERRUPT_MASK,A read of this register returns the value of the AMBA (AXI/AHB) error interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
newline
|
|
bitfld.long 0x4 5. "RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION_INTERRUPT_MASK,retry limit exceeded or late collision interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
newline
|
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bitfld.long 0x4 2. "RX_USED_INTERRUPT_MASK,A read of this register returns the value of the RX Used interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
newline
|
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bitfld.long 0x4 1. "RECEIVE_COMPLETE_INTERRUPT_MASK,receive complete interrupt mask." "0: Interrupt is enabled,1: Interrupt is disabled"
|
|
line.long 0x8 "INT_Q3_MASK,int_q3_mask to int_q7_mask doesn't present. Access to the register returns AHB error."
|
|
hexmask.long 0x8 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x1658++0x3
|
|
line.long 0x0 "INT_Q7_MASK,Not presents."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x1660++0x3
|
|
line.long 0x0 "INT_Q8_ENABLE,int_q8_enable to int_q15_enable doesn't present. Access to the register returns AHB error."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x167C++0x7
|
|
line.long 0x0 "INT_Q15_ENABLE,Not presents."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
line.long 0x4 "INT_Q8_DISABLE,int_q8_disable to int_q15_disable doesn't present. Access to the register returns AHB error."
|
|
hexmask.long 0x4 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x169C++0x7
|
|
line.long 0x0 "INT_Q15_DISABLE,Not presents."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
line.long 0x4 "INT_Q8_MASK,int_q8_mask to int_q15_mask doesn't present. Access to the register returns AHB error."
|
|
hexmask.long 0x4 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
rgroup.long 0x16BC++0x3
|
|
line.long 0x0 "INT_Q15_MASK,Not presents."
|
|
hexmask.long 0x0 0.--31. 1. "REMOVED_31_0,Write ignore read 0"
|
|
group.long 0x16E0++0x11F
|
|
line.long 0x0 "SCREENING_TYPE_2_ETHERTYPE_REG_0,Ethertype Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RSVD_31_16,N/A"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "COMPARE_VALUE,'EtherType compare value'"
|
|
line.long 0x4 "SCREENING_TYPE_2_ETHERTYPE_REG_1,Ethertype Register"
|
|
hexmask.long.word 0x4 16.--31. 1. "RSVD_31_16,N/A"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "COMPARE_VALUE,'EtherType compare value'"
|
|
line.long 0x8 "SCREENING_TYPE_2_ETHERTYPE_REG_2,Ethertype Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "RSVD_31_16,N/A"
|
|
newline
|
|
hexmask.long.word 0x8 0.--15. 1. "COMPARE_VALUE,'EtherType compare value'"
|
|
line.long 0xC "SCREENING_TYPE_2_ETHERTYPE_REG_3,Ethertype Register"
|
|
hexmask.long.word 0xC 16.--31. 1. "RSVD_31_16,N/A"
|
|
newline
|
|
hexmask.long.word 0xC 0.--15. 1. "COMPARE_VALUE,'EtherType compare value'"
|
|
line.long 0x10 "SCREENING_TYPE_2_ETHERTYPE_REG_4,Ethertype Register"
|
|
hexmask.long.word 0x10 16.--31. 1. "RSVD_31_16,N/A"
|
|
newline
|
|
hexmask.long.word 0x10 0.--15. 1. "COMPARE_VALUE,'EtherType compare value'"
|
|
line.long 0x14 "SCREENING_TYPE_2_ETHERTYPE_REG_5,Ethertype Register"
|
|
hexmask.long.word 0x14 16.--31. 1. "RSVD_31_16,N/A"
|
|
newline
|
|
hexmask.long.word 0x14 0.--15. 1. "COMPARE_VALUE,'EtherType compare value'"
|
|
line.long 0x18 "SCREENING_TYPE_2_ETHERTYPE_REG_6,Ethertype Register"
|
|
hexmask.long.word 0x18 16.--31. 1. "RSVD_31_16,N/A"
|
|
newline
|
|
hexmask.long.word 0x18 0.--15. 1. "COMPARE_VALUE,'EtherType compare value'"
|
|
line.long 0x1C "SCREENING_TYPE_2_ETHERTYPE_REG_7,Ethertype Register"
|
|
hexmask.long.word 0x1C 16.--31. 1. "RSVD_31_16,N/A"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--15. 1. "COMPARE_VALUE,'EtherType compare value'"
|
|
line.long 0x20 "TYPE2_COMPARE_0_WORD_0,'Compare A. B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame. ANDed with the MASK Value if the mask.."
|
|
hexmask.long.word 0x20 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x20 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x24 "TYPE2_COMPARE_0_WORD_1,'Type2 Compare Word 1'"
|
|
hexmask.long.tbyte 0x24 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x24 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x24 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x24 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x28 "TYPE2_COMPARE_1_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x28 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x28 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x2C "TYPE2_COMPARE_1_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x2C 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x2C 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x2C 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x2C 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x30 "TYPE2_COMPARE_2_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x30 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x30 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x34 "TYPE2_COMPARE_2_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x34 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x34 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x34 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x34 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x38 "TYPE2_COMPARE_3_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x38 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x38 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x3C "TYPE2_COMPARE_3_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x3C 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x3C 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x3C 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x3C 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x40 "TYPE2_COMPARE_4_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x40 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x40 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x44 "TYPE2_COMPARE_4_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x44 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x44 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x44 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x44 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x48 "TYPE2_COMPARE_5_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x48 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x48 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x4C "TYPE2_COMPARE_5_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x4C 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x4C 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x4C 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x4C 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x50 "TYPE2_COMPARE_6_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x50 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x50 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x54 "TYPE2_COMPARE_6_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x54 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x54 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x54 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x54 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x58 "TYPE2_COMPARE_7_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x58 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x58 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x5C "TYPE2_COMPARE_7_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x5C 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x5C 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x5C 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x5C 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x60 "TYPE2_COMPARE_8_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x60 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x60 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x64 "TYPE2_COMPARE_8_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x64 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x64 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x64 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x64 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x68 "TYPE2_COMPARE_9_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x68 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x68 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x6C "TYPE2_COMPARE_9_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x6C 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x6C 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x6C 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x6C 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x70 "TYPE2_COMPARE_10_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x70 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x70 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x74 "TYPE2_COMPARE_10_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x74 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x74 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x74 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x74 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x78 "TYPE2_COMPARE_11_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x78 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x78 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x7C "TYPE2_COMPARE_11_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x7C 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x7C 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x7C 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x7C 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x80 "TYPE2_COMPARE_12_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x80 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x80 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x84 "TYPE2_COMPARE_12_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x84 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x84 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x84 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x84 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x88 "TYPE2_COMPARE_13_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x88 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x88 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x8C "TYPE2_COMPARE_13_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x8C 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x8C 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x8C 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x8C 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x90 "TYPE2_COMPARE_14_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x90 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x90 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x94 "TYPE2_COMPARE_14_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x94 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x94 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x94 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x94 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x98 "TYPE2_COMPARE_15_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x98 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x98 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x9C "TYPE2_COMPARE_15_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x9C 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x9C 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x9C 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x9C 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0xA0 "TYPE2_COMPARE_16_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0xA0 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0xA0 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0xA4 "TYPE2_COMPARE_16_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0xA4 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0xA4 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0xA4 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0xA4 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0xA8 "TYPE2_COMPARE_17_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0xA8 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0xA8 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0xAC "TYPE2_COMPARE_17_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0xAC 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0xAC 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0xAC 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0xAC 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0xB0 "TYPE2_COMPARE_18_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0xB0 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0xB0 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0xB4 "TYPE2_COMPARE_18_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0xB4 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0xB4 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0xB4 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0xB4 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0xB8 "TYPE2_COMPARE_19_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0xB8 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0xB8 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0xBC "TYPE2_COMPARE_19_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0xBC 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0xBC 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0xBC 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0xBC 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0xC0 "TYPE2_COMPARE_20_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0xC0 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0xC0 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0xC4 "TYPE2_COMPARE_20_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0xC4 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0xC4 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0xC4 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0xC4 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0xC8 "TYPE2_COMPARE_21_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0xC8 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0xC8 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0xCC "TYPE2_COMPARE_21_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0xCC 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0xCC 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0xCC 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0xCC 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0xD0 "TYPE2_COMPARE_22_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0xD0 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0xD0 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0xD4 "TYPE2_COMPARE_22_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0xD4 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0xD4 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0xD4 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0xD4 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0xD8 "TYPE2_COMPARE_23_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0xD8 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0xD8 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0xDC "TYPE2_COMPARE_23_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0xDC 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0xDC 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0xDC 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0xDC 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0xE0 "TYPE2_COMPARE_24_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0xE0 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0xE0 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0xE4 "TYPE2_COMPARE_24_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0xE4 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0xE4 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0xE4 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0xE4 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0xE8 "TYPE2_COMPARE_25_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0xE8 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0xE8 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0xEC "TYPE2_COMPARE_25_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0xEC 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0xEC 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0xEC 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0xEC 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0xF0 "TYPE2_COMPARE_26_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0xF0 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0xF0 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0xF4 "TYPE2_COMPARE_26_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0xF4 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0xF4 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0xF4 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0xF4 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0xF8 "TYPE2_COMPARE_27_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0xF8 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0xF8 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0xFC "TYPE2_COMPARE_27_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0xFC 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0xFC 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0xFC 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0xFC 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x100 "TYPE2_COMPARE_28_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x100 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x100 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x104 "TYPE2_COMPARE_28_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x104 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x104 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x104 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x104 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x108 "TYPE2_COMPARE_29_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x108 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x108 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x10C "TYPE2_COMPARE_29_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x10C 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x10C 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x10C 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x10C 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x110 "TYPE2_COMPARE_30_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x110 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x110 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x114 "TYPE2_COMPARE_30_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x114 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x114 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x114 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x114 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
line.long 0x118 "TYPE2_COMPARE_31_WORD_0,same as type2_compare_0_word_0"
|
|
hexmask.long.word 0x118 16.--31. 1. "COMPARE_VALUE_TYPE2,2 byte Compare Value."
|
|
newline
|
|
hexmask.long.word 0x118 0.--15. 1. "MASK_VALUE,These bits can be either a 2 byte mask field or an additional 2 byte Compare Value."
|
|
line.long 0x11C "TYPE2_COMPARE_31_WORD_1,same as type2_compare_0_word_1"
|
|
hexmask.long.tbyte 0x11C 10.--31. 1. "RSVD_31_10,N/A"
|
|
newline
|
|
bitfld.long 0x11C 9. "DISABLE_MASK,'This bit is used to control whether the compare register word_0 contains a 4-byte compare value or a 2-byte compare value with a 2-byte mask value." "0,1"
|
|
newline
|
|
bitfld.long 0x11C 7.--8. "COMPARE_OFFSET,'Compare byte offset." "0: Offset from beginning of the frame,1: Offset from byte after Ether Type,?,?"
|
|
newline
|
|
hexmask.long.byte 0x11C 0.--6. 1. "OFFSET_VALUE,'Offset value in bytes'"
|
|
tree.end
|
|
tree.end
|
|
tree "EVTGEN (Event Generator)"
|
|
base ad:0x403F0000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "ENABLED,IP enable:" "0: N/A,1: N/A"
|
|
rgroup.long 0x4++0x7
|
|
line.long 0x0 "COMP0_STATUS,Comparator structures comparator 0 status"
|
|
hexmask.long.word 0x0 0.--15. 1. "COMP0_OUT,Active comparator 'comp0_out[]' outputs."
|
|
line.long 0x4 "COMP1_STATUS,Comparator structures comparator 1 status"
|
|
hexmask.long.word 0x4 0.--15. 1. "COMP1_OUT,DeepSleep comparator 'comp1_out_lf[]' outputs (synchronized from clk_lf to the IP clock)."
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x0 "COUNTER_STATUS,Counter status"
|
|
bitfld.long 0x0 31. "VALID,Active counter validity:" "0,1"
|
|
line.long 0x4 "COUNTER,Counter"
|
|
hexmask.long 0x4 0.--31. 1. "INT32,Active counter 'counter_int[31:0]' on clk_ref_div."
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "RATIO_CTL,Ratio control"
|
|
bitfld.long 0x0 31. "VALID,Ratio value valid:" "0,1"
|
|
bitfld.long 0x0 30. "DYNAMIC,Specifies if RATIO_CTL.VALID and RATIO are under SW or HW control:" "?,1: HW control"
|
|
bitfld.long 0x0 16.--18. "DYNAMIC_MODE,Weighted average calculation (only used when DYNAMIC is '1'):" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "RATIO,Ratio"
|
|
hexmask.long.word 0x4 16.--31. 1. "INT16,Integer component of ratio value."
|
|
hexmask.long.byte 0x4 8.--15. 1. "FRAC8,Fractional component of ratio value."
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "REF_CLOCK_CTL,Reference clock control"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_DIV,Divider control for clk_ref_div:"
|
|
group.long 0x700++0xB
|
|
line.long 0x0 "INTR,Interrupt"
|
|
hexmask.long.word 0x0 0.--15. 1. "COMP0,This interrupt cause field is activated (HW sets the field to '1') when a comparator 0 event is generated (Active counter 'counter_int[31:0]' becomes greater or equal to COMP0.INT[31:0])."
|
|
line.long 0x4 "INTR_SET,Interrupt set"
|
|
hexmask.long.word 0x4 0.--15. 1. "COMP0,SW writes a '1' to this field to set the corresponding field in the INTR register."
|
|
line.long 0x8 "INTR_MASK,Interrupt mask"
|
|
hexmask.long.word 0x8 0.--15. 1. "COMP0,Mask bit for corresponding field in the INTR register."
|
|
rgroup.long 0x70C++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
hexmask.long.word 0x0 0.--15. 1. "COMP0,Logical and of corresponding INTR and INTR_MASK fields."
|
|
group.long 0x710++0xB
|
|
line.long 0x0 "INTR_DPSLP,DeepSleep interrupt"
|
|
hexmask.long.word 0x0 0.--15. 1. "COMP1,This interrupt cause field is activated (HW sets the field to '1') when a comparator 1 event is generated (DeepSleep counter 'counter_int_lf[31:0]' becomes greater or equal to COMP1.INT[31:0])."
|
|
line.long 0x4 "INTR_DPSLP_SET,DeepSleep interrupt set"
|
|
hexmask.long.word 0x4 0.--15. 1. "COMP1,SW writes a '1' to this field to set the corresponding field in the INTR register."
|
|
line.long 0x8 "INTR_DPSLP_MASK,DeepSleep interrupt mask"
|
|
hexmask.long.word 0x8 0.--15. 1. "COMP1,Mask bit for corresponding field in the INTR register."
|
|
rgroup.long 0x71C++0x3
|
|
line.long 0x0 "INTR_DPSLP_MASKED,DeepSleep interrupt masked"
|
|
hexmask.long.word 0x0 0.--15. 1. "COMP1,Logical and of corresponding INTR and INTR_MASK fields."
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x403F0800 ad:0x403F0820 ad:0x403F0840 ad:0x403F0860 ad:0x403F0880 ad:0x403F08A0 ad:0x403F08C0 ad:0x403F08E0 ad:0x403F0900 ad:0x403F0920 ad:0x403F0940 ad:0x403F0960 ad:0x403F0980 ad:0x403F09A0 ad:0x403F09C0 ad:0x403F09E0)
|
|
tree "COMP_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0xB
|
|
line.long 0x0 "COMP_CTL,Comparator control"
|
|
bitfld.long 0x0 31. "ENABLED,Comparator structure enable:" "0,1"
|
|
bitfld.long 0x0 16. "TR_OUT_EDGE,Specifies the 'tr_out' output trigger:" "0,1"
|
|
bitfld.long 0x0 1. "COMP1_EN,DeepSleep comparator (COMP1) enable:" "0,1"
|
|
bitfld.long 0x0 0. "COMP0_EN,Active comparator (COMP0) enable:" "0,1"
|
|
line.long 0x4 "COMP0,Comparator 0 (Active functionality)"
|
|
hexmask.long 0x4 0.--31. 1. "INT32,This value is a 32-bit unsigned integer in the range [0 2^32-1]. The comparator 'comp0_out' output is activated when the Active counter 'counter_int[31:0]' becomes greater or equal to COMP0."
|
|
line.long 0x8 "COMP1,Comparator 1 (DeepSleep functionality)"
|
|
hexmask.long 0x8 0.--31. 1. "INT32,This value is a 32-bit unsigned integer in the range [0 2^32-1]. The comparator 'comp1_out_lf' output is activated when the DeepSleep counter 'counter_int_lf[31:0]' becomes greater or equal to COMP1."
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "FAULT (Fault Structures)"
|
|
base ad:0x40210000
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40210000 ad:0x40210100 ad:0x40210200 ad:0x40210300)
|
|
tree "STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTL,Fault control"
|
|
bitfld.long 0x0 2. "RESET_REQ_EN,Reset request enable:" "0,1"
|
|
bitfld.long 0x0 1. "OUT_EN,IO output signal enable:" "0,1"
|
|
bitfld.long 0x0 0. "TR_EN,Trigger output enable:" "0,1"
|
|
group.long ($2+0xC)++0x3
|
|
line.long 0x0 "STATUS,Fault status"
|
|
bitfld.long 0x0 31. "VALID,Valid indication:" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "IDX,The fault source index for which fault information is captured in DATA0 through DATA3. The fault information is fault source specific and described below."
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x10)++0x3
|
|
line.long 0x0 "DATA[$1],Fault data"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Captured fault source data."
|
|
repeat.end
|
|
rgroup.long ($2+0x40)++0xB
|
|
line.long 0x0 "PENDING0,Fault pending 0"
|
|
hexmask.long 0x0 0.--31. 1. "SOURCE,This field specifies the following sources:"
|
|
line.long 0x4 "PENDING1,Fault pending 1"
|
|
hexmask.long 0x4 0.--31. 1. "SOURCE,This field specifies the following sources:"
|
|
line.long 0x8 "PENDING2,Fault pending 2"
|
|
hexmask.long 0x8 0.--31. 1. "SOURCE,This field specifies the following sources:"
|
|
group.long ($2+0x50)++0xB
|
|
line.long 0x0 "MASK0,Fault mask 0"
|
|
hexmask.long 0x0 0.--31. 1. "SOURCE,Fault source enables:"
|
|
line.long 0x4 "MASK1,Fault mask 1"
|
|
hexmask.long 0x4 0.--31. 1. "SOURCE,Fault source enables:"
|
|
line.long 0x8 "MASK2,Fault mask 2"
|
|
hexmask.long 0x8 0.--31. 1. "SOURCE,Fault source enables:"
|
|
group.long ($2+0xC0)++0xB
|
|
line.long 0x0 "INTR,Interrupt"
|
|
bitfld.long 0x0 0. "FAULT,This interrupt cause field is activated (HW sets the field to '1') when an enabled (MASK0/MASK1/MASK2) pending fault source is captured:" "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set"
|
|
bitfld.long 0x4 0. "FAULT,SW writes a '1' to this field to set the corresponding field in the INTR register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x8 0. "FAULT,Mask bit for corresponding field in the INTR register." "0,1"
|
|
rgroup.long ($2+0xCC)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 0. "FAULT,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "FLASHC (Flash Controller)"
|
|
base ad:0x0
|
|
tree "FLASHC"
|
|
base ad:0x40240000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "FLASH_CTL,Control"
|
|
bitfld.long 0x0 24. "WORK_SEQ_RD_EN,Enable sequential read mode for Work Flash for read accesses on the AXI port." "0: Sequential read mode for Work Flash is disabled,1: Sequential read mode for Work Flash is enabled"
|
|
bitfld.long 0x0 22. "WORK_ERR_SILENT,Specifies bus transfer behavior for a non-recoverable error on the FLASH macro work interface (either a non-correctable ECC error or a FLASH macro work interface internal error):" "0: Bus transfer has a bus error,1: Bus transfer does NOT have a bus error; i"
|
|
newline
|
|
bitfld.long 0x0 21. "WORK_ECC_INJ_EN,N/A" "0,1"
|
|
bitfld.long 0x0 20. "WORK_ECC_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "MAIN_ERR_SILENT,Specifies bus transfer behavior for a non-recoverable error on the FLASH macro main interface (either a non-correctable ECC error or a FLASH macro main interface internal error):" "0: Bus transfer has a bus error,1: Bus transfer does NOT have a bus error; i"
|
|
bitfld.long 0x0 17. "MAIN_ECC_INJ_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MAIN_ECC_EN,N/A" "0,1"
|
|
bitfld.long 0x0 13. "WORK_BANK_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "MAIN_BANK_MODE,N/A" "0,1"
|
|
bitfld.long 0x0 9. "WORK_MAP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "MAIN_MAP,N/A" "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "WS,FLASH macro wait states (same for main and work interfaces):"
|
|
line.long 0x4 "FLASH_PWR_CTL,Flash power control"
|
|
bitfld.long 0x4 1. "ENABLE_HV,Controls 'enable_hv' pin of the Flash memory." "0,1"
|
|
bitfld.long 0x4 0. "ENABLE,Controls 'enable' pin of the Flash memory." "0,1"
|
|
line.long 0x8 "FLASH_CMD,Command"
|
|
bitfld.long 0x8 1. "BUFF_INV,Invalidation of ALL buffers (does not invalidate the caches). SW writes a '1' to clear the buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and.." "0,1"
|
|
bitfld.long 0x8 0. "INV,Invalidation of ALL caches (for CM0+) and ALL buffers. SW writes a '1' to clear the caches. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast.." "0,1"
|
|
group.long 0x2A0++0x3
|
|
line.long 0x0 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PARITY,N/A"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "WORD_ADDR,N/A"
|
|
group.long 0x2B0++0x7
|
|
line.long 0x0 "FM_SRAM_ECC_CTL0,eCT Flash SRAM ECC control 0"
|
|
hexmask.long 0x0 0.--31. 1. "ECC_INJ_DATA,32-bit data for ECC error injection test of eCT Flash SRAM ECC logic."
|
|
line.long 0x4 "FM_SRAM_ECC_CTL1,eCT Flash SRAM ECC control 1"
|
|
hexmask.long.byte 0x4 0.--6. 1. "ECC_INJ_PARITY,7-bit parity for ECC error injection test of eCT Flash SRAM ECC logic."
|
|
rgroup.long 0x2B8++0x3
|
|
line.long 0x0 "FM_SRAM_ECC_CTL2,eCT Flash SRAM ECC control 2"
|
|
hexmask.long 0x0 0.--31. 1. "CORRECTED_DATA,32-bit corrected data output of the ECC syndrome logic."
|
|
group.long 0x2BC++0x3
|
|
line.long 0x0 "FM_SRAM_ECC_CTL3,eCT Flash SRAM ECC control 3"
|
|
rbitfld.long 0x0 8. "ECC_TEST_FAIL,Status of ECC test." "0: ECC was performed,1: ECC test failed because eCT Flash macro is busy.."
|
|
bitfld.long 0x0 4. "ECC_INJ_EN,eCT Flash SRAM ECC error injection test enable. Follow the steps below for ECC logic test:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ECC_ENABLE,ECC generation/check enable for eCT Flash SRAM memory." "0,1"
|
|
group.long 0x400++0xB
|
|
line.long 0x0 "CM0_CA_CTL0,CM0+ cache control"
|
|
bitfld.long 0x0 31. "CA_EN,Cache enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 30. "PREF_EN,Prefetch enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "SET_ADDR,Specifies the cache set for which cache information is provided in CM0_CA_STATUS0/1/2." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--17. "WAY,Specifies the cache way for which cache information is provided in CM0_CA_STATUS0/1/2." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 1. "RAM_ECC_INJ_EN,Enable error injection for cache." "0,1"
|
|
bitfld.long 0x0 0. "RAM_ECC_EN,Enable ECC checking for cache accesses:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "CM0_CA_CTL1,CM0+ cache control"
|
|
hexmask.long.word 0x4 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x4 0.--1. "PWR_MODE,Specifies power mode for CM0 cache." "0: Power OFF the CM0 cache SRAM.,1: Undefined,2: Put CM0 cache SRAM in retained mode.,3: Enable/Turn ON the CM0 cache SRAM."
|
|
line.long 0x8 "CM0_CA_CTL2,CM0+ cache control"
|
|
hexmask.long.word 0x8 0.--9. 1. "PWRUP_DELAY,Number clock cycles delay needed after power domain power up"
|
|
rgroup.long 0x440++0xB
|
|
line.long 0x0 "CM0_CA_STATUS0,CM0+ cache status 0"
|
|
hexmask.long 0x0 0.--31. 1. "VALID32,Sixteen valid bits of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR."
|
|
line.long 0x4 "CM0_CA_STATUS1,CM0+ cache status 1"
|
|
hexmask.long 0x4 0.--31. 1. "TAG,Cache line address of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR."
|
|
line.long 0x8 "CM0_CA_STATUS2,CM0+ cache status 2"
|
|
hexmask.long.byte 0x8 0.--5. 1. "LRU,Six bit LRU representation of the cache set specified by CM0_CA_CTL.SET_ADDR. The encoding of the field is as follows ('X_LRU_Y' indicates that way X is Less Recently Used than way Y):"
|
|
group.long 0x460++0x3
|
|
line.long 0x0 "CM0_STATUS,CM0+ interface status"
|
|
bitfld.long 0x0 1. "WORK_INTERNAL_ERR,See CM0_STATUS.MAIN_INTERNAL_ERROR." "0,1"
|
|
bitfld.long 0x0 0. "MAIN_INTERNAL_ERR,Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM0+ (or debug access via SYS_AP/CM0_AP) access." "0,1"
|
|
group.long 0x4E0++0x3
|
|
line.long 0x0 "CM7_0_STATUS,CM7 #0 interface status"
|
|
bitfld.long 0x0 1. "WORK_INTERNAL_ERR,See CM7_0_STATUS.MAIN_INTERNAL_ERROR." "0,1"
|
|
bitfld.long 0x0 0. "MAIN_INTERNAL_ERR,Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM7_0 (or debug access via SYS_AP/CM7_0_AP) access." "0,1"
|
|
group.long 0x560++0xB
|
|
line.long 0x0 "CM7_1_STATUS,CM7 #1 interface status"
|
|
bitfld.long 0x0 1. "WORK_INTERNAL_ERR,See CM7_1_STATUS.MAIN_INTERNAL_ERROR." "0,1"
|
|
bitfld.long 0x0 0. "MAIN_INTERNAL_ERR,Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM7_1 (or debug access via SYS_AP/CM7_1_AP) access." "0,1"
|
|
line.long 0x4 "CM7_2_STATUS,CM7 #2 interface status"
|
|
bitfld.long 0x4 1. "WORK_INTERNAL_ERR,See CM7_2_STATUS.MAIN_INTERNAL_ERROR." "0,1"
|
|
bitfld.long 0x4 0. "MAIN_INTERNAL_ERR,Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM7_2 (or debug access via SYS_AP/CM7_2_AP) access." "0,1"
|
|
line.long 0x8 "CM7_3_STATUS,CM7 #3 interface status"
|
|
bitfld.long 0x8 1. "WORK_INTERNAL_ERR,See CM7_2_STATUS.MAIN_INTERNAL_ERROR." "0,1"
|
|
bitfld.long 0x8 0. "MAIN_INTERNAL_ERR,Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM7_3 (or debug access via SYS_AP/CM7_3_AP) access." "0,1"
|
|
group.long 0x580++0x3
|
|
line.long 0x0 "CRYPTO_BUFF_CTL,Cryptography buffer control"
|
|
bitfld.long 0x0 30. "PREF_EN,Prefetch enable:" "0: Disabled,1: Enabled"
|
|
group.long 0x600++0x3
|
|
line.long 0x0 "DW0_BUFF_CTL,Datawire 0 buffer control"
|
|
bitfld.long 0x0 30. "PREF_EN,See CRYPTO_BUFF_CTL." "0,1"
|
|
group.long 0x680++0x3
|
|
line.long 0x0 "DW1_BUFF_CTL,Datawire 1 buffer control"
|
|
bitfld.long 0x0 30. "PREF_EN,See CRYPTO_BUFF_CTL." "0,1"
|
|
group.long 0x700++0x3
|
|
line.long 0x0 "DMAC_BUFF_CTL,DMA controller buffer control"
|
|
bitfld.long 0x0 30. "PREF_EN,See CRYPTO_BUFF_CTL." "0,1"
|
|
group.long 0x780++0x3
|
|
line.long 0x0 "SLOW0_MS_BUFF_CTL,Slow external master 0 buffer control"
|
|
bitfld.long 0x0 30. "PREF_EN,See CRYPTO_BUFF_CTL." "0,1"
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "SLOW1_MS_BUFF_CTL,Slow external master 1 buffer control"
|
|
bitfld.long 0x0 30. "PREF_EN,See CRYPTO_BUFF_CTL." "0,1"
|
|
tree "FM_CTL_ECT (Flash Macro Registers)"
|
|
base ad:0x4024F000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "FM_CTL,Flash Macro Control"
|
|
bitfld.long 0x0 31. "EMB_START,'0': not active" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "FM_MODE,Flash macro mode selection:"
|
|
line.long 0x4 "FM_CODE_MARGIN,Flash Macro Margin Mode on Code Flash"
|
|
bitfld.long 0x4 31. "MARGIN_MODE_EN,when set puts the s40ect Flash IP In Margin mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "MARGIN_MODE_RDREG_CHNG_EN,when set will also use the MARGIN_RDREG_TRIM from above. Default is not to use" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "MARGIN_PGM_ERS_B,0: ERS Margin is checked" "0: ERS Margin is checked,1: PGM Margin is checked"
|
|
newline
|
|
hexmask.long.byte 0x4 10.--15. 1. "MARGIN_RDREG_TRIM,rdreg_c trim to be used in Margin mode if enabled by MARGIN_MODE_RDREG_CHNG_EN"
|
|
newline
|
|
bitfld.long 0x4 9. "MARGIN_DCS_TRIM_EN,0: internal device defaults used from Margin reads reference current" "0: internal device defaults used from Margin reads..,1: MARGIN_DCS_TRIM configuration is used during.."
|
|
newline
|
|
hexmask.long.word 0x4 0.--8. 1. "MARGIN_DCS_TRIM,see above table to set the DCS reference current value to be used during Margin mode. (default set to 5uS = 0x143) which gives a Margin to the Erase side. 7uA would probably be used for Margin to the PGM side"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "FM_ADDR,Flash Macro Address"
|
|
hexmask.long 0x0 0.--31. 1. "FM_ADDR,Code or Work Flash Address to be used during write operations (PGM/ERS)"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "INTR,Interrupt"
|
|
bitfld.long 0x0 0. "INTR,Set to '1' when event is detected. Write INTR field with '1' to clear bit. Write INTR_SET field with '1' to set bit." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt Set"
|
|
bitfld.long 0x4 0. "INTR_SET,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt Mask"
|
|
bitfld.long 0x8 0. "INTR_MASK,Mask for corresponding field in the INTR register" "0,1"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt Masked"
|
|
bitfld.long 0x0 0. "INTR_MASKED,Logical and of corresponding request and mask fields." "0,1"
|
|
wgroup.long 0x30++0x3
|
|
line.long 0x0 "ECC_OVERRIDE,ECC Data In override information and control bits"
|
|
bitfld.long 0x0 31. "ECC_OVERRIDE_CODE,0: no override. Using internal ECC engine to calculate the ECC of the Code Flash" "0: no override,?"
|
|
newline
|
|
bitfld.long 0x0 30. "ECC_OVERRIDE_WORK,0: no override. Using internal ECC engine to calculate the ECC of the Work Flash" "0: no override,?"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "ECC_OVERRIDE_SYNDROME,The override syndrome itself to be used in case one of the enables are set. It will take [7:0] in the case of Code flash and [6:0] in the case of work flash to bypass the internal generated syndrome"
|
|
wgroup.long 0x40++0x3
|
|
line.long 0x0 "FM_DATA,Flash macro data_in[31 to 0] both Code and Work Flash"
|
|
hexmask.long 0x0 0.--31. 1. "FM_DATA,Pgm command data in going to the internal write buffer (WBUF)."
|
|
group.long 0x64++0x3
|
|
line.long 0x0 "BOOKMARK,Bookmark register - keeps the current FW HV seq"
|
|
hexmask.long 0x0 0.--31. 1. "BOOKMARK,Used by FW. Keeps the Current HV cycle sequence"
|
|
group.long 0x400++0x3
|
|
line.long 0x0 "MAIN_FLASH_SAFETY,Main (Code) Flash Security enable"
|
|
bitfld.long 0x0 0. "MAINFLASHWRITEENABLE,'0': Main Flash embedded operations are blocked" "0,1"
|
|
rgroup.long 0x404++0x3
|
|
line.long 0x0 "STATUS,Status read from Flash Macro"
|
|
bitfld.long 0x0 31. "BUSY,Whenever the device is in embedded mode the RDY goes low. Should be the same as c_interrupt pin of the IP (but inverted)" "0: rdy,1: busy in embedded"
|
|
newline
|
|
bitfld.long 0x0 30. "HANG,After embedded operation (pgm/erase) this flag will tell if it was successful or failed" "0: PASS,1: FAIL"
|
|
newline
|
|
bitfld.long 0x0 29. "NATIVE_POR,Indicates a Native Flash state (UV) or sorted one." "0: SORTED DEVICE,1: NATIVE"
|
|
newline
|
|
bitfld.long 0x0 28. "POR_2B_ECC_ERROR,Indicates an internal ECC error of 2b while downloading info in POR from NVM to VM." "0: No error,1: ECC 2b Error in POR"
|
|
newline
|
|
bitfld.long 0x0 27. "POR_1B_ECC_CORRECTED,Indicates internal ECC found 1b error while downloading info in POR from NVM to VM and fixed it." "0: No error,?"
|
|
newline
|
|
bitfld.long 0x0 6. "BLANK_CHCEK_PASS,Indicates the Blank check command result is PASS (Blank)" "0: Not Blank,1: Blank"
|
|
newline
|
|
bitfld.long 0x0 5. "BLANK_CHECK_WORK,Indicates if Blank Check mode is currently running on the work flash" "0: not running,1: running"
|
|
newline
|
|
bitfld.long 0x0 4. "ERS_SUSPEND,Indicates if Erase operation (Code/Work) is currently being suspended" "0: not suspended,1: suspended"
|
|
newline
|
|
bitfld.long 0x0 3. "ERASE_WORK,Indicates if active Erase operation to the Work flash is taking place" "0: not running,1: running"
|
|
newline
|
|
bitfld.long 0x0 2. "ERASE_CODE,Indicates if active Erase operation to the Code flash is taking place" "0: not running,1: running"
|
|
newline
|
|
bitfld.long 0x0 1. "PGM_WORK,Indicates if active PGM operation to the Work flash is taking place" "0: not running,1: running"
|
|
newline
|
|
bitfld.long 0x0 0. "PGM_CODE,Indicates if active PGM operation to the Code flash is taking place" "0: not running,1: running"
|
|
group.long 0x500++0x3
|
|
line.long 0x0 "WORK_FLASH_SAFETY,Work Flash Security enable"
|
|
bitfld.long 0x0 0. "WORKFLASHWRITEENABLE,0: Work Flash embedded operations are blocked" "0: Work Flash embedded operations are blocked,1: Work Flash embedded operations are enabled"
|
|
tree.end
|
|
tree.end
|
|
tree "FLASHC1"
|
|
base ad:0x40250000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "FLASH_CTL,Control"
|
|
bitfld.long 0x0 24. "WORK_SEQ_RD_EN,Enable sequential read mode for Work Flash for read accesses on the AXI port." "0: Sequential read mode for Work Flash is disabled,1: Sequential read mode for Work Flash is enabled"
|
|
bitfld.long 0x0 22. "WORK_ERR_SILENT,Specifies bus transfer behavior for a non-recoverable error on the FLASH macro work interface (either a non-correctable ECC error or a FLASH macro work interface internal error):" "0: Bus transfer has a bus error,1: Bus transfer does NOT have a bus error; i"
|
|
newline
|
|
bitfld.long 0x0 21. "WORK_ECC_INJ_EN,N/A" "0,1"
|
|
bitfld.long 0x0 20. "WORK_ECC_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "MAIN_ERR_SILENT,Specifies bus transfer behavior for a non-recoverable error on the FLASH macro main interface (either a non-correctable ECC error or a FLASH macro main interface internal error):" "0: Bus transfer has a bus error,1: Bus transfer does NOT have a bus error; i"
|
|
bitfld.long 0x0 17. "MAIN_ECC_INJ_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MAIN_ECC_EN,N/A" "0,1"
|
|
bitfld.long 0x0 13. "WORK_BANK_MODE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "MAIN_BANK_MODE,N/A" "0,1"
|
|
bitfld.long 0x0 9. "WORK_MAP,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "MAIN_MAP,N/A" "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "WS,FLASH macro wait states (same for main and work interfaces):"
|
|
line.long 0x4 "FLASH_PWR_CTL,Flash power control"
|
|
bitfld.long 0x4 1. "ENABLE_HV,Controls 'enable_hv' pin of the Flash memory." "0,1"
|
|
bitfld.long 0x4 0. "ENABLE,Controls 'enable' pin of the Flash memory." "0,1"
|
|
line.long 0x8 "FLASH_CMD,Command"
|
|
bitfld.long 0x8 1. "BUFF_INV,Invalidation of ALL buffers (does not invalidate the caches). SW writes a '1' to clear the buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and.." "0,1"
|
|
bitfld.long 0x8 0. "INV,Invalidation of ALL caches (for CM0+) and ALL buffers. SW writes a '1' to clear the caches. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast.." "0,1"
|
|
group.long 0x2A0++0x3
|
|
line.long 0x0 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PARITY,N/A"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "WORD_ADDR,N/A"
|
|
group.long 0x2B0++0x7
|
|
line.long 0x0 "FM_SRAM_ECC_CTL0,eCT Flash SRAM ECC control 0"
|
|
hexmask.long 0x0 0.--31. 1. "ECC_INJ_DATA,32-bit data for ECC error injection test of eCT Flash SRAM ECC logic."
|
|
line.long 0x4 "FM_SRAM_ECC_CTL1,eCT Flash SRAM ECC control 1"
|
|
hexmask.long.byte 0x4 0.--6. 1. "ECC_INJ_PARITY,7-bit parity for ECC error injection test of eCT Flash SRAM ECC logic."
|
|
rgroup.long 0x2B8++0x3
|
|
line.long 0x0 "FM_SRAM_ECC_CTL2,eCT Flash SRAM ECC control 2"
|
|
hexmask.long 0x0 0.--31. 1. "CORRECTED_DATA,32-bit corrected data output of the ECC syndrome logic."
|
|
group.long 0x2BC++0x3
|
|
line.long 0x0 "FM_SRAM_ECC_CTL3,eCT Flash SRAM ECC control 3"
|
|
rbitfld.long 0x0 8. "ECC_TEST_FAIL,Status of ECC test." "0: ECC was performed,1: ECC test failed because eCT Flash macro is busy.."
|
|
bitfld.long 0x0 4. "ECC_INJ_EN,eCT Flash SRAM ECC error injection test enable. Follow the steps below for ECC logic test:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ECC_ENABLE,ECC generation/check enable for eCT Flash SRAM memory." "0,1"
|
|
group.long 0x400++0xB
|
|
line.long 0x0 "CM0_CA_CTL0,CM0+ cache control"
|
|
bitfld.long 0x0 31. "CA_EN,Cache enable:" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 30. "PREF_EN,Prefetch enable:" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "SET_ADDR,Specifies the cache set for which cache information is provided in CM0_CA_STATUS0/1/2." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--17. "WAY,Specifies the cache way for which cache information is provided in CM0_CA_STATUS0/1/2." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 1. "RAM_ECC_INJ_EN,Enable error injection for cache." "0,1"
|
|
bitfld.long 0x0 0. "RAM_ECC_EN,Enable ECC checking for cache accesses:" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "CM0_CA_CTL1,CM0+ cache control"
|
|
hexmask.long.word 0x4 16.--31. 1. "VECTKEYSTAT,Register key (to prevent accidental writes)."
|
|
bitfld.long 0x4 0.--1. "PWR_MODE,Specifies power mode for CM0 cache." "0: Power OFF the CM0 cache SRAM.,1: Undefined,2: Put CM0 cache SRAM in retained mode.,3: Enable/Turn ON the CM0 cache SRAM."
|
|
line.long 0x8 "CM0_CA_CTL2,CM0+ cache control"
|
|
hexmask.long.word 0x8 0.--9. 1. "PWRUP_DELAY,Number clock cycles delay needed after power domain power up"
|
|
rgroup.long 0x440++0xB
|
|
line.long 0x0 "CM0_CA_STATUS0,CM0+ cache status 0"
|
|
hexmask.long 0x0 0.--31. 1. "VALID32,Sixteen valid bits of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR."
|
|
line.long 0x4 "CM0_CA_STATUS1,CM0+ cache status 1"
|
|
hexmask.long 0x4 0.--31. 1. "TAG,Cache line address of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR."
|
|
line.long 0x8 "CM0_CA_STATUS2,CM0+ cache status 2"
|
|
hexmask.long.byte 0x8 0.--5. 1. "LRU,Six bit LRU representation of the cache set specified by CM0_CA_CTL.SET_ADDR. The encoding of the field is as follows ('X_LRU_Y' indicates that way X is Less Recently Used than way Y):"
|
|
group.long 0x460++0x3
|
|
line.long 0x0 "CM0_STATUS,CM0+ interface status"
|
|
bitfld.long 0x0 1. "WORK_INTERNAL_ERR,See CM0_STATUS.MAIN_INTERNAL_ERROR." "0,1"
|
|
bitfld.long 0x0 0. "MAIN_INTERNAL_ERR,Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM0+ (or debug access via SYS_AP/CM0_AP) access." "0,1"
|
|
group.long 0x4E0++0x3
|
|
line.long 0x0 "CM7_0_STATUS,CM7 #0 interface status"
|
|
bitfld.long 0x0 1. "WORK_INTERNAL_ERR,See CM7_0_STATUS.MAIN_INTERNAL_ERROR." "0,1"
|
|
bitfld.long 0x0 0. "MAIN_INTERNAL_ERR,Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM7_0 (or debug access via SYS_AP/CM7_0_AP) access." "0,1"
|
|
group.long 0x560++0xB
|
|
line.long 0x0 "CM7_1_STATUS,CM7 #1 interface status"
|
|
bitfld.long 0x0 1. "WORK_INTERNAL_ERR,See CM7_1_STATUS.MAIN_INTERNAL_ERROR." "0,1"
|
|
bitfld.long 0x0 0. "MAIN_INTERNAL_ERR,Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM7_1 (or debug access via SYS_AP/CM7_1_AP) access." "0,1"
|
|
line.long 0x4 "CM7_2_STATUS,CM7 #2 interface status"
|
|
bitfld.long 0x4 1. "WORK_INTERNAL_ERR,See CM7_2_STATUS.MAIN_INTERNAL_ERROR." "0,1"
|
|
bitfld.long 0x4 0. "MAIN_INTERNAL_ERR,Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM7_2 (or debug access via SYS_AP/CM7_2_AP) access." "0,1"
|
|
line.long 0x8 "CM7_3_STATUS,CM7 #3 interface status"
|
|
bitfld.long 0x8 1. "WORK_INTERNAL_ERR,See CM7_2_STATUS.MAIN_INTERNAL_ERROR." "0,1"
|
|
bitfld.long 0x8 0. "MAIN_INTERNAL_ERR,Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM7_3 (or debug access via SYS_AP/CM7_3_AP) access." "0,1"
|
|
group.long 0x580++0x3
|
|
line.long 0x0 "CRYPTO_BUFF_CTL,Cryptography buffer control"
|
|
bitfld.long 0x0 30. "PREF_EN,Prefetch enable:" "0: Disabled,1: Enabled"
|
|
group.long 0x600++0x3
|
|
line.long 0x0 "DW0_BUFF_CTL,Datawire 0 buffer control"
|
|
bitfld.long 0x0 30. "PREF_EN,See CRYPTO_BUFF_CTL." "0,1"
|
|
group.long 0x680++0x3
|
|
line.long 0x0 "DW1_BUFF_CTL,Datawire 1 buffer control"
|
|
bitfld.long 0x0 30. "PREF_EN,See CRYPTO_BUFF_CTL." "0,1"
|
|
group.long 0x700++0x3
|
|
line.long 0x0 "DMAC_BUFF_CTL,DMA controller buffer control"
|
|
bitfld.long 0x0 30. "PREF_EN,See CRYPTO_BUFF_CTL." "0,1"
|
|
group.long 0x780++0x3
|
|
line.long 0x0 "SLOW0_MS_BUFF_CTL,Slow external master 0 buffer control"
|
|
bitfld.long 0x0 30. "PREF_EN,See CRYPTO_BUFF_CTL." "0,1"
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "SLOW1_MS_BUFF_CTL,Slow external master 1 buffer control"
|
|
bitfld.long 0x0 30. "PREF_EN,See CRYPTO_BUFF_CTL." "0,1"
|
|
tree "FM_CTL_ECT (Flash Macro Registers)"
|
|
base ad:0x4025F000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "FM_CTL,Flash Macro Control"
|
|
bitfld.long 0x0 31. "EMB_START,'0': not active" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "FM_MODE,Flash macro mode selection:"
|
|
line.long 0x4 "FM_CODE_MARGIN,Flash Macro Margin Mode on Code Flash"
|
|
bitfld.long 0x4 31. "MARGIN_MODE_EN,when set puts the s40ect Flash IP In Margin mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "MARGIN_MODE_RDREG_CHNG_EN,when set will also use the MARGIN_RDREG_TRIM from above. Default is not to use" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "MARGIN_PGM_ERS_B,0: ERS Margin is checked" "0: ERS Margin is checked,1: PGM Margin is checked"
|
|
newline
|
|
hexmask.long.byte 0x4 10.--15. 1. "MARGIN_RDREG_TRIM,rdreg_c trim to be used in Margin mode if enabled by MARGIN_MODE_RDREG_CHNG_EN"
|
|
newline
|
|
bitfld.long 0x4 9. "MARGIN_DCS_TRIM_EN,0: internal device defaults used from Margin reads reference current" "0: internal device defaults used from Margin reads..,1: MARGIN_DCS_TRIM configuration is used during.."
|
|
newline
|
|
hexmask.long.word 0x4 0.--8. 1. "MARGIN_DCS_TRIM,see above table to set the DCS reference current value to be used during Margin mode. (default set to 5uS = 0x143) which gives a Margin to the Erase side. 7uA would probably be used for Margin to the PGM side"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "FM_ADDR,Flash Macro Address"
|
|
hexmask.long 0x0 0.--31. 1. "FM_ADDR,Code or Work Flash Address to be used during write operations (PGM/ERS)"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "INTR,Interrupt"
|
|
bitfld.long 0x0 0. "INTR,Set to '1' when event is detected. Write INTR field with '1' to clear bit. Write INTR_SET field with '1' to set bit." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt Set"
|
|
bitfld.long 0x4 0. "INTR_SET,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt Mask"
|
|
bitfld.long 0x8 0. "INTR_MASK,Mask for corresponding field in the INTR register" "0,1"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt Masked"
|
|
bitfld.long 0x0 0. "INTR_MASKED,Logical and of corresponding request and mask fields." "0,1"
|
|
wgroup.long 0x30++0x3
|
|
line.long 0x0 "ECC_OVERRIDE,ECC Data In override information and control bits"
|
|
bitfld.long 0x0 31. "ECC_OVERRIDE_CODE,0: no override. Using internal ECC engine to calculate the ECC of the Code Flash" "0: no override,?"
|
|
newline
|
|
bitfld.long 0x0 30. "ECC_OVERRIDE_WORK,0: no override. Using internal ECC engine to calculate the ECC of the Work Flash" "0: no override,?"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "ECC_OVERRIDE_SYNDROME,The override syndrome itself to be used in case one of the enables are set. It will take [7:0] in the case of Code flash and [6:0] in the case of work flash to bypass the internal generated syndrome"
|
|
wgroup.long 0x40++0x3
|
|
line.long 0x0 "FM_DATA,Flash macro data_in[31 to 0] both Code and Work Flash"
|
|
hexmask.long 0x0 0.--31. 1. "FM_DATA,Pgm command data in going to the internal write buffer (WBUF)."
|
|
group.long 0x64++0x3
|
|
line.long 0x0 "BOOKMARK,Bookmark register - keeps the current FW HV seq"
|
|
hexmask.long 0x0 0.--31. 1. "BOOKMARK,Used by FW. Keeps the Current HV cycle sequence"
|
|
group.long 0x400++0x3
|
|
line.long 0x0 "MAIN_FLASH_SAFETY,Main (Code) Flash Security enable"
|
|
bitfld.long 0x0 0. "MAINFLASHWRITEENABLE,'0': Main Flash embedded operations are blocked" "0,1"
|
|
rgroup.long 0x404++0x3
|
|
line.long 0x0 "STATUS,Status read from Flash Macro"
|
|
bitfld.long 0x0 31. "BUSY,Whenever the device is in embedded mode the RDY goes low. Should be the same as c_interrupt pin of the IP (but inverted)" "0: rdy,1: busy in embedded"
|
|
newline
|
|
bitfld.long 0x0 30. "HANG,After embedded operation (pgm/erase) this flag will tell if it was successful or failed" "0: PASS,1: FAIL"
|
|
newline
|
|
bitfld.long 0x0 29. "NATIVE_POR,Indicates a Native Flash state (UV) or sorted one." "0: SORTED DEVICE,1: NATIVE"
|
|
newline
|
|
bitfld.long 0x0 28. "POR_2B_ECC_ERROR,Indicates an internal ECC error of 2b while downloading info in POR from NVM to VM." "0: No error,1: ECC 2b Error in POR"
|
|
newline
|
|
bitfld.long 0x0 27. "POR_1B_ECC_CORRECTED,Indicates internal ECC found 1b error while downloading info in POR from NVM to VM and fixed it." "0: No error,?"
|
|
newline
|
|
bitfld.long 0x0 6. "BLANK_CHCEK_PASS,Indicates the Blank check command result is PASS (Blank)" "0: Not Blank,1: Blank"
|
|
newline
|
|
bitfld.long 0x0 5. "BLANK_CHECK_WORK,Indicates if Blank Check mode is currently running on the work flash" "0: not running,1: running"
|
|
newline
|
|
bitfld.long 0x0 4. "ERS_SUSPEND,Indicates if Erase operation (Code/Work) is currently being suspended" "0: not suspended,1: suspended"
|
|
newline
|
|
bitfld.long 0x0 3. "ERASE_WORK,Indicates if active Erase operation to the Work flash is taking place" "0: not running,1: running"
|
|
newline
|
|
bitfld.long 0x0 2. "ERASE_CODE,Indicates if active Erase operation to the Code flash is taking place" "0: not running,1: running"
|
|
newline
|
|
bitfld.long 0x0 1. "PGM_WORK,Indicates if active PGM operation to the Work flash is taking place" "0: not running,1: running"
|
|
newline
|
|
bitfld.long 0x0 0. "PGM_CODE,Indicates if active PGM operation to the Code flash is taking place" "0: not running,1: running"
|
|
group.long 0x500++0x3
|
|
line.long 0x0 "WORK_FLASH_SAFETY,Work Flash Security enable"
|
|
bitfld.long 0x0 0. "WORKFLASHWRITEENABLE,0: Work Flash embedded operations are blocked" "0: Work Flash embedded operations are blocked,1: Work Flash embedded operations are enabled"
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree "FLEXRAY (FlexRay Bus Interface)"
|
|
base ad:0x40560000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CTL,Control Register"
|
|
bitfld.long 0x0 31. "ENABLED,This bit enables the operation of this IP." "0: N/A,1: N/A"
|
|
line.long 0x4 "DMA_CTL,DMA Control Register"
|
|
bitfld.long 0x4 2. "ODMAFFE,OBF DMA FIFO enable" "0: N/A,1: N/A"
|
|
bitfld.long 0x4 1. "ODMATOE,OBF DMA trigger output enable" "0: N/A,1: N/A"
|
|
newline
|
|
bitfld.long 0x4 0. "IDMATOE,IBF DMA trigger output enable" "0: N/A,1: N/A"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "TEST1,Test Register 1"
|
|
hexmask.long.byte 0x0 28.--31. 1. "CERB,N/A"
|
|
hexmask.long.byte 0x0 24.--27. 1. "CERA,N/A"
|
|
newline
|
|
bitfld.long 0x0 21. "TXENB,Control of Channel B Transmit Enable Pin" "0: eray_txen2_n pin drives a '0',1: eray_txen2_n pin drives a '1'"
|
|
bitfld.long 0x0 20. "TXENA,Control of Channel A Transmit Enable Pin" "0: eray_txen1_n pin drives a '0',1: eray_txen1_n pin drives a '1'"
|
|
newline
|
|
bitfld.long 0x0 19. "TXB,Control of Channel B Transmit Pin" "0: eray_txd2 pin drives a '0',1: eray_txd2 pin drives a '1'"
|
|
bitfld.long 0x0 18. "TXA,Control of Channel A Transmit Pin" "0: eray_txd1 pin drives a '0',1: eray_txd1 pin drives a '1'"
|
|
newline
|
|
rbitfld.long 0x0 17. "RXB,Monitor Channel B Receive Pin" "0: eray_rxd2 = '0',1: eray_rxd2 = '1'"
|
|
rbitfld.long 0x0 16. "RXA,Monitor Channel A Receive Pin" "0: eray_rxd1 = '0',1: eray_rxd1 = '1'"
|
|
newline
|
|
rbitfld.long 0x0 9. "AOB,Activity on B" "0: No activity detected,1: Activity detected"
|
|
rbitfld.long 0x0 8. "AOA,Activity on A" "0: No activity detected,1: Activity detected"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "TMC,Test Multiplexer Control" "0: N/A,1: RAM Test Mode,2: N/A,3: N/A"
|
|
bitfld.long 0x0 1. "ELBE,External Loop Back Enable" "0: Internal Loop Back,1: External Loop Back"
|
|
newline
|
|
bitfld.long 0x0 0. "WRTEN,Write Test Register Enable" "0: Write access to test registers disabled,1: Write access to test registers enabled"
|
|
line.long 0x4 "TEST2,Test Register 2"
|
|
rbitfld.long 0x4 15. "RDPB,Read Parity Bit" "0,1"
|
|
bitfld.long 0x4 14. "WRPB,Write Parity Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "SSEL,Segment Select" "0: access to RAM bytes 0000h to 03FFh enabled,1: access to RAM bytes 0400h to 07FFh enabled,2: N/A,3: N/A,4: N/A,5: N/A,6: N/A,7: N/A"
|
|
bitfld.long 0x4 0.--2. "RS,RAM Select" "0: Input Buffer RAM 1,1: Input Buffer RAM 2,2: N/A,3: N/A,4: N/A,5: N/A,6: N/A,?"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "LCK,Lock Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "TMK,Test Mode Key"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CLK,Configuration Lock Key"
|
|
group.long 0x20++0x2F
|
|
line.long 0x0 "EIR,Error Interrupt Register"
|
|
bitfld.long 0x0 26. "TABB,Transmission Across Boundary Channel B" "0: No transmission across slot boundary detected on..,1: Transmission across slot boundary detected on.."
|
|
bitfld.long 0x0 25. "LTVB,Latest Transmit Violation Channel B" "0: No latest transmit violation detected on channel B,1: Latest transmit violation detected on channel B"
|
|
newline
|
|
bitfld.long 0x0 24. "EDB,Error Detected on Channel B" "0: No error detected on channel B,1: Error detected on channel B"
|
|
bitfld.long 0x0 18. "TABA,Transmission Across Boundary Channel A" "0: No transmission across slot boundary detected on..,1: Transmission across slot boundary detected on.."
|
|
newline
|
|
bitfld.long 0x0 17. "LTVA,Latest Transmit Violation Channel A" "0: No latest transmit violation detected on channel A,1: Latest transmit violation detected on channel A"
|
|
bitfld.long 0x0 16. "EDA,Error Detected on Channel A" "0: No error detected on channel A,1: Error detected on channel A"
|
|
newline
|
|
bitfld.long 0x0 11. "MHF,Message Handler Constraints Flag" "0: No Message Handler failure detected,1: Message Handler failure detected"
|
|
bitfld.long 0x0 10. "IOBA,Illegal Output buffer Access" "0: No illegal Host access to Output Buffer occurred,1: Illegal Host access to Output Buffer occurred"
|
|
newline
|
|
bitfld.long 0x0 9. "IIBA,Illegal Input Buffer Access" "0: No illegal Host access to Input Buffer occurred,1: Illegal Host access to Input Buffer occurred"
|
|
bitfld.long 0x0 8. "EFA,Empty FIFO Access" "0: No Host access to empty FIFO occurred,1: Host access to empty FIFO occurred"
|
|
newline
|
|
bitfld.long 0x0 7. "RFO,Receive FIFO Overrun" "0: No receive FIFO overrun detected,1: A receive FIFO overrun has been detected"
|
|
bitfld.long 0x0 6. "PERR,Parity Error" "0: No parity error detected,1: Parity error detected"
|
|
newline
|
|
bitfld.long 0x0 5. "CCL,CHI Command Locked" "0: CHI command accepted,1: CHI command not accepted"
|
|
bitfld.long 0x0 4. "CCF,Clock Correction Failure" "0: No clock correction error,1: Clock correction failed"
|
|
newline
|
|
bitfld.long 0x0 3. "SFO,Sync Frame Overflow" "0: Number of received sync frames <= GTUC2,1: More sync frames received than configured by GTUC2"
|
|
bitfld.long 0x0 2. "SFBM,Sync Frames Below Minimum" "0: Sync node: 1 or more sync frames received,1: Less than the required minimum of sync frames.."
|
|
newline
|
|
bitfld.long 0x0 1. "CNA,Command Not Accepted" "0: CHI command accepted,1: CHI command not accepted"
|
|
bitfld.long 0x0 0. "PEMC,POC Error Mode Changed" "0: Error mode has not changed,1: Error mode has changed"
|
|
line.long 0x4 "SIR,Status Interrupt Register"
|
|
bitfld.long 0x4 25. "MTSB,MTS Received on Channel B (vSS!ValidMTSB)" "0: No MTS symbol received on channel B,1: MTS symbol received on channel B"
|
|
bitfld.long 0x4 24. "WUPB,Wakeup Pattern Channel B" "0: No wakeup pattern received on channel B,1: Wakeup pattern received on channel B"
|
|
newline
|
|
bitfld.long 0x4 17. "MTSA,MTS Received on Channel A (vSS!ValidMTSA)" "0: No MTS symbol received on channel A,1: MTS symbol received on channel A"
|
|
bitfld.long 0x4 16. "WUPA,Wakeup Pattern Channel A" "0: No wakeup pattern received on channel A,1: Wakeup pattern received on channel A"
|
|
newline
|
|
bitfld.long 0x4 15. "SDS,Start of Dynamic Segment" "0: Dynamic segment not yet started,1: Dynamic segment started"
|
|
bitfld.long 0x4 14. "MBSI,Message Buffer Status Interrupt" "0: No message buffer status change of message..,1: Message buffer status of at least one message.."
|
|
newline
|
|
bitfld.long 0x4 13. "SUCS,Startup Completed Successfully" "0: No startup completed successfully,1: Startup completed successfully"
|
|
bitfld.long 0x4 12. "SWE,Stop Watch Event" "0: No Stop Watch Event,1: Stop Watch Event occurred"
|
|
newline
|
|
bitfld.long 0x4 11. "TOBC,Transfer Output Buffer Completed" "0: No transfer completed,1: Transfer between Message RAM and Output Buffer.."
|
|
bitfld.long 0x4 10. "TIBC,Transfer Input Buffer Completed" "0: No transfer completed,1: Transfer between Input Buffer and Message RAM.."
|
|
newline
|
|
bitfld.long 0x4 9. "TI1,Timer Interrupt 1" "0: No Timer Interrupt 1,1: Timer Interrupt 1 occurred"
|
|
bitfld.long 0x4 8. "TI0,Timer Interrupt 0" "0: No Timer Interrupt 0,1: Timer Interrupt 0 occurred"
|
|
newline
|
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bitfld.long 0x4 7. "NMVC,Network Management Vector Changed" "0: No change in the network management vector,1: Network management vector changed"
|
|
bitfld.long 0x4 6. "RFCL,Receive FIFO Critical Level" "0: Receive FIFO below critical level,1: Receive FIFO critical level reached"
|
|
newline
|
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bitfld.long 0x4 5. "RFNE,Receive FIFO Not Empty" "0: Receive FIFO is empty,1: Receive FIFO is not empty"
|
|
bitfld.long 0x4 4. "RXI,Receive Interrupt" "0: No ND flag of a receive buffer with MBI = '1'..,1: At least one ND flag of a receive buffer with.."
|
|
newline
|
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bitfld.long 0x4 3. "TXI,Transmit Interrupt" "0: No frame transmitted from a transmit buffer with..,1: At least one frame was transmitted from a.."
|
|
bitfld.long 0x4 2. "CYCS,Cycle Start Interrupt" "0: No communication cycle started,1: Communication cycle started"
|
|
newline
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bitfld.long 0x4 1. "CAS,Collision Avoidance Symbol" "0: No bit pattern matching the CAS symbol received,1: Bit pattern matching the CAS symbol received"
|
|
bitfld.long 0x4 0. "WST,Wakeup Status" "0: Wakeup status unchanged,1: Wakeup status changed"
|
|
line.long 0x8 "EILS,Error Interrupt Line Select"
|
|
bitfld.long 0x8 26. "TABBL,Transmission Across Boundary Channel B Interrupt Line" "0,1"
|
|
bitfld.long 0x8 25. "LTVBL,Latest Transmit Violation Channel B Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 24. "EDBL,Error Detected on Channel B Interrupt Line" "0,1"
|
|
bitfld.long 0x8 18. "TABAL,Transmission Across Boundary Channel A Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 17. "LTVAL,Latest Transmit Violation Channel A Interrupt Line" "0,1"
|
|
bitfld.long 0x8 16. "EDAL,Error Detected on Channel A Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 11. "MHFL,Message Handler Constraints Flag Interrupt Line" "0,1"
|
|
bitfld.long 0x8 10. "IOBAL,Illegal Output Buffer Access Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 9. "IIBAL,Illegal Input Buffer Access Interrupt Line" "0,1"
|
|
bitfld.long 0x8 8. "EFAL,Empty FIFO Access Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 7. "RFOL,Receive FIFO Overrun Interrupt Line" "0,1"
|
|
bitfld.long 0x8 6. "PERRL,Parity Error Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 5. "CCLL,CHI Command Locked Interrupt Line" "0,1"
|
|
bitfld.long 0x8 4. "CCFL,Clock Correction Failure Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 3. "SFOL,Sync Frame Overflow Interrupt Line" "0,1"
|
|
bitfld.long 0x8 2. "SFBML,Sync Frames Below Minimum Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 1. "CNAL,Command Not Accepted Interrupt Line" "0,1"
|
|
bitfld.long 0x8 0. "PEMCL,POC Error Mode Changed Interrupt Line" "0,1"
|
|
line.long 0xC "SILS,Status Interrupt Line Select"
|
|
bitfld.long 0xC 25. "MTSBL,Media Access Test Symbol Channel B Interrupt Line" "0,1"
|
|
bitfld.long 0xC 24. "WUPBL,Wakeup Pattern Channel B Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0xC 17. "MTSAL,Media Access Test Symbol Channel A Interrupt Line" "0,1"
|
|
bitfld.long 0xC 16. "WUPAL,Wakeup Pattern Channel A Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0xC 15. "SDSL,Start of Dynamic Segment Interrupt Line" "0,1"
|
|
bitfld.long 0xC 14. "MBSIL,Message Buffer Status Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0xC 13. "SUCSL,Startup Completed Successfully Interrupt Line" "0,1"
|
|
bitfld.long 0xC 12. "SWEL,Stop Watch Event Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0xC 11. "TOBCL,Transfer Output Buffer Completed Interrupt Line" "0,1"
|
|
bitfld.long 0xC 10. "TIBCL,Transfer Input Buffer Completed Interrupt Line" "0,1"
|
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newline
|
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bitfld.long 0xC 9. "TI1L,Timer Interrupt 1 Line" "0,1"
|
|
bitfld.long 0xC 8. "TI0L,Timer Interrupt 0 Line" "0,1"
|
|
newline
|
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bitfld.long 0xC 7. "NMVCL,Network Management Vector Changed Interrupt Line" "0,1"
|
|
bitfld.long 0xC 6. "RFCLL,Receive FIFO Critical Level Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0xC 5. "RFNEL,Receive FIFO Not Empty Interrupt Line" "0,1"
|
|
bitfld.long 0xC 4. "RXIL,Receive Interrupt Line" "0,1"
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newline
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bitfld.long 0xC 3. "TXIL,Transmit Interrupt Line" "0,1"
|
|
bitfld.long 0xC 2. "CYCSL,Cycle Start Interrupt Line" "0,1"
|
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newline
|
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bitfld.long 0xC 1. "CASL,Collision Avoidance Symbol Interrupt Line" "0,1"
|
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bitfld.long 0xC 0. "WSTL,Wakeup Status Interrupt Line" "0,1"
|
|
line.long 0x10 "EIES,Error Interrupt Enable Set"
|
|
bitfld.long 0x10 26. "TABBE,Transmission Across Boundary Channel B Interrupt Enable" "0,1"
|
|
bitfld.long 0x10 25. "LTVBE,Latest Transmit Violation Channel B Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x10 24. "EDBE,Error Detected on Channel B Interrupt Enable" "0,1"
|
|
bitfld.long 0x10 18. "TABAE,Transmission Across Boundary Channel A Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x10 17. "LTVAE,Latest Transmit Violation Channel A Interrupt Enable" "0,1"
|
|
bitfld.long 0x10 16. "EDAE,Error Detected on Channel A Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x10 11. "MHFE,Message Handler Constraints Flag Interrupt Enable" "0,1"
|
|
bitfld.long 0x10 10. "IOBAE,Illegal Output Buffer Access Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x10 9. "IIBAE,Illegal Input Buffer Access Interrupt Enable" "0,1"
|
|
bitfld.long 0x10 8. "EFAE,Empty FIFO Access Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x10 7. "RFOE,Receive FIFO Overrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x10 6. "PERRE,Parity Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x10 5. "CCLE,CHI Command Locked Interrupt Enable" "0,1"
|
|
bitfld.long 0x10 4. "CCFE,Clock Correction Failure Interrupt Enable" "0,1"
|
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newline
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bitfld.long 0x10 3. "SFOE,Sync Frame Overflow Interrupt Enable" "0,1"
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bitfld.long 0x10 2. "SFBME,Sync Frames Below Minimum Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x10 1. "CNAE,Command Not Accepted Interrupt Enable" "0,1"
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|
bitfld.long 0x10 0. "PEMCE,POC Error Mode Changed Interrupt Enable" "0,1"
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line.long 0x14 "EIER,Error Interrupt Enable Reset"
|
|
bitfld.long 0x14 26. "TABBE,Transmission Across Boundary Channel B Interrupt Enable" "0,1"
|
|
bitfld.long 0x14 25. "LTVBE,Latest Transmit Violation Channel B Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x14 24. "EDBE,Error Detected on Channel B Interrupt Enable" "0,1"
|
|
bitfld.long 0x14 18. "TABAE,Transmission Across Boundary Channel A Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x14 17. "LTVAE,Latest Transmit Violation Channel A Interrupt Enable" "0,1"
|
|
bitfld.long 0x14 16. "EDAE,Error Detected on Channel A Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x14 11. "MHFE,Message Handler Constraints Flag Interrupt Enable" "0,1"
|
|
bitfld.long 0x14 10. "IOBAE,Illegal Output Buffer Access Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x14 9. "IIBAE,Illegal Input Buffer Access Interrupt Enable" "0,1"
|
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bitfld.long 0x14 8. "EFAE,Empty FIFO Access Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x14 7. "RFOE,Receive FIFO Overrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x14 6. "PERRE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x14 5. "CCLE,CHI Command Locked Interrupt Enable" "0,1"
|
|
bitfld.long 0x14 4. "CCFE,Clock Correction Failure Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x14 3. "SFOE,Sync Frame Overflow Interrupt Enable" "0,1"
|
|
bitfld.long 0x14 2. "SFBME,Sync Frames Below Minimum Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x14 1. "CNAE,Command Not Accepted Interrupt Enable" "0,1"
|
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bitfld.long 0x14 0. "PEMCE,POC Error Mode Changed Interrupt Enable" "0,1"
|
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line.long 0x18 "SIES,Status Interrupt Enable Set"
|
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bitfld.long 0x18 25. "MTSBE,MTS Received on Channel B Interrupt Enable" "0,1"
|
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bitfld.long 0x18 24. "WUPBE,Wakeup Pattern Channel B Interrupt Enable" "0,1"
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newline
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bitfld.long 0x18 17. "MTSAE,MTS Received on Channel A Interrupt Enable" "0,1"
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bitfld.long 0x18 16. "WUPAE,Wakeup Pattern Channel A Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x18 15. "SDSE,Start of Dynamic Segment Interrupt Enable" "0,1"
|
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bitfld.long 0x18 14. "MBSIE,Message Buffer Status Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x18 13. "SUCSE,Startup Completed Successfully Interrupt Enable" "0,1"
|
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bitfld.long 0x18 12. "SWEE,Stop Watch Event Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x18 11. "TOBCE,Transfer Output Buffer Completed Interrupt Enable" "0,1"
|
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bitfld.long 0x18 10. "TIBCE,Transfer Input Buffer Completed Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x18 9. "TI1E,Timer Interrupt 1 Enable" "0,1"
|
|
bitfld.long 0x18 8. "TI0E,Timer Interrupt 0 Enable" "0,1"
|
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newline
|
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bitfld.long 0x18 7. "NMVCE,Network Management Vector Changed Interrupt Enable" "0,1"
|
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bitfld.long 0x18 6. "RFCLE,Receive FIFO Critical Level Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x18 5. "RFNEE,Receive FIFO Not Empty Interrupt Enable" "0,1"
|
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bitfld.long 0x18 4. "RXIE,Receive Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x18 3. "TXIE,Transmit Interrupt Enable" "0,1"
|
|
bitfld.long 0x18 2. "CYCSE,Cycle Start Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x18 1. "CASE,Collision Avoidance Symbol Interrupt Enable" "0,1"
|
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bitfld.long 0x18 0. "WSTE,Wakeup Status Interrupt Enable" "0,1"
|
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line.long 0x1C "SIER,Status Interrupt Enable Reset"
|
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bitfld.long 0x1C 25. "MTSBE,MTS Received on Channel B Interrupt Enable" "0,1"
|
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bitfld.long 0x1C 24. "WUPBE,Wakeup Pattern Channel B Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x1C 17. "MTSAE,MTS Received on Channel A Interrupt Enable" "0,1"
|
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bitfld.long 0x1C 16. "WUPAE,Wakeup Pattern Channel A Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x1C 15. "SDSE,Start of Dynamic Segment Interrupt Enable" "0,1"
|
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bitfld.long 0x1C 14. "MBSIE,Message Buffer Status Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x1C 13. "SUCSE,Startup Completed Successfully Interrupt Enable" "0,1"
|
|
bitfld.long 0x1C 12. "SWEE,Stop Watch Event Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x1C 11. "TOBCE,Transfer Output Buffer Completed Interrupt Enable" "0,1"
|
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bitfld.long 0x1C 10. "TIBCE,Transfer Input Buffer Completed Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x1C 9. "TI1E,Timer Interrupt 1 Enable" "0,1"
|
|
bitfld.long 0x1C 8. "TI0E,Timer Interrupt 0 Enable" "0,1"
|
|
newline
|
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bitfld.long 0x1C 7. "NMVCE,Network Management Vector Changed Interrupt Enable" "0,1"
|
|
bitfld.long 0x1C 6. "RFCLE,Receive FIFO Critical Level Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x1C 5. "RFNEE,Receive FIFO Not Empty Interrupt Enable" "0,1"
|
|
bitfld.long 0x1C 4. "RXIE,Receive Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x1C 3. "TXIE,Transmit Interrupt Enable" "0,1"
|
|
bitfld.long 0x1C 2. "CYCSE,Cycle Start Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 1. "CASE,Collision Avoidance Symbol Interrupt Enable" "0,1"
|
|
bitfld.long 0x1C 0. "WSTE,Wakeup Status Interrupt Enable" "0,1"
|
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line.long 0x20 "ILE,Interrupt Line Enable"
|
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bitfld.long 0x20 1. "EINT1_,Enable Interrupt Line 1" "0: Interrupt line eray_int1 disabled,1: Interrupt line eray_int1 enabled"
|
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bitfld.long 0x20 0. "EINT0_,Enable Interrupt Line 0" "0: Interrupt line eray_int0 disabled,1: Interrupt line eray_int0 enabled"
|
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line.long 0x24 "T0C,Timer 0 Configuration"
|
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hexmask.long.word 0x24 16.--29. 1. "T0MO,Timer 0 Macrotick Offset"
|
|
hexmask.long.byte 0x24 8.--14. 1. "T0CC,Timer 0 Cycle Code"
|
|
newline
|
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bitfld.long 0x24 1. "T0MS,Timer 0 Mode Select" "0: Single-shot mode,1: Continuous mode"
|
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bitfld.long 0x24 0. "T0RC,Timer 0 Run Control" "0: Timer 0 halted,1: Timer 0 running"
|
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line.long 0x28 "T1C,Timer 1 Configuration"
|
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hexmask.long.word 0x28 16.--29. 1. "T1MC,Timer 1 Macrotick Count"
|
|
bitfld.long 0x28 1. "T1MS,Timer 1 Mode Select" "0: Single-shot mode,1: Continuous mode"
|
|
newline
|
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bitfld.long 0x28 0. "T1RC,Timer 1 Run Control" "0: Timer 1 halted,1: Timer 1 running"
|
|
line.long 0x2C "STPW1,Stop Watch Register 1"
|
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hexmask.long.word 0x2C 16.--29. 1. "SMTV,Stop Watch Captured Macrotick Value"
|
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hexmask.long.byte 0x2C 8.--13. 1. "SCCV,Stop Watch Captured Cycle Counter Value"
|
|
newline
|
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bitfld.long 0x2C 6. "EINT1,Enable Interrupt 1 Trigger" "0: Stop watch trigger by interrupt 1 disabled,1: Interrupt 1 event triggers stop watch"
|
|
bitfld.long 0x2C 5. "EINT0,Enable Interrupt 0 Trigger" "0: Stop watch trigger by interrupt 0 disabled,1: Interrupt 0 event triggers stop watch"
|
|
newline
|
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bitfld.long 0x2C 4. "EETP,Enable External Trigger Pin" "0: Stop watch trigger via pin eray_stpwt disabled,1: Edge on pin eray_stpwt triggers stop watch"
|
|
bitfld.long 0x2C 3. "SSWT,Software Stop Watch Trigger" "0: Software trigger reset,1: Stop watch activated by software trigger"
|
|
newline
|
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bitfld.long 0x2C 2. "EDGE,Stop Watch Trigger Edge Select" "0: Falling edge,1: Rising edge"
|
|
bitfld.long 0x2C 1. "SWMS,Stop Watch Mode Select" "0: Single-shot mode,1: Continuous mode"
|
|
newline
|
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bitfld.long 0x2C 0. "ESWT,Enable Stop Watch Trigger" "0: Stop watch trigger disabled,1: Stop watch trigger enabled"
|
|
rgroup.long 0x50++0x3
|
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line.long 0x0 "STPW2,Stop Watch Register 2"
|
|
hexmask.long.word 0x0 16.--26. 1. "SSCVB,Stop Watch Captured Slot Counter Value Channel B"
|
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hexmask.long.word 0x0 0.--10. 1. "SSCVA,Stop Watch Captured Slot Counter Value Channel A"
|
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group.long 0x80++0x1B
|
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line.long 0x0 "SUCC1,SUC Configuration Register 1"
|
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bitfld.long 0x0 27. "CCHB,Connected to Channel B (pChannels)" "0: Not connected to channel B,1: Node connected to channel B"
|
|
bitfld.long 0x0 26. "CCHA,Connected to Channel A (pChannels)" "0: Not connected to channel A,1: Node connected to channel A"
|
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newline
|
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bitfld.long 0x0 25. "MTSB_,Select Channel B for MTS Transmission" "0: Channel B disabled for MTS transmission,1: Channel B selected for MTS transmission"
|
|
bitfld.long 0x0 24. "MTSA_,Select Channel A for MTS Transmission" "0: Channel A disabled for MTS transmission,1: Channel A selected for MTS transmission"
|
|
newline
|
|
bitfld.long 0x0 23. "HCSE,Halt due to Clock Sync Error (pAllowHaltDueToClock)" "0: CC will enter / remain in NORMAL_PASSIVE,1: CC will enter HALT state"
|
|
bitfld.long 0x0 22. "TSM,Transmission Slot Mode (pSingleSlotEnabled)" "0: ALL Slot Mode,1: SINGLE Slot Mode"
|
|
newline
|
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bitfld.long 0x0 21. "WUCS,Wakeup Channel Select (pWakeupChannel)" "0: Send wakeup pattern on channel A,1: Send wakeup pattern on channel B"
|
|
hexmask.long.byte 0x0 16.--20. 1. "PTA,Passive to Active (pAllowPassiveToActive)"
|
|
newline
|
|
hexmask.long.byte 0x0 11.--15. 1. "CSA,Cold Start Attempts (gColdStartAttempts)"
|
|
bitfld.long 0x0 9. "TXSY,Transmit Sync Frame in Key Slot (pKeySlotUsedForSync)" "0: No sync frame transmission in key slot,1: Key slot used to transmit sync frame"
|
|
newline
|
|
bitfld.long 0x0 8. "TXST,Transmit Startup Frame in Key Slot (pKeySlotUsedForStartup)" "0: No startup frame transmission in key slot,1: Key slot used to transmit startup frame"
|
|
rbitfld.long 0x0 7. "PBSY,POC Busy" "0: POC not busy,1: POC is busy"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "CMD,N/A"
|
|
line.long 0x4 "SUCC2,SUC Configuration Register 2"
|
|
hexmask.long.byte 0x4 24.--27. 1. "LTN,Listen Timeout Noise (gListenNoise - 1)"
|
|
hexmask.long.tbyte 0x4 0.--20. 1. "LT,Listen Timeout (pdListenTimeout)"
|
|
line.long 0x8 "SUCC3,SUC Configuration Register 3"
|
|
hexmask.long.byte 0x8 4.--7. 1. "WCF,Maximum Without Clock Correction Fatal (gMaxWithoutClockCorrectionFatal)"
|
|
hexmask.long.byte 0x8 0.--3. 1. "WCP,Maximum Without Clock Correction Passive (gMaxWithoutClockCorrectionPassive)"
|
|
line.long 0xC "NEMC,NEM Configuration Register"
|
|
hexmask.long.byte 0xC 0.--3. 1. "NML,Network Management Vector Length (gNetworkManagementVectorLength)"
|
|
line.long 0x10 "PRTC1,PRT Configuration Register 1"
|
|
hexmask.long.byte 0x10 26.--31. 1. "RWP,Repetitions of Tx Wakeup Pattern (pWakeupPattern)"
|
|
hexmask.long.word 0x10 16.--24. 1. "RXW,Wakeup Symbol Receive Window Length (gdWakeupSymbolRxWindow)"
|
|
newline
|
|
bitfld.long 0x10 14.--15. "BRP,Baud Rate Prescaler (gdSampleClockPeriod pSamplesPerMicrotick)" "0: N/A,1: eray_sclk,2: eray_sclk,3: N/A"
|
|
bitfld.long 0x10 12.--13. "SPP,Strobe Point Position" "0: N/A,1: Sample 4,2: N/A,3: N/A"
|
|
newline
|
|
rbitfld.long 0x10 10. "CASM6,Part of CASM[6:0] but fixed to 1" "0,1"
|
|
hexmask.long.byte 0x10 4.--9. 1. "CASM,Collision Avoidance Symbol Max (gdCASRxLowMax)"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--3. 1. "TSST,Transmission Start Sequence Transmitter (gdTSSTransmitter)"
|
|
line.long 0x14 "PRTC2,PRT Configuration Register 2"
|
|
hexmask.long.byte 0x14 24.--29. 1. "TXL,Wakeup Symbol Transmit Low (gdWakeupSymbolTxLow)"
|
|
hexmask.long.byte 0x14 16.--23. 1. "TXI_,Wakeup Symbol Transmit Idle (gdWakeupSymbolTxIdle)"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--13. 1. "RXL,Wakeup Symbol Receive Low (gdWakeupSymbolRxLow)"
|
|
hexmask.long.byte 0x14 0.--5. 1. "RXI_,Wakeup Symbol Receive Idle (gdWakeupSymbolRxIdle)"
|
|
line.long 0x18 "MHDC,MHD Configuration Register"
|
|
hexmask.long.word 0x18 16.--28. 1. "SLT,Start of Latest Transmit (pLatestTx)"
|
|
hexmask.long.byte 0x18 0.--6. 1. "SFDL,Static Frame Data Length (gPayloadLengthStatic)"
|
|
group.long 0xA0++0x2B
|
|
line.long 0x0 "GTUC1,GTU Configuration Register 1"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "UT,Microtick per Cycle (pMicroPerCycle)"
|
|
line.long 0x4 "GTUC2,GTU Configuration Register 2"
|
|
hexmask.long.byte 0x4 16.--19. 1. "SNM,Sync Node Max (gSyncNodeMax)"
|
|
hexmask.long.word 0x4 0.--13. 1. "MPC,Macrotick Per Cycle (gMacroPerCycle)"
|
|
line.long 0x8 "GTUC3,GTU Configuration Register 3"
|
|
hexmask.long.byte 0x8 24.--30. 1. "MIOB,Macrotick Initial Offset Channel B (pMacroInitialOffset[B])"
|
|
hexmask.long.byte 0x8 16.--22. 1. "MIOA,Macrotick Initial Offset Channel A (pMacroInitialOffset[A])"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "UIOB,Microtick Initial Offset Channel B (pMicroInitialOffset[B])"
|
|
hexmask.long.byte 0x8 0.--7. 1. "UIOA,Microtick Initial Offset Channel A (pMicroInitialOffset[A])"
|
|
line.long 0xC "GTUC4,GTU Configuration Register 4"
|
|
hexmask.long.word 0xC 16.--29. 1. "OCS,Offset Correction Start (gOffsetCorrectionStart - 1)"
|
|
hexmask.long.word 0xC 0.--13. 1. "NIT,Network Idle Time Start (gMacroPerCycle - gdNIT - 1)"
|
|
line.long 0x10 "GTUC5,GTU Configuration Register 5"
|
|
hexmask.long.byte 0x10 24.--31. 1. "DEC,Decoding Correction (pDecodingCorrection)"
|
|
hexmask.long.byte 0x10 16.--20. 1. "CDD,Cluster Drift Damping (pClusterDriftDamping)"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "DCB,Delay Compensation Channel B (pDelayCompensation[B])"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DCA,Delay Compensation Channel A (pDelayCompensation[A])"
|
|
line.long 0x14 "GTUC6,GTU Configuration Register 6"
|
|
hexmask.long.word 0x14 16.--26. 1. "MOD,Maximum Oscillator Drift (pdMaxDrift)"
|
|
hexmask.long.word 0x14 0.--10. 1. "ASR,Accepted Startup Range (pdAcceptedStartupRange)"
|
|
line.long 0x18 "GTUC7,GTU Configuration Register 7"
|
|
hexmask.long.word 0x18 16.--25. 1. "NSS,Number of Static Slots (gNumberOfStaticSlots)"
|
|
hexmask.long.word 0x18 0.--9. 1. "SSL,Static Slot Length (gdStaticSlot)"
|
|
line.long 0x1C "GTUC8,GTU Configuration Register 8"
|
|
hexmask.long.word 0x1C 16.--28. 1. "NMS,Number of Minislots (gNumberOfMinislots)"
|
|
hexmask.long.byte 0x1C 0.--5. 1. "MSL,Minislot Length (gdMinislot)"
|
|
line.long 0x20 "GTUC9,GTU Configuration Register 9"
|
|
bitfld.long 0x20 16.--17. "DSI,Dynamic Slot Idle Phase (gdDynamicSlotIdlePhase)" "?,?,2: N/A,?"
|
|
hexmask.long.byte 0x20 8.--12. 1. "MAPO,Minislot Action Point Offset (gdMinislotActionPointOffset)"
|
|
newline
|
|
hexmask.long.byte 0x20 0.--5. 1. "APO,Action Point Offset (gdActionPointOffset)"
|
|
line.long 0x24 "GTUC10,GTU Configuration Register 10"
|
|
hexmask.long.word 0x24 16.--26. 1. "MRC,Maximum Rate Correction (pRateCorrectionOut)"
|
|
hexmask.long.word 0x24 0.--13. 1. "MOC,Maximum Offset Correction (pOffsetCorrectionOut)"
|
|
line.long 0x28 "GTUC11,GTU Configuration Register 11"
|
|
bitfld.long 0x28 24.--26. "ERC,External Rate Correction (pExternRateCorrection)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x28 16.--18. "EOC,External Offset Correction (pExternOffsetCorrection)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x28 8.--9. "ERCC,External Rate Correction Control (vExternRateControl)" "0: N/A,1: No external rate correction,2: N/A,3: N/A"
|
|
bitfld.long 0x28 0.--1. "EOCC,External Offset Correction Control (vExternOffsetControl)" "0: N/A,1: No external offset correction,2: N/A,3: N/A"
|
|
rgroup.long 0x100++0x7
|
|
line.long 0x0 "CCSV,CC Status Vector"
|
|
hexmask.long.byte 0x0 24.--29. 1. "PSL,POC Status Log"
|
|
hexmask.long.byte 0x0 19.--23. 1. "RCA,Remaining Coldstart Attempts (vRemainingColdstartAttempts)"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "WSV,N/A" "0: N/A,1: N/A,2: N/A,3: N/A,4: N/A,5: N/A,6: N/A,?"
|
|
bitfld.long 0x0 14. "CSI,Cold Start Inhibit (vColdStartInhibit)" "0: Cold starting of node enabled,1: Cold starting of node disabled"
|
|
newline
|
|
bitfld.long 0x0 13. "CSAI,Coldstart Abort Indicator" "0,1"
|
|
bitfld.long 0x0 12. "CSNI,Coldstart Noise Indicator (vPOC!ColdstartNoise)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "SLM,N/A" "0: N/A,?,2: N/A,3: N/A"
|
|
bitfld.long 0x0 7. "HRQ,Halt Request (vPOC!CHIHaltRequest)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FSI,Freeze Status Indicator (vPOC!Freeze)" "0,1"
|
|
hexmask.long.byte 0x0 0.--5. 1. "POCS,N/A"
|
|
line.long 0x4 "CCEV,CC Error Vector"
|
|
hexmask.long.byte 0x4 8.--12. 1. "PTAC,Passive to Active Count (vAllowPassiveToActive)"
|
|
bitfld.long 0x4 6.--7. "ERRM,N/A" "0: N/A,1: N/A,2: N/A,?"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "CCFC,Clock Correction Failed Counter (vClockCorrectionFailed)"
|
|
rgroup.long 0x110++0x17
|
|
line.long 0x0 "SCV,Slot Counter Value"
|
|
hexmask.long.word 0x0 16.--26. 1. "SCCB,Slot Counter Channel B (vSlotCounter[B])"
|
|
hexmask.long.word 0x0 0.--10. 1. "SCCA,Slot Counter Channel A (vSlotCounter[A])"
|
|
line.long 0x4 "MTCCV,Macrotick and Cycle Counter Value"
|
|
hexmask.long.byte 0x4 16.--21. 1. "CCV,Cycle Counter Value (vCycleCounter)"
|
|
hexmask.long.word 0x4 0.--13. 1. "MTV,Macrotick Value (vMacrotick)"
|
|
line.long 0x8 "RCV,Rate Correction Value"
|
|
hexmask.long.word 0x8 0.--11. 1. "RCV,Rate Correction Value (vRateCorrection)"
|
|
line.long 0xC "OCV,Offset Correction Value"
|
|
hexmask.long.tbyte 0xC 0.--18. 1. "OCV,Offset Correction Value (vOffsetCorrection)"
|
|
line.long 0x10 "SFS,Sync Frame Status"
|
|
bitfld.long 0x10 19. "RCLR,Rate Correction Limit Reached" "0: Rate correction below limit,1: Rate correction limit reached"
|
|
bitfld.long 0x10 18. "MRCS,Missing Rate Correction Signal" "0: Rate correction signal valid,1: Missing rate correction signal"
|
|
newline
|
|
bitfld.long 0x10 17. "OCLR,Offset Correction Limit Reached" "0: Offset correction below limit,1: Offset correction limit reached"
|
|
bitfld.long 0x10 16. "MOCS,Missing Offset Correction Signal" "0: Offset correction signal valid,1: Missing offset correction signal"
|
|
newline
|
|
hexmask.long.byte 0x10 12.--15. 1. "VSBO,Valid Sync Frames Channel B odd communication cycle"
|
|
hexmask.long.byte 0x10 8.--11. 1. "VSBE,Valid Sync Frames Channel B even communication cycle"
|
|
newline
|
|
hexmask.long.byte 0x10 4.--7. 1. "VSAO,Valid Sync Frames Channel A odd communication cycle"
|
|
hexmask.long.byte 0x10 0.--3. 1. "VSAE,Valid Sync Frames Channel A even communication cycle"
|
|
line.long 0x14 "SWNIT,Symbol Window and NIT Status"
|
|
bitfld.long 0x14 11. "SBNB,Slot Boundary Violation during NIT Channel B (vSS!BViolationB)" "0: No slot boundary violation detected,1: Slot boundary violation during NIT detected on.."
|
|
bitfld.long 0x14 10. "SENB,Syntax Error during NIT Channel B (vSS!SyntaxErrorB)" "0: No syntax error detected,1: Syntax error during NIT detected on channel B"
|
|
newline
|
|
bitfld.long 0x14 9. "SBNA,Slot Boundary Violation during NIT Channel A (vSS!BViolationA)" "0: No slot boundary violation detected,1: Slot boundary violation during NIT detected on.."
|
|
bitfld.long 0x14 8. "SENA,Syntax Error during NIT Channel A (vSS!SyntaxErrorA)" "0: No syntax error detected,1: Syntax error during NIT detected on channel A"
|
|
newline
|
|
bitfld.long 0x14 7. "MTSB__,MTS Received on Channel B (vSS!ValidMTSB)" "0: No MTS symbol received on channel B,1: MTS symbol received on channel B"
|
|
bitfld.long 0x14 6. "MTSA__,MTS Received on Channel A (vSS!ValidMTSA)" "0: No MTS symbol received on channel A,1: MTS symbol received on channel A"
|
|
newline
|
|
bitfld.long 0x14 5. "TCSB,Transmission Conflict in Symbol Window Channel B (vSS!TxConflictB)" "0: No transmission conflict detected,1: Transmission conflict in symbol window detected.."
|
|
bitfld.long 0x14 4. "SBSB,Slot Boundary Violation in Symbol Window Channel B (vSS!BViolationB)" "0: No slot boundary violation detected,1: Slot boundary violation during symbol window.."
|
|
newline
|
|
bitfld.long 0x14 3. "SESB,Syntax Error in Symbol Window Channel B (vSS!SyntaxErrorB)" "0: No syntax error detected,1: Syntax error during symbol window detected on.."
|
|
bitfld.long 0x14 2. "TCSA,Transmission Conflict in Symbol Window Channel A (vSS!TxConflictA)" "0: No transmission conflict detected,1: Transmission conflict in symbol window detected.."
|
|
newline
|
|
bitfld.long 0x14 1. "SBSA,Slot Boundary Violation in Symbol Window Channel A (vSS!BViolationA)" "0: No slot boundary violation detected,1: Slot boundary violation during symbol window.."
|
|
bitfld.long 0x14 0. "SESA,Syntax Error in Symbol Window Channel A (vSS!SyntaxErrorA)" "0: No syntax error detected,1: Syntax error during symbol window detected on.."
|
|
group.long 0x128++0x3
|
|
line.long 0x0 "ACS,Aggregated Channel Status"
|
|
bitfld.long 0x0 12. "SBVB,Slot Boundary Violation on Channel B (vSS!BViolationB)" "0: No slot boundary violation observed,1: Slot boundary violation"
|
|
bitfld.long 0x0 11. "CIB,Communication Indicator Channel B" "0: No valid frame,1: Valid frame"
|
|
newline
|
|
bitfld.long 0x0 10. "CEDB,Content Error Detected on Channel B (vSS!ContentErrorB)" "0: No frame with content error received,1: Frame"
|
|
bitfld.long 0x0 9. "SEDB,Syntax Error Detected on Channel B (vSS!SyntaxErrorB)" "0: No syntax error observed,1: Syntax error"
|
|
newline
|
|
bitfld.long 0x0 8. "VFRB_,Valid Frame Received on Channel B (vSS!ValidFrameB)" "0: No valid frame received,1: Valid frame"
|
|
bitfld.long 0x0 4. "SBVA,Slot Boundary Violation on Channel A (vSS!BViolationA)" "0: No slot boundary violation observed,1: Slot boundary violation"
|
|
newline
|
|
bitfld.long 0x0 3. "CIA,Communication Indicator Channel A" "0: No valid frame,1: Valid frame"
|
|
bitfld.long 0x0 2. "CEDA,Content Error Detected on Channel A (vSS!ContentErrorA)" "0: No frame with content error received,1: Frame"
|
|
newline
|
|
bitfld.long 0x0 1. "SEDA,Syntax Error Detected on Channel A (vSS!SyntaxErrorA)" "0: No syntax error observed,1: Syntax error"
|
|
bitfld.long 0x0 0. "VFRA_,Valid Frame Received on Channel A (vSS!ValidFrameA)" "0: No valid frame received,1: Valid frame"
|
|
repeat 15. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x130)++0x3
|
|
line.long 0x0 "ESID[$1],Even Sync ID [1...15]"
|
|
bitfld.long 0x0 15. "RXEB,Received / Configured Even Sync ID on Channel B" "0: No sync frame received on channel B / node not..,1: Sync frame received on channel B / node.."
|
|
bitfld.long 0x0 14. "RXEA,Received / Configured Even Sync ID on Channel A" "0: No sync frame received on channel A / node not..,1: Sync frame received on channel A / node.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--9. 1. "EID,Even Sync ID (vsSyncIDListA B even)"
|
|
repeat.end
|
|
repeat 15. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x170)++0x3
|
|
line.long 0x0 "OSID[$1],Odd Sync ID [1...15]"
|
|
bitfld.long 0x0 15. "RXOB,Received / Configured Odd Sync ID on Channel B" "0: No sync frame received on channel B / node not..,1: Sync frame received on channel B / node.."
|
|
bitfld.long 0x0 14. "RXOA,Received / Configured Odd Sync ID on Channel A" "0: No sync frame received on channel A / node not..,1: Sync frame received on channel A / node.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--9. 1. "OID,Odd Sync ID (vsSyncIDListA B odd)"
|
|
repeat.end
|
|
rgroup.long 0x1B0++0xB
|
|
line.long 0x0 "NMV1,Network Management Vector 1"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DATA3,Data3"
|
|
hexmask.long.byte 0x0 16.--23. 1. "DATA2,Data2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "DATA1,Data1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA0,Data0"
|
|
line.long 0x4 "NMV2,Network Management Vector 2"
|
|
hexmask.long.byte 0x4 24.--31. 1. "DATA7,Data7"
|
|
hexmask.long.byte 0x4 16.--23. 1. "DATA6,Data6"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "DATA5,Data5"
|
|
hexmask.long.byte 0x4 0.--7. 1. "DATA4,Data4"
|
|
line.long 0x8 "NMV3,Network Management Vector 3"
|
|
hexmask.long.byte 0x8 24.--31. 1. "DATA11,Data11"
|
|
hexmask.long.byte 0x8 16.--23. 1. "DATA10,Data10"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "DATA9,Data9"
|
|
hexmask.long.byte 0x8 0.--7. 1. "DATA8,Data8"
|
|
group.long 0x300++0x13
|
|
line.long 0x0 "MRC,Message RAM Configuration"
|
|
bitfld.long 0x0 26. "SPLM,Sync Frame Payload Multiplex" "0: Only message buffer 0 locked against..,1: Both message buffers 0 and 1 are locked against.."
|
|
bitfld.long 0x0 24.--25. "SEC,Secure Buffers" "0: Reconfiguration of message buffers enabled with..,1: Reconfiguration of message buffers with numbers..,2: N/A,3: N/A"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "LCB,Last Configured Buffer"
|
|
hexmask.long.byte 0x0 8.--15. 1. "FFB,First Buffer of FIFO"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "FDB,N/A"
|
|
line.long 0x4 "FRF,FIFO Rejection Filter"
|
|
bitfld.long 0x4 24. "RNF,Reject Null Frames" "0: Null frames are stored in the FIFO,1: Reject all null frames"
|
|
bitfld.long 0x4 23. "RSS,Reject in Static Segment" "0: FIFO also used for static segment,1: Reject messages in static segment"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--22. 1. "CYF,Cycle Counter Filter"
|
|
hexmask.long.word 0x4 2.--12. 1. "FID_,Frame ID Filter"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "CH,Channel Filter" "0: receive on both channels,1: receive only on channel B,2: N/A,3: N/A"
|
|
line.long 0x8 "FRFM,FIFO Rejection Filter Mask"
|
|
hexmask.long.word 0x8 2.--12. 1. "MFID,Mask Frame ID Filter"
|
|
line.long 0xC "FCL,FIFO Critical Level"
|
|
hexmask.long.byte 0xC 0.--7. 1. "CL,Critical Level"
|
|
line.long 0x10 "MHDS,Message Handler Status"
|
|
hexmask.long.byte 0x10 24.--30. 1. "MBU,Message Buffer Updated"
|
|
hexmask.long.byte 0x10 16.--22. 1. "MBT,Message Buffer Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--14. 1. "FMB,Faulty Message Buffer"
|
|
rbitfld.long 0x10 7. "CRAM,Clear all internal RAM's" "0: No execution of the CHI command CLEAR_RAMS,1: Execution of the CHI command CLEAR_RAMS ongoing"
|
|
newline
|
|
bitfld.long 0x10 6. "MFMB,Multiple Faulty Message Buffers detected" "0: No additional faulty message buffer,1: Another faulty message buffer was detected while.."
|
|
bitfld.long 0x10 5. "FMBD,Faulty Message Buffer Detected" "0: No faulty message buffer,1: Message buffer referenced by FMB[6:0] holds.."
|
|
newline
|
|
bitfld.long 0x10 4. "PTBF2,Parity Error Transient Buffer RAM B" "0: No parity error,1: Parity error occurred when reading Transient.."
|
|
bitfld.long 0x10 3. "PTBF1,Parity Error Transient Buffer RAM A" "0: No parity error,1: Parity error occurred when reading Transient.."
|
|
newline
|
|
bitfld.long 0x10 2. "PMR,Parity Error Message RAM" "0: No parity error,1: Parity error occurred when reading the Message RAM"
|
|
bitfld.long 0x10 1. "POBF,Parity Error Output Buffer RAM 1 2" "0: No parity error,1: Parity error occurred when reading Output Buffer.."
|
|
newline
|
|
bitfld.long 0x10 0. "PIBF,Parity Error Input Buffer RAM 1 2" "0: No parity error,1: Parity error occurred when reading Input Buffer.."
|
|
rgroup.long 0x314++0x7
|
|
line.long 0x0 "LDTS,Last Dynamic Transmit Slot"
|
|
hexmask.long.word 0x0 16.--26. 1. "LDTB,Last Dynamic Transmission Channel B"
|
|
hexmask.long.word 0x0 0.--10. 1. "LDTA,Last Dynamic Transmission Channel A"
|
|
line.long 0x4 "FSR,FIFO Status Register"
|
|
hexmask.long.byte 0x4 8.--15. 1. "RFFL,Receive FIFO Fill Level"
|
|
bitfld.long 0x4 2. "RFO_,Receive FIFO Overrun" "0: No receive FIFO overrun detected,1: A receive FIFO overrun has been detected"
|
|
newline
|
|
bitfld.long 0x4 1. "RFCL_,Receive FIFO Critical Level" "0: Receive FIFO below critical level,1: Receive FIFO critical level reached"
|
|
bitfld.long 0x4 0. "RFNE_,Receive FIFO Not Empty" "0: Receive FIFO is empty,1: Receive FIFO is not empty"
|
|
group.long 0x31C++0x3
|
|
line.long 0x0 "MHDF,Message Handler Constraints Flags"
|
|
bitfld.long 0x0 8. "WAHP,Write Attempt to Header Partition" "0: No write attempt to header partition,1: Write attempt to header partition"
|
|
bitfld.long 0x0 7. "TNSB,Transmission Not Started Channel B" "0: No transmission not started on channel B,1: Transmission not started on channel B"
|
|
newline
|
|
bitfld.long 0x0 6. "TNSA,Transmission Not Started Channel A" "0: No transmission not started on channel A,1: Transmission not started on channel A"
|
|
bitfld.long 0x0 5. "TBFB,Transient Buffer Access Failure B" "0: No TBF B access failure,1: TBF B access failure"
|
|
newline
|
|
bitfld.long 0x0 4. "TBFA,Transient Buffer Access Failure A" "0: No TBF A access failure,1: TBF A access failure"
|
|
bitfld.long 0x0 3. "FNFB,Find Sequence Not Finished Channel B" "0: No find sequence not finished for channel B,1: Find sequence not finished for channel B"
|
|
newline
|
|
bitfld.long 0x0 2. "FNFA,Find Sequence Not Finished Channel A" "0: No find sequence not finished for channel A,1: Find sequence not finished for channel A"
|
|
bitfld.long 0x0 1. "SNUB,Status Not Updated Channel B" "0: No overload condition occurred when updating MBS..,1: MBS for channel B not updated"
|
|
newline
|
|
bitfld.long 0x0 0. "SNUA,Status Not Updated Channel A" "0: No overload condition occurred when updating MBS..,1: MBS for channel A not updated"
|
|
rgroup.long 0x320++0x2F
|
|
line.long 0x0 "TXRQ1,Transmission Request 1"
|
|
hexmask.long 0x0 0.--31. 1. "TXR,Transmission Request"
|
|
line.long 0x4 "TXRQ2,Transmission Request 2"
|
|
hexmask.long 0x4 0.--31. 1. "TXR,Transmission Request"
|
|
line.long 0x8 "TXRQ3,Transmission Request 3"
|
|
hexmask.long 0x8 0.--31. 1. "TXR,Transmission Request"
|
|
line.long 0xC "TXRQ4,Transmission Request 4"
|
|
hexmask.long 0xC 0.--31. 1. "TXR,Transmission Request"
|
|
line.long 0x10 "NDAT1,New Data 1"
|
|
hexmask.long 0x10 0.--31. 1. "ND,New Data"
|
|
line.long 0x14 "NDAT2,New Data 2"
|
|
hexmask.long 0x14 0.--31. 1. "ND,New Data"
|
|
line.long 0x18 "NDAT3,New Data 3"
|
|
hexmask.long 0x18 0.--31. 1. "ND,New Data"
|
|
line.long 0x1C "NDAT4,New Data 4"
|
|
hexmask.long 0x1C 0.--31. 1. "ND,New Data"
|
|
line.long 0x20 "MBSC1,Message Buffer Status Changed 1"
|
|
hexmask.long 0x20 0.--31. 1. "MBC,Message Buffer Status Changed"
|
|
line.long 0x24 "MBSC2,Message Buffer Status Changed 2"
|
|
hexmask.long 0x24 0.--31. 1. "MBC,Message Buffer Status Changed"
|
|
line.long 0x28 "MBSC3,Message Buffer Status Changed 3"
|
|
hexmask.long 0x28 0.--31. 1. "MBC,Message Buffer Status Changed"
|
|
line.long 0x2C "MBSC4,Message Buffer Status Changed 4"
|
|
hexmask.long 0x2C 0.--31. 1. "MBC,Message Buffer Status Changed"
|
|
rgroup.long 0x3F0++0x7
|
|
line.long 0x0 "CREL,Core Release Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release"
|
|
hexmask.long.byte 0x0 20.--27. 1. "STEP,Step of Core Release"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,Design Time Stamp Year"
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,Design Time Stamp Month"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,Design Time Stamp Day"
|
|
line.long 0x4 "ENDN,Endian Register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value"
|
|
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x400)++0x3
|
|
line.long 0x0 "WRDS[$1],Write Data Section [1...64]"
|
|
hexmask.long 0x0 0.--31. 1. "MD,Message Data"
|
|
repeat.end
|
|
group.long 0x500++0xB
|
|
line.long 0x0 "WRHS1,Write Header Section 1"
|
|
bitfld.long 0x0 29. "MBI,Message Buffer Interrupt" "0: The corresponding message buffer interrupt is..,1: The corresponding message buffer interrupt is.."
|
|
bitfld.long 0x0 28. "TXM,Transmission Mode" "0: Continuous mode,1: Single-shot mode"
|
|
newline
|
|
bitfld.long 0x0 27. "PPIT,Payload Preamble Indicator Transmit" "0: Payload Preamble Indicator not set,1: Payload Preamble Indicator set"
|
|
bitfld.long 0x0 26. "CFG,Message Buffer Direction Configuration Bit" "0: The corresponding buffer is configured as..,1: The corresponding buffer is configured as.."
|
|
newline
|
|
bitfld.long 0x0 25. "CHB,Channel Filter Control B" "0: N/A,1: N/A"
|
|
bitfld.long 0x0 24. "CHA,Channel Filter Control A" "0: N/A,1: N/A"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "CYC,Cycle Code"
|
|
hexmask.long.word 0x0 0.--10. 1. "FID,Frame ID"
|
|
line.long 0x4 "WRHS2,Write Header Section 2"
|
|
hexmask.long.byte 0x4 16.--22. 1. "PLC,Payload Length Configured"
|
|
hexmask.long.word 0x4 0.--10. 1. "CRC,Header CRC (vRF!Header!HeaderCRC)"
|
|
line.long 0x8 "WRHS3,Write Header Section 3"
|
|
hexmask.long.word 0x8 0.--10. 1. "DP,Data Pointer"
|
|
group.long 0x510++0x7
|
|
line.long 0x0 "IBCM,Input Buffer Command Mask"
|
|
rbitfld.long 0x0 18. "STXRS,Set Transmission Request Shadow" "0: Reset TXR flag,1: Set TXR flag"
|
|
rbitfld.long 0x0 17. "LDSS,Load Data Section Shadow" "0: Data section is not updated,1: Data section selected for transfer from Input.."
|
|
newline
|
|
rbitfld.long 0x0 16. "LHSS,Load Header Section Shadow" "0: Header section is not updated,1: Header section selected for transfer from Input.."
|
|
bitfld.long 0x0 2. "STXRH,Set Transmission Request Host" "0: Reset TXR flag,1: Set TXR flag"
|
|
newline
|
|
bitfld.long 0x0 1. "LDSH,Load Data Section Host" "0: Data section is not updated,1: Data section selected for transfer from Input.."
|
|
bitfld.long 0x0 0. "LHSH,Load Header Section Host" "0: Header section is not updated,1: Header section selected for transfer from Input.."
|
|
line.long 0x4 "IBCR,Input Buffer Command Request"
|
|
rbitfld.long 0x4 31. "IBSYS,Input Buffer Busy Shadow" "0: Transfer between IBF Shadow and Message RAM..,1: Transfer between IBF Shadow and Message RAM in.."
|
|
hexmask.long.byte 0x4 16.--22. 1. "IBRS,Input Buffer Request Shadow"
|
|
newline
|
|
rbitfld.long 0x4 15. "IBSYH,Input Buffer Busy Host" "0: No request pending,1: Request while transfer between IBF Shadow and.."
|
|
hexmask.long.byte 0x4 0.--6. 1. "IBRH,Input Buffer Request Host"
|
|
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x600)++0x3
|
|
line.long 0x0 "RDDS[$1],Read Data Section [1...64]"
|
|
hexmask.long 0x0 0.--31. 1. "MD,Message Data"
|
|
repeat.end
|
|
rgroup.long 0x700++0xF
|
|
line.long 0x0 "RDHS1,Read Header Section 1"
|
|
bitfld.long 0x0 29. "MBI,Message Buffer Interrupt" "0,1"
|
|
bitfld.long 0x0 28. "TXM,Transmission Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "PPIT,Payload Preamble Indicator Transmit" "0,1"
|
|
bitfld.long 0x0 26. "CFG,Message Buffer Direction Configuration Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "CHB,Channel Filter Control B" "0,1"
|
|
bitfld.long 0x0 24. "CHA,Channel Filter Control A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "CYC,Cycle Code"
|
|
hexmask.long.word 0x0 0.--10. 1. "FID,Frame ID"
|
|
line.long 0x4 "RDHS2,Read Header Section 2"
|
|
hexmask.long.byte 0x4 24.--30. 1. "PLR,Payload Length Received (vRF!Header!Length)"
|
|
hexmask.long.byte 0x4 16.--22. 1. "PLC,Payload Length Configured"
|
|
newline
|
|
hexmask.long.word 0x4 0.--10. 1. "CRC,Header CRC (vRF!Header!HeaderCRC)"
|
|
line.long 0x8 "RDHS3,Read Header Section 3"
|
|
bitfld.long 0x8 29. "RES,N/A" "0,1"
|
|
bitfld.long 0x8 28. "PPI,Payload Preamble Indicator (vRF!Header!PPIndicator)" "0: The payload segment of the received frame does..,1: Static segment: Network management vector in the.."
|
|
newline
|
|
bitfld.long 0x8 27. "NFI,Null Frame Indicator (vRF!Header!NFIndicator)" "0: Up to now no data frame has been stored into the..,1: At least one data frame has been stored into the.."
|
|
bitfld.long 0x8 26. "SYN,Sync Frame Indicator (vRF!Header!SyFIndicator)" "0: The received frame is not a sync frame,1: The received frame is a sync frame"
|
|
newline
|
|
bitfld.long 0x8 25. "SFI,Startup Frame Indicator (vRF!Header!SuFIndicator)" "0: The received frame is not a startup frame,1: The received frame is a startup frame"
|
|
bitfld.long 0x8 24. "RCI,Received on Channel Indicator (vSS!Channel)" "0: Frame received on channel B,1: Frame received on channel A"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "RCC,Receive Cycle Count (vRF!Header!CycleCount)"
|
|
hexmask.long.word 0x8 0.--10. 1. "DP,Data Pointer"
|
|
line.long 0xC "MBS,Message Buffer Status"
|
|
bitfld.long 0xC 29. "RESS,N/A" "0,1"
|
|
bitfld.long 0xC 28. "PPIS,Payload Preamble Indicator Status (vRF!Header!PPIndicator)" "0: The payload segment of the received frame does..,1: Static segment: Network management vector at the.."
|
|
newline
|
|
bitfld.long 0xC 27. "NFIS,Null Frame Indicator Status (vRF!Header!NFIndicator)" "0: Received frame is a null frame,1: Received frame is not a null frame"
|
|
bitfld.long 0xC 26. "SYNS,Sync Frame Indicator Status (vRF!Header!SyFIndicator)" "0: No sync frame received,1: The received frame is a sync frame"
|
|
newline
|
|
bitfld.long 0xC 25. "SFIS,Startup Frame Indicator Status (vRF!Header!SuFIndicator)" "0: No startup frame received,1: The received frame is a startup frame"
|
|
bitfld.long 0xC 24. "RCIS,Received on Channel Indicator Status (vSS!Channel)" "0: Frame received on channel B,1: Frame received on channel A"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--21. 1. "CCS,Cycle Count Status"
|
|
bitfld.long 0xC 15. "FTB,Frame Transmitted on Channel B" "0: No data frame transmitted on channel B,1: Data frame transmitted on channel B"
|
|
newline
|
|
bitfld.long 0xC 14. "FTA,Frame Transmitted on Channel A" "0: No data frame transmitted on channel A,1: Data frame transmitted on channel A"
|
|
bitfld.long 0xC 12. "MLST,Message Lost" "0: No message lost,1: Unprocessed message was overwritten"
|
|
newline
|
|
bitfld.long 0xC 11. "ESB,Empty Slot Channel B" "0: Bus activity detected in the assigned slot on..,1: No bus activity detected in the assigned slot on.."
|
|
bitfld.long 0xC 10. "ESA,Empty Slot Channel A" "0: Bus activity detected in the assigned slot on..,1: No bus activity detected in the assigned slot on.."
|
|
newline
|
|
bitfld.long 0xC 9. "TCIB,Transmission Conflict Indication Channel B (vSS!TxConflictB)" "0: No transmission conflict occurred on channel B,1: Transmission conflict occurred on channel B"
|
|
bitfld.long 0xC 8. "TCIA,Transmission Conflict Indication Channel A (vSS!TxConflictA)" "0: No transmission conflict occurred on channel A,1: Transmission conflict occurred on channel A"
|
|
newline
|
|
bitfld.long 0xC 7. "SVOB,Slot Boundary Violation Observed on Channel B (vSS!BViolationB)" "0: No slot boundary violation observed on channel B,1: Slot boundary violation observed on channel B"
|
|
bitfld.long 0xC 6. "SVOA,Slot Boundary Violation Observed on Channel A (vSS!BViolationA)" "0: No slot boundary violation observed on channel A,1: Slot boundary violation observed on channel A"
|
|
newline
|
|
bitfld.long 0xC 5. "CEOB,Content Error Observed on Channel B (vSS!ContentErrorB)" "0: No content error observed on channel B,1: Content error observed on channel B"
|
|
bitfld.long 0xC 4. "CEOA,Content Error Observed on Channel A (vSS!ContentErrorA)" "0: No content error observed on channel A,1: Content error observed on channel A"
|
|
newline
|
|
bitfld.long 0xC 3. "SEOB,Syntax Error Observed on Channel B (vSS!SyntaxErrorB)" "0: No syntax error observed on channel B,1: Syntax error observed on channel B"
|
|
bitfld.long 0xC 2. "SEOA,Syntax Error Observed on Channel A (vSS!SyntaxErrorA)" "0: No syntax error observed on channel A,1: Syntax error observed on channel A"
|
|
newline
|
|
bitfld.long 0xC 1. "VFRB,Valid Frame Received on Channel B (vSS!ValidFrameB)" "0: No valid frame received on channel B,1: Valid frame received on channel B"
|
|
bitfld.long 0xC 0. "VFRA,Valid Frame Received on Channel A (vSS!ValidFrameA)" "0: No valid frame received on channel A,1: Valid frame received on channel A"
|
|
group.long 0x710++0x7
|
|
line.long 0x0 "OBCM,Output Buffer Command Mask"
|
|
rbitfld.long 0x0 17. "RDSH,Read Data Section Host" "0: Data section is not read,1: Data section selected for transfer from Message.."
|
|
rbitfld.long 0x0 16. "RHSH,Read Header Section Host" "0: Header section is not read,1: Header section selected for transfer from.."
|
|
newline
|
|
bitfld.long 0x0 1. "RDSS,Read Data Section Shadow" "0: Data section is not read,1: Data section selected for transfer from Message.."
|
|
bitfld.long 0x0 0. "RHSS,Read Header Section Shadow" "0: Header section is not read,1: Header section selected for transfer from.."
|
|
line.long 0x4 "OBCR,Output Buffer Command Request"
|
|
hexmask.long.byte 0x4 16.--22. 1. "OBRH,Output Buffer Request Host"
|
|
rbitfld.long 0x4 15. "OBSYS,Output Buffer Busy Shadow" "0: No transfer in progress,1: Transfer between Message RAM and OBF Shadow in.."
|
|
newline
|
|
bitfld.long 0x4 9. "REQ,Request Message RAM Transfer" "0: No request,1: Transfer to OBF Shadow requested"
|
|
bitfld.long 0x4 8. "VIEW,View Shadow Buffer" "0: No action,1: Swap OBF Shadow and OBF Host"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "OBRS,Output Buffer Request Shadow"
|
|
group.long 0xBF0++0xB
|
|
line.long 0x0 "WRHS1_MIR2,Write Header Section 1 (2nd mirror)"
|
|
bitfld.long 0x0 29. "MBI,Message Buffer Interrupt" "0: The corresponding message buffer interrupt is..,1: The corresponding message buffer interrupt is.."
|
|
bitfld.long 0x0 28. "TXM,Transmission Mode" "0: Continuous mode,1: Single-shot mode"
|
|
newline
|
|
bitfld.long 0x0 27. "PPIT,Payload Preamble Indicator Transmit" "0: Payload Preamble Indicator not set,1: Payload Preamble Indicator set"
|
|
bitfld.long 0x0 26. "CFG,Message Buffer Direction Configuration Bit" "0: The corresponding buffer is configured as..,1: The corresponding buffer is configured as.."
|
|
newline
|
|
bitfld.long 0x0 25. "CHB,Channel Filter Control B" "0: N/A,1: N/A"
|
|
bitfld.long 0x0 24. "CHA,Channel Filter Control A" "0: N/A,1: N/A"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "CYC,Cycle Code"
|
|
hexmask.long.word 0x0 0.--10. 1. "FID,Frame ID"
|
|
line.long 0x4 "WRHS2_MIR2,Write Header Section 2 (2nd mirror)"
|
|
hexmask.long.byte 0x4 16.--22. 1. "PLC,Payload Length Configured"
|
|
hexmask.long.word 0x4 0.--10. 1. "CRC,Header CRC (vRF!Header!HeaderCRC)"
|
|
line.long 0x8 "WRHS3_MIR2,Write Header Section 3 (2nd mirror)"
|
|
hexmask.long.word 0x8 0.--10. 1. "DP,Data Pointer"
|
|
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xC00)++0x3
|
|
line.long 0x0 "WRDS_MIR[$1],Write Data Section [1...64] (mirror)"
|
|
hexmask.long 0x0 0.--31. 1. "MD,Message Data"
|
|
repeat.end
|
|
group.long 0xD00++0xB
|
|
line.long 0x0 "WRHS1_MIR,Write Header Section 1 (mirror)"
|
|
bitfld.long 0x0 29. "MBI,Message Buffer Interrupt" "0: The corresponding message buffer interrupt is..,1: The corresponding message buffer interrupt is.."
|
|
bitfld.long 0x0 28. "TXM,Transmission Mode" "0: Continuous mode,1: Single-shot mode"
|
|
newline
|
|
bitfld.long 0x0 27. "PPIT,Payload Preamble Indicator Transmit" "0: Payload Preamble Indicator not set,1: Payload Preamble Indicator set"
|
|
bitfld.long 0x0 26. "CFG,Message Buffer Direction Configuration Bit" "0: The corresponding buffer is configured as..,1: The corresponding buffer is configured as.."
|
|
newline
|
|
bitfld.long 0x0 25. "CHB,Channel Filter Control B" "0: N/A,1: N/A"
|
|
bitfld.long 0x0 24. "CHA,Channel Filter Control A" "0: N/A,1: N/A"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "CYC,Cycle Code"
|
|
hexmask.long.word 0x0 0.--10. 1. "FID,Frame ID"
|
|
line.long 0x4 "WRHS2_MIR,Write Header Section 2 (mirror)"
|
|
hexmask.long.byte 0x4 16.--22. 1. "PLC,Payload Length Configured"
|
|
hexmask.long.word 0x4 0.--10. 1. "CRC,Header CRC (vRF!Header!HeaderCRC)"
|
|
line.long 0x8 "WRHS3_MIR,Write Header Section 3 (mirror)"
|
|
hexmask.long.word 0x8 0.--10. 1. "DP,Data Pointer"
|
|
group.long 0xD10++0x7
|
|
line.long 0x0 "IBCM_MIR,Input Buffer Command Mask (mirror)"
|
|
rbitfld.long 0x0 18. "STXRS,Set Transmission Request Shadow" "0: Reset TXR flag,1: Set TXR flag"
|
|
rbitfld.long 0x0 17. "LDSS,Load Data Section Shadow" "0: Data section is not updated,1: Data section selected for transfer from Input.."
|
|
newline
|
|
rbitfld.long 0x0 16. "LHSS,Load Header Section Shadow" "0: Header section is not updated,1: Header section selected for transfer from Input.."
|
|
bitfld.long 0x0 2. "STXRH,Set Transmission Request Host" "0: Reset TXR flag,1: Set TXR flag"
|
|
newline
|
|
bitfld.long 0x0 1. "LDSH,Load Data Section Host" "0: Data section is not updated,1: Data section selected for transfer from Input.."
|
|
bitfld.long 0x0 0. "LHSH,Load Header Section Host" "0: Header section is not updated,1: Header section selected for transfer from Input.."
|
|
line.long 0x4 "IBCR_MIR,Input Buffer Command Request (mirror)"
|
|
rbitfld.long 0x4 31. "IBSYS,Input Buffer Busy Shadow" "0: Transfer between IBF Shadow and Message RAM..,1: Transfer between IBF Shadow and Message RAM in.."
|
|
hexmask.long.byte 0x4 16.--22. 1. "IBRS,Input Buffer Request Shadow"
|
|
newline
|
|
rbitfld.long 0x4 15. "IBSYH,Input Buffer Busy Host" "0: No request pending,1: Request while transfer between IBF Shadow and.."
|
|
hexmask.long.byte 0x4 0.--6. 1. "IBRH,Input Buffer Request Host"
|
|
rgroup.long 0xDF0++0xF
|
|
line.long 0x0 "RDHS1_MIR2,Read Header Section 1 (2nd mirror)"
|
|
bitfld.long 0x0 29. "MBI,Message Buffer Interrupt" "0,1"
|
|
bitfld.long 0x0 28. "TXM,Transmission Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "PPIT,Payload Preamble Indicator Transmit" "0,1"
|
|
bitfld.long 0x0 26. "CFG,Message Buffer Direction Configuration Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "CHB,Channel Filter Control B" "0,1"
|
|
bitfld.long 0x0 24. "CHA,Channel Filter Control A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "CYC,Cycle Code"
|
|
hexmask.long.word 0x0 0.--10. 1. "FID,Frame ID"
|
|
line.long 0x4 "RDHS2_MIR2,Read Header Section 2 (2nd mirror)"
|
|
hexmask.long.byte 0x4 24.--30. 1. "PLR,Payload Length Received (vRF!Header!Length)"
|
|
hexmask.long.byte 0x4 16.--22. 1. "PLC,Payload Length Configured"
|
|
newline
|
|
hexmask.long.word 0x4 0.--10. 1. "CRC,Header CRC (vRF!Header!HeaderCRC)"
|
|
line.long 0x8 "RDHS3_MIR2,Read Header Section 3 (2nd mirror)"
|
|
bitfld.long 0x8 29. "RES,N/A" "0,1"
|
|
bitfld.long 0x8 28. "PPI,Payload Preamble Indicator (vRF!Header!PPIndicator)" "0: The payload segment of the received frame does..,1: Static segment: Network management vector in the.."
|
|
newline
|
|
bitfld.long 0x8 27. "NFI,Null Frame Indicator (vRF!Header!NFIndicator)" "0: Up to now no data frame has been stored into the..,1: At least one data frame has been stored into the.."
|
|
bitfld.long 0x8 26. "SYN,Sync Frame Indicator (vRF!Header!SyFIndicator)" "0: The received frame is not a sync frame,1: The received frame is a sync frame"
|
|
newline
|
|
bitfld.long 0x8 25. "SFI,Startup Frame Indicator (vRF!Header!SuFIndicator)" "0: The received frame is not a startup frame,1: The received frame is a startup frame"
|
|
bitfld.long 0x8 24. "RCI,Received on Channel Indicator (vSS!Channel)" "0: Frame received on channel B,1: Frame received on channel A"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "RCC,Receive Cycle Count (vRF!Header!CycleCount)"
|
|
hexmask.long.word 0x8 0.--10. 1. "DP,Data Pointer"
|
|
line.long 0xC "MBS_MIR2,Message Buffer Status (2nd mirror)"
|
|
bitfld.long 0xC 29. "RESS,N/A" "0,1"
|
|
bitfld.long 0xC 28. "PPIS,Payload Preamble Indicator Status (vRF!Header!PPIndicator)" "0: The payload segment of the received frame does..,1: Static segment: Network management vector at the.."
|
|
newline
|
|
bitfld.long 0xC 27. "NFIS,Null Frame Indicator Status (vRF!Header!NFIndicator)" "0: Received frame is a null frame,1: Received frame is not a null frame"
|
|
bitfld.long 0xC 26. "SYNS,Sync Frame Indicator Status (vRF!Header!SyFIndicator)" "0: No sync frame received,1: The received frame is a sync frame"
|
|
newline
|
|
bitfld.long 0xC 25. "SFIS,Startup Frame Indicator Status (vRF!Header!SuFIndicator)" "0: No startup frame received,1: The received frame is a startup frame"
|
|
bitfld.long 0xC 24. "RCIS,Received on Channel Indicator Status (vSS!Channel)" "0: Frame received on channel B,1: Frame received on channel A"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--21. 1. "CCS,Cycle Count Status"
|
|
bitfld.long 0xC 15. "FTB,Frame Transmitted on Channel B" "0: No data frame transmitted on channel B,1: Data frame transmitted on channel B"
|
|
newline
|
|
bitfld.long 0xC 14. "FTA,Frame Transmitted on Channel A" "0: No data frame transmitted on channel A,1: Data frame transmitted on channel A"
|
|
bitfld.long 0xC 12. "MLST,Message Lost" "0: No message lost,1: Unprocessed message was overwritten"
|
|
newline
|
|
bitfld.long 0xC 11. "ESB,Empty Slot Channel B" "0: Bus activity detected in the assigned slot on..,1: No bus activity detected in the assigned slot on.."
|
|
bitfld.long 0xC 10. "ESA,Empty Slot Channel A" "0: Bus activity detected in the assigned slot on..,1: No bus activity detected in the assigned slot on.."
|
|
newline
|
|
bitfld.long 0xC 9. "TCIB,Transmission Conflict Indication Channel B (vSS!TxConflictB)" "0: No transmission conflict occurred on channel B,1: Transmission conflict occurred on channel B"
|
|
bitfld.long 0xC 8. "TCIA,Transmission Conflict Indication Channel A (vSS!TxConflictA)" "0: No transmission conflict occurred on channel A,1: Transmission conflict occurred on channel A"
|
|
newline
|
|
bitfld.long 0xC 7. "SVOB,Slot Boundary Violation Observed on Channel B (vSS!BViolationB)" "0: No slot boundary violation observed on channel B,1: Slot boundary violation observed on channel B"
|
|
bitfld.long 0xC 6. "SVOA,Slot Boundary Violation Observed on Channel A (vSS!BViolationA)" "0: No slot boundary violation observed on channel A,1: Slot boundary violation observed on channel A"
|
|
newline
|
|
bitfld.long 0xC 5. "CEOB,Content Error Observed on Channel B (vSS!ContentErrorB)" "0: No content error observed on channel B,1: Content error observed on channel B"
|
|
bitfld.long 0xC 4. "CEOA,Content Error Observed on Channel A (vSS!ContentErrorA)" "0: No content error observed on channel A,1: Content error observed on channel A"
|
|
newline
|
|
bitfld.long 0xC 3. "SEOB,Syntax Error Observed on Channel B (vSS!SyntaxErrorB)" "0: No syntax error observed on channel B,1: Syntax error observed on channel B"
|
|
bitfld.long 0xC 2. "SEOA,Syntax Error Observed on Channel A (vSS!SyntaxErrorA)" "0: No syntax error observed on channel A,1: Syntax error observed on channel A"
|
|
newline
|
|
bitfld.long 0xC 1. "VFRB,Valid Frame Received on Channel B (vSS!ValidFrameB)" "0: No valid frame received on channel B,1: Valid frame received on channel B"
|
|
bitfld.long 0xC 0. "VFRA,Valid Frame Received on Channel A (vSS!ValidFrameA)" "0: No valid frame received on channel A,1: Valid frame received on channel A"
|
|
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0xE00)++0x3
|
|
line.long 0x0 "RDDS_MIR[$1],Read Data Section [1...64] (mirror)"
|
|
hexmask.long 0x0 0.--31. 1. "MD,Message Data"
|
|
repeat.end
|
|
rgroup.long 0xF00++0xF
|
|
line.long 0x0 "RDHS1_MIR,Read Header Section 1 (mirror)"
|
|
bitfld.long 0x0 29. "MBI,Message Buffer Interrupt" "0,1"
|
|
bitfld.long 0x0 28. "TXM,Transmission Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "PPIT,Payload Preamble Indicator Transmit" "0,1"
|
|
bitfld.long 0x0 26. "CFG,Message Buffer Direction Configuration Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "CHB,Channel Filter Control B" "0,1"
|
|
bitfld.long 0x0 24. "CHA,Channel Filter Control A" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "CYC,Cycle Code"
|
|
hexmask.long.word 0x0 0.--10. 1. "FID,Frame ID"
|
|
line.long 0x4 "RDHS2_MIR,Read Header Section 2 (mirror)"
|
|
hexmask.long.byte 0x4 24.--30. 1. "PLR,Payload Length Received (vRF!Header!Length)"
|
|
hexmask.long.byte 0x4 16.--22. 1. "PLC,Payload Length Configured"
|
|
newline
|
|
hexmask.long.word 0x4 0.--10. 1. "CRC,Header CRC (vRF!Header!HeaderCRC)"
|
|
line.long 0x8 "RDHS3_MIR,Read Header Section 3 (mirror)"
|
|
bitfld.long 0x8 29. "RES,N/A" "0,1"
|
|
bitfld.long 0x8 28. "PPI,Payload Preamble Indicator (vRF!Header!PPIndicator)" "0: The payload segment of the received frame does..,1: Static segment: Network management vector in the.."
|
|
newline
|
|
bitfld.long 0x8 27. "NFI,Null Frame Indicator (vRF!Header!NFIndicator)" "0: Up to now no data frame has been stored into the..,1: At least one data frame has been stored into the.."
|
|
bitfld.long 0x8 26. "SYN,Sync Frame Indicator (vRF!Header!SyFIndicator)" "0: The received frame is not a sync frame,1: The received frame is a sync frame"
|
|
newline
|
|
bitfld.long 0x8 25. "SFI,Startup Frame Indicator (vRF!Header!SuFIndicator)" "0: The received frame is not a startup frame,1: The received frame is a startup frame"
|
|
bitfld.long 0x8 24. "RCI,Received on Channel Indicator (vSS!Channel)" "0: Frame received on channel B,1: Frame received on channel A"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "RCC,Receive Cycle Count (vRF!Header!CycleCount)"
|
|
hexmask.long.word 0x8 0.--10. 1. "DP,Data Pointer"
|
|
line.long 0xC "MBS_MIR,Message Buffer Status (mirror)"
|
|
bitfld.long 0xC 29. "RESS,N/A" "0,1"
|
|
bitfld.long 0xC 28. "PPIS,Payload Preamble Indicator Status (vRF!Header!PPIndicator)" "0: The payload segment of the received frame does..,1: Static segment: Network management vector at the.."
|
|
newline
|
|
bitfld.long 0xC 27. "NFIS,Null Frame Indicator Status (vRF!Header!NFIndicator)" "0: Received frame is a null frame,1: Received frame is not a null frame"
|
|
bitfld.long 0xC 26. "SYNS,Sync Frame Indicator Status (vRF!Header!SyFIndicator)" "0: No sync frame received,1: The received frame is a sync frame"
|
|
newline
|
|
bitfld.long 0xC 25. "SFIS,Startup Frame Indicator Status (vRF!Header!SuFIndicator)" "0: No startup frame received,1: The received frame is a startup frame"
|
|
bitfld.long 0xC 24. "RCIS,Received on Channel Indicator Status (vSS!Channel)" "0: Frame received on channel B,1: Frame received on channel A"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--21. 1. "CCS,Cycle Count Status"
|
|
bitfld.long 0xC 15. "FTB,Frame Transmitted on Channel B" "0: No data frame transmitted on channel B,1: Data frame transmitted on channel B"
|
|
newline
|
|
bitfld.long 0xC 14. "FTA,Frame Transmitted on Channel A" "0: No data frame transmitted on channel A,1: Data frame transmitted on channel A"
|
|
bitfld.long 0xC 12. "MLST,Message Lost" "0: No message lost,1: Unprocessed message was overwritten"
|
|
newline
|
|
bitfld.long 0xC 11. "ESB,Empty Slot Channel B" "0: Bus activity detected in the assigned slot on..,1: No bus activity detected in the assigned slot on.."
|
|
bitfld.long 0xC 10. "ESA,Empty Slot Channel A" "0: Bus activity detected in the assigned slot on..,1: No bus activity detected in the assigned slot on.."
|
|
newline
|
|
bitfld.long 0xC 9. "TCIB,Transmission Conflict Indication Channel B (vSS!TxConflictB)" "0: No transmission conflict occurred on channel B,1: Transmission conflict occurred on channel B"
|
|
bitfld.long 0xC 8. "TCIA,Transmission Conflict Indication Channel A (vSS!TxConflictA)" "0: No transmission conflict occurred on channel A,1: Transmission conflict occurred on channel A"
|
|
newline
|
|
bitfld.long 0xC 7. "SVOB,Slot Boundary Violation Observed on Channel B (vSS!BViolationB)" "0: No slot boundary violation observed on channel B,1: Slot boundary violation observed on channel B"
|
|
bitfld.long 0xC 6. "SVOA,Slot Boundary Violation Observed on Channel A (vSS!BViolationA)" "0: No slot boundary violation observed on channel A,1: Slot boundary violation observed on channel A"
|
|
newline
|
|
bitfld.long 0xC 5. "CEOB,Content Error Observed on Channel B (vSS!ContentErrorB)" "0: No content error observed on channel B,1: Content error observed on channel B"
|
|
bitfld.long 0xC 4. "CEOA,Content Error Observed on Channel A (vSS!ContentErrorA)" "0: No content error observed on channel A,1: Content error observed on channel A"
|
|
newline
|
|
bitfld.long 0xC 3. "SEOB,Syntax Error Observed on Channel B (vSS!SyntaxErrorB)" "0: No syntax error observed on channel B,1: Syntax error observed on channel B"
|
|
bitfld.long 0xC 2. "SEOA,Syntax Error Observed on Channel A (vSS!SyntaxErrorA)" "0: No syntax error observed on channel A,1: Syntax error observed on channel A"
|
|
newline
|
|
bitfld.long 0xC 1. "VFRB,Valid Frame Received on Channel B (vSS!ValidFrameB)" "0: No valid frame received on channel B,1: Valid frame received on channel B"
|
|
bitfld.long 0xC 0. "VFRA,Valid Frame Received on Channel A (vSS!ValidFrameA)" "0: No valid frame received on channel A,1: Valid frame received on channel A"
|
|
group.long 0xF10++0x7
|
|
line.long 0x0 "OBCM_MIR,Output Buffer Command Mask (mirror)"
|
|
rbitfld.long 0x0 17. "RDSH,Read Data Section Host" "0: Data section is not read,1: Data section selected for transfer from Message.."
|
|
rbitfld.long 0x0 16. "RHSH,Read Header Section Host" "0: Header section is not read,1: Header section selected for transfer from.."
|
|
newline
|
|
bitfld.long 0x0 1. "RDSS,Read Data Section Shadow" "0: Data section is not read,1: Data section selected for transfer from Message.."
|
|
bitfld.long 0x0 0. "RHSS,Read Header Section Shadow" "0: Header section is not read,1: Header section selected for transfer from.."
|
|
line.long 0x4 "OBCR_MIR,Output Buffer Command Request (mirror)"
|
|
hexmask.long.byte 0x4 16.--22. 1. "OBRH,Output Buffer Request Host"
|
|
rbitfld.long 0x4 15. "OBSYS,Output Buffer Busy Shadow" "0: No transfer in progress,1: Transfer between Message RAM and OBF Shadow in.."
|
|
newline
|
|
bitfld.long 0x4 9. "REQ,Request Message RAM Transfer" "0: No request,1: Transfer to OBF Shadow requested"
|
|
bitfld.long 0x4 8. "VIEW,View Shadow Buffer" "0: No action,1: Swap OBF Shadow and OBF Host"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "OBRS,Output Buffer Request Shadow"
|
|
tree.end
|
|
tree "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"
|
|
base ad:0x40310000
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40310000 ad:0x40310080 ad:0x40310100 ad:0x40310180 ad:0x40310200 ad:0x40310280 ad:0x40310300 ad:0x40310380 ad:0x40310400 ad:0x40310480 ad:0x40310500 ad:0x40310580 ad:0x40310600 ad:0x40310680 ad:0x40310700 ad:0x40310780)
|
|
tree "PRT[$1]"
|
|
base $2
|
|
group.long ($2)++0xF
|
|
line.long 0x0 "OUT,Port output data register"
|
|
bitfld.long 0x0 7. "OUT7,IO output data for pin 7" "0,1"
|
|
bitfld.long 0x0 6. "OUT6,IO output data for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OUT5,IO output data for pin 5" "0,1"
|
|
bitfld.long 0x0 4. "OUT4,IO output data for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OUT3,IO output data for pin 3" "0,1"
|
|
bitfld.long 0x0 2. "OUT2,IO output data for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OUT1,IO output data for pin 1" "0,1"
|
|
bitfld.long 0x0 0. "OUT0,IO output data for pin 0" "0,1"
|
|
line.long 0x4 "OUT_CLR,Port output data clear register"
|
|
bitfld.long 0x4 7. "OUT7,IO clear output for pin 7" "0,1"
|
|
bitfld.long 0x4 6. "OUT6,IO clear output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OUT5,IO clear output for pin 5" "0,1"
|
|
bitfld.long 0x4 4. "OUT4,IO clear output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OUT3,IO clear output for pin 3" "0,1"
|
|
bitfld.long 0x4 2. "OUT2,IO clear output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "OUT1,IO clear output for pin 1" "0,1"
|
|
bitfld.long 0x4 0. "OUT0,IO clear output for pin 0:" "0,1"
|
|
line.long 0x8 "OUT_SET,Port output data set register"
|
|
bitfld.long 0x8 7. "OUT7,IO set output for pin 7" "0,1"
|
|
bitfld.long 0x8 6. "OUT6,IO set output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OUT5,IO set output for pin 5" "0,1"
|
|
bitfld.long 0x8 4. "OUT4,IO set output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "OUT3,IO set output for pin 3" "0,1"
|
|
bitfld.long 0x8 2. "OUT2,IO set output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "OUT1,IO set output for pin 1" "0,1"
|
|
bitfld.long 0x8 0. "OUT0,IO set output for pin 0:" "0,1"
|
|
line.long 0xC "OUT_INV,Port output data invert register"
|
|
bitfld.long 0xC 7. "OUT7,IO invert output for pin 7" "0,1"
|
|
bitfld.long 0xC 6. "OUT6,IO invert output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "OUT5,IO invert output for pin 5" "0,1"
|
|
bitfld.long 0xC 4. "OUT4,IO invert output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "OUT3,IO invert output for pin 3" "0,1"
|
|
bitfld.long 0xC 2. "OUT2,IO invert output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "OUT1,IO invert output for pin 1" "0,1"
|
|
bitfld.long 0xC 0. "OUT0,IO invert output for pin 0:" "0,1"
|
|
rgroup.long ($2+0x10)++0x3
|
|
line.long 0x0 "IN,Port input state register"
|
|
bitfld.long 0x0 8. "FLT_IN,Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register." "0,1"
|
|
bitfld.long 0x0 7. "IN7,IO pin state for pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "IN6,IO pin state for pin 6" "0,1"
|
|
bitfld.long 0x0 5. "IN5,IO pin state for pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IN4,IO pin state for pin 4" "0,1"
|
|
bitfld.long 0x0 3. "IN3,IO pin state for pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "IN2,IO pin state for pin 2" "0,1"
|
|
bitfld.long 0x0 1. "IN1,IO pin state for pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IN0,IO pin state for pin 0" "0,1"
|
|
group.long ($2+0x14)++0x7
|
|
line.long 0x0 "INTR,Port interrupt status register"
|
|
rbitfld.long 0x0 24. "FLT_IN_IN,Filtered pin state for pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
rbitfld.long 0x0 23. "IN_IN7,IO pin state for pin 7" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 22. "IN_IN6,IO pin state for pin 6" "0,1"
|
|
rbitfld.long 0x0 21. "IN_IN5,IO pin state for pin 5" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 20. "IN_IN4,IO pin state for pin 4" "0,1"
|
|
rbitfld.long 0x0 19. "IN_IN3,IO pin state for pin 3" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 18. "IN_IN2,IO pin state for pin 2" "0,1"
|
|
rbitfld.long 0x0 17. "IN_IN1,IO pin state for pin 1" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "IN_IN0,IO pin state for pin 0" "0,1"
|
|
bitfld.long 0x0 8. "FLT_EDGE,Edge detected on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "EDGE7,Edge detect for IO pin 7" "0,1"
|
|
bitfld.long 0x0 6. "EDGE6,Edge detect for IO pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EDGE5,Edge detect for IO pin 5" "0,1"
|
|
bitfld.long 0x0 4. "EDGE4,Edge detect for IO pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EDGE3,Edge detect for IO pin 3" "0,1"
|
|
bitfld.long 0x0 2. "EDGE2,Edge detect for IO pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EDGE1,Edge detect for IO pin 1" "0,1"
|
|
bitfld.long 0x0 0. "EDGE0,Edge detect for IO pin 0" "0,1"
|
|
line.long 0x4 "INTR_MASK,Port interrupt mask register"
|
|
bitfld.long 0x4 8. "FLT_EDGE,Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x4 7. "EDGE7,Masks edge interrupt on IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "EDGE6,Masks edge interrupt on IO pin 6" "0,1"
|
|
bitfld.long 0x4 5. "EDGE5,Masks edge interrupt on IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EDGE4,Masks edge interrupt on IO pin 4" "0,1"
|
|
bitfld.long 0x4 3. "EDGE3,Masks edge interrupt on IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "EDGE2,Masks edge interrupt on IO pin 2" "0,1"
|
|
bitfld.long 0x4 1. "EDGE1,Masks edge interrupt on IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "EDGE0,Masks edge interrupt on IO pin 0" "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Port interrupt masked status register"
|
|
bitfld.long 0x0 8. "FLT_EDGE,Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x0 7. "EDGE7,Edge detected and masked on IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "EDGE6,Edge detected and masked on IO pin 6" "0,1"
|
|
bitfld.long 0x0 5. "EDGE5,Edge detected and masked on IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EDGE4,Edge detected and masked on IO pin 4" "0,1"
|
|
bitfld.long 0x0 3. "EDGE3,Edge detected and masked on IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EDGE2,Edge detected and masked on IO pin 2" "0,1"
|
|
bitfld.long 0x0 1. "EDGE1,Edge detected and masked on IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EDGE0,Edge detected AND masked on IO pin 0" "0,1"
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "INTR_SET,Port interrupt set register"
|
|
bitfld.long 0x0 8. "FLT_EDGE,Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x0 7. "EDGE7,Sets edge detect interrupt for IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "EDGE6,Sets edge detect interrupt for IO pin 6" "0,1"
|
|
bitfld.long 0x0 5. "EDGE5,Sets edge detect interrupt for IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EDGE4,Sets edge detect interrupt for IO pin 4" "0,1"
|
|
bitfld.long 0x0 3. "EDGE3,Sets edge detect interrupt for IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EDGE2,Sets edge detect interrupt for IO pin 2" "0,1"
|
|
bitfld.long 0x0 1. "EDGE1,Sets edge detect interrupt for IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EDGE0,Sets edge detect interrupt for IO pin 0" "0,1"
|
|
group.long ($2+0x40)++0x13
|
|
line.long 0x0 "INTR_CFG,Port interrupt configuration register"
|
|
bitfld.long 0x0 18.--20. "FLT_SEL,Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--17. "FLT_EDGE_SEL,Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL" "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "EDGE7_SEL,Sets which edge will trigger an IRQ for IO pin 7" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "EDGE6_SEL,Sets which edge will trigger an IRQ for IO pin 6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "EDGE5_SEL,Sets which edge will trigger an IRQ for IO pin 5" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EDGE4_SEL,Sets which edge will trigger an IRQ for IO pin 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "EDGE3_SEL,Sets which edge will trigger an IRQ for IO pin 3" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "EDGE2_SEL,Sets which edge will trigger an IRQ for IO pin 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "EDGE1_SEL,Sets which edge will trigger an IRQ for IO pin 1" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "EDGE0_SEL,Sets which edge will trigger an IRQ for IO pin 0" "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
|
|
line.long 0x4 "CFG,Port configuration register"
|
|
bitfld.long 0x4 31. "IN_EN7,Enables the input buffer for IO pin 7" "0,1"
|
|
bitfld.long 0x4 28.--30. "DRIVE_MODE7,The GPIO drive mode for IO pin 7. Resistive pull-up and pull-down is selected in the drive mode." "0: Output buffer is off creating a high impedance..,1: N/A,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
newline
|
|
bitfld.long 0x4 27. "IN_EN6,Enables the input buffer for IO pin 6" "0,1"
|
|
bitfld.long 0x4 24.--26. "DRIVE_MODE6,The GPIO drive mode for IO pin 6. Resistive pull-up and pull-down is selected in the drive mode." "0: Output buffer is off creating a high impedance..,1: N/A,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
newline
|
|
bitfld.long 0x4 23. "IN_EN5,Enables the input buffer for IO pin 5" "0,1"
|
|
bitfld.long 0x4 20.--22. "DRIVE_MODE5,The GPIO drive mode for IO pin 5. Resistive pull-up and pull-down is selected in the drive mode." "0: Output buffer is off creating a high impedance..,1: N/A,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
newline
|
|
bitfld.long 0x4 19. "IN_EN4,Enables the input buffer for IO pin 4" "0,1"
|
|
bitfld.long 0x4 16.--18. "DRIVE_MODE4,The GPIO drive mode for IO pin 4. Resistive pull-up and pull-down is selected in the drive mode." "0: Output buffer is off creating a high impedance..,1: N/A,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
newline
|
|
bitfld.long 0x4 15. "IN_EN3,Enables the input buffer for IO pin 3" "0,1"
|
|
bitfld.long 0x4 12.--14. "DRIVE_MODE3,The GPIO drive mode for IO pin 3. Resistive pull-up and pull-down is selected in the drive mode." "0: Output buffer is off creating a high impedance..,1: N/A,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
newline
|
|
bitfld.long 0x4 11. "IN_EN2,Enables the input buffer for IO pin 2" "0,1"
|
|
bitfld.long 0x4 8.--10. "DRIVE_MODE2,The GPIO drive mode for IO pin 2. Resistive pull-up and pull-down is selected in the drive mode." "0: Output buffer is off creating a high impedance..,1: N/A,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
newline
|
|
bitfld.long 0x4 7. "IN_EN1,Enables the input buffer for IO pin 1" "0,1"
|
|
bitfld.long 0x4 4.--6. "DRIVE_MODE1,The GPIO drive mode for IO pin 1. Resistive pull-up and pull-down is selected in the drive mode." "0: Output buffer is off creating a high impedance..,1: N/A,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
newline
|
|
bitfld.long 0x4 3. "IN_EN0,Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue." "0,1"
|
|
bitfld.long 0x4 0.--2. "DRIVE_MODE0,The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode." "0: Output buffer is off creating a high impedance..,1: N/A,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
line.long 0x8 "CFG_IN,Port input buffer configuration register"
|
|
bitfld.long 0x8 7. "VTRIP_SEL7_0,Configures the pin 7 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 6. "VTRIP_SEL6_0,Configures the pin 6 input buffer mode (trip points and hysteresis)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "VTRIP_SEL5_0,Configures the pin 5 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 4. "VTRIP_SEL4_0,Configures the pin 4 input buffer mode (trip points and hysteresis)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "VTRIP_SEL3_0,Configures the pin 3 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 2. "VTRIP_SEL2_0,Configures the pin 2 input buffer mode (trip points and hysteresis)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "VTRIP_SEL1_0,Configures the pin 1 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 0. "VTRIP_SEL0_0,Configures the pin 0 input buffer mode (trip points and hysteresis)" "0: PSoC6:: Input buffer compatible with CMOS and..,1: PSoC6:: Input buffer compatible with TTL and.."
|
|
line.long 0xC "CFG_OUT,Port output buffer configuration register"
|
|
bitfld.long 0xC 30.--31. "DRIVE_SEL7,Sets the GPIO drive strength for IO pin 7" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "DRIVE_SEL6,Sets the GPIO drive strength for IO pin 6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 26.--27. "DRIVE_SEL5,Sets the GPIO drive strength for IO pin 5" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "DRIVE_SEL4,Sets the GPIO drive strength for IO pin 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 22.--23. "DRIVE_SEL3,Sets the GPIO drive strength for IO pin 3" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "DRIVE_SEL2,Sets the GPIO drive strength for IO pin 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 18.--19. "DRIVE_SEL1,Sets the GPIO drive strength for IO pin 1" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "DRIVE_SEL0,Sets the GPIO drive strength for IO pin 0" "0: Please refer to architecture TRM section I/O..,1: Please refer to architecture TRM section I/O..,2: Please refer to architecture TRM section I/O..,3: Please refer to architecture TRM section I/O.."
|
|
newline
|
|
bitfld.long 0xC 7. "SLOW7,Enables slow slew rate for IO pin 7" "0,1"
|
|
bitfld.long 0xC 6. "SLOW6,Enables slow slew rate for IO pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "SLOW5,Enables slow slew rate for IO pin 5" "0,1"
|
|
bitfld.long 0xC 4. "SLOW4,Enables slow slew rate for IO pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "SLOW3,Enables slow slew rate for IO pin 3" "0,1"
|
|
bitfld.long 0xC 2. "SLOW2,Enables slow slew rate for IO pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "SLOW1,Enables slow slew rate for IO pin 1" "0,1"
|
|
bitfld.long 0xC 0. "SLOW0,Enables slow slew rate for IO pin 0" "0,1"
|
|
line.long 0x10 "CFG_SIO,Port SIO configuration register"
|
|
bitfld.long 0x10 29.--31. "VOH_SEL67,See corresponding definition for IO pins 0 and 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 27.--28. "VREF_SEL67,See corresponding definition for IO pins 0 and 1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 26. "VTRIP_SEL67,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
bitfld.long 0x10 25. "IBUF_SEL67,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
newline
|
|
bitfld.long 0x10 24. "VREG_EN67,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
bitfld.long 0x10 21.--23. "VOH_SEL45,See corresponding definition for IO pins 0 and 1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 19.--20. "VREF_SEL45,See corresponding definition for IO pins 0 and 1" "0,1,2,3"
|
|
bitfld.long 0x10 18. "VTRIP_SEL45,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
newline
|
|
bitfld.long 0x10 17. "IBUF_SEL45,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
bitfld.long 0x10 16. "VREG_EN45,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13.--15. "VOH_SEL23,See corresponding definition for IO pins 0 and 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 11.--12. "VREF_SEL23,See corresponding definition for IO pins 0 and 1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 10. "VTRIP_SEL23,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
bitfld.long 0x10 9. "IBUF_SEL23,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "VREG_EN23,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
bitfld.long 0x10 5.--7. "VOH_SEL01,Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'):" "0: Trip point=0,1: a) VREF_SEL=00,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x10 3.--4. "VREF_SEL01,Selects reference voltage (Vref) trip-point of the input buffer:" "0,1,2,3"
|
|
bitfld.long 0x10 2. "VTRIP_SEL01,Selects the input buffer trip-point in single ended input buffer mode (IBUF_SEL = '0'):" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "IBUF_SEL01,Selects the input buffer mode:" "0: Singled ended input buffer,1: Differential input buffer"
|
|
bitfld.long 0x10 0. "VREG_EN01,The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output.." "0,1"
|
|
group.long ($2+0x58)++0x3
|
|
line.long 0x0 "CFG_IN_AUTOLVL,Port input buffer AUTOLVL configuration register"
|
|
bitfld.long 0x0 7. "VTRIP_SEL7_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 6. "VTRIP_SEL6_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "VTRIP_SEL5_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 4. "VTRIP_SEL4_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "VTRIP_SEL3_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 2. "VTRIP_SEL2_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "VTRIP_SEL1_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 0. "VTRIP_SEL0_1,Configures the input buffer mode (trip points and hysteresis) for GPIO upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. This field is used along with CFG_IN.VTRIP_SEL0_0 field as below:" "0: input buffer is compatible with automotive,1: input buffer is compatible with automotive"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x40310800 ad:0x40310880 ad:0x40310900 ad:0x40310980 ad:0x40310A00 ad:0x40310A80 ad:0x40310B00 ad:0x40310B80 ad:0x40310C00 ad:0x40310C80 ad:0x40310D00 ad:0x40310D80 ad:0x40310E00 ad:0x40310E80 ad:0x40310F00 ad:0x40310F80)
|
|
tree "PRT[$1]"
|
|
base $2
|
|
group.long ($2)++0xF
|
|
line.long 0x0 "OUT,Port output data register"
|
|
bitfld.long 0x0 7. "OUT7,IO output data for pin 7" "0,1"
|
|
bitfld.long 0x0 6. "OUT6,IO output data for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OUT5,IO output data for pin 5" "0,1"
|
|
bitfld.long 0x0 4. "OUT4,IO output data for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OUT3,IO output data for pin 3" "0,1"
|
|
bitfld.long 0x0 2. "OUT2,IO output data for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OUT1,IO output data for pin 1" "0,1"
|
|
bitfld.long 0x0 0. "OUT0,IO output data for pin 0" "0,1"
|
|
line.long 0x4 "OUT_CLR,Port output data clear register"
|
|
bitfld.long 0x4 7. "OUT7,IO clear output for pin 7" "0,1"
|
|
bitfld.long 0x4 6. "OUT6,IO clear output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OUT5,IO clear output for pin 5" "0,1"
|
|
bitfld.long 0x4 4. "OUT4,IO clear output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OUT3,IO clear output for pin 3" "0,1"
|
|
bitfld.long 0x4 2. "OUT2,IO clear output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "OUT1,IO clear output for pin 1" "0,1"
|
|
bitfld.long 0x4 0. "OUT0,IO clear output for pin 0:" "0,1"
|
|
line.long 0x8 "OUT_SET,Port output data set register"
|
|
bitfld.long 0x8 7. "OUT7,IO set output for pin 7" "0,1"
|
|
bitfld.long 0x8 6. "OUT6,IO set output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OUT5,IO set output for pin 5" "0,1"
|
|
bitfld.long 0x8 4. "OUT4,IO set output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "OUT3,IO set output for pin 3" "0,1"
|
|
bitfld.long 0x8 2. "OUT2,IO set output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "OUT1,IO set output for pin 1" "0,1"
|
|
bitfld.long 0x8 0. "OUT0,IO set output for pin 0:" "0,1"
|
|
line.long 0xC "OUT_INV,Port output data invert register"
|
|
bitfld.long 0xC 7. "OUT7,IO invert output for pin 7" "0,1"
|
|
bitfld.long 0xC 6. "OUT6,IO invert output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "OUT5,IO invert output for pin 5" "0,1"
|
|
bitfld.long 0xC 4. "OUT4,IO invert output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "OUT3,IO invert output for pin 3" "0,1"
|
|
bitfld.long 0xC 2. "OUT2,IO invert output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "OUT1,IO invert output for pin 1" "0,1"
|
|
bitfld.long 0xC 0. "OUT0,IO invert output for pin 0:" "0,1"
|
|
rgroup.long ($2+0x10)++0x3
|
|
line.long 0x0 "IN,Port input state register"
|
|
bitfld.long 0x0 8. "FLT_IN,Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register." "0,1"
|
|
bitfld.long 0x0 7. "IN7,IO pin state for pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "IN6,IO pin state for pin 6" "0,1"
|
|
bitfld.long 0x0 5. "IN5,IO pin state for pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IN4,IO pin state for pin 4" "0,1"
|
|
bitfld.long 0x0 3. "IN3,IO pin state for pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "IN2,IO pin state for pin 2" "0,1"
|
|
bitfld.long 0x0 1. "IN1,IO pin state for pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IN0,IO pin state for pin 0" "0,1"
|
|
group.long ($2+0x14)++0x7
|
|
line.long 0x0 "INTR,Port interrupt status register"
|
|
rbitfld.long 0x0 24. "FLT_IN_IN,Filtered pin state for pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
rbitfld.long 0x0 23. "IN_IN7,IO pin state for pin 7" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 22. "IN_IN6,IO pin state for pin 6" "0,1"
|
|
rbitfld.long 0x0 21. "IN_IN5,IO pin state for pin 5" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 20. "IN_IN4,IO pin state for pin 4" "0,1"
|
|
rbitfld.long 0x0 19. "IN_IN3,IO pin state for pin 3" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 18. "IN_IN2,IO pin state for pin 2" "0,1"
|
|
rbitfld.long 0x0 17. "IN_IN1,IO pin state for pin 1" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "IN_IN0,IO pin state for pin 0" "0,1"
|
|
bitfld.long 0x0 8. "FLT_EDGE,Edge detected on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "EDGE7,Edge detect for IO pin 7" "0,1"
|
|
bitfld.long 0x0 6. "EDGE6,Edge detect for IO pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EDGE5,Edge detect for IO pin 5" "0,1"
|
|
bitfld.long 0x0 4. "EDGE4,Edge detect for IO pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EDGE3,Edge detect for IO pin 3" "0,1"
|
|
bitfld.long 0x0 2. "EDGE2,Edge detect for IO pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EDGE1,Edge detect for IO pin 1" "0,1"
|
|
bitfld.long 0x0 0. "EDGE0,Edge detect for IO pin 0" "0,1"
|
|
line.long 0x4 "INTR_MASK,Port interrupt mask register"
|
|
bitfld.long 0x4 8. "FLT_EDGE,Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x4 7. "EDGE7,Masks edge interrupt on IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "EDGE6,Masks edge interrupt on IO pin 6" "0,1"
|
|
bitfld.long 0x4 5. "EDGE5,Masks edge interrupt on IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EDGE4,Masks edge interrupt on IO pin 4" "0,1"
|
|
bitfld.long 0x4 3. "EDGE3,Masks edge interrupt on IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "EDGE2,Masks edge interrupt on IO pin 2" "0,1"
|
|
bitfld.long 0x4 1. "EDGE1,Masks edge interrupt on IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "EDGE0,Masks edge interrupt on IO pin 0" "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Port interrupt masked status register"
|
|
bitfld.long 0x0 8. "FLT_EDGE,Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x0 7. "EDGE7,Edge detected and masked on IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "EDGE6,Edge detected and masked on IO pin 6" "0,1"
|
|
bitfld.long 0x0 5. "EDGE5,Edge detected and masked on IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EDGE4,Edge detected and masked on IO pin 4" "0,1"
|
|
bitfld.long 0x0 3. "EDGE3,Edge detected and masked on IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EDGE2,Edge detected and masked on IO pin 2" "0,1"
|
|
bitfld.long 0x0 1. "EDGE1,Edge detected and masked on IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EDGE0,Edge detected AND masked on IO pin 0" "0,1"
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "INTR_SET,Port interrupt set register"
|
|
bitfld.long 0x0 8. "FLT_EDGE,Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x0 7. "EDGE7,Sets edge detect interrupt for IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "EDGE6,Sets edge detect interrupt for IO pin 6" "0,1"
|
|
bitfld.long 0x0 5. "EDGE5,Sets edge detect interrupt for IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EDGE4,Sets edge detect interrupt for IO pin 4" "0,1"
|
|
bitfld.long 0x0 3. "EDGE3,Sets edge detect interrupt for IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EDGE2,Sets edge detect interrupt for IO pin 2" "0,1"
|
|
bitfld.long 0x0 1. "EDGE1,Sets edge detect interrupt for IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EDGE0,Sets edge detect interrupt for IO pin 0" "0,1"
|
|
group.long ($2+0x40)++0x13
|
|
line.long 0x0 "INTR_CFG,Port interrupt configuration register"
|
|
bitfld.long 0x0 18.--20. "FLT_SEL,Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--17. "FLT_EDGE_SEL,Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL" "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "EDGE7_SEL,Sets which edge will trigger an IRQ for IO pin 7" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "EDGE6_SEL,Sets which edge will trigger an IRQ for IO pin 6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "EDGE5_SEL,Sets which edge will trigger an IRQ for IO pin 5" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EDGE4_SEL,Sets which edge will trigger an IRQ for IO pin 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "EDGE3_SEL,Sets which edge will trigger an IRQ for IO pin 3" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "EDGE2_SEL,Sets which edge will trigger an IRQ for IO pin 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "EDGE1_SEL,Sets which edge will trigger an IRQ for IO pin 1" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "EDGE0_SEL,Sets which edge will trigger an IRQ for IO pin 0" "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
|
|
line.long 0x4 "CFG,Port configuration register"
|
|
bitfld.long 0x4 31. "IN_EN7,Enables the input buffer for IO pin 7" "0,1"
|
|
bitfld.long 0x4 28.--30. "DRIVE_MODE7,The GPIO drive mode for IO pin 7. Resistive pull-up and pull-down is selected in the drive mode." "0: Output buffer is off creating a high impedance..,1: N/A,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
newline
|
|
bitfld.long 0x4 27. "IN_EN6,Enables the input buffer for IO pin 6" "0,1"
|
|
bitfld.long 0x4 24.--26. "DRIVE_MODE6,The GPIO drive mode for IO pin 6. Resistive pull-up and pull-down is selected in the drive mode." "0: Output buffer is off creating a high impedance..,1: N/A,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
newline
|
|
bitfld.long 0x4 23. "IN_EN5,Enables the input buffer for IO pin 5" "0,1"
|
|
bitfld.long 0x4 20.--22. "DRIVE_MODE5,The GPIO drive mode for IO pin 5. Resistive pull-up and pull-down is selected in the drive mode." "0: Output buffer is off creating a high impedance..,1: N/A,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
newline
|
|
bitfld.long 0x4 19. "IN_EN4,Enables the input buffer for IO pin 4" "0,1"
|
|
bitfld.long 0x4 16.--18. "DRIVE_MODE4,The GPIO drive mode for IO pin 4. Resistive pull-up and pull-down is selected in the drive mode." "0: Output buffer is off creating a high impedance..,1: N/A,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
newline
|
|
bitfld.long 0x4 15. "IN_EN3,Enables the input buffer for IO pin 3" "0,1"
|
|
bitfld.long 0x4 12.--14. "DRIVE_MODE3,The GPIO drive mode for IO pin 3. Resistive pull-up and pull-down is selected in the drive mode." "0: Output buffer is off creating a high impedance..,1: N/A,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
newline
|
|
bitfld.long 0x4 11. "IN_EN2,Enables the input buffer for IO pin 2" "0,1"
|
|
bitfld.long 0x4 8.--10. "DRIVE_MODE2,The GPIO drive mode for IO pin 2. Resistive pull-up and pull-down is selected in the drive mode." "0: Output buffer is off creating a high impedance..,1: N/A,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
newline
|
|
bitfld.long 0x4 7. "IN_EN1,Enables the input buffer for IO pin 1" "0,1"
|
|
bitfld.long 0x4 4.--6. "DRIVE_MODE1,The GPIO drive mode for IO pin 1. Resistive pull-up and pull-down is selected in the drive mode." "0: Output buffer is off creating a high impedance..,1: N/A,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
newline
|
|
bitfld.long 0x4 3. "IN_EN0,Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue." "0,1"
|
|
bitfld.long 0x4 0.--2. "DRIVE_MODE0,The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode." "0: Output buffer is off creating a high impedance..,1: N/A,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
line.long 0x8 "CFG_IN,Port input buffer configuration register"
|
|
bitfld.long 0x8 7. "VTRIP_SEL7_0,Configures the pin 7 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 6. "VTRIP_SEL6_0,Configures the pin 6 input buffer mode (trip points and hysteresis)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "VTRIP_SEL5_0,Configures the pin 5 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 4. "VTRIP_SEL4_0,Configures the pin 4 input buffer mode (trip points and hysteresis)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "VTRIP_SEL3_0,Configures the pin 3 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 2. "VTRIP_SEL2_0,Configures the pin 2 input buffer mode (trip points and hysteresis)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "VTRIP_SEL1_0,Configures the pin 1 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 0. "VTRIP_SEL0_0,Configures the pin 0 input buffer mode (trip points and hysteresis)" "0: PSoC6:: Input buffer compatible with CMOS and..,1: PSoC6:: Input buffer compatible with TTL and.."
|
|
line.long 0xC "CFG_OUT,Port output buffer configuration register"
|
|
bitfld.long 0xC 30.--31. "DRIVE_SEL7,Sets the GPIO drive strength for IO pin 7" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "DRIVE_SEL6,Sets the GPIO drive strength for IO pin 6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 26.--27. "DRIVE_SEL5,Sets the GPIO drive strength for IO pin 5" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "DRIVE_SEL4,Sets the GPIO drive strength for IO pin 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 22.--23. "DRIVE_SEL3,Sets the GPIO drive strength for IO pin 3" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "DRIVE_SEL2,Sets the GPIO drive strength for IO pin 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 18.--19. "DRIVE_SEL1,Sets the GPIO drive strength for IO pin 1" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "DRIVE_SEL0,Sets the GPIO drive strength for IO pin 0" "0: Please refer to architecture TRM section I/O..,1: Please refer to architecture TRM section I/O..,2: Please refer to architecture TRM section I/O..,3: Please refer to architecture TRM section I/O.."
|
|
newline
|
|
bitfld.long 0xC 7. "SLOW7,Enables slow slew rate for IO pin 7" "0,1"
|
|
bitfld.long 0xC 6. "SLOW6,Enables slow slew rate for IO pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "SLOW5,Enables slow slew rate for IO pin 5" "0,1"
|
|
bitfld.long 0xC 4. "SLOW4,Enables slow slew rate for IO pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "SLOW3,Enables slow slew rate for IO pin 3" "0,1"
|
|
bitfld.long 0xC 2. "SLOW2,Enables slow slew rate for IO pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "SLOW1,Enables slow slew rate for IO pin 1" "0,1"
|
|
bitfld.long 0xC 0. "SLOW0,Enables slow slew rate for IO pin 0" "0,1"
|
|
line.long 0x10 "CFG_SIO,Port SIO configuration register"
|
|
bitfld.long 0x10 29.--31. "VOH_SEL67,See corresponding definition for IO pins 0 and 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 27.--28. "VREF_SEL67,See corresponding definition for IO pins 0 and 1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 26. "VTRIP_SEL67,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
bitfld.long 0x10 25. "IBUF_SEL67,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
newline
|
|
bitfld.long 0x10 24. "VREG_EN67,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
bitfld.long 0x10 21.--23. "VOH_SEL45,See corresponding definition for IO pins 0 and 1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 19.--20. "VREF_SEL45,See corresponding definition for IO pins 0 and 1" "0,1,2,3"
|
|
bitfld.long 0x10 18. "VTRIP_SEL45,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
newline
|
|
bitfld.long 0x10 17. "IBUF_SEL45,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
bitfld.long 0x10 16. "VREG_EN45,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13.--15. "VOH_SEL23,See corresponding definition for IO pins 0 and 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 11.--12. "VREF_SEL23,See corresponding definition for IO pins 0 and 1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 10. "VTRIP_SEL23,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
bitfld.long 0x10 9. "IBUF_SEL23,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "VREG_EN23,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
bitfld.long 0x10 5.--7. "VOH_SEL01,Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'):" "0: Trip point=0,1: a) VREF_SEL=00,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x10 3.--4. "VREF_SEL01,Selects reference voltage (Vref) trip-point of the input buffer:" "0,1,2,3"
|
|
bitfld.long 0x10 2. "VTRIP_SEL01,Selects the input buffer trip-point in single ended input buffer mode (IBUF_SEL = '0'):" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "IBUF_SEL01,Selects the input buffer mode:" "0: Singled ended input buffer,1: Differential input buffer"
|
|
bitfld.long 0x10 0. "VREG_EN01,The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output.." "0,1"
|
|
group.long ($2+0x58)++0x3
|
|
line.long 0x0 "CFG_IN_AUTOLVL,Port input buffer AUTOLVL configuration register"
|
|
bitfld.long 0x0 7. "VTRIP_SEL7_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 6. "VTRIP_SEL6_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "VTRIP_SEL5_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 4. "VTRIP_SEL4_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "VTRIP_SEL3_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 2. "VTRIP_SEL2_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "VTRIP_SEL1_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 0. "VTRIP_SEL0_1,Configures the input buffer mode (trip points and hysteresis) for GPIO upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. This field is used along with CFG_IN.VTRIP_SEL0_0 field as below:" "0: input buffer is compatible with automotive,1: input buffer is compatible with automotive"
|
|
tree.end
|
|
repeat.end
|
|
repeat 3. (list 0x20 0x21 0x22)(list ad:0x40311000 ad:0x40311080 ad:0x40311100)
|
|
tree "PRT[$1]"
|
|
base $2
|
|
group.long ($2)++0xF
|
|
line.long 0x0 "OUT,Port output data register"
|
|
bitfld.long 0x0 7. "OUT7,IO output data for pin 7" "0,1"
|
|
bitfld.long 0x0 6. "OUT6,IO output data for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OUT5,IO output data for pin 5" "0,1"
|
|
bitfld.long 0x0 4. "OUT4,IO output data for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OUT3,IO output data for pin 3" "0,1"
|
|
bitfld.long 0x0 2. "OUT2,IO output data for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OUT1,IO output data for pin 1" "0,1"
|
|
bitfld.long 0x0 0. "OUT0,IO output data for pin 0" "0,1"
|
|
line.long 0x4 "OUT_CLR,Port output data clear register"
|
|
bitfld.long 0x4 7. "OUT7,IO clear output for pin 7" "0,1"
|
|
bitfld.long 0x4 6. "OUT6,IO clear output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OUT5,IO clear output for pin 5" "0,1"
|
|
bitfld.long 0x4 4. "OUT4,IO clear output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OUT3,IO clear output for pin 3" "0,1"
|
|
bitfld.long 0x4 2. "OUT2,IO clear output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "OUT1,IO clear output for pin 1" "0,1"
|
|
bitfld.long 0x4 0. "OUT0,IO clear output for pin 0:" "0,1"
|
|
line.long 0x8 "OUT_SET,Port output data set register"
|
|
bitfld.long 0x8 7. "OUT7,IO set output for pin 7" "0,1"
|
|
bitfld.long 0x8 6. "OUT6,IO set output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OUT5,IO set output for pin 5" "0,1"
|
|
bitfld.long 0x8 4. "OUT4,IO set output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "OUT3,IO set output for pin 3" "0,1"
|
|
bitfld.long 0x8 2. "OUT2,IO set output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "OUT1,IO set output for pin 1" "0,1"
|
|
bitfld.long 0x8 0. "OUT0,IO set output for pin 0:" "0,1"
|
|
line.long 0xC "OUT_INV,Port output data invert register"
|
|
bitfld.long 0xC 7. "OUT7,IO invert output for pin 7" "0,1"
|
|
bitfld.long 0xC 6. "OUT6,IO invert output for pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "OUT5,IO invert output for pin 5" "0,1"
|
|
bitfld.long 0xC 4. "OUT4,IO invert output for pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "OUT3,IO invert output for pin 3" "0,1"
|
|
bitfld.long 0xC 2. "OUT2,IO invert output for pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "OUT1,IO invert output for pin 1" "0,1"
|
|
bitfld.long 0xC 0. "OUT0,IO invert output for pin 0:" "0,1"
|
|
rgroup.long ($2+0x10)++0x3
|
|
line.long 0x0 "IN,Port input state register"
|
|
bitfld.long 0x0 8. "FLT_IN,Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register." "0,1"
|
|
bitfld.long 0x0 7. "IN7,IO pin state for pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "IN6,IO pin state for pin 6" "0,1"
|
|
bitfld.long 0x0 5. "IN5,IO pin state for pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IN4,IO pin state for pin 4" "0,1"
|
|
bitfld.long 0x0 3. "IN3,IO pin state for pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "IN2,IO pin state for pin 2" "0,1"
|
|
bitfld.long 0x0 1. "IN1,IO pin state for pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IN0,IO pin state for pin 0" "0,1"
|
|
group.long ($2+0x14)++0x7
|
|
line.long 0x0 "INTR,Port interrupt status register"
|
|
rbitfld.long 0x0 24. "FLT_IN_IN,Filtered pin state for pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
rbitfld.long 0x0 23. "IN_IN7,IO pin state for pin 7" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 22. "IN_IN6,IO pin state for pin 6" "0,1"
|
|
rbitfld.long 0x0 21. "IN_IN5,IO pin state for pin 5" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 20. "IN_IN4,IO pin state for pin 4" "0,1"
|
|
rbitfld.long 0x0 19. "IN_IN3,IO pin state for pin 3" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 18. "IN_IN2,IO pin state for pin 2" "0,1"
|
|
rbitfld.long 0x0 17. "IN_IN1,IO pin state for pin 1" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "IN_IN0,IO pin state for pin 0" "0,1"
|
|
bitfld.long 0x0 8. "FLT_EDGE,Edge detected on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "EDGE7,Edge detect for IO pin 7" "0,1"
|
|
bitfld.long 0x0 6. "EDGE6,Edge detect for IO pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EDGE5,Edge detect for IO pin 5" "0,1"
|
|
bitfld.long 0x0 4. "EDGE4,Edge detect for IO pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EDGE3,Edge detect for IO pin 3" "0,1"
|
|
bitfld.long 0x0 2. "EDGE2,Edge detect for IO pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EDGE1,Edge detect for IO pin 1" "0,1"
|
|
bitfld.long 0x0 0. "EDGE0,Edge detect for IO pin 0" "0,1"
|
|
line.long 0x4 "INTR_MASK,Port interrupt mask register"
|
|
bitfld.long 0x4 8. "FLT_EDGE,Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x4 7. "EDGE7,Masks edge interrupt on IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "EDGE6,Masks edge interrupt on IO pin 6" "0,1"
|
|
bitfld.long 0x4 5. "EDGE5,Masks edge interrupt on IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EDGE4,Masks edge interrupt on IO pin 4" "0,1"
|
|
bitfld.long 0x4 3. "EDGE3,Masks edge interrupt on IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "EDGE2,Masks edge interrupt on IO pin 2" "0,1"
|
|
bitfld.long 0x4 1. "EDGE1,Masks edge interrupt on IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "EDGE0,Masks edge interrupt on IO pin 0" "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Port interrupt masked status register"
|
|
bitfld.long 0x0 8. "FLT_EDGE,Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x0 7. "EDGE7,Edge detected and masked on IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "EDGE6,Edge detected and masked on IO pin 6" "0,1"
|
|
bitfld.long 0x0 5. "EDGE5,Edge detected and masked on IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EDGE4,Edge detected and masked on IO pin 4" "0,1"
|
|
bitfld.long 0x0 3. "EDGE3,Edge detected and masked on IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EDGE2,Edge detected and masked on IO pin 2" "0,1"
|
|
bitfld.long 0x0 1. "EDGE1,Edge detected and masked on IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EDGE0,Edge detected AND masked on IO pin 0" "0,1"
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "INTR_SET,Port interrupt set register"
|
|
bitfld.long 0x0 8. "FLT_EDGE,Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL" "0,1"
|
|
bitfld.long 0x0 7. "EDGE7,Sets edge detect interrupt for IO pin 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "EDGE6,Sets edge detect interrupt for IO pin 6" "0,1"
|
|
bitfld.long 0x0 5. "EDGE5,Sets edge detect interrupt for IO pin 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EDGE4,Sets edge detect interrupt for IO pin 4" "0,1"
|
|
bitfld.long 0x0 3. "EDGE3,Sets edge detect interrupt for IO pin 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EDGE2,Sets edge detect interrupt for IO pin 2" "0,1"
|
|
bitfld.long 0x0 1. "EDGE1,Sets edge detect interrupt for IO pin 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EDGE0,Sets edge detect interrupt for IO pin 0" "0,1"
|
|
group.long ($2+0x40)++0x13
|
|
line.long 0x0 "INTR_CFG,Port interrupt configuration register"
|
|
bitfld.long 0x0 18.--20. "FLT_SEL,Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--17. "FLT_EDGE_SEL,Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL" "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "EDGE7_SEL,Sets which edge will trigger an IRQ for IO pin 7" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "EDGE6_SEL,Sets which edge will trigger an IRQ for IO pin 6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "EDGE5_SEL,Sets which edge will trigger an IRQ for IO pin 5" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EDGE4_SEL,Sets which edge will trigger an IRQ for IO pin 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "EDGE3_SEL,Sets which edge will trigger an IRQ for IO pin 3" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "EDGE2_SEL,Sets which edge will trigger an IRQ for IO pin 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "EDGE1_SEL,Sets which edge will trigger an IRQ for IO pin 1" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "EDGE0_SEL,Sets which edge will trigger an IRQ for IO pin 0" "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
|
|
line.long 0x4 "CFG,Port configuration register"
|
|
bitfld.long 0x4 31. "IN_EN7,Enables the input buffer for IO pin 7" "0,1"
|
|
bitfld.long 0x4 28.--30. "DRIVE_MODE7,The GPIO drive mode for IO pin 7. Resistive pull-up and pull-down is selected in the drive mode." "0: Output buffer is off creating a high impedance..,1: N/A,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
newline
|
|
bitfld.long 0x4 27. "IN_EN6,Enables the input buffer for IO pin 6" "0,1"
|
|
bitfld.long 0x4 24.--26. "DRIVE_MODE6,The GPIO drive mode for IO pin 6. Resistive pull-up and pull-down is selected in the drive mode." "0: Output buffer is off creating a high impedance..,1: N/A,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
newline
|
|
bitfld.long 0x4 23. "IN_EN5,Enables the input buffer for IO pin 5" "0,1"
|
|
bitfld.long 0x4 20.--22. "DRIVE_MODE5,The GPIO drive mode for IO pin 5. Resistive pull-up and pull-down is selected in the drive mode." "0: Output buffer is off creating a high impedance..,1: N/A,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
newline
|
|
bitfld.long 0x4 19. "IN_EN4,Enables the input buffer for IO pin 4" "0,1"
|
|
bitfld.long 0x4 16.--18. "DRIVE_MODE4,The GPIO drive mode for IO pin 4. Resistive pull-up and pull-down is selected in the drive mode." "0: Output buffer is off creating a high impedance..,1: N/A,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
newline
|
|
bitfld.long 0x4 15. "IN_EN3,Enables the input buffer for IO pin 3" "0,1"
|
|
bitfld.long 0x4 12.--14. "DRIVE_MODE3,The GPIO drive mode for IO pin 3. Resistive pull-up and pull-down is selected in the drive mode." "0: Output buffer is off creating a high impedance..,1: N/A,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
newline
|
|
bitfld.long 0x4 11. "IN_EN2,Enables the input buffer for IO pin 2" "0,1"
|
|
bitfld.long 0x4 8.--10. "DRIVE_MODE2,The GPIO drive mode for IO pin 2. Resistive pull-up and pull-down is selected in the drive mode." "0: Output buffer is off creating a high impedance..,1: N/A,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
newline
|
|
bitfld.long 0x4 7. "IN_EN1,Enables the input buffer for IO pin 1" "0,1"
|
|
bitfld.long 0x4 4.--6. "DRIVE_MODE1,The GPIO drive mode for IO pin 1. Resistive pull-up and pull-down is selected in the drive mode." "0: Output buffer is off creating a high impedance..,1: N/A,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
newline
|
|
bitfld.long 0x4 3. "IN_EN0,Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue." "0,1"
|
|
bitfld.long 0x4 0.--2. "DRIVE_MODE0,The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode." "0: Output buffer is off creating a high impedance..,1: N/A,2: Resistive pull up For GPIO & UDB/DSI..,3: Resistive pull down For GPIO & UDB/DSI..,4: Open drain drives low For GPIO & UDB/DSI..,5: Open drain drives high For GPIO & UDB/DSI..,6: Strong D_OUTput buffer For GPIO & UDB/DSI..,7: Pull up or pull down For GPIO & UDB/DSI.."
|
|
line.long 0x8 "CFG_IN,Port input buffer configuration register"
|
|
bitfld.long 0x8 7. "VTRIP_SEL7_0,Configures the pin 7 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 6. "VTRIP_SEL6_0,Configures the pin 6 input buffer mode (trip points and hysteresis)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "VTRIP_SEL5_0,Configures the pin 5 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 4. "VTRIP_SEL4_0,Configures the pin 4 input buffer mode (trip points and hysteresis)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "VTRIP_SEL3_0,Configures the pin 3 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 2. "VTRIP_SEL2_0,Configures the pin 2 input buffer mode (trip points and hysteresis)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "VTRIP_SEL1_0,Configures the pin 1 input buffer mode (trip points and hysteresis)" "0,1"
|
|
bitfld.long 0x8 0. "VTRIP_SEL0_0,Configures the pin 0 input buffer mode (trip points and hysteresis)" "0: PSoC6:: Input buffer compatible with CMOS and..,1: PSoC6:: Input buffer compatible with TTL and.."
|
|
line.long 0xC "CFG_OUT,Port output buffer configuration register"
|
|
bitfld.long 0xC 30.--31. "DRIVE_SEL7,Sets the GPIO drive strength for IO pin 7" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "DRIVE_SEL6,Sets the GPIO drive strength for IO pin 6" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 26.--27. "DRIVE_SEL5,Sets the GPIO drive strength for IO pin 5" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "DRIVE_SEL4,Sets the GPIO drive strength for IO pin 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 22.--23. "DRIVE_SEL3,Sets the GPIO drive strength for IO pin 3" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "DRIVE_SEL2,Sets the GPIO drive strength for IO pin 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 18.--19. "DRIVE_SEL1,Sets the GPIO drive strength for IO pin 1" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "DRIVE_SEL0,Sets the GPIO drive strength for IO pin 0" "0: Please refer to architecture TRM section I/O..,1: Please refer to architecture TRM section I/O..,2: Please refer to architecture TRM section I/O..,3: Please refer to architecture TRM section I/O.."
|
|
newline
|
|
bitfld.long 0xC 7. "SLOW7,Enables slow slew rate for IO pin 7" "0,1"
|
|
bitfld.long 0xC 6. "SLOW6,Enables slow slew rate for IO pin 6" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "SLOW5,Enables slow slew rate for IO pin 5" "0,1"
|
|
bitfld.long 0xC 4. "SLOW4,Enables slow slew rate for IO pin 4" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "SLOW3,Enables slow slew rate for IO pin 3" "0,1"
|
|
bitfld.long 0xC 2. "SLOW2,Enables slow slew rate for IO pin 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "SLOW1,Enables slow slew rate for IO pin 1" "0,1"
|
|
bitfld.long 0xC 0. "SLOW0,Enables slow slew rate for IO pin 0" "0,1"
|
|
line.long 0x10 "CFG_SIO,Port SIO configuration register"
|
|
bitfld.long 0x10 29.--31. "VOH_SEL67,See corresponding definition for IO pins 0 and 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 27.--28. "VREF_SEL67,See corresponding definition for IO pins 0 and 1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 26. "VTRIP_SEL67,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
bitfld.long 0x10 25. "IBUF_SEL67,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
newline
|
|
bitfld.long 0x10 24. "VREG_EN67,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
bitfld.long 0x10 21.--23. "VOH_SEL45,See corresponding definition for IO pins 0 and 1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x10 19.--20. "VREF_SEL45,See corresponding definition for IO pins 0 and 1" "0,1,2,3"
|
|
bitfld.long 0x10 18. "VTRIP_SEL45,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
newline
|
|
bitfld.long 0x10 17. "IBUF_SEL45,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
bitfld.long 0x10 16. "VREG_EN45,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13.--15. "VOH_SEL23,See corresponding definition for IO pins 0 and 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 11.--12. "VREF_SEL23,See corresponding definition for IO pins 0 and 1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 10. "VTRIP_SEL23,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
bitfld.long 0x10 9. "IBUF_SEL23,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "VREG_EN23,See corresponding definition for IO pins 0 and 1" "0,1"
|
|
bitfld.long 0x10 5.--7. "VOH_SEL01,Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'):" "0: Trip point=0,1: a) VREF_SEL=00,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x10 3.--4. "VREF_SEL01,Selects reference voltage (Vref) trip-point of the input buffer:" "0,1,2,3"
|
|
bitfld.long 0x10 2. "VTRIP_SEL01,Selects the input buffer trip-point in single ended input buffer mode (IBUF_SEL = '0'):" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "IBUF_SEL01,Selects the input buffer mode:" "0: Singled ended input buffer,1: Differential input buffer"
|
|
bitfld.long 0x10 0. "VREG_EN01,The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output.." "0,1"
|
|
group.long ($2+0x58)++0x3
|
|
line.long 0x0 "CFG_IN_AUTOLVL,Port input buffer AUTOLVL configuration register"
|
|
bitfld.long 0x0 7. "VTRIP_SEL7_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 6. "VTRIP_SEL6_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "VTRIP_SEL5_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 4. "VTRIP_SEL4_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "VTRIP_SEL3_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 2. "VTRIP_SEL2_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "VTRIP_SEL1_1,Input buffer compatible with automotive (elevated Vil) interfaces." "0,1"
|
|
bitfld.long 0x0 0. "VTRIP_SEL0_1,Configures the input buffer mode (trip points and hysteresis) for GPIO upper bit. Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field. This field is used along with CFG_IN.VTRIP_SEL0_0 field as below:" "0: input buffer is compatible with automotive,1: input buffer is compatible with automotive"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40310000
|
|
rgroup.long 0x4000++0x13
|
|
line.long 0x0 "INTR_CAUSE0,Interrupt port cause register 0"
|
|
hexmask.long 0x0 0.--31. 1. "PORT_INT,Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line.."
|
|
line.long 0x4 "INTR_CAUSE1,Interrupt port cause register 1"
|
|
hexmask.long 0x4 0.--31. 1. "PORT_INT,Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line.."
|
|
line.long 0x8 "INTR_CAUSE2,Interrupt port cause register 2"
|
|
hexmask.long 0x8 0.--31. 1. "PORT_INT,Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line.."
|
|
line.long 0xC "INTR_CAUSE3,Interrupt port cause register 3"
|
|
hexmask.long 0xC 0.--31. 1. "PORT_INT,Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line.."
|
|
line.long 0x10 "VDD_ACTIVE,Extern power supply detection register"
|
|
bitfld.long 0x10 31. "VDDD_ACTIVE,This bit indicates presence of the VDDD supply. This bit will always read-back 1. The VDDD supply has robust brown-out protection monitoring and it is not possible to read back this register without a valid supply. (This bit is used in.." "0,1"
|
|
bitfld.long 0x10 30. "VDDA_ACTIVE,Same as VDDIO_ACTIVE for the analog supply VDDA." "0,1"
|
|
hexmask.long.word 0x10 0.--15. 1. "VDDIO_ACTIVE,Indicates presence or absence of VDDIO supplies (i.e. other than VDDD VDDA) on the device (supplies are numbered 0..n-1). Note that VDDIO supplies have basic (crude) supply detectors only. If separate robust brown-out detection is.."
|
|
group.long 0x4014++0x7
|
|
line.long 0x0 "VDD_INTR,Supply detection interrupt register"
|
|
bitfld.long 0x0 31. "VDDD_ACTIVE,The VDDD supply is always present during operation so a supply transition can not occur. This bit will always read back '1'." "0,1"
|
|
bitfld.long 0x0 30. "VDDA_ACTIVE,Same as VDDIO_ACTIVE for the analog supply VDDA." "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "VDDIO_ACTIVE,Supply state change detected."
|
|
line.long 0x4 "VDD_INTR_MASK,Supply detection interrupt mask register"
|
|
bitfld.long 0x4 31. "VDDD_ACTIVE,Same as VDDIO_ACTIVE for the digital supply VDDD." "0,1"
|
|
bitfld.long 0x4 30. "VDDA_ACTIVE,Same as VDDIO_ACTIVE for the analog supply VDDA." "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "VDDIO_ACTIVE,Masks supply interrupt on VDDIO."
|
|
rgroup.long 0x401C++0x3
|
|
line.long 0x0 "VDD_INTR_MASKED,Supply detection interrupt masked register"
|
|
bitfld.long 0x0 31. "VDDD_ACTIVE,Same as VDDIO_ACTIVE for the digital supply VDDD." "0,1"
|
|
bitfld.long 0x0 30. "VDDA_ACTIVE,Same as VDDIO_ACTIVE for the analog supply VDDA." "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "VDDIO_ACTIVE,Supply transition detected AND masked"
|
|
group.long 0x4020++0x3
|
|
line.long 0x0 "VDD_INTR_SET,Supply detection interrupt set register"
|
|
bitfld.long 0x0 31. "VDDD_ACTIVE,Same as VDDIO_ACTIVE for the digital supply VDDD." "0,1"
|
|
bitfld.long 0x0 30. "VDDA_ACTIVE,Same as VDDIO_ACTIVE for the analog supply VDDA." "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "VDDIO_ACTIVE,Sets supply interrupt."
|
|
tree.end
|
|
tree "HSIOM (High Speed IO Matrix)"
|
|
base ad:0x40300000
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40300000 ad:0x40300010 ad:0x40300020 ad:0x40300030 ad:0x40300040 ad:0x40300050 ad:0x40300060 ad:0x40300070 ad:0x40300080 ad:0x40300090 ad:0x403000A0 ad:0x403000B0 ad:0x403000C0 ad:0x403000D0 ad:0x403000E0 ad:0x403000F0)
|
|
tree "PRT[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "PORT_SEL0,Port selection 0"
|
|
hexmask.long.byte 0x0 24.--28. 1. "IO3_SEL,Selects the peripheral connections of Pin 3."
|
|
hexmask.long.byte 0x0 16.--20. 1. "IO2_SEL,Selects the peripheral connections of Pin 2."
|
|
hexmask.long.byte 0x0 8.--12. 1. "IO1_SEL,Selects the peripheral connections of Pin 1."
|
|
hexmask.long.byte 0x0 0.--4. 1. "IO0_SEL,Selects the peripheral connections of Pin 0. Note that available connectivity options vary depending on the device port and the pin. See the device Datasheet for a list of peripheral connections available at each pin."
|
|
line.long 0x4 "PORT_SEL1,Port selection 1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "IO7_SEL,Selects the peripheral connections of Pin 6."
|
|
hexmask.long.byte 0x4 16.--20. 1. "IO6_SEL,Selects the peripheral connections of Pin 5."
|
|
hexmask.long.byte 0x4 8.--12. 1. "IO5_SEL,Selects the peripheral connections of Pin 4."
|
|
hexmask.long.byte 0x4 0.--4. 1. "IO4_SEL,Selects the peripheral connections of Pin 4. See PORT_SEL0 for connection details."
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x40300100 ad:0x40300110 ad:0x40300120 ad:0x40300130 ad:0x40300140 ad:0x40300150 ad:0x40300160 ad:0x40300170 ad:0x40300180 ad:0x40300190 ad:0x403001A0 ad:0x403001B0 ad:0x403001C0 ad:0x403001D0 ad:0x403001E0 ad:0x403001F0)
|
|
tree "PRT[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "PORT_SEL0,Port selection 0"
|
|
hexmask.long.byte 0x0 24.--28. 1. "IO3_SEL,Selects the peripheral connections of Pin 3."
|
|
hexmask.long.byte 0x0 16.--20. 1. "IO2_SEL,Selects the peripheral connections of Pin 2."
|
|
hexmask.long.byte 0x0 8.--12. 1. "IO1_SEL,Selects the peripheral connections of Pin 1."
|
|
hexmask.long.byte 0x0 0.--4. 1. "IO0_SEL,Selects the peripheral connections of Pin 0. Note that available connectivity options vary depending on the device port and the pin. See the device Datasheet for a list of peripheral connections available at each pin."
|
|
line.long 0x4 "PORT_SEL1,Port selection 1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "IO7_SEL,Selects the peripheral connections of Pin 6."
|
|
hexmask.long.byte 0x4 16.--20. 1. "IO6_SEL,Selects the peripheral connections of Pin 5."
|
|
hexmask.long.byte 0x4 8.--12. 1. "IO5_SEL,Selects the peripheral connections of Pin 4."
|
|
hexmask.long.byte 0x4 0.--4. 1. "IO4_SEL,Selects the peripheral connections of Pin 4. See PORT_SEL0 for connection details."
|
|
tree.end
|
|
repeat.end
|
|
repeat 3. (list 0x20 0x21 0x22)(list ad:0x40300200 ad:0x40300210 ad:0x40300220)
|
|
tree "PRT[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "PORT_SEL0,Port selection 0"
|
|
hexmask.long.byte 0x0 24.--28. 1. "IO3_SEL,Selects the peripheral connections of Pin 3."
|
|
hexmask.long.byte 0x0 16.--20. 1. "IO2_SEL,Selects the peripheral connections of Pin 2."
|
|
hexmask.long.byte 0x0 8.--12. 1. "IO1_SEL,Selects the peripheral connections of Pin 1."
|
|
hexmask.long.byte 0x0 0.--4. 1. "IO0_SEL,Selects the peripheral connections of Pin 0. Note that available connectivity options vary depending on the device port and the pin. See the device Datasheet for a list of peripheral connections available at each pin."
|
|
line.long 0x4 "PORT_SEL1,Port selection 1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "IO7_SEL,Selects the peripheral connections of Pin 6."
|
|
hexmask.long.byte 0x4 16.--20. 1. "IO6_SEL,Selects the peripheral connections of Pin 5."
|
|
hexmask.long.byte 0x4 8.--12. 1. "IO5_SEL,Selects the peripheral connections of Pin 4."
|
|
hexmask.long.byte 0x4 0.--4. 1. "IO4_SEL,Selects the peripheral connections of Pin 4. See PORT_SEL0 for connection details."
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40300000
|
|
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x2000)++0x3
|
|
line.long 0x0 "AMUX_SPLIT_CTL[$1],AMUX splitter cell control"
|
|
bitfld.long 0x0 6. "SWITCH_BB_S0,T-switch control for AMUXBUSB vssa/ground switch." "0,1"
|
|
bitfld.long 0x0 5. "SWITCH_BB_SR,T-switch control for Right AMUXBUSB switch." "0,1"
|
|
bitfld.long 0x0 4. "SWITCH_BB_SL,T-switch control for Left AMUXBUSB switch." "0,1"
|
|
bitfld.long 0x0 2. "SWITCH_AA_S0,T-switch control for AMUXBUSA vssa/ground switch:" "0,1"
|
|
bitfld.long 0x0 1. "SWITCH_AA_SR,T-switch control for Right AMUXBUSA switch:" "0,1"
|
|
bitfld.long 0x0 0. "SWITCH_AA_SL,T-switch control for Left AMUXBUSA switch:" "0,1"
|
|
repeat.end
|
|
group.long 0x2200++0xF
|
|
line.long 0x0 "MONITOR_CTL_0,Power/Ground Monitor cell control 0"
|
|
hexmask.long 0x0 0.--31. 1. "MONITOR_EN,control for switch which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:"
|
|
line.long 0x4 "MONITOR_CTL_1,Power/Ground Monitor cell control 1"
|
|
hexmask.long 0x4 0.--31. 1. "MONITOR_EN,control for switch which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:"
|
|
line.long 0x8 "MONITOR_CTL_2,Power/Ground Monitor cell control 2"
|
|
hexmask.long 0x8 0.--31. 1. "MONITOR_EN,control for switch which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:"
|
|
line.long 0xC "MONITOR_CTL_3,Power/Ground Monitor cell control 3"
|
|
hexmask.long 0xC 0.--31. 1. "MONITOR_EN,control for switch which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:"
|
|
group.long 0x2240++0x3
|
|
line.long 0x0 "ALT_JTAG_EN,Alternate JTAG IF selection register"
|
|
bitfld.long 0x0 31. "ENABLE,Provides the selection for alternate JTAG IF connectivity." "0: Primary JTAG interface is selected,1: Secondary"
|
|
tree.end
|
|
tree "I2S (Inter-IC Sound)"
|
|
base ad:0x0
|
|
tree "I2S0"
|
|
base ad:0x40800000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "RX_ENABLED,Enables the I2S RX component:" "0,1"
|
|
bitfld.long 0x0 30. "TX_ENABLED,Enables the I2S TX component:" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "CLOCK_CTL,Clock control"
|
|
bitfld.long 0x0 16. "MCLK_EN,Enable MCLK - enables MCLK divider operation" "0,1"
|
|
bitfld.long 0x0 12.--13. "MCLK_DIV,Selects clock divider for MCLK_OUT." "0: Divide clk_audio_i2s by 1 (Bypass),1: Divide clk_audio_i2s by 2,2: Divide clk_audio_i2s by 4,3: Divide clk-audio_i2s by 8"
|
|
newline
|
|
bitfld.long 0x0 8. "CLOCK_SEL,Selects clock to be used by I2S:" "0,1"
|
|
hexmask.long.byte 0x0 0.--5. 1. "CLOCK_DIV,Frequency divisor for generating I2S clock frequency."
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "CLOCK_STAT,Clock Status"
|
|
bitfld.long 0x0 0. "MCLK_DIV_OFF,MCLK Divider OFF" "0: Indicates MCLK Divider not a reset state,1: Indicates MCLK Divider at reset state"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "CMD,Command"
|
|
bitfld.long 0x0 16. "RX_START,Receiver enable:" "0,1"
|
|
bitfld.long 0x0 8. "TX_PAUSE,Pause enable:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TX_START,Transmitter enable:" "0,1"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "TR_CTL,Trigger control"
|
|
bitfld.long 0x0 16. "RX_REQ_EN,Trigger output ('tr_i2s_rx_req') enable for requests of DMA transfer in reception" "0,1"
|
|
bitfld.long 0x0 0. "TX_REQ_EN,Trigger output ('tr_i2s_tx_req') enable for requests of DMA transfer in transmission" "0,1"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "TX_CTL,Transmitter control"
|
|
bitfld.long 0x0 25. "SCKI_POL,TX slave bit clock polarity." "0,1"
|
|
bitfld.long 0x0 24. "SCKO_POL,TX master bit clock polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--22. "WORD_LEN,Word length in number of bits:" "0: 8-bit,1: 16-bit,2: 18-bit,3: 20-bit,4: 24-bit,5: 32-bit,?,?"
|
|
bitfld.long 0x0 16.--18. "CH_LEN,Channel length in number of bits:" "0: 8-bit,1: 16-bit,2: 18-bit,3: 20-bit,4: 24-bit,5: 32-bit,?,?"
|
|
newline
|
|
bitfld.long 0x0 13. "WD_EN,Set watchdog for 'tx_ws_in':" "0,1"
|
|
bitfld.long 0x0 12. "OVHDATA,Set overhead value:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "WS_PULSE,Set WS pulse width in TDM mode:" "0: Pulse width is 1 SCK period,1: Pulse width is 1 channel length"
|
|
bitfld.long 0x0 8.--9. "I2S_MODE,Select I2S left-justified or TDM:" "0: Left Justified,1: I2S mode,2: TDM mode A the 1st Channel align to WSO Rising..,3: TDM mode B the 1st Channel align to WSO Rising.."
|
|
newline
|
|
bitfld.long 0x0 7. "MS,Set interface in master or slave mode:" "0: Slave,1: Master"
|
|
bitfld.long 0x0 4.--6. "CH_NR,Specifies number of channels per frame:" "0: 1 channel,1: 2 channels,2: 3 channels,3: 4 channels,4: 5 channels,5: 6 channels,6: 7 channels,7: 8 channels"
|
|
newline
|
|
bitfld.long 0x0 3. "B_CLOCK_INV,Serial data transmission is advanced by 0.5 SCK cycles. This bit is valid only in TX slave mode." "0: Serial data will be transmitted off the SCK..,1: Serial data will be transmitted off the SCK.."
|
|
line.long 0x4 "TX_WATCHDOG,Transmitter watchdog"
|
|
hexmask.long 0x4 0.--31. 1. "WD_COUNTER,Start value of the TX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock 'clk_sys'."
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "RX_CTL,Receiver control"
|
|
bitfld.long 0x0 25. "SCKI_POL,RX slave bit clock polarity." "0,1"
|
|
bitfld.long 0x0 24. "SCKO_POL,RX master bit clock polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "BIT_EXTENSION,When reception word length is shorter than the word length of RX_FIFO_RD extension mode of upper bit should be set." "0,1"
|
|
bitfld.long 0x0 20.--22. "WORD_LEN,Word length in number of bits:" "0: 8-bit,1: 16-bit,2: 18-bit,3: 20-bit,4: 24-bit,5: 32-bit,?,?"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "CH_LEN,Channel length in number of bits:" "0: 8-bit,1: 16-bit,2: 18-bit,3: 20-bit,4: 24-bit,5: 32-bit,?,?"
|
|
bitfld.long 0x0 13. "WD_EN,Set watchdog for 'rx_ws_in'" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "WS_PULSE,Set WS pulse width in TDM mode:" "0: Pulse width is 1 SCK period,1: Pulse width is 1 channel length"
|
|
bitfld.long 0x0 8.--9. "I2S_MODE,Select I2S left-justified or TDM:" "0: Left Justified,1: I2S mode,2: TDM mode A the 1st Channel align to WSO Rising..,3: TDM mode B the 1st Channel align to WSO Rising.."
|
|
newline
|
|
bitfld.long 0x0 7. "MS,Set interface in master or slave mode:" "0: Slave,1: Master"
|
|
bitfld.long 0x0 4.--6. "CH_NR,Specifies number of channels per frame:" "0: 1 channel,1: 2 channels,2: 3 channels,3: 4 channels,4: 5 channels,5: 6 channels,6: 7 channels,7: 8 channels"
|
|
newline
|
|
bitfld.long 0x0 3. "B_CLOCK_INV,Serial data capture is delayed by 0.5 SCK cycles. This bit is valid only in RX master mode." "0: Serial data will be captured by the SCK falling..,1: Serial data will be captured by the SCK rising.."
|
|
line.long 0x4 "RX_WATCHDOG,Receiver watchdog"
|
|
hexmask.long 0x4 0.--31. 1. "WD_COUNTER,Start value of the RX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock 'clk_sys'."
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "TX_FIFO_CTL,TX FIFO control"
|
|
bitfld.long 0x0 17. "FREEZE,When '1' hardware reads from the TX FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer. This field is used only for debugging purposes." "0,1"
|
|
bitfld.long 0x0 16. "CLEAR,When '1' the TX FIFO and TX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the TX FIFO has less entries than the number of this field a transmitter trigger event is generated."
|
|
rgroup.long 0x204++0x3
|
|
line.long 0x0 "TX_FIFO_STATUS,TX FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,TX FIFO write pointer: FIFO location at which a new data frame is written by the host. This field is used only for debugging purposes."
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,TX FIFO read pointer: FIFO location from which a data frame is read by the hardware.This field is used only for debugging purposes."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "USED,Number of entries in the TX FIFO. The field value is in the range [0 256]."
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "TX_FIFO_WR,TX FIFO write"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data written into the TX FIFO. Behavior is similar to that of a PUSH operation."
|
|
group.long 0x300++0x3
|
|
line.long 0x0 "RX_FIFO_CTL,RX FIFO control"
|
|
bitfld.long 0x0 17. "FREEZE,When '1' hardware writes to the RX FIFO have no effect. Freeze will not advance the RX FIFO write pointer. This field is used only for debugging purposee." "0,1"
|
|
bitfld.long 0x0 16. "CLEAR,When '1' the RX FIFO and RX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the RX FIFO has more entries than the number of this field a receiver trigger event is generated."
|
|
rgroup.long 0x304++0xB
|
|
line.long 0x0 "RX_FIFO_STATUS,RX FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,RX FIFO write pointer: FIFO location at which a new data frame is written by the hardware. This field is used only for debugging purposes."
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,RX FIFO read pointer: FIFO location from which a data frame is read by the host. This field is used only for debugging purposes."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "USED,Number of entries in the RX FIFO. The field value is in the range [0 256]."
|
|
line.long 0x4 "RX_FIFO_RD,RX FIFO read"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data read from the RX FIFO. Reading a data frame will remove the data frame from the RX FIFO; i.e. behavior is similar to that of a POP operation."
|
|
line.long 0x8 "RX_FIFO_RD_SILENT,RX FIFO silent read"
|
|
hexmask.long 0x8 0.--31. 1. "DATA,Data read from the RX FIFO. Reading a data frame will NOT remove the data frame from the RX FIFO; i.e. behavior is similar to that of a PEEK operation. This field is used only for debugging purposes."
|
|
group.long 0xF00++0xB
|
|
line.long 0x0 "INTR,Interrupt register"
|
|
bitfld.long 0x0 24. "RX_WD,Triggers (sets to '1') when the Rx watchdog event occurs." "0,1"
|
|
bitfld.long 0x0 22. "RX_UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "RX_OVERFLOW,Attempt to write to a full RX FIFO." "0,1"
|
|
bitfld.long 0x0 19. "RX_FULL,RX FIFO is full." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RX_NOT_EMPTY,RX FIFO is not empty." "0,1"
|
|
bitfld.long 0x0 16. "RX_TRIGGER,More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTRL." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TX_WD,Triggers (sets to '1') when the Tx watchdog event occurs." "0,1"
|
|
bitfld.long 0x0 6. "TX_UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and TX_EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TX_OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
|
|
bitfld.long 0x0 4. "TX_EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TX_NOT_FULL,TX FIFO is not full." "0,1"
|
|
bitfld.long 0x0 0. "TX_TRIGGER,Less entries in the TX FIFO than the value specified by TRIGGER_LEVEL in TX_FIFO_CTRL." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set register"
|
|
bitfld.long 0x4 24. "RX_WD,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 22. "RX_UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "RX_OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 19. "RX_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "RX_NOT_EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 16. "RX_TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TX_WD,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 6. "TX_UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "TX_OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 4. "TX_EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TX_NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 0. "TX_TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x8 24. "RX_WD,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 22. "RX_UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "RX_OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 19. "RX_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 18. "RX_NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 16. "RX_TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "TX_WD,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 6. "TX_UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "TX_OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 4. "TX_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "TX_NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 0. "TX_TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked register"
|
|
bitfld.long 0x0 24. "RX_WD,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 22. "RX_UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "RX_OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 19. "RX_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RX_NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 16. "RX_TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TX_WD,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 6. "TX_UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TX_OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 4. "TX_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TX_NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 0. "TX_TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
tree "I2S1"
|
|
base ad:0x40801000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "RX_ENABLED,Enables the I2S RX component:" "0,1"
|
|
bitfld.long 0x0 30. "TX_ENABLED,Enables the I2S TX component:" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "CLOCK_CTL,Clock control"
|
|
bitfld.long 0x0 16. "MCLK_EN,Enable MCLK - enables MCLK divider operation" "0,1"
|
|
bitfld.long 0x0 12.--13. "MCLK_DIV,Selects clock divider for MCLK_OUT." "0: Divide clk_audio_i2s by 1 (Bypass),1: Divide clk_audio_i2s by 2,2: Divide clk_audio_i2s by 4,3: Divide clk-audio_i2s by 8"
|
|
newline
|
|
bitfld.long 0x0 8. "CLOCK_SEL,Selects clock to be used by I2S:" "0,1"
|
|
hexmask.long.byte 0x0 0.--5. 1. "CLOCK_DIV,Frequency divisor for generating I2S clock frequency."
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "CLOCK_STAT,Clock Status"
|
|
bitfld.long 0x0 0. "MCLK_DIV_OFF,MCLK Divider OFF" "0: Indicates MCLK Divider not a reset state,1: Indicates MCLK Divider at reset state"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "CMD,Command"
|
|
bitfld.long 0x0 16. "RX_START,Receiver enable:" "0,1"
|
|
bitfld.long 0x0 8. "TX_PAUSE,Pause enable:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TX_START,Transmitter enable:" "0,1"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "TR_CTL,Trigger control"
|
|
bitfld.long 0x0 16. "RX_REQ_EN,Trigger output ('tr_i2s_rx_req') enable for requests of DMA transfer in reception" "0,1"
|
|
bitfld.long 0x0 0. "TX_REQ_EN,Trigger output ('tr_i2s_tx_req') enable for requests of DMA transfer in transmission" "0,1"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "TX_CTL,Transmitter control"
|
|
bitfld.long 0x0 25. "SCKI_POL,TX slave bit clock polarity." "0,1"
|
|
bitfld.long 0x0 24. "SCKO_POL,TX master bit clock polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--22. "WORD_LEN,Word length in number of bits:" "0: 8-bit,1: 16-bit,2: 18-bit,3: 20-bit,4: 24-bit,5: 32-bit,?,?"
|
|
bitfld.long 0x0 16.--18. "CH_LEN,Channel length in number of bits:" "0: 8-bit,1: 16-bit,2: 18-bit,3: 20-bit,4: 24-bit,5: 32-bit,?,?"
|
|
newline
|
|
bitfld.long 0x0 13. "WD_EN,Set watchdog for 'tx_ws_in':" "0,1"
|
|
bitfld.long 0x0 12. "OVHDATA,Set overhead value:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "WS_PULSE,Set WS pulse width in TDM mode:" "0: Pulse width is 1 SCK period,1: Pulse width is 1 channel length"
|
|
bitfld.long 0x0 8.--9. "I2S_MODE,Select I2S left-justified or TDM:" "0: Left Justified,1: I2S mode,2: TDM mode A the 1st Channel align to WSO Rising..,3: TDM mode B the 1st Channel align to WSO Rising.."
|
|
newline
|
|
bitfld.long 0x0 7. "MS,Set interface in master or slave mode:" "0: Slave,1: Master"
|
|
bitfld.long 0x0 4.--6. "CH_NR,Specifies number of channels per frame:" "0: 1 channel,1: 2 channels,2: 3 channels,3: 4 channels,4: 5 channels,5: 6 channels,6: 7 channels,7: 8 channels"
|
|
newline
|
|
bitfld.long 0x0 3. "B_CLOCK_INV,Serial data transmission is advanced by 0.5 SCK cycles. This bit is valid only in TX slave mode." "0: Serial data will be transmitted off the SCK..,1: Serial data will be transmitted off the SCK.."
|
|
line.long 0x4 "TX_WATCHDOG,Transmitter watchdog"
|
|
hexmask.long 0x4 0.--31. 1. "WD_COUNTER,Start value of the TX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock 'clk_sys'."
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "RX_CTL,Receiver control"
|
|
bitfld.long 0x0 25. "SCKI_POL,RX slave bit clock polarity." "0,1"
|
|
bitfld.long 0x0 24. "SCKO_POL,RX master bit clock polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "BIT_EXTENSION,When reception word length is shorter than the word length of RX_FIFO_RD extension mode of upper bit should be set." "0,1"
|
|
bitfld.long 0x0 20.--22. "WORD_LEN,Word length in number of bits:" "0: 8-bit,1: 16-bit,2: 18-bit,3: 20-bit,4: 24-bit,5: 32-bit,?,?"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "CH_LEN,Channel length in number of bits:" "0: 8-bit,1: 16-bit,2: 18-bit,3: 20-bit,4: 24-bit,5: 32-bit,?,?"
|
|
bitfld.long 0x0 13. "WD_EN,Set watchdog for 'rx_ws_in'" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "WS_PULSE,Set WS pulse width in TDM mode:" "0: Pulse width is 1 SCK period,1: Pulse width is 1 channel length"
|
|
bitfld.long 0x0 8.--9. "I2S_MODE,Select I2S left-justified or TDM:" "0: Left Justified,1: I2S mode,2: TDM mode A the 1st Channel align to WSO Rising..,3: TDM mode B the 1st Channel align to WSO Rising.."
|
|
newline
|
|
bitfld.long 0x0 7. "MS,Set interface in master or slave mode:" "0: Slave,1: Master"
|
|
bitfld.long 0x0 4.--6. "CH_NR,Specifies number of channels per frame:" "0: 1 channel,1: 2 channels,2: 3 channels,3: 4 channels,4: 5 channels,5: 6 channels,6: 7 channels,7: 8 channels"
|
|
newline
|
|
bitfld.long 0x0 3. "B_CLOCK_INV,Serial data capture is delayed by 0.5 SCK cycles. This bit is valid only in RX master mode." "0: Serial data will be captured by the SCK falling..,1: Serial data will be captured by the SCK rising.."
|
|
line.long 0x4 "RX_WATCHDOG,Receiver watchdog"
|
|
hexmask.long 0x4 0.--31. 1. "WD_COUNTER,Start value of the RX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock 'clk_sys'."
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "TX_FIFO_CTL,TX FIFO control"
|
|
bitfld.long 0x0 17. "FREEZE,When '1' hardware reads from the TX FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer. This field is used only for debugging purposes." "0,1"
|
|
bitfld.long 0x0 16. "CLEAR,When '1' the TX FIFO and TX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the TX FIFO has less entries than the number of this field a transmitter trigger event is generated."
|
|
rgroup.long 0x204++0x3
|
|
line.long 0x0 "TX_FIFO_STATUS,TX FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,TX FIFO write pointer: FIFO location at which a new data frame is written by the host. This field is used only for debugging purposes."
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,TX FIFO read pointer: FIFO location from which a data frame is read by the hardware.This field is used only for debugging purposes."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "USED,Number of entries in the TX FIFO. The field value is in the range [0 256]."
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "TX_FIFO_WR,TX FIFO write"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data written into the TX FIFO. Behavior is similar to that of a PUSH operation."
|
|
group.long 0x300++0x3
|
|
line.long 0x0 "RX_FIFO_CTL,RX FIFO control"
|
|
bitfld.long 0x0 17. "FREEZE,When '1' hardware writes to the RX FIFO have no effect. Freeze will not advance the RX FIFO write pointer. This field is used only for debugging purposee." "0,1"
|
|
bitfld.long 0x0 16. "CLEAR,When '1' the RX FIFO and RX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the RX FIFO has more entries than the number of this field a receiver trigger event is generated."
|
|
rgroup.long 0x304++0xB
|
|
line.long 0x0 "RX_FIFO_STATUS,RX FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,RX FIFO write pointer: FIFO location at which a new data frame is written by the hardware. This field is used only for debugging purposes."
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,RX FIFO read pointer: FIFO location from which a data frame is read by the host. This field is used only for debugging purposes."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "USED,Number of entries in the RX FIFO. The field value is in the range [0 256]."
|
|
line.long 0x4 "RX_FIFO_RD,RX FIFO read"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data read from the RX FIFO. Reading a data frame will remove the data frame from the RX FIFO; i.e. behavior is similar to that of a POP operation."
|
|
line.long 0x8 "RX_FIFO_RD_SILENT,RX FIFO silent read"
|
|
hexmask.long 0x8 0.--31. 1. "DATA,Data read from the RX FIFO. Reading a data frame will NOT remove the data frame from the RX FIFO; i.e. behavior is similar to that of a PEEK operation. This field is used only for debugging purposes."
|
|
group.long 0xF00++0xB
|
|
line.long 0x0 "INTR,Interrupt register"
|
|
bitfld.long 0x0 24. "RX_WD,Triggers (sets to '1') when the Rx watchdog event occurs." "0,1"
|
|
bitfld.long 0x0 22. "RX_UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "RX_OVERFLOW,Attempt to write to a full RX FIFO." "0,1"
|
|
bitfld.long 0x0 19. "RX_FULL,RX FIFO is full." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RX_NOT_EMPTY,RX FIFO is not empty." "0,1"
|
|
bitfld.long 0x0 16. "RX_TRIGGER,More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTRL." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TX_WD,Triggers (sets to '1') when the Tx watchdog event occurs." "0,1"
|
|
bitfld.long 0x0 6. "TX_UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and TX_EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TX_OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
|
|
bitfld.long 0x0 4. "TX_EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TX_NOT_FULL,TX FIFO is not full." "0,1"
|
|
bitfld.long 0x0 0. "TX_TRIGGER,Less entries in the TX FIFO than the value specified by TRIGGER_LEVEL in TX_FIFO_CTRL." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set register"
|
|
bitfld.long 0x4 24. "RX_WD,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 22. "RX_UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "RX_OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 19. "RX_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "RX_NOT_EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 16. "RX_TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TX_WD,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 6. "TX_UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "TX_OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 4. "TX_EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TX_NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 0. "TX_TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x8 24. "RX_WD,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 22. "RX_UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "RX_OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 19. "RX_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 18. "RX_NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 16. "RX_TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "TX_WD,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 6. "TX_UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "TX_OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 4. "TX_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "TX_NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 0. "TX_TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked register"
|
|
bitfld.long 0x0 24. "RX_WD,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 22. "RX_UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "RX_OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 19. "RX_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RX_NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 16. "RX_TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TX_WD,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 6. "TX_UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TX_OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 4. "TX_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TX_NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 0. "TX_TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
tree "I2S2"
|
|
base ad:0x40802000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "RX_ENABLED,Enables the I2S RX component:" "0,1"
|
|
bitfld.long 0x0 30. "TX_ENABLED,Enables the I2S TX component:" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "CLOCK_CTL,Clock control"
|
|
bitfld.long 0x0 16. "MCLK_EN,Enable MCLK - enables MCLK divider operation" "0,1"
|
|
bitfld.long 0x0 12.--13. "MCLK_DIV,Selects clock divider for MCLK_OUT." "0: Divide clk_audio_i2s by 1 (Bypass),1: Divide clk_audio_i2s by 2,2: Divide clk_audio_i2s by 4,3: Divide clk-audio_i2s by 8"
|
|
newline
|
|
bitfld.long 0x0 8. "CLOCK_SEL,Selects clock to be used by I2S:" "0,1"
|
|
hexmask.long.byte 0x0 0.--5. 1. "CLOCK_DIV,Frequency divisor for generating I2S clock frequency."
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "CLOCK_STAT,Clock Status"
|
|
bitfld.long 0x0 0. "MCLK_DIV_OFF,MCLK Divider OFF" "0: Indicates MCLK Divider not a reset state,1: Indicates MCLK Divider at reset state"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "CMD,Command"
|
|
bitfld.long 0x0 16. "RX_START,Receiver enable:" "0,1"
|
|
bitfld.long 0x0 8. "TX_PAUSE,Pause enable:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TX_START,Transmitter enable:" "0,1"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "TR_CTL,Trigger control"
|
|
bitfld.long 0x0 16. "RX_REQ_EN,Trigger output ('tr_i2s_rx_req') enable for requests of DMA transfer in reception" "0,1"
|
|
bitfld.long 0x0 0. "TX_REQ_EN,Trigger output ('tr_i2s_tx_req') enable for requests of DMA transfer in transmission" "0,1"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "TX_CTL,Transmitter control"
|
|
bitfld.long 0x0 25. "SCKI_POL,TX slave bit clock polarity." "0,1"
|
|
bitfld.long 0x0 24. "SCKO_POL,TX master bit clock polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--22. "WORD_LEN,Word length in number of bits:" "0: 8-bit,1: 16-bit,2: 18-bit,3: 20-bit,4: 24-bit,5: 32-bit,?,?"
|
|
bitfld.long 0x0 16.--18. "CH_LEN,Channel length in number of bits:" "0: 8-bit,1: 16-bit,2: 18-bit,3: 20-bit,4: 24-bit,5: 32-bit,?,?"
|
|
newline
|
|
bitfld.long 0x0 13. "WD_EN,Set watchdog for 'tx_ws_in':" "0,1"
|
|
bitfld.long 0x0 12. "OVHDATA,Set overhead value:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "WS_PULSE,Set WS pulse width in TDM mode:" "0: Pulse width is 1 SCK period,1: Pulse width is 1 channel length"
|
|
bitfld.long 0x0 8.--9. "I2S_MODE,Select I2S left-justified or TDM:" "0: Left Justified,1: I2S mode,2: TDM mode A the 1st Channel align to WSO Rising..,3: TDM mode B the 1st Channel align to WSO Rising.."
|
|
newline
|
|
bitfld.long 0x0 7. "MS,Set interface in master or slave mode:" "0: Slave,1: Master"
|
|
bitfld.long 0x0 4.--6. "CH_NR,Specifies number of channels per frame:" "0: 1 channel,1: 2 channels,2: 3 channels,3: 4 channels,4: 5 channels,5: 6 channels,6: 7 channels,7: 8 channels"
|
|
newline
|
|
bitfld.long 0x0 3. "B_CLOCK_INV,Serial data transmission is advanced by 0.5 SCK cycles. This bit is valid only in TX slave mode." "0: Serial data will be transmitted off the SCK..,1: Serial data will be transmitted off the SCK.."
|
|
line.long 0x4 "TX_WATCHDOG,Transmitter watchdog"
|
|
hexmask.long 0x4 0.--31. 1. "WD_COUNTER,Start value of the TX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock 'clk_sys'."
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "RX_CTL,Receiver control"
|
|
bitfld.long 0x0 25. "SCKI_POL,RX slave bit clock polarity." "0,1"
|
|
bitfld.long 0x0 24. "SCKO_POL,RX master bit clock polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "BIT_EXTENSION,When reception word length is shorter than the word length of RX_FIFO_RD extension mode of upper bit should be set." "0,1"
|
|
bitfld.long 0x0 20.--22. "WORD_LEN,Word length in number of bits:" "0: 8-bit,1: 16-bit,2: 18-bit,3: 20-bit,4: 24-bit,5: 32-bit,?,?"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "CH_LEN,Channel length in number of bits:" "0: 8-bit,1: 16-bit,2: 18-bit,3: 20-bit,4: 24-bit,5: 32-bit,?,?"
|
|
bitfld.long 0x0 13. "WD_EN,Set watchdog for 'rx_ws_in'" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "WS_PULSE,Set WS pulse width in TDM mode:" "0: Pulse width is 1 SCK period,1: Pulse width is 1 channel length"
|
|
bitfld.long 0x0 8.--9. "I2S_MODE,Select I2S left-justified or TDM:" "0: Left Justified,1: I2S mode,2: TDM mode A the 1st Channel align to WSO Rising..,3: TDM mode B the 1st Channel align to WSO Rising.."
|
|
newline
|
|
bitfld.long 0x0 7. "MS,Set interface in master or slave mode:" "0: Slave,1: Master"
|
|
bitfld.long 0x0 4.--6. "CH_NR,Specifies number of channels per frame:" "0: 1 channel,1: 2 channels,2: 3 channels,3: 4 channels,4: 5 channels,5: 6 channels,6: 7 channels,7: 8 channels"
|
|
newline
|
|
bitfld.long 0x0 3. "B_CLOCK_INV,Serial data capture is delayed by 0.5 SCK cycles. This bit is valid only in RX master mode." "0: Serial data will be captured by the SCK falling..,1: Serial data will be captured by the SCK rising.."
|
|
line.long 0x4 "RX_WATCHDOG,Receiver watchdog"
|
|
hexmask.long 0x4 0.--31. 1. "WD_COUNTER,Start value of the RX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock 'clk_sys'."
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "TX_FIFO_CTL,TX FIFO control"
|
|
bitfld.long 0x0 17. "FREEZE,When '1' hardware reads from the TX FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer. This field is used only for debugging purposes." "0,1"
|
|
bitfld.long 0x0 16. "CLEAR,When '1' the TX FIFO and TX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the TX FIFO has less entries than the number of this field a transmitter trigger event is generated."
|
|
rgroup.long 0x204++0x3
|
|
line.long 0x0 "TX_FIFO_STATUS,TX FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,TX FIFO write pointer: FIFO location at which a new data frame is written by the host. This field is used only for debugging purposes."
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,TX FIFO read pointer: FIFO location from which a data frame is read by the hardware.This field is used only for debugging purposes."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "USED,Number of entries in the TX FIFO. The field value is in the range [0 256]."
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "TX_FIFO_WR,TX FIFO write"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data written into the TX FIFO. Behavior is similar to that of a PUSH operation."
|
|
group.long 0x300++0x3
|
|
line.long 0x0 "RX_FIFO_CTL,RX FIFO control"
|
|
bitfld.long 0x0 17. "FREEZE,When '1' hardware writes to the RX FIFO have no effect. Freeze will not advance the RX FIFO write pointer. This field is used only for debugging purposee." "0,1"
|
|
bitfld.long 0x0 16. "CLEAR,When '1' the RX FIFO and RX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is.." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the RX FIFO has more entries than the number of this field a receiver trigger event is generated."
|
|
rgroup.long 0x304++0xB
|
|
line.long 0x0 "RX_FIFO_STATUS,RX FIFO status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,RX FIFO write pointer: FIFO location at which a new data frame is written by the hardware. This field is used only for debugging purposes."
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,RX FIFO read pointer: FIFO location from which a data frame is read by the host. This field is used only for debugging purposes."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "USED,Number of entries in the RX FIFO. The field value is in the range [0 256]."
|
|
line.long 0x4 "RX_FIFO_RD,RX FIFO read"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data read from the RX FIFO. Reading a data frame will remove the data frame from the RX FIFO; i.e. behavior is similar to that of a POP operation."
|
|
line.long 0x8 "RX_FIFO_RD_SILENT,RX FIFO silent read"
|
|
hexmask.long 0x8 0.--31. 1. "DATA,Data read from the RX FIFO. Reading a data frame will NOT remove the data frame from the RX FIFO; i.e. behavior is similar to that of a PEEK operation. This field is used only for debugging purposes."
|
|
group.long 0xF00++0xB
|
|
line.long 0x0 "INTR,Interrupt register"
|
|
bitfld.long 0x0 24. "RX_WD,Triggers (sets to '1') when the Rx watchdog event occurs." "0,1"
|
|
bitfld.long 0x0 22. "RX_UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "RX_OVERFLOW,Attempt to write to a full RX FIFO." "0,1"
|
|
bitfld.long 0x0 19. "RX_FULL,RX FIFO is full." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RX_NOT_EMPTY,RX FIFO is not empty." "0,1"
|
|
bitfld.long 0x0 16. "RX_TRIGGER,More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTRL." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TX_WD,Triggers (sets to '1') when the Tx watchdog event occurs." "0,1"
|
|
bitfld.long 0x0 6. "TX_UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and TX_EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TX_OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
|
|
bitfld.long 0x0 4. "TX_EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TX_NOT_FULL,TX FIFO is not full." "0,1"
|
|
bitfld.long 0x0 0. "TX_TRIGGER,Less entries in the TX FIFO than the value specified by TRIGGER_LEVEL in TX_FIFO_CTRL." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set register"
|
|
bitfld.long 0x4 24. "RX_WD,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 22. "RX_UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "RX_OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 19. "RX_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "RX_NOT_EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 16. "RX_TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TX_WD,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 6. "TX_UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "TX_OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 4. "TX_EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TX_NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x4 0. "TX_TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x8 24. "RX_WD,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 22. "RX_UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "RX_OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 19. "RX_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 18. "RX_NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 16. "RX_TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "TX_WD,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 6. "TX_UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "TX_OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 4. "TX_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "TX_NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
bitfld.long 0x8 0. "TX_TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked register"
|
|
bitfld.long 0x0 24. "RX_WD,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 22. "RX_UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "RX_OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 19. "RX_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RX_NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 16. "RX_TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TX_WD,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 6. "TX_UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TX_OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 4. "TX_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TX_NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 0. "TX_TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "IPC (Interprocessor Communication)"
|
|
base ad:0x40220000
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40220000 ad:0x40220020 ad:0x40220040 ad:0x40220060 ad:0x40220080 ad:0x402200A0 ad:0x402200C0 ad:0x402200E0 ad:0x40220100 ad:0x40220120 ad:0x40220140 ad:0x40220160 ad:0x40220180 ad:0x402201A0 ad:0x402201C0 ad:0x402201E0)
|
|
tree "STRUCT[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "ACQUIRE,IPC acquire"
|
|
bitfld.long 0x0 31. "SUCCESS,Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED):" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MS,This field specifies the bus master identifier that successfully acquired the lock."
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,This field specifies the protection context that successfully acquired the lock."
|
|
bitfld.long 0x0 1. "NS,Secure/non-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,User/privileged access control:" "0,1"
|
|
wgroup.long ($2+0x4)++0x7
|
|
line.long 0x0 "RELEASE,IPC release"
|
|
hexmask.long.word 0x0 0.--15. 1. "INTR_RELEASE,Writing this field releases a lock and allows for the generation of release events to the IPC interrupt structures but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC.."
|
|
line.long 0x4 "NOTIFY,IPC notification"
|
|
hexmask.long.word 0x4 0.--15. 1. "INTR_NOTIFY,This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1' but only for those IPC interrupt structures for which the.."
|
|
group.long ($2+0xC)++0x7
|
|
line.long 0x0 "DATA0,IPC data 0"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,This field holds a 32-bit data element that is associated with the IPC structure."
|
|
line.long 0x4 "DATA1,IPC data 1"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,This field holds a 32-bit data element that is associated with the IPC structure."
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "LOCK_STATUS,IPC lock status"
|
|
bitfld.long 0x0 31. "ACQUIRED,Specifies if the lock is acquired. This field is set to '1' if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1'). If zero P NS PC and MS are not valid." "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MS,This field specifies the bus master identifier that successfully acquired the lock."
|
|
hexmask.long.byte 0x0 4.--7. 1. "PC,This field specifies the protection context that successfully acquired the lock."
|
|
bitfld.long 0x0 1. "NS,This field specifies the secure/non-secure access control:" "0,1"
|
|
bitfld.long 0x0 0. "P,This field specifies the user/privileged access control:" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40221000 ad:0x40221020 ad:0x40221040 ad:0x40221060 ad:0x40221080 ad:0x402210A0 ad:0x402210C0 ad:0x402210E0 ad:0x40221100 ad:0x40221120 ad:0x40221140 ad:0x40221160 ad:0x40221180 ad:0x402211A0 ad:0x402211C0 ad:0x402211E0)
|
|
tree "INTR_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0xB
|
|
line.long 0x0 "INTR,Interrupt"
|
|
hexmask.long.word 0x0 16.--31. 1. "NOTIFY,These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause."
|
|
hexmask.long.word 0x0 0.--15. 1. "RELEASE,These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause."
|
|
line.long 0x4 "INTR_SET,Interrupt set"
|
|
hexmask.long.word 0x4 16.--31. 1. "NOTIFY,SW writes a '1' to this field to set the corresponding field in the INTR register."
|
|
hexmask.long.word 0x4 0.--15. 1. "RELEASE,SW writes a '1' to this field to set the corresponding field in the INTR register."
|
|
line.long 0x8 "INTR_MASK,Interrupt mask"
|
|
hexmask.long.word 0x8 16.--31. 1. "NOTIFY,Mask bit for corresponding field in the INTR register."
|
|
hexmask.long.word 0x8 0.--15. 1. "RELEASE,Mask bit for corresponding field in the INTR register."
|
|
rgroup.long ($2+0xC)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
hexmask.long.word 0x0 16.--31. 1. "NOTIFY,Logical and of corresponding INTR and INTR_MASK fields."
|
|
hexmask.long.word 0x0 0.--15. 1. "RELEASE,Logical and of corresponding request and mask bits."
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "LIN (Local Interconnect Network)"
|
|
base ad:0x40500000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "ERROR_CTL,Error control"
|
|
bitfld.long 0x0 31. "ENABLED,Error injection enable:" "0,1"
|
|
bitfld.long 0x0 23. "TX_CHECKSUM_STOP_ERROR,The checksum field STOP bits are inverted to '0'." "0,1"
|
|
bitfld.long 0x0 22. "TX_CHECKSUM_ERROR,The checksum field is inverted." "0,1"
|
|
bitfld.long 0x0 21. "TX_DATA_STOP_ERROR,The data field STOP bits are inverted to '0'." "0,1"
|
|
bitfld.long 0x0 19. "TX_PID_STOP_ERROR,The PID field STOP bits are inverted to '0'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TX_PARITY_ERROR,In LIN mode the PID parity bit P[1] is inverted from !(ID[5] ^ ID[4] ^ ID[3] ^ ID[1]) to (ID[5] ^ ID[4] ^ ID[3] ^ ID[1])." "0,1"
|
|
bitfld.long 0x0 17. "TX_SYNC_STOP_ERROR,The synchronization field STOP bits are inverted to '0'." "0,1"
|
|
bitfld.long 0x0 16. "TX_SYNC_ERROR,The synchronization field is changed from 0x55 to 0x00." "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "CH_IDX,Specifies the channel index of the channel to which HW injected channel transmitter errors applies."
|
|
line.long 0x4 "TEST_CTL,Test control"
|
|
bitfld.long 0x4 31. "ENABLED,Test enable:" "0,1"
|
|
bitfld.long 0x4 16. "MODE,Test mode:" "0,1"
|
|
hexmask.long.byte 0x4 0.--4. 1. "CH_IDX,Specifies the channel index of the channel to which test applies. The channel IO signals of channel indices CH_IDX and CH_NR-1 are connected as specified by MODE. CH_IDX should be in the range [0 CH_NR-2] as channel index CH_NR-1 is always.."
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40508000 ad:0x40508100 ad:0x40508200 ad:0x40508300 ad:0x40508400 ad:0x40508500 ad:0x40508600 ad:0x40508700 ad:0x40508800 ad:0x40508900 ad:0x40508A00 ad:0x40508B00 ad:0x40508C00 ad:0x40508D00 ad:0x40508E00 ad:0x40508F00)
|
|
tree "CH[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "CTL0,Control 0"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 30. "FILTER_EN,RX filter (for 'lin_rx_in'):" "0,1"
|
|
bitfld.long 0x0 29. "PARITY_EN,Parity generation enable:" "0,1"
|
|
bitfld.long 0x0 28. "PARITY,Parity mode:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "BIT_ERROR_IGNORE,Specifies behavior on a detected bit error during header or response transmission:" "0,1"
|
|
bitfld.long 0x0 24. "MODE,Mode of operation:" "0: LIN mode.,1: UART mode."
|
|
hexmask.long.byte 0x0 16.--20. 1. "BREAK_WAKEUP_LENGTH,Break/wakeup length (minus 1) in bit periods:"
|
|
bitfld.long 0x0 8.--9. "BREAK_DELIMITER_LENGTH,In LIN mode this field specifies the break delimiter length:" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 4. "AUTO_EN,LIN transceiver auto enable:" "0,1"
|
|
bitfld.long 0x0 0.--1. "STOP_BITS,STOP bit periods:" "0,1,2,3"
|
|
line.long 0x4 "CTL1,Control 1"
|
|
bitfld.long 0x4 24.--25. "FRAME_TIMEOUT_SEL,Specifies the frame timeout mode:" "0,1,2,3"
|
|
hexmask.long.byte 0x4 16.--23. 1. "FRAME_TIMEOUT,Specifies the maximum allowed length (timeout value) for a frame frame header or frame response in bit periods. The LIN specification prescribes to set the maximum length to 1.4x the nominal length (Theader_max = 1.4 x Theader_nom and.."
|
|
bitfld.long 0x4 8. "CHECKSUM_ENHANCED,Checksum mode:" "0,1"
|
|
bitfld.long 0x4 0.--2. "DATA_NR,Number of data fields (minus 1) in the response (not including the checksum):" "0,1,2,3,4,5,6,7"
|
|
rgroup.long ($2+0x8)++0x3
|
|
line.long 0x0 "STATUS,Status"
|
|
bitfld.long 0x0 28. "RX_RESPONSE_CHECKSUM_ERROR,Copy of INTR.RX_RESPONSE_CHECKSUM_ERROR." "0,1"
|
|
bitfld.long 0x0 27. "RX_RESPONSE_FRAME_ERROR,Copy of INTR.RX_RESPONSE_FRAME_ERROR." "0,1"
|
|
bitfld.long 0x0 26. "RX_HEADER_PARITY_ERROR,Copy of INTR.RX_HEADER_PARITY_ERROR." "0,1"
|
|
bitfld.long 0x0 25. "RX_HEADER_SYNC_ERROR,Copy of INTR.RX_HEADER_SYNC_ERROR." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "RX_HEADER_FRAME_ERROR,Copy of INTR.RX_HEADER_FRAME_ERROR." "0,1"
|
|
bitfld.long 0x0 17. "TX_RESPONSE_BIT_ERROR,Copy of INTR.TX_RESPONSE_BIT_ERROR." "0,1"
|
|
bitfld.long 0x0 16. "TX_HEADER_BIT_ERROR,Copy of INTR.TX_HEADER_BIT_ERROR." "0,1"
|
|
bitfld.long 0x0 13. "RX_DONE,Receiver done:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "TX_DONE,Transmitter done:" "0,1"
|
|
bitfld.long 0x0 9. "RX_BUSY,Receiver busy." "0,1"
|
|
bitfld.long 0x0 8. "TX_BUSY,Transmitter busy." "0,1"
|
|
bitfld.long 0x0 5. "RX_DATA0_FRAME_ERROR,Frame response first data field frame error. HW sets this field to '1' when the received STOP bits of the first response data field have an unexpected value (only after a RX_HEADER command) and this data byte is 0x00. HW clears.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "HEADER_RESPONSE,Frame header / response identifier (only valid when TX_BUSY or RX_BUSY is '1'):" "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DATA_IDX,Number of transferred data and checksum fields in the response (also acts as an index/address into response data field and checksum field registers (DATA0 DATA1 PID_CHECKSUM)) :"
|
|
group.long ($2+0x10)++0x3
|
|
line.long 0x0 "CMD,Command"
|
|
bitfld.long 0x0 9. "RX_RESPONSE,SW sets this field to '1' to receive a response. HW sets this field to '0' on successful completion of ANY of the legal command sequences (NOT set to '0' when an error is detected)." "0,1"
|
|
bitfld.long 0x0 8. "RX_HEADER,SW sets this field to '1' to receive a header. HW sets this field to '0' on successful completion of the ANY of the legal command sequences (NOT set to '0' when an error is detected in LIN mode)." "0,1"
|
|
bitfld.long 0x0 2. "TX_WAKEUP,SW sets this field to '1' to transmit a wakeup signal. HW sets this field to '0' on successful completion of ANY of the legal command sequences (also set to '0' when an error is detected)." "0,1"
|
|
bitfld.long 0x0 1. "TX_RESPONSE,SW sets this field to '1' to transmit a response. HW sets this field to '0' on successful completion of ANY of the legal command sequences (also set to '0' when an error is detected)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TX_HEADER,SW sets this field to '1' to transmit a header. HW sets this field to '0' on successful completion of ANY of the following legal command sequences (also set to '0' when an error is detected):" "0,1"
|
|
group.long ($2+0x60)++0x3
|
|
line.long 0x0 "TX_RX_STATUS,TX/RX status"
|
|
bitfld.long 0x0 26. "EN_OUT,LIN transceiver enable ('en_out' 'lin_en_out'). This field controls the enable (or low active sleep enable) of the external transceiver:" "0,1"
|
|
rbitfld.long 0x0 24. "TX_OUT,LIN transmitter output ('tx_out' 'lin_tx_out')." "0,1"
|
|
rbitfld.long 0x0 17. "RX_IN,LIN receiver input ('rx_in' 'lin_rx_in' in functional mode)." "0,1"
|
|
rbitfld.long 0x0 16. "TX_IN,LIN transmitter input ('tx_in' 'lin_tx_in' in functional mode). TX_IN and RX_IN can be used to determine a wakeup source. Note that wakeup source detection relies on the external transceiver functionality." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "SYNC_COUNTER,Synchronization counter in LIN channel clock periods. After the receipt of a synchronization field this fields reflects the duration of the synchronization field. Ideally SYNC_COUNTER = 8*16 = 128 (the synchronization fields consists of.."
|
|
group.long ($2+0x80)++0xB
|
|
line.long 0x0 "PID_CHECKSUM,PID and checksum"
|
|
hexmask.long.byte 0x0 8.--15. 1. "CHECKSUM,Checksum."
|
|
hexmask.long.byte 0x0 0.--7. 1. "PID,Header protected identifier (PID)."
|
|
line.long 0x4 "DATA0,Response data 0"
|
|
hexmask.long.byte 0x4 24.--31. 1. "DATA4,Data field 4."
|
|
hexmask.long.byte 0x4 16.--23. 1. "DATA3,Data field 3."
|
|
hexmask.long.byte 0x4 8.--15. 1. "DATA2,Data field 2."
|
|
hexmask.long.byte 0x4 0.--7. 1. "DATA1,Data field 1."
|
|
line.long 0x8 "DATA1,Response data 1"
|
|
hexmask.long.byte 0x8 24.--31. 1. "DATA8,Data field 8."
|
|
hexmask.long.byte 0x8 16.--23. 1. "DATA7,Data field 7."
|
|
hexmask.long.byte 0x8 8.--15. 1. "DATA6,Data field 6."
|
|
hexmask.long.byte 0x8 0.--7. 1. "DATA5,Data field 5."
|
|
group.long ($2+0xC0)++0xB
|
|
line.long 0x0 "INTR,Interrupt"
|
|
bitfld.long 0x0 28. "RX_RESPONSE_CHECKSUM_ERROR,HW sets this field to '1' when the calculated checksum over the received PID and data fields is not the same as the received checksum." "0,1"
|
|
bitfld.long 0x0 27. "RX_RESPONSE_FRAME_ERROR,HW sets this field to '1' when the received START or STOP bits have an unexpected value (during response reception). HW does NOT use this field for the STOP bits of the first data field after a RX_HEADER command if the received.." "0,1"
|
|
bitfld.long 0x0 26. "RX_HEADER_PARITY_ERROR,HW sets this field to '1' when the received PID field has a parity error." "0,1"
|
|
bitfld.long 0x0 25. "RX_HEADER_SYNC_ERROR,HW sets this field to '1' when the received synchronization field is not received within the synchronization counter range [106 152] (see TX_RX_STATUS.SYNC_COUNTER)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "RX_HEADER_FRAME_ERROR,HW sets this field to '1' when the received START or STOP bits have an unexpected value (during header reception)." "0,1"
|
|
bitfld.long 0x0 17. "TX_RESPONSE_BIT_ERROR,HW sets this field to '1' when a transmitted 'lin_tx_out' value does NOT match a received 'lin_rx_in' value (during response transmission)." "0,1"
|
|
bitfld.long 0x0 16. "TX_HEADER_BIT_ERROR,HW sets this field to '1' when a transmitted 'lin_tx_out' value does NOT match a received 'lin_rx_in' value (during header transmission). This specific test allows for delay through the external transceiver. This mismatch is an.." "0,1"
|
|
bitfld.long 0x0 14. "TIMEOUT,HW sets this field to '1' when a frame frame header or frame response timeout is detected (per CTL.FRAME_TIMEOUT_SEL)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RX_NOISE_DETECT,HW sets this field to '1' when isolated '0' or '1' 'in_rx_in' values are observed or when during sampling the last three 'lin_rx_in' values do NOT all have the same value. This mismatch is an indication of noise on the LIN line." "0,1"
|
|
bitfld.long 0x0 11. "RX_HEADER_SYNC_DONE,HW sets this field to '1' when a synchronization field is received (including trailing STOP bits)." "0,1"
|
|
bitfld.long 0x0 10. "RX_BREAK_WAKEUP_DONE,HW sets this field to '1' when a break or wakeup signal is received (per CTL.BREAK_WAKEUP_LENGTH). This cause is activated on a transition from dominant/'0' state to recessive/'1' state; i.e. at the end of the wakeup signal." "0,1"
|
|
bitfld.long 0x0 9. "RX_RESPONSE_DONE,HW sets this field to '1' when a frame response (data fields and checksum field) is received (the CMD.RX_RESPONSE is completed). If CTL.AUTO_EN is '1' this includes the 4-bit period external transceiver disable post-amble." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RX_HEADER_DONE,HW sets this field to '1' when a frame header (break field synchronization field and PID field) is received (the CMD.RX_HEADER is completed). Specifically:" "0,1"
|
|
bitfld.long 0x0 2. "TX_WAKEUP_DONE,HW sets this field to '1' when a wakeup signal is transmitted (per CTL.BREAK_WAKEUP_LENGTH). This cause is activated on a transition from dominant/'0' state to recessive/'1' state; i.e. at the end of the wakeup signal." "0,1"
|
|
bitfld.long 0x0 1. "TX_RESPONSE_DONE,HW sets this field to '1' when a frame response (data fields and checksum field) is transmitted (the CMD.TX_RESPONSE is completed). If CTL.AUTO_EN is '1' this includes the 4-bit period external transceiver disable post-amble." "0,1"
|
|
bitfld.long 0x0 0. "TX_HEADER_DONE,HW sets this field to '1' when a frame header (break field synchronization field and PID field) is transmitted (the CMD.TX_HEADER is completed). Specifically:" "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set"
|
|
bitfld.long 0x4 28. "RX_RESPONSE_CHECKSUM_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 27. "RX_RESPONSE_FRAME_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 26. "RX_HEADER_PARITY_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 25. "RX_HEADER_SYNC_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "RX_HEADER_FRAME_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 17. "TX_RESPONSE_BIT_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 16. "TX_HEADER_BIT_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 14. "TIMEOUT,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "RX_NOISE_DETECT,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 11. "RX_HEADER_SYNC_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 10. "RX_BREAK_WAKEUP_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 9. "RX_RESPONSE_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "RX_HEADER_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 2. "TX_WAKEUP_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 1. "TX_RESPONSE_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 0. "TX_HEADER_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x8 28. "RX_RESPONSE_CHECKSUM_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 27. "RX_RESPONSE_FRAME_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 26. "RX_HEADER_PARITY_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 25. "RX_HEADER_SYNC_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "RX_HEADER_FRAME_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 17. "TX_RESPONSE_BIT_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 16. "TX_HEADER_BIT_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 14. "TIMEOUT,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "RX_NOISE_DETECT,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 11. "RX_HEADER_SYNC_DONE,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 10. "RX_BREAK_WAKEUP_DONE,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 9. "RX_RESPONSE_DONE,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "RX_HEADER_DONE,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 2. "TX_WAKEUP_DONE,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 1. "TX_RESPONSE_DONE,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 0. "TX_HEADER_DONE,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0xCC)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 28. "RX_RESPONSE_CHECKSUM_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 27. "RX_RESPONSE_FRAME_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 26. "RX_HEADER_PARITY_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 25. "RX_HEADER_SYNC_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "RX_HEADER_FRAME_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 17. "TX_RESPONSE_BIT_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 16. "TX_HEADER_BIT_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 14. "TIMEOUT,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RX_NOISE_DETECT,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 11. "RX_HEADER_SYNC_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 10. "RX_BREAK_WAKEUP_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 9. "RX_RESPONSE_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RX_HEADER_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 2. "TX_WAKEUP_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 1. "TX_RESPONSE_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 0. "TX_HEADER_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 4. (list 0x10 0x11 0x12 0x13)(list ad:0x40509000 ad:0x40509100 ad:0x40509200 ad:0x40509300)
|
|
tree "CH[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "CTL0,Control 0"
|
|
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
|
|
bitfld.long 0x0 30. "FILTER_EN,RX filter (for 'lin_rx_in'):" "0,1"
|
|
bitfld.long 0x0 29. "PARITY_EN,Parity generation enable:" "0,1"
|
|
bitfld.long 0x0 28. "PARITY,Parity mode:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "BIT_ERROR_IGNORE,Specifies behavior on a detected bit error during header or response transmission:" "0,1"
|
|
bitfld.long 0x0 24. "MODE,Mode of operation:" "0: LIN mode.,1: UART mode."
|
|
hexmask.long.byte 0x0 16.--20. 1. "BREAK_WAKEUP_LENGTH,Break/wakeup length (minus 1) in bit periods:"
|
|
bitfld.long 0x0 8.--9. "BREAK_DELIMITER_LENGTH,In LIN mode this field specifies the break delimiter length:" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 4. "AUTO_EN,LIN transceiver auto enable:" "0,1"
|
|
bitfld.long 0x0 0.--1. "STOP_BITS,STOP bit periods:" "0,1,2,3"
|
|
line.long 0x4 "CTL1,Control 1"
|
|
bitfld.long 0x4 24.--25. "FRAME_TIMEOUT_SEL,Specifies the frame timeout mode:" "0,1,2,3"
|
|
hexmask.long.byte 0x4 16.--23. 1. "FRAME_TIMEOUT,Specifies the maximum allowed length (timeout value) for a frame frame header or frame response in bit periods. The LIN specification prescribes to set the maximum length to 1.4x the nominal length (Theader_max = 1.4 x Theader_nom and.."
|
|
bitfld.long 0x4 8. "CHECKSUM_ENHANCED,Checksum mode:" "0,1"
|
|
bitfld.long 0x4 0.--2. "DATA_NR,Number of data fields (minus 1) in the response (not including the checksum):" "0,1,2,3,4,5,6,7"
|
|
rgroup.long ($2+0x8)++0x3
|
|
line.long 0x0 "STATUS,Status"
|
|
bitfld.long 0x0 28. "RX_RESPONSE_CHECKSUM_ERROR,Copy of INTR.RX_RESPONSE_CHECKSUM_ERROR." "0,1"
|
|
bitfld.long 0x0 27. "RX_RESPONSE_FRAME_ERROR,Copy of INTR.RX_RESPONSE_FRAME_ERROR." "0,1"
|
|
bitfld.long 0x0 26. "RX_HEADER_PARITY_ERROR,Copy of INTR.RX_HEADER_PARITY_ERROR." "0,1"
|
|
bitfld.long 0x0 25. "RX_HEADER_SYNC_ERROR,Copy of INTR.RX_HEADER_SYNC_ERROR." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "RX_HEADER_FRAME_ERROR,Copy of INTR.RX_HEADER_FRAME_ERROR." "0,1"
|
|
bitfld.long 0x0 17. "TX_RESPONSE_BIT_ERROR,Copy of INTR.TX_RESPONSE_BIT_ERROR." "0,1"
|
|
bitfld.long 0x0 16. "TX_HEADER_BIT_ERROR,Copy of INTR.TX_HEADER_BIT_ERROR." "0,1"
|
|
bitfld.long 0x0 13. "RX_DONE,Receiver done:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "TX_DONE,Transmitter done:" "0,1"
|
|
bitfld.long 0x0 9. "RX_BUSY,Receiver busy." "0,1"
|
|
bitfld.long 0x0 8. "TX_BUSY,Transmitter busy." "0,1"
|
|
bitfld.long 0x0 5. "RX_DATA0_FRAME_ERROR,Frame response first data field frame error. HW sets this field to '1' when the received STOP bits of the first response data field have an unexpected value (only after a RX_HEADER command) and this data byte is 0x00. HW clears.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "HEADER_RESPONSE,Frame header / response identifier (only valid when TX_BUSY or RX_BUSY is '1'):" "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DATA_IDX,Number of transferred data and checksum fields in the response (also acts as an index/address into response data field and checksum field registers (DATA0 DATA1 PID_CHECKSUM)) :"
|
|
group.long ($2+0x10)++0x3
|
|
line.long 0x0 "CMD,Command"
|
|
bitfld.long 0x0 9. "RX_RESPONSE,SW sets this field to '1' to receive a response. HW sets this field to '0' on successful completion of ANY of the legal command sequences (NOT set to '0' when an error is detected)." "0,1"
|
|
bitfld.long 0x0 8. "RX_HEADER,SW sets this field to '1' to receive a header. HW sets this field to '0' on successful completion of the ANY of the legal command sequences (NOT set to '0' when an error is detected in LIN mode)." "0,1"
|
|
bitfld.long 0x0 2. "TX_WAKEUP,SW sets this field to '1' to transmit a wakeup signal. HW sets this field to '0' on successful completion of ANY of the legal command sequences (also set to '0' when an error is detected)." "0,1"
|
|
bitfld.long 0x0 1. "TX_RESPONSE,SW sets this field to '1' to transmit a response. HW sets this field to '0' on successful completion of ANY of the legal command sequences (also set to '0' when an error is detected)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TX_HEADER,SW sets this field to '1' to transmit a header. HW sets this field to '0' on successful completion of ANY of the following legal command sequences (also set to '0' when an error is detected):" "0,1"
|
|
group.long ($2+0x60)++0x3
|
|
line.long 0x0 "TX_RX_STATUS,TX/RX status"
|
|
bitfld.long 0x0 26. "EN_OUT,LIN transceiver enable ('en_out' 'lin_en_out'). This field controls the enable (or low active sleep enable) of the external transceiver:" "0,1"
|
|
rbitfld.long 0x0 24. "TX_OUT,LIN transmitter output ('tx_out' 'lin_tx_out')." "0,1"
|
|
rbitfld.long 0x0 17. "RX_IN,LIN receiver input ('rx_in' 'lin_rx_in' in functional mode)." "0,1"
|
|
rbitfld.long 0x0 16. "TX_IN,LIN transmitter input ('tx_in' 'lin_tx_in' in functional mode). TX_IN and RX_IN can be used to determine a wakeup source. Note that wakeup source detection relies on the external transceiver functionality." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "SYNC_COUNTER,Synchronization counter in LIN channel clock periods. After the receipt of a synchronization field this fields reflects the duration of the synchronization field. Ideally SYNC_COUNTER = 8*16 = 128 (the synchronization fields consists of.."
|
|
group.long ($2+0x80)++0xB
|
|
line.long 0x0 "PID_CHECKSUM,PID and checksum"
|
|
hexmask.long.byte 0x0 8.--15. 1. "CHECKSUM,Checksum."
|
|
hexmask.long.byte 0x0 0.--7. 1. "PID,Header protected identifier (PID)."
|
|
line.long 0x4 "DATA0,Response data 0"
|
|
hexmask.long.byte 0x4 24.--31. 1. "DATA4,Data field 4."
|
|
hexmask.long.byte 0x4 16.--23. 1. "DATA3,Data field 3."
|
|
hexmask.long.byte 0x4 8.--15. 1. "DATA2,Data field 2."
|
|
hexmask.long.byte 0x4 0.--7. 1. "DATA1,Data field 1."
|
|
line.long 0x8 "DATA1,Response data 1"
|
|
hexmask.long.byte 0x8 24.--31. 1. "DATA8,Data field 8."
|
|
hexmask.long.byte 0x8 16.--23. 1. "DATA7,Data field 7."
|
|
hexmask.long.byte 0x8 8.--15. 1. "DATA6,Data field 6."
|
|
hexmask.long.byte 0x8 0.--7. 1. "DATA5,Data field 5."
|
|
group.long ($2+0xC0)++0xB
|
|
line.long 0x0 "INTR,Interrupt"
|
|
bitfld.long 0x0 28. "RX_RESPONSE_CHECKSUM_ERROR,HW sets this field to '1' when the calculated checksum over the received PID and data fields is not the same as the received checksum." "0,1"
|
|
bitfld.long 0x0 27. "RX_RESPONSE_FRAME_ERROR,HW sets this field to '1' when the received START or STOP bits have an unexpected value (during response reception). HW does NOT use this field for the STOP bits of the first data field after a RX_HEADER command if the received.." "0,1"
|
|
bitfld.long 0x0 26. "RX_HEADER_PARITY_ERROR,HW sets this field to '1' when the received PID field has a parity error." "0,1"
|
|
bitfld.long 0x0 25. "RX_HEADER_SYNC_ERROR,HW sets this field to '1' when the received synchronization field is not received within the synchronization counter range [106 152] (see TX_RX_STATUS.SYNC_COUNTER)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "RX_HEADER_FRAME_ERROR,HW sets this field to '1' when the received START or STOP bits have an unexpected value (during header reception)." "0,1"
|
|
bitfld.long 0x0 17. "TX_RESPONSE_BIT_ERROR,HW sets this field to '1' when a transmitted 'lin_tx_out' value does NOT match a received 'lin_rx_in' value (during response transmission)." "0,1"
|
|
bitfld.long 0x0 16. "TX_HEADER_BIT_ERROR,HW sets this field to '1' when a transmitted 'lin_tx_out' value does NOT match a received 'lin_rx_in' value (during header transmission). This specific test allows for delay through the external transceiver. This mismatch is an.." "0,1"
|
|
bitfld.long 0x0 14. "TIMEOUT,HW sets this field to '1' when a frame frame header or frame response timeout is detected (per CTL.FRAME_TIMEOUT_SEL)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RX_NOISE_DETECT,HW sets this field to '1' when isolated '0' or '1' 'in_rx_in' values are observed or when during sampling the last three 'lin_rx_in' values do NOT all have the same value. This mismatch is an indication of noise on the LIN line." "0,1"
|
|
bitfld.long 0x0 11. "RX_HEADER_SYNC_DONE,HW sets this field to '1' when a synchronization field is received (including trailing STOP bits)." "0,1"
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|
bitfld.long 0x0 10. "RX_BREAK_WAKEUP_DONE,HW sets this field to '1' when a break or wakeup signal is received (per CTL.BREAK_WAKEUP_LENGTH). This cause is activated on a transition from dominant/'0' state to recessive/'1' state; i.e. at the end of the wakeup signal." "0,1"
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|
bitfld.long 0x0 9. "RX_RESPONSE_DONE,HW sets this field to '1' when a frame response (data fields and checksum field) is received (the CMD.RX_RESPONSE is completed). If CTL.AUTO_EN is '1' this includes the 4-bit period external transceiver disable post-amble." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RX_HEADER_DONE,HW sets this field to '1' when a frame header (break field synchronization field and PID field) is received (the CMD.RX_HEADER is completed). Specifically:" "0,1"
|
|
bitfld.long 0x0 2. "TX_WAKEUP_DONE,HW sets this field to '1' when a wakeup signal is transmitted (per CTL.BREAK_WAKEUP_LENGTH). This cause is activated on a transition from dominant/'0' state to recessive/'1' state; i.e. at the end of the wakeup signal." "0,1"
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|
bitfld.long 0x0 1. "TX_RESPONSE_DONE,HW sets this field to '1' when a frame response (data fields and checksum field) is transmitted (the CMD.TX_RESPONSE is completed). If CTL.AUTO_EN is '1' this includes the 4-bit period external transceiver disable post-amble." "0,1"
|
|
bitfld.long 0x0 0. "TX_HEADER_DONE,HW sets this field to '1' when a frame header (break field synchronization field and PID field) is transmitted (the CMD.TX_HEADER is completed). Specifically:" "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set"
|
|
bitfld.long 0x4 28. "RX_RESPONSE_CHECKSUM_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 27. "RX_RESPONSE_FRAME_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 26. "RX_HEADER_PARITY_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 25. "RX_HEADER_SYNC_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "RX_HEADER_FRAME_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 17. "TX_RESPONSE_BIT_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 16. "TX_HEADER_BIT_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 14. "TIMEOUT,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "RX_NOISE_DETECT,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 11. "RX_HEADER_SYNC_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 10. "RX_BREAK_WAKEUP_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 9. "RX_RESPONSE_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "RX_HEADER_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 2. "TX_WAKEUP_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 1. "TX_RESPONSE_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
bitfld.long 0x4 0. "TX_HEADER_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask"
|
|
bitfld.long 0x8 28. "RX_RESPONSE_CHECKSUM_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 27. "RX_RESPONSE_FRAME_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 26. "RX_HEADER_PARITY_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 25. "RX_HEADER_SYNC_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "RX_HEADER_FRAME_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 17. "TX_RESPONSE_BIT_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 16. "TX_HEADER_BIT_ERROR,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 14. "TIMEOUT,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "RX_NOISE_DETECT,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 11. "RX_HEADER_SYNC_DONE,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 10. "RX_BREAK_WAKEUP_DONE,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 9. "RX_RESPONSE_DONE,Mask for corresponding field in INTR register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "RX_HEADER_DONE,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 2. "TX_WAKEUP_DONE,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 1. "TX_RESPONSE_DONE,Mask for corresponding field in INTR register." "0,1"
|
|
bitfld.long 0x8 0. "TX_HEADER_DONE,Mask for corresponding field in INTR register." "0,1"
|
|
rgroup.long ($2+0xCC)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked"
|
|
bitfld.long 0x0 28. "RX_RESPONSE_CHECKSUM_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 27. "RX_RESPONSE_FRAME_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 26. "RX_HEADER_PARITY_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 25. "RX_HEADER_SYNC_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "RX_HEADER_FRAME_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 17. "TX_RESPONSE_BIT_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 16. "TX_HEADER_BIT_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 14. "TIMEOUT,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RX_NOISE_DETECT,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 11. "RX_HEADER_SYNC_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 10. "RX_BREAK_WAKEUP_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 9. "RX_RESPONSE_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RX_HEADER_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 2. "TX_WAKEUP_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 1. "TX_RESPONSE_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
bitfld.long 0x0 0. "TX_HEADER_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "PASS (Programmable Analog Subsystem for S40E)"
|
|
base ad:0x40900000
|
|
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40900000 ad:0x40901000 ad:0x40902000)
|
|
tree "SAR[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "CTL,Analog control register."
|
|
bitfld.long 0x0 31. "ENABLED,- 0: SAR IP disabled (put analog in power down and stop clocks) also clears all pending triggers." "0: SAR IP disabled,1: SAR IP enabled"
|
|
bitfld.long 0x0 30. "ADC_EN,Enable the SAR ADC and SAR sequencer (only valid if ENABLED=1)" "0: SARADC and SARSEQ are disabled,1: SAR ADC and SARSEQ are enabled"
|
|
newline
|
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bitfld.long 0x0 29. "SARMUX_EN,Enable the SARMUX (only valid if ENABLED=1)" "0: SARMUX disabled,1: SARMUX enabled"
|
|
bitfld.long 0x0 10. "HALF_LSB,When set take an extra cycle to convert the half LSB and add it to 12-bit result for Missing Code Recovery" "0: disable half LSB conversion,1: enable half LSB conversion"
|
|
newline
|
|
bitfld.long 0x0 9. "MSB_STRETCH,When set use 2 cycles for the Most Significant Bit (MSB)" "0: Use 1 clock cycle for MSB,1: Use 2 clock cycles for MSB"
|
|
bitfld.long 0x0 8. "IDLE_PWRDWN,When idle automatically power down the analog." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "PWRUP_TIME,Number cycles to wait to power up after IDLE_PWRDWN."
|
|
line.long 0x4 "DIAG_CTL,Diagnostic Reference control register."
|
|
bitfld.long 0x4 31. "DIAG_EN,Diagnostic Reference enable (only valid if ENABLED=1)" "0: Diagnostic Reference disabled,1: Diagnostic Reference enabled"
|
|
hexmask.long.byte 0x4 0.--3. 1. "DIAG_SEL,Select Diagnostic Reference function"
|
|
group.long ($2+0x10)++0x3
|
|
line.long 0x0 "PRECOND_CTL,Preconditioning control register."
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRECOND_TIME,Number ADC clock cycles that Preconditioning is done before the sample window starts. If OVERLAP_EN=0 there will be 1 additional break before make cycle between preconditioning and sampling."
|
|
group.long ($2+0x80)++0x7
|
|
line.long 0x0 "ANA_CAL,Current analog calibration values"
|
|
hexmask.long.byte 0x0 16.--20. 1. "AGAIN,Analog gain correction"
|
|
hexmask.long.byte 0x0 0.--7. 1. "AOFFSET,Analog offset correction"
|
|
line.long 0x4 "DIG_CAL,Current digital calibration values"
|
|
hexmask.long.byte 0x4 16.--21. 1. "DGAIN,Digital gain correction."
|
|
hexmask.long.word 0x4 0.--11. 1. "DOFFSET,Digital offset correction"
|
|
group.long ($2+0x90)++0xB
|
|
line.long 0x0 "ANA_CAL_ALT,Alternate analog calibration values"
|
|
hexmask.long.byte 0x0 16.--20. 1. "AGAIN,See corresponding ANA_CAL field"
|
|
hexmask.long.byte 0x0 0.--7. 1. "AOFFSET,See corresponding ANA_CAL field"
|
|
line.long 0x4 "DIG_CAL_ALT,Alternate digital calibration values"
|
|
hexmask.long.byte 0x4 16.--21. 1. "DGAIN,See corresponding DIG_CAL field"
|
|
hexmask.long.word 0x4 0.--11. 1. "DOFFSET,See corresponding DIG_CAL field"
|
|
line.long 0x8 "CAL_UPD_CMD,Calibration update command"
|
|
bitfld.long 0x8 0. "UPDATE,Calibration update command: coherently copy values from alternate calibration regs to current calibration regs." "0,1"
|
|
rgroup.long ($2+0x100)++0x3
|
|
line.long 0x0 "TR_PEND,Trigger pending status"
|
|
hexmask.long 0x0 0.--31. 1. "TR_PEND,Trigger Pending."
|
|
rgroup.long ($2+0x180)++0xF
|
|
line.long 0x0 "WORK_VALID,Channel working data register 'valid' bits"
|
|
hexmask.long 0x0 0.--31. 1. "WORK_VALID,If set the corresponding WORK register is valid i.e. was already acquired during the current group scan. If this bit is low then either the channel is not enabled not yet acquired or it is used as a pulse detect channel."
|
|
line.long 0x4 "WORK_RANGE,Range detected"
|
|
hexmask.long 0x4 0.--31. 1. "RANGE,N/A"
|
|
line.long 0x8 "WORK_RANGE_HI,Range detect above Hi flag"
|
|
hexmask.long 0x8 0.--31. 1. "ABOVE_HI,Out of range was detected and the value was above the Hi threshold"
|
|
line.long 0xC "WORK_PULSE,Pulse detected"
|
|
hexmask.long 0xC 0.--31. 1. "PULSE,N/A"
|
|
rgroup.long ($2+0x1A0)++0x7
|
|
line.long 0x0 "RESULT_VALID,Channel result data register 'valid' bits"
|
|
hexmask.long 0x0 0.--31. 1. "RESULT_VALID,If set the corresponding RESULT register is valid i.e. was acquired during the preceding group scan. If this bit is low after a group scan completed then either the channel is not enabled or is used as a pulse detect channel."
|
|
line.long 0x4 "RESULT_RANGE_HI,Channel Range above Hi flags"
|
|
hexmask.long 0x4 0.--31. 1. "ABOVE_HI,Out of range was detected and the value was above the Hi threshold"
|
|
rgroup.long ($2+0x200)++0x7
|
|
line.long 0x0 "STATUS,Current status of internal SAR registers (mostly for debug)"
|
|
bitfld.long 0x0 31. "BUSY,If high then the SAR is busy with a conversion." "0,1"
|
|
bitfld.long 0x0 30. "PWRUP_BUSY,If high then the SAR is waiting for PWRUP_TIME due to IDLE_PWRDWN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "DBG_FREEZE,If high then the SAR is prevented from starting a new acquisition see DBG_FREEZE_EN." "0,1"
|
|
bitfld.long 0x0 12.--13. "CUR_PREEMPT_TYPE,Preempting type of current group/channel only valid if BUSY." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "CUR_PRIO,priority of current group/channel only valid if BUSY." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--4. 1. "CUR_CHAN,current channel being acquired only valid if BUSY."
|
|
line.long 0x4 "AVG_STAT,Current averaging status (for debug)"
|
|
hexmask.long.byte 0x4 24.--31. 1. "CUR_AVG_CNT,the current value of the averaging counter. Note that the value shown is updated after the sample window and therefore runs ahead of the accumulator update."
|
|
hexmask.long.tbyte 0x4 0.--19. 1. "CUR_AVG_ACCU,the current value of the averaging accumulator"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list 0x800 0x840 0x880 0x8C0 0x900 0x940 0x980 0x9C0 0xA00 0xA40 0xA80 0xAC0 0xB00 0xB40 0xB80 0xBC0)
|
|
tree "CH[$1]"
|
|
group.long ($2)++0x1B
|
|
line.long 0x0 "TR_CTL,Trigger control."
|
|
bitfld.long 0x0 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output" "0: tr_ch_done generates a 2 cycle pulse (clk_sys)..,1: tr_ch_done is a level output until the result.."
|
|
newline
|
|
bitfld.long 0x0 11. "GROUP_END,0: continue group with next channel" "0: continue group with next channel,1: last channel of a group"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return Restart..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "PRIO,Channel priority:" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first channel,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: N/A,4: N/A,5: N/A,6: N/A,7: Always triggered (also called idle) can only be.."
|
|
line.long 0x4 "SAMPLE_CTL,Sample control."
|
|
bitfld.long 0x4 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values." "0: use regular calibration values,1: use alternate calibration values"
|
|
newline
|
|
hexmask.long.word 0x4 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles. Minimum is 1 (0 gives the same result as 1) minimum time needed for proper settling is at least 412ns i.e.11 clock cycles at the max frequency of 26.7MHz."
|
|
newline
|
|
bitfld.long 0x4 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used." "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input for..,3: Select Diagnostic reference instead of analog.."
|
|
newline
|
|
bitfld.long 0x4 12.--13. "PRECOND_MODE,Select preconditioning mode." "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output during.."
|
|
newline
|
|
bitfld.long 0x4 11. "EXT_MUX_EN,External analog mux enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--10. "EXT_MUX_SEL,External analog mux select." "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x4 6.--7. "PORT_ADDR,Select the physical port. This field is only valid for ADC0." "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0 undefined..,2: ADC0 uses SARMUX2 (only valid for ADC0 undefined..,3: ADC0 uses SARMUX3 (only valid for ADC0 undefined.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "PIN_ADDR,N/A"
|
|
line.long 0x8 "POST_CTL,Post processing control"
|
|
bitfld.long 0x8 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels" "0: Default: tr_sar_ch_done is set when the group is..,1: tr_sar_ch_done is only set if any of the.."
|
|
newline
|
|
bitfld.long 0x8 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--20. 1. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled)"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value"
|
|
newline
|
|
bitfld.long 0x8 7. "SIGN_EXT,Output data is sign extended" "0: Default: result data is unsigned (zero extended..,1: Result data is signed (sign extended if needed)"
|
|
newline
|
|
bitfld.long 0x8 6. "LEFT_ALIGN,Left or right align data in result[15:0]." "0: the data is right aligned in result[11:0],1: the data is left aligned in result[15:4] with.."
|
|
newline
|
|
bitfld.long 0x8 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: N/A,6: N/A,7: N/A"
|
|
line.long 0xC "RANGE_CTL,Range thresholds"
|
|
hexmask.long.word 0xC 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
|
|
newline
|
|
hexmask.long.word 0xC 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
|
|
line.long 0x10 "INTR,Interrupt request register."
|
|
bitfld.long 0x10 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup. Write with '1' to clear bit." "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero. This interrupt is mutual exclusive with Range detect interrupt. Write with '1' to clear bit." "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers. This interrupt is mutual exclusive with Pulse detect.." "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending. Write with '1' to clear bit." "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED. Note that it is possible that also the GRP_DONE interrupt is set. If that is the case one or more new triggers.." "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done. Write with '1' to clear bit." "0,1"
|
|
line.long 0x14 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x14 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x14 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x18 "INTR_MASK,Interrupt mask register."
|
|
bitfld.long 0x18 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x18 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x18 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x18 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long ($2+0x1C)++0xF
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x0 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
line.long 0x4 "WORK,Working data register"
|
|
bitfld.long 0x4 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "WORK,SAR conversion working data of the channel. The data is written here right after sampling this channel."
|
|
line.long 0x8 "RESULT,Result data register"
|
|
bitfld.long 0x8 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x8 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x8 0.--15. 1. "RESULT,SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled."
|
|
line.long 0xC "GRP_STAT,Group status register"
|
|
bitfld.long 0xC 16. "GRP_BUSY,Group acquisition busy." "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "CH_OVERFLOW,Channel Overflow." "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "CH_PULSE_COMPLETE,Channel Pulse complete." "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "CH_RANGE_COMPLETE,Channel Range complete." "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "GRP_OVERFLOW,Group Overflow." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "GRP_CANCELLED,Group Cancelled." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "GRP_COMPLETE,Group acquisition complete." "0,1"
|
|
group.long ($2+0x38)++0x7
|
|
line.long 0x0 "ENABLE,Enable register"
|
|
bitfld.long 0x0 0. "CHAN_EN,Channel enable." "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
|
|
line.long 0x4 "TR_CMD,Software triggers"
|
|
bitfld.long 0x4 0. "START,Software start trigger. When written with '1' a start trigger is generated which sets the corresponding TR_PEND bit (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list 0xC00 0xC40 0xC80 0xCC0 0xD00 0xD40 0xD80 0xDC0 0xE00 0xE40 0xE80 0xEC0 0xF00 0xF40 0xF80 0xFC0)
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|
tree "CH[$1]"
|
|
group.long ($2)++0x1B
|
|
line.long 0x0 "TR_CTL,Trigger control."
|
|
bitfld.long 0x0 31. "DONE_LEVEL,select level or pulse for 'tr_ch_done' trigger output" "0: tr_ch_done generates a 2 cycle pulse (clk_sys)..,1: tr_ch_done is a level output until the result.."
|
|
newline
|
|
bitfld.long 0x0 11. "GROUP_END,0: continue group with next channel" "0: continue group with next channel,1: last channel of a group"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "PREEMPT_TYPE,Preemption type allow for this group" "0: Abort ongoing acquisition do not return Clear..,1: Abort ongoing acquisition up on return Restart..,2: Abort ongoing acquisition up on return Resume..,3: Complete ongoing acquisition (including.."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "PRIO,Channel priority:" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "SEL,Trigger select" "0: Use for channels in group except the first channel,1: Trigger from corresponding TCPWM channel,2: Generic trigger input 0,3: N/A,4: N/A,5: N/A,6: N/A,7: Always triggered (also called idle) can only be.."
|
|
line.long 0x4 "SAMPLE_CTL,Sample control."
|
|
bitfld.long 0x4 31. "ALT_CAL,Use alternate calibration values instead of the current calibration values." "0: use regular calibration values,1: use alternate calibration values"
|
|
newline
|
|
hexmask.long.word 0x4 16.--27. 1. "SAMPLE_TIME,Sample time (aperture) in ADC clock cycles. Minimum is 1 (0 gives the same result as 1) minimum time needed for proper settling is at least 412ns i.e.11 clock cycles at the max frequency of 26.7MHz."
|
|
newline
|
|
bitfld.long 0x4 14.--15. "OVERLAP_DIAG,Select Overlap mode or SARMUX Diagnostics in both cases the Diagnostic reference is used." "0: No overlap or SARMUX Diagnostics,1: Sample the selected analog input for 2..,2: Like normal sample the selected analog input for..,3: Select Diagnostic reference instead of analog.."
|
|
newline
|
|
bitfld.long 0x4 12.--13. "PRECOND_MODE,Select preconditioning mode." "0: No preconditioning,1: Discharge to VREFL,2: Charge to VREFH,3: Connect the Diagnostic reference output during.."
|
|
newline
|
|
bitfld.long 0x4 11. "EXT_MUX_EN,External analog mux enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--10. "EXT_MUX_SEL,External analog mux select." "0: Select EXT_MUX[x]_0 pin,1: Select EXT_MUX[x]_1 pin,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x4 6.--7. "PORT_ADDR,Select the physical port. This field is only valid for ADC0." "0: ADC uses it's own SARMUX,1: ADC0 uses SARMUX1 (only valid for ADC0 undefined..,2: ADC0 uses SARMUX2 (only valid for ADC0 undefined..,3: ADC0 uses SARMUX3 (only valid for ADC0 undefined.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "PIN_ADDR,N/A"
|
|
line.long 0x8 "POST_CTL,Post processing control"
|
|
bitfld.long 0x8 25. "TR_DONE_GRP_VIO,Select tr_sar_ch_done mode for last channel of a group ignored for all other channels" "0: Default: tr_sar_ch_done is set when the group is..,1: tr_sar_ch_done is only set if any of the.."
|
|
newline
|
|
bitfld.long 0x8 22.--23. "RANGE_MODE,Range detect mode" "0: Below Low threshold (result < Lo),1: Inside range (Lo <= result < Hi),2: Above high threshold (Hi <= result),3: Outside range (result < Lo || Hi <= result)"
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|
newline
|
|
hexmask.long.byte 0x8 16.--20. 1. "SHIFT_R,Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled)"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "AVG_CNT,Either averaging count (minus 1) or Pulse positive reload value"
|
|
newline
|
|
bitfld.long 0x8 7. "SIGN_EXT,Output data is sign extended" "0: Default: result data is unsigned (zero extended..,1: Result data is signed (sign extended if needed)"
|
|
newline
|
|
bitfld.long 0x8 6. "LEFT_ALIGN,Left or right align data in result[15:0]." "0: the data is right aligned in result[11:0],1: the data is left aligned in result[15:4] with.."
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|
newline
|
|
bitfld.long 0x8 0.--2. "POST_PROC,Post processing" "0: No postprocessing,1: Averaging,2: Averaging followed by Range detect,3: Range detect,4: Range detect followed by pulse detect,5: N/A,6: N/A,7: N/A"
|
|
line.long 0xC "RANGE_CTL,Range thresholds"
|
|
hexmask.long.word 0xC 16.--31. 1. "RANGE_HI,Range detect high threshold (Hi)"
|
|
newline
|
|
hexmask.long.word 0xC 0.--15. 1. "RANGE_LO,Range detect low threshold (Lo)"
|
|
line.long 0x10 "INTR,Interrupt request register."
|
|
bitfld.long 0x10 10. "CH_OVERFLOW,Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup. Write with '1' to clear bit." "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "CH_PULSE,Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero. This interrupt is mutual exclusive with Range detect interrupt. Write with '1' to clear bit." "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "CH_RANGE,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers. This interrupt is mutual exclusive with Pulse detect.." "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "GRP_OVERFLOW,Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending. Write with '1' to clear bit." "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "GRP_CANCELLED,Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED. Note that it is possible that also the GRP_DONE interrupt is set. If that is the case one or more new triggers.." "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "GRP_DONE,Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done. Write with '1' to clear bit." "0,1"
|
|
line.long 0x14 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x14 10. "CH_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. "CH_PULSE_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x14 8. "CH_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "GRP_OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "GRP_CANCELLED_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "GRP_DONE_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x18 "INTR_MASK,Interrupt mask register."
|
|
bitfld.long 0x18 10. "CH_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x18 9. "CH_PULSE_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x18 8. "CH_RANGE_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "GRP_OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x18 1. "GRP_CANCELLED_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "GRP_DONE_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long ($2+0x1C)++0xF
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x0 10. "CH_OVERFLOW_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CH_PULSE_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "CH_RANGE_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "GRP_OVERFLOW_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "GRP_CANCELLED_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "GRP_DONE_MASKED,Logical and of corresponding request and mask bits." "0,1"
|
|
line.long 0x4 "WORK,Working data register"
|
|
bitfld.long 0x4 31. "VALID_MIR,mirror bit of corresponding bit in WORK_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "PULSE_MIR,mirror bit of corresponding bit in WORK_PULSE register" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RANGE_MIR,mirror bit of corresponding bit in WORK_RANGE register" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "WORK,SAR conversion working data of the channel. The data is written here right after sampling this channel."
|
|
line.long 0x8 "RESULT,Result data register"
|
|
bitfld.long 0x8 31. "VALID_MIR,mirror bit of the corresponding bit in RESULT_VALID register" "0,1"
|
|
newline
|
|
bitfld.long 0x8 30. "PULSE_INTR_MIR,mirror bit of INTR.CH_PULSE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "RANGE_INTR_MIR,mirror bit of INTR.CH_RANGE bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 28. "ABOVE_HI_MIR,mirror bit of the corresponding ABOVE_HI bit" "0,1"
|
|
newline
|
|
hexmask.long.word 0x8 0.--15. 1. "RESULT,SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled."
|
|
line.long 0xC "GRP_STAT,Group status register"
|
|
bitfld.long 0xC 16. "GRP_BUSY,Group acquisition busy." "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "CH_OVERFLOW,Channel Overflow." "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "CH_PULSE_COMPLETE,Channel Pulse complete." "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "CH_RANGE_COMPLETE,Channel Range complete." "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "GRP_OVERFLOW,Group Overflow." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "GRP_CANCELLED,Group Cancelled." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "GRP_COMPLETE,Group acquisition complete." "0,1"
|
|
group.long ($2+0x38)++0x7
|
|
line.long 0x0 "ENABLE,Enable register"
|
|
bitfld.long 0x0 0. "CHAN_EN,Channel enable." "0: the corresponding channel is disabled,1: the corresponding channel is enabled"
|
|
line.long 0x4 "TR_CMD,Software triggers"
|
|
bitfld.long 0x4 0. "START,Software start trigger. When written with '1' a start trigger is generated which sets the corresponding TR_PEND bit (only if the channel is enabled). A read always returns a 0." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
tree "EPASS_MMIO"
|
|
base ad:0x409F0000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "PASS_CTL,PASS control register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "DBG_FREEZE_EN,Debug pause enable 1 per ADC."
|
|
bitfld.long 0x0 21.--22. "REFBUF_MODE,Reference mode." "0: No reference,1: Reference = buffered Vbg from SRSS,2: undefined,3: Reference = unbuffered Vbg from SRSS"
|
|
newline
|
|
bitfld.long 0x0 5. "SUPPLY_MON_LVL_B,Supply monitor level select for AMUXBUS_B" "0: amuxbus_b_mon = VRL,1: amuxbus_b_mon = VRH"
|
|
bitfld.long 0x0 4. "SUPPLY_MON_EN_B,Supply monitor enable for AMUXBUS_B (amuxbus_b_mon)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SUPPLY_MON_LVL_A,Supply monitor level select for AMUXBUS_A" "0: amuxbus_a_mon = VRL,1: amuxbus_a_mon = VRH"
|
|
bitfld.long 0x0 0. "SUPPLY_MON_EN_A,Supply monitor enable for AMUXBUS_A (amuxbus_a_mon)" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "SAR_TR_IN_SEL[$1],per SAR generic input trigger select"
|
|
hexmask.long.byte 0x0 16.--19. 1. "IN4_SEL,Select generic trigger for SAR generic trigger input 4"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IN3_SEL,Select generic trigger for SAR generic trigger input 3"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "IN2_SEL,Select generic trigger for SAR generic trigger input 2"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IN1_SEL,Select generic trigger for SAR generic trigger input 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "IN0_SEL,Select generic trigger for SAR generic trigger input 0"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "SAR_TR_OUT_SEL[$1],per SAR generic output trigger select"
|
|
hexmask.long.byte 0x0 8.--13. 1. "OUT1_SEL,Select SAR output trigger for generic trigger output 1"
|
|
hexmask.long.byte 0x0 0.--5. 1. "OUT0_SEL,Select SAR output trigger for generic trigger output 0"
|
|
repeat.end
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "TEST_CTL,Test control bits"
|
|
bitfld.long 0x0 12. "TS_CAL_SPARE,Spare" "0,1"
|
|
bitfld.long 0x0 8.--9. "TS_CAL_CUR_SEL,Select the current going into the BJT for Temperature Sensor Calibration" "0: Select 1 uA,1: Select 2 uA,2: Select 5 uA,3: Select 10 uA"
|
|
newline
|
|
bitfld.long 0x0 6. "TS_CAL_VI_SEL,Select current or voltage output on 'v_temp' pin for Temperature Sensor Calibration" "0: Current is selected,1: Voltage is selected"
|
|
bitfld.long 0x0 5. "TS_CAL_DIODE_PNP_EN,Enable signal for PNP transistor. This transistor will be used only during calibration for accurate estimation of chip temp." "0: Turn PNP off,1: Configure PNP as a diode"
|
|
newline
|
|
bitfld.long 0x0 4. "TS_CAL_DIODE_EN,Diode Enable disconnect or connect the base and collector terminal of the BJT" "0,1"
|
|
bitfld.long 0x0 3. "TS_CAL_VE_OUT,Voltage Emitter switch control for Temperature Sensor Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TS_CAL_VB_OUT,Voltage Base switch control for Temperature Sensor Calibration" "0,1"
|
|
bitfld.long 0x0 0. "TS_CAL_CUR_IN,External current input switch control for Temperature Sensor Calibration" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "PERI (Peripheral Interconnect)"
|
|
base ad:0x40000000
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "TIMEOUT_CTL,Timeout control"
|
|
hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,This field specifies a number of clock cycles (clk_slow). If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection) the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and.."
|
|
group.long 0x220++0x3
|
|
line.long 0x0 "TR_CMD,Trigger command"
|
|
bitfld.long 0x0 31. "ACTIVATE,SW sets this field to '1' to activate (set to '1') a trigger as identified by TR_SEL TR_EDGE and OUT_SEL. HW sets this field to '0' for edge sensitive triggers AFTER the selected trigger is activated for two clk_peri cycles." "0,1"
|
|
bitfld.long 0x0 30. "OUT_SEL,Specifies whether trigger activation is for a specific input or output trigger of the trigger multiplexer. Activation of a specific input trigger will result in activation of all output triggers that have the specific input trigger selected.." "?,1: to-1 groups"
|
|
bitfld.long 0x0 29. "TR_EDGE,Specifies if the activated trigger is treated as a level sensitive or edge sensitive trigger." "0,1"
|
|
hexmask.long.byte 0x0 8.--12. 1. "GROUP_SEL,Specifies the trigger group:"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TR_SEL,Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not present the trigger activation has no effect."
|
|
group.long 0x2000++0x3
|
|
line.long 0x0 "ECC_CTL,ECC control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR."
|
|
bitfld.long 0x0 18. "ECC_INJ_EN,Enable error injection for PERI protection structure SRAM." "0,1"
|
|
bitfld.long 0x0 16. "ECC_EN,Enable ECC:" "0,1"
|
|
hexmask.long.word 0x0 0.--10. 1. "WORD_ADDR,Specifies the word address where the parity is injected."
|
|
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x40004000 ad:0x40004040 ad:0x40004080 ad:0x400040C0 ad:0x40004100 ad:0x40004140 ad:0x40004180 ad:0x400041C0 ad:0x40004200 ad:0x40004240)
|
|
tree "GR[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CLOCK_CTL,Clock control"
|
|
hexmask.long.byte 0x0 8.--15. 1. "INT8_DIV,Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1 256]."
|
|
group.long ($2+0x10)++0x3
|
|
line.long 0x0 "SL_CTL,Slave control"
|
|
bitfld.long 0x0 15. "ENABLED_15,N/A" "0,1"
|
|
bitfld.long 0x0 14. "ENABLED_14,N/A" "0,1"
|
|
bitfld.long 0x0 13. "ENABLED_13,N/A" "0,1"
|
|
bitfld.long 0x0 12. "ENABLED_12,N/A" "0,1"
|
|
bitfld.long 0x0 11. "ENABLED_11,N/A" "0,1"
|
|
bitfld.long 0x0 10. "ENABLED_10,N/A" "0,1"
|
|
bitfld.long 0x0 9. "ENABLED_9,N/A" "0,1"
|
|
bitfld.long 0x0 8. "ENABLED_8,N/A" "0,1"
|
|
bitfld.long 0x0 7. "ENABLED_7,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "ENABLED_6,N/A" "0,1"
|
|
bitfld.long 0x0 5. "ENABLED_5,N/A" "0,1"
|
|
bitfld.long 0x0 4. "ENABLED_4,N/A" "0,1"
|
|
bitfld.long 0x0 3. "ENABLED_3,N/A" "0,1"
|
|
bitfld.long 0x0 2. "ENABLED_2,Peripheral group slave 2 enable. If the slave is disabled its clock is gated off (constant '0') and its resets are activated." "0,1"
|
|
bitfld.long 0x0 1. "ENABLED_1,Peripheral group slave 1 enable. If the slave is disabled its clock is gated off (constant '0') and its resets are activated." "0,1"
|
|
bitfld.long 0x0 0. "ENABLED_0,Peripheral group slave 0 enable. If the slave is disabled its clock is gated off (constant '0') and its resets are activated." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 13. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC)(list ad:0x40008000 ad:0x40008400 ad:0x40008800 ad:0x40008C00 ad:0x40009000 ad:0x40009400 ad:0x40009800 ad:0x40009C00 ad:0x4000A000 ad:0x4000A400 ad:0x4000A800 ad:0x4000AC00 ad:0x4000B000)
|
|
tree "TR_GR[$1]"
|
|
base $2
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "TR_CTL[$1],Trigger control register"
|
|
bitfld.long 0x0 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation." "0,1"
|
|
bitfld.long 0x0 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger." "0,1"
|
|
bitfld.long 0x0 8. "TR_INV,Specifies if the output trigger is inverted." "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TR_SEL,Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0.."
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
repeat 14. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD)(list ad:0x4000C000 ad:0x4000C400 ad:0x4000C800 ad:0x4000CC00 ad:0x4000D000 ad:0x4000D400 ad:0x4000D800 ad:0x4000DC00 ad:0x4000E000 ad:0x4000E400 ad:0x4000E800 ad:0x4000EC00 ad:0x4000F000 ad:0x4000F400)
|
|
tree "TR_1TO1_GR[$1]"
|
|
base $2
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "TR_CTL[$1],Trigger control register"
|
|
bitfld.long 0x0 12. "DBG_FREEZE_EN,Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation." "0,1"
|
|
bitfld.long 0x0 9. "TR_EDGE,Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger." "0,1"
|
|
bitfld.long 0x0 8. "TR_INV,Specifies if the output trigger is inverted." "0,1"
|
|
bitfld.long 0x0 0. "TR_SEL,Specifies input trigger:" "0,1"
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "PERI_MS (Peripheral interconnect - Master Interface)"
|
|
base ad:0x40020000
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40020000 ad:0x40020040 ad:0x40020080 ad:0x400200C0 ad:0x40020100 ad:0x40020140 ad:0x40020180 ad:0x400201C0 ad:0x40020200 ad:0x40020240 ad:0x40020280 ad:0x400202C0 ad:0x40020300 ad:0x40020340 ad:0x40020380 ad:0x400203C0)
|
|
tree "PPU_PR[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x40020400 ad:0x40020440 ad:0x40020480 ad:0x400204C0 ad:0x40020500 ad:0x40020540 ad:0x40020580 ad:0x400205C0 ad:0x40020600 ad:0x40020640 ad:0x40020680 ad:0x400206C0 ad:0x40020700 ad:0x40020740 ad:0x40020780 ad:0x400207C0)
|
|
tree "PPU_PR[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40020800 ad:0x40020840 ad:0x40020880 ad:0x400208C0 ad:0x40020900 ad:0x40020940 ad:0x40020980 ad:0x400209C0 ad:0x40020A00 ad:0x40020A40 ad:0x40020A80 ad:0x40020AC0 ad:0x40020B00 ad:0x40020B40 ad:0x40020B80 ad:0x40020BC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x40020C00 ad:0x40020C40 ad:0x40020C80 ad:0x40020CC0 ad:0x40020D00 ad:0x40020D40 ad:0x40020D80 ad:0x40020DC0 ad:0x40020E00 ad:0x40020E40 ad:0x40020E80 ad:0x40020EC0 ad:0x40020F00 ad:0x40020F40 ad:0x40020F80 ad:0x40020FC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F)(list ad:0x40021000 ad:0x40021040 ad:0x40021080 ad:0x400210C0 ad:0x40021100 ad:0x40021140 ad:0x40021180 ad:0x400211C0 ad:0x40021200 ad:0x40021240 ad:0x40021280 ad:0x400212C0 ad:0x40021300 ad:0x40021340 ad:0x40021380 ad:0x400213C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F)(list ad:0x40021400 ad:0x40021440 ad:0x40021480 ad:0x400214C0 ad:0x40021500 ad:0x40021540 ad:0x40021580 ad:0x400215C0 ad:0x40021600 ad:0x40021640 ad:0x40021680 ad:0x400216C0 ad:0x40021700 ad:0x40021740 ad:0x40021780 ad:0x400217C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F)(list ad:0x40021800 ad:0x40021840 ad:0x40021880 ad:0x400218C0 ad:0x40021900 ad:0x40021940 ad:0x40021980 ad:0x400219C0 ad:0x40021A00 ad:0x40021A40 ad:0x40021A80 ad:0x40021AC0 ad:0x40021B00 ad:0x40021B40 ad:0x40021B80 ad:0x40021BC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F)(list ad:0x40021C00 ad:0x40021C40 ad:0x40021C80 ad:0x40021CC0 ad:0x40021D00 ad:0x40021D40 ad:0x40021D80 ad:0x40021DC0 ad:0x40021E00 ad:0x40021E40 ad:0x40021E80 ad:0x40021EC0 ad:0x40021F00 ad:0x40021F40 ad:0x40021F80 ad:0x40021FC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F)(list ad:0x40022000 ad:0x40022040 ad:0x40022080 ad:0x400220C0 ad:0x40022100 ad:0x40022140 ad:0x40022180 ad:0x400221C0 ad:0x40022200 ad:0x40022240 ad:0x40022280 ad:0x400222C0 ad:0x40022300 ad:0x40022340 ad:0x40022380 ad:0x400223C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F)(list ad:0x40022400 ad:0x40022440 ad:0x40022480 ad:0x400224C0 ad:0x40022500 ad:0x40022540 ad:0x40022580 ad:0x400225C0 ad:0x40022600 ad:0x40022640 ad:0x40022680 ad:0x400226C0 ad:0x40022700 ad:0x40022740 ad:0x40022780 ad:0x400227C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F)(list ad:0x40022800 ad:0x40022840 ad:0x40022880 ad:0x400228C0 ad:0x40022900 ad:0x40022940 ad:0x40022980 ad:0x400229C0 ad:0x40022A00 ad:0x40022A40 ad:0x40022A80 ad:0x40022AC0 ad:0x40022B00 ad:0x40022B40 ad:0x40022B80 ad:0x40022BC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F)(list ad:0x40022C00 ad:0x40022C40 ad:0x40022C80 ad:0x40022CC0 ad:0x40022D00 ad:0x40022D40 ad:0x40022D80 ad:0x40022DC0 ad:0x40022E00 ad:0x40022E40 ad:0x40022E80 ad:0x40022EC0 ad:0x40022F00 ad:0x40022F40 ad:0x40022F80 ad:0x40022FC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF)(list ad:0x40023000 ad:0x40023040 ad:0x40023080 ad:0x400230C0 ad:0x40023100 ad:0x40023140 ad:0x40023180 ad:0x400231C0 ad:0x40023200 ad:0x40023240 ad:0x40023280 ad:0x400232C0 ad:0x40023300 ad:0x40023340 ad:0x40023380 ad:0x400233C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF)(list ad:0x40023400 ad:0x40023440 ad:0x40023480 ad:0x400234C0 ad:0x40023500 ad:0x40023540 ad:0x40023580 ad:0x400235C0 ad:0x40023600 ad:0x40023640 ad:0x40023680 ad:0x400236C0 ad:0x40023700 ad:0x40023740 ad:0x40023780 ad:0x400237C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF)(list ad:0x40023800 ad:0x40023840 ad:0x40023880 ad:0x400238C0 ad:0x40023900 ad:0x40023940 ad:0x40023980 ad:0x400239C0 ad:0x40023A00 ad:0x40023A40 ad:0x40023A80 ad:0x40023AC0 ad:0x40023B00 ad:0x40023B40 ad:0x40023B80 ad:0x40023BC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF)(list ad:0x40023C00 ad:0x40023C40 ad:0x40023C80 ad:0x40023CC0 ad:0x40023D00 ad:0x40023D40 ad:0x40023D80 ad:0x40023DC0 ad:0x40023E00 ad:0x40023E40 ad:0x40023E80 ad:0x40023EC0 ad:0x40023F00 ad:0x40023F40 ad:0x40023F80 ad:0x40023FC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF)(list ad:0x40024000 ad:0x40024040 ad:0x40024080 ad:0x400240C0 ad:0x40024100 ad:0x40024140 ad:0x40024180 ad:0x400241C0 ad:0x40024200 ad:0x40024240 ad:0x40024280 ad:0x400242C0 ad:0x40024300 ad:0x40024340 ad:0x40024380 ad:0x400243C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF)(list ad:0x40024400 ad:0x40024440 ad:0x40024480 ad:0x400244C0 ad:0x40024500 ad:0x40024540 ad:0x40024580 ad:0x400245C0 ad:0x40024600 ad:0x40024640 ad:0x40024680 ad:0x400246C0 ad:0x40024700 ad:0x40024740 ad:0x40024780 ad:0x400247C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x100 0x101 0x102 0x103 0x104 0x105 0x106 0x107 0x108 0x109 0x10A 0x10B 0x10C 0x10D 0x10E 0x10F)(list ad:0x40024800 ad:0x40024840 ad:0x40024880 ad:0x400248C0 ad:0x40024900 ad:0x40024940 ad:0x40024980 ad:0x400249C0 ad:0x40024A00 ad:0x40024A40 ad:0x40024A80 ad:0x40024AC0 ad:0x40024B00 ad:0x40024B40 ad:0x40024B80 ad:0x40024BC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x110 0x111 0x112 0x113 0x114 0x115 0x116 0x117 0x118 0x119 0x11A 0x11B 0x11C 0x11D 0x11E 0x11F)(list ad:0x40024C00 ad:0x40024C40 ad:0x40024C80 ad:0x40024CC0 ad:0x40024D00 ad:0x40024D40 ad:0x40024D80 ad:0x40024DC0 ad:0x40024E00 ad:0x40024E40 ad:0x40024E80 ad:0x40024EC0 ad:0x40024F00 ad:0x40024F40 ad:0x40024F80 ad:0x40024FC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x120 0x121 0x122 0x123 0x124 0x125 0x126 0x127 0x128 0x129 0x12A 0x12B 0x12C 0x12D 0x12E 0x12F)(list ad:0x40025000 ad:0x40025040 ad:0x40025080 ad:0x400250C0 ad:0x40025100 ad:0x40025140 ad:0x40025180 ad:0x400251C0 ad:0x40025200 ad:0x40025240 ad:0x40025280 ad:0x400252C0 ad:0x40025300 ad:0x40025340 ad:0x40025380 ad:0x400253C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x130 0x131 0x132 0x133 0x134 0x135 0x136 0x137 0x138 0x139 0x13A 0x13B 0x13C 0x13D 0x13E 0x13F)(list ad:0x40025400 ad:0x40025440 ad:0x40025480 ad:0x400254C0 ad:0x40025500 ad:0x40025540 ad:0x40025580 ad:0x400255C0 ad:0x40025600 ad:0x40025640 ad:0x40025680 ad:0x400256C0 ad:0x40025700 ad:0x40025740 ad:0x40025780 ad:0x400257C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x140 0x141 0x142 0x143 0x144 0x145 0x146 0x147 0x148 0x149 0x14A 0x14B 0x14C 0x14D 0x14E 0x14F)(list ad:0x40025800 ad:0x40025840 ad:0x40025880 ad:0x400258C0 ad:0x40025900 ad:0x40025940 ad:0x40025980 ad:0x400259C0 ad:0x40025A00 ad:0x40025A40 ad:0x40025A80 ad:0x40025AC0 ad:0x40025B00 ad:0x40025B40 ad:0x40025B80 ad:0x40025BC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x150 0x151 0x152 0x153 0x154 0x155 0x156 0x157 0x158 0x159 0x15A 0x15B 0x15C 0x15D 0x15E 0x15F)(list ad:0x40025C00 ad:0x40025C40 ad:0x40025C80 ad:0x40025CC0 ad:0x40025D00 ad:0x40025D40 ad:0x40025D80 ad:0x40025DC0 ad:0x40025E00 ad:0x40025E40 ad:0x40025E80 ad:0x40025EC0 ad:0x40025F00 ad:0x40025F40 ad:0x40025F80 ad:0x40025FC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x160 0x161 0x162 0x163 0x164 0x165 0x166 0x167 0x168 0x169 0x16A 0x16B 0x16C 0x16D 0x16E 0x16F)(list ad:0x40026000 ad:0x40026040 ad:0x40026080 ad:0x400260C0 ad:0x40026100 ad:0x40026140 ad:0x40026180 ad:0x400261C0 ad:0x40026200 ad:0x40026240 ad:0x40026280 ad:0x400262C0 ad:0x40026300 ad:0x40026340 ad:0x40026380 ad:0x400263C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x170 0x171 0x172 0x173 0x174 0x175 0x176 0x177 0x178 0x179 0x17A 0x17B 0x17C 0x17D 0x17E 0x17F)(list ad:0x40026400 ad:0x40026440 ad:0x40026480 ad:0x400264C0 ad:0x40026500 ad:0x40026540 ad:0x40026580 ad:0x400265C0 ad:0x40026600 ad:0x40026640 ad:0x40026680 ad:0x400266C0 ad:0x40026700 ad:0x40026740 ad:0x40026780 ad:0x400267C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x180 0x181 0x182 0x183 0x184 0x185 0x186 0x187 0x188 0x189 0x18A 0x18B 0x18C 0x18D 0x18E 0x18F)(list ad:0x40026800 ad:0x40026840 ad:0x40026880 ad:0x400268C0 ad:0x40026900 ad:0x40026940 ad:0x40026980 ad:0x400269C0 ad:0x40026A00 ad:0x40026A40 ad:0x40026A80 ad:0x40026AC0 ad:0x40026B00 ad:0x40026B40 ad:0x40026B80 ad:0x40026BC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x190 0x191 0x192 0x193 0x194 0x195 0x196 0x197 0x198 0x199 0x19A 0x19B 0x19C 0x19D 0x19E 0x19F)(list ad:0x40026C00 ad:0x40026C40 ad:0x40026C80 ad:0x40026CC0 ad:0x40026D00 ad:0x40026D40 ad:0x40026D80 ad:0x40026DC0 ad:0x40026E00 ad:0x40026E40 ad:0x40026E80 ad:0x40026EC0 ad:0x40026F00 ad:0x40026F40 ad:0x40026F80 ad:0x40026FC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x1A0 0x1A1 0x1A2 0x1A3 0x1A4 0x1A5 0x1A6 0x1A7 0x1A8 0x1A9 0x1AA 0x1AB 0x1AC 0x1AD 0x1AE 0x1AF)(list ad:0x40027000 ad:0x40027040 ad:0x40027080 ad:0x400270C0 ad:0x40027100 ad:0x40027140 ad:0x40027180 ad:0x400271C0 ad:0x40027200 ad:0x40027240 ad:0x40027280 ad:0x400272C0 ad:0x40027300 ad:0x40027340 ad:0x40027380 ad:0x400273C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x1B0 0x1B1 0x1B2 0x1B3 0x1B4 0x1B5 0x1B6 0x1B7 0x1B8 0x1B9 0x1BA 0x1BB 0x1BC 0x1BD 0x1BE 0x1BF)(list ad:0x40027400 ad:0x40027440 ad:0x40027480 ad:0x400274C0 ad:0x40027500 ad:0x40027540 ad:0x40027580 ad:0x400275C0 ad:0x40027600 ad:0x40027640 ad:0x40027680 ad:0x400276C0 ad:0x40027700 ad:0x40027740 ad:0x40027780 ad:0x400277C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x1C0 0x1C1 0x1C2 0x1C3 0x1C4 0x1C5 0x1C6 0x1C7 0x1C8 0x1C9 0x1CA 0x1CB 0x1CC 0x1CD 0x1CE 0x1CF)(list ad:0x40027800 ad:0x40027840 ad:0x40027880 ad:0x400278C0 ad:0x40027900 ad:0x40027940 ad:0x40027980 ad:0x400279C0 ad:0x40027A00 ad:0x40027A40 ad:0x40027A80 ad:0x40027AC0 ad:0x40027B00 ad:0x40027B40 ad:0x40027B80 ad:0x40027BC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x1D0 0x1D1 0x1D2 0x1D3 0x1D4 0x1D5 0x1D6 0x1D7 0x1D8 0x1D9 0x1DA 0x1DB 0x1DC 0x1DD 0x1DE 0x1DF)(list ad:0x40027C00 ad:0x40027C40 ad:0x40027C80 ad:0x40027CC0 ad:0x40027D00 ad:0x40027D40 ad:0x40027D80 ad:0x40027DC0 ad:0x40027E00 ad:0x40027E40 ad:0x40027E80 ad:0x40027EC0 ad:0x40027F00 ad:0x40027F40 ad:0x40027F80 ad:0x40027FC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x1E0 0x1E1 0x1E2 0x1E3 0x1E4 0x1E5 0x1E6 0x1E7 0x1E8 0x1E9 0x1EA 0x1EB 0x1EC 0x1ED 0x1EE 0x1EF)(list ad:0x40028000 ad:0x40028040 ad:0x40028080 ad:0x400280C0 ad:0x40028100 ad:0x40028140 ad:0x40028180 ad:0x400281C0 ad:0x40028200 ad:0x40028240 ad:0x40028280 ad:0x400282C0 ad:0x40028300 ad:0x40028340 ad:0x40028380 ad:0x400283C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x1F0 0x1F1 0x1F2 0x1F3 0x1F4 0x1F5 0x1F6 0x1F7 0x1F8 0x1F9 0x1FA 0x1FB 0x1FC 0x1FD 0x1FE 0x1FF)(list ad:0x40028400 ad:0x40028440 ad:0x40028480 ad:0x400284C0 ad:0x40028500 ad:0x40028540 ad:0x40028580 ad:0x400285C0 ad:0x40028600 ad:0x40028640 ad:0x40028680 ad:0x400286C0 ad:0x40028700 ad:0x40028740 ad:0x40028780 ad:0x400287C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x200 0x201 0x202 0x203 0x204 0x205 0x206 0x207 0x208 0x209 0x20A 0x20B 0x20C 0x20D 0x20E 0x20F)(list ad:0x40028800 ad:0x40028840 ad:0x40028880 ad:0x400288C0 ad:0x40028900 ad:0x40028940 ad:0x40028980 ad:0x400289C0 ad:0x40028A00 ad:0x40028A40 ad:0x40028A80 ad:0x40028AC0 ad:0x40028B00 ad:0x40028B40 ad:0x40028B80 ad:0x40028BC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x210 0x211 0x212 0x213 0x214 0x215 0x216 0x217 0x218 0x219 0x21A 0x21B 0x21C 0x21D 0x21E 0x21F)(list ad:0x40028C00 ad:0x40028C40 ad:0x40028C80 ad:0x40028CC0 ad:0x40028D00 ad:0x40028D40 ad:0x40028D80 ad:0x40028DC0 ad:0x40028E00 ad:0x40028E40 ad:0x40028E80 ad:0x40028EC0 ad:0x40028F00 ad:0x40028F40 ad:0x40028F80 ad:0x40028FC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x220 0x221 0x222 0x223 0x224 0x225 0x226 0x227 0x228 0x229 0x22A 0x22B 0x22C 0x22D 0x22E 0x22F)(list ad:0x40029000 ad:0x40029040 ad:0x40029080 ad:0x400290C0 ad:0x40029100 ad:0x40029140 ad:0x40029180 ad:0x400291C0 ad:0x40029200 ad:0x40029240 ad:0x40029280 ad:0x400292C0 ad:0x40029300 ad:0x40029340 ad:0x40029380 ad:0x400293C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x230 0x231 0x232 0x233 0x234 0x235 0x236 0x237 0x238 0x239 0x23A 0x23B 0x23C 0x23D 0x23E 0x23F)(list ad:0x40029400 ad:0x40029440 ad:0x40029480 ad:0x400294C0 ad:0x40029500 ad:0x40029540 ad:0x40029580 ad:0x400295C0 ad:0x40029600 ad:0x40029640 ad:0x40029680 ad:0x400296C0 ad:0x40029700 ad:0x40029740 ad:0x40029780 ad:0x400297C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x240 0x241 0x242 0x243 0x244 0x245 0x246 0x247 0x248 0x249 0x24A 0x24B 0x24C 0x24D 0x24E 0x24F)(list ad:0x40029800 ad:0x40029840 ad:0x40029880 ad:0x400298C0 ad:0x40029900 ad:0x40029940 ad:0x40029980 ad:0x400299C0 ad:0x40029A00 ad:0x40029A40 ad:0x40029A80 ad:0x40029AC0 ad:0x40029B00 ad:0x40029B40 ad:0x40029B80 ad:0x40029BC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x250 0x251 0x252 0x253 0x254 0x255 0x256 0x257 0x258 0x259 0x25A 0x25B 0x25C 0x25D 0x25E 0x25F)(list ad:0x40029C00 ad:0x40029C40 ad:0x40029C80 ad:0x40029CC0 ad:0x40029D00 ad:0x40029D40 ad:0x40029D80 ad:0x40029DC0 ad:0x40029E00 ad:0x40029E40 ad:0x40029E80 ad:0x40029EC0 ad:0x40029F00 ad:0x40029F40 ad:0x40029F80 ad:0x40029FC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x260 0x261 0x262 0x263 0x264 0x265 0x266 0x267 0x268 0x269 0x26A 0x26B 0x26C 0x26D 0x26E 0x26F)(list ad:0x4002A000 ad:0x4002A040 ad:0x4002A080 ad:0x4002A0C0 ad:0x4002A100 ad:0x4002A140 ad:0x4002A180 ad:0x4002A1C0 ad:0x4002A200 ad:0x4002A240 ad:0x4002A280 ad:0x4002A2C0 ad:0x4002A300 ad:0x4002A340 ad:0x4002A380 ad:0x4002A3C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x270 0x271 0x272 0x273 0x274 0x275 0x276 0x277 0x278 0x279 0x27A 0x27B 0x27C 0x27D 0x27E 0x27F)(list ad:0x4002A400 ad:0x4002A440 ad:0x4002A480 ad:0x4002A4C0 ad:0x4002A500 ad:0x4002A540 ad:0x4002A580 ad:0x4002A5C0 ad:0x4002A600 ad:0x4002A640 ad:0x4002A680 ad:0x4002A6C0 ad:0x4002A700 ad:0x4002A740 ad:0x4002A780 ad:0x4002A7C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x280 0x281 0x282 0x283 0x284 0x285 0x286 0x287 0x288 0x289 0x28A 0x28B 0x28C 0x28D 0x28E 0x28F)(list ad:0x4002A800 ad:0x4002A840 ad:0x4002A880 ad:0x4002A8C0 ad:0x4002A900 ad:0x4002A940 ad:0x4002A980 ad:0x4002A9C0 ad:0x4002AA00 ad:0x4002AA40 ad:0x4002AA80 ad:0x4002AAC0 ad:0x4002AB00 ad:0x4002AB40 ad:0x4002AB80 ad:0x4002ABC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x290 0x291 0x292 0x293 0x294 0x295 0x296 0x297 0x298 0x299 0x29A 0x29B 0x29C 0x29D 0x29E 0x29F)(list ad:0x4002AC00 ad:0x4002AC40 ad:0x4002AC80 ad:0x4002ACC0 ad:0x4002AD00 ad:0x4002AD40 ad:0x4002AD80 ad:0x4002ADC0 ad:0x4002AE00 ad:0x4002AE40 ad:0x4002AE80 ad:0x4002AEC0 ad:0x4002AF00 ad:0x4002AF40 ad:0x4002AF80 ad:0x4002AFC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x2A0 0x2A1 0x2A2 0x2A3 0x2A4 0x2A5 0x2A6 0x2A7 0x2A8 0x2A9 0x2AA 0x2AB 0x2AC 0x2AD 0x2AE 0x2AF)(list ad:0x4002B000 ad:0x4002B040 ad:0x4002B080 ad:0x4002B0C0 ad:0x4002B100 ad:0x4002B140 ad:0x4002B180 ad:0x4002B1C0 ad:0x4002B200 ad:0x4002B240 ad:0x4002B280 ad:0x4002B2C0 ad:0x4002B300 ad:0x4002B340 ad:0x4002B380 ad:0x4002B3C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x2B0 0x2B1 0x2B2 0x2B3 0x2B4 0x2B5 0x2B6 0x2B7 0x2B8 0x2B9 0x2BA 0x2BB 0x2BC 0x2BD 0x2BE 0x2BF)(list ad:0x4002B400 ad:0x4002B440 ad:0x4002B480 ad:0x4002B4C0 ad:0x4002B500 ad:0x4002B540 ad:0x4002B580 ad:0x4002B5C0 ad:0x4002B600 ad:0x4002B640 ad:0x4002B680 ad:0x4002B6C0 ad:0x4002B700 ad:0x4002B740 ad:0x4002B780 ad:0x4002B7C0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x2C0 0x2C1 0x2C2 0x2C3 0x2C4 0x2C5 0x2C6 0x2C7 0x2C8 0x2C9 0x2CA 0x2CB 0x2CC 0x2CD 0x2CE 0x2CF)(list ad:0x4002B800 ad:0x4002B840 ad:0x4002B880 ad:0x4002B8C0 ad:0x4002B900 ad:0x4002B940 ad:0x4002B980 ad:0x4002B9C0 ad:0x4002BA00 ad:0x4002BA40 ad:0x4002BA80 ad:0x4002BAC0 ad:0x4002BB00 ad:0x4002BB40 ad:0x4002BB80 ad:0x4002BBC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x2D0 0x2D1 0x2D2 0x2D3 0x2D4 0x2D5 0x2D6 0x2D7 0x2D8 0x2D9 0x2DA 0x2DB 0x2DC 0x2DD 0x2DE 0x2DF)(list ad:0x4002BC00 ad:0x4002BC40 ad:0x4002BC80 ad:0x4002BCC0 ad:0x4002BD00 ad:0x4002BD40 ad:0x4002BD80 ad:0x4002BDC0 ad:0x4002BE00 ad:0x4002BE40 ad:0x4002BE80 ad:0x4002BEC0 ad:0x4002BF00 ad:0x4002BF40 ad:0x4002BF80 ad:0x4002BFC0)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 10. (list 0x2E0 0x2E1 0x2E2 0x2E3 0x2E4 0x2E5 0x2E6 0x2E7 0x2E8 0x2E9)(list ad:0x4002C000 ad:0x4002C040 ad:0x4002C080 ad:0x4002C0C0 ad:0x4002C100 ad:0x4002C140 ad:0x4002C180 ad:0x4002C1C0 ad:0x4002C200 ad:0x4002C240)
|
|
tree "PPU_FX[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "SL_ADDR,Slave region. base address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR30,This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore some of the lesser significant address bits of ADDR30 must be '0's. E.g. a 64 KB.."
|
|
line.long 0x4 "SL_SIZE,Slave region. size"
|
|
bitfld.long 0x4 31. "VALID,Slave region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the slave region:"
|
|
group.long ($2+0x10)++0xF
|
|
line.long 0x0 "SL_ATT0,Slave attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
bitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
bitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
bitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
bitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
bitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
bitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "SL_ATT1,Slave attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
bitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
bitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
bitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
bitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
bitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
bitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
bitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
bitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "SL_ATT2,Slave attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
bitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
bitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
bitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
bitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
bitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
bitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
bitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
bitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "SL_ATT3,Slave attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
bitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
bitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
bitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
bitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
bitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
bitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
bitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
bitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
rgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "MS_ADDR,Master region. base address"
|
|
hexmask.long 0x0 6.--31. 1. "ADDR26,This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register."
|
|
line.long 0x4 "MS_SIZE,Master region. size"
|
|
bitfld.long 0x4 31. "VALID,Master region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the size of the master region:"
|
|
group.long ($2+0x30)++0xF
|
|
line.long 0x0 "MS_ATT0,Master attributes 0"
|
|
bitfld.long 0x0 28. "PC3_NS,Protection context 3 non-secure." "0,1"
|
|
bitfld.long 0x0 27. "PC3_PW,Protection context 3 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 26. "PC3_PR,Protection context 3 privileged read enable." "0,1"
|
|
bitfld.long 0x0 25. "PC3_UW,Protection context 3 user write enable." "0,1"
|
|
rbitfld.long 0x0 24. "PC3_UR,Protection context 3 user read enable." "0,1"
|
|
bitfld.long 0x0 20. "PC2_NS,Protection context 2 non-secure." "0,1"
|
|
bitfld.long 0x0 19. "PC2_PW,Protection context 2 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 18. "PC2_PR,Protection context 2 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PC2_UW,Protection context 2 user write enable." "0,1"
|
|
rbitfld.long 0x0 16. "PC2_UR,Protection context 2 user read enable." "0,1"
|
|
bitfld.long 0x0 12. "PC1_NS,Protection context 1 non-secure." "0,1"
|
|
bitfld.long 0x0 11. "PC1_PW,Protection context 1 privileged write enable." "0,1"
|
|
rbitfld.long 0x0 10. "PC1_PR,Protection context 1 privileged read enable." "0,1"
|
|
bitfld.long 0x0 9. "PC1_UW,Protection context 1 user write enable." "0,1"
|
|
rbitfld.long 0x0 8. "PC1_UR,Protection context 1 user read enable." "0,1"
|
|
rbitfld.long 0x0 4. "PC0_NS,Protection context 0 non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 3. "PC0_PW,Protection context 0 privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 2. "PC0_PR,Protection context 0 privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 1. "PC0_UW,Protection context 0 user write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "PC0_UR,Protection context 0 user read enable:" "0,1"
|
|
line.long 0x4 "MS_ATT1,Master attributes 1"
|
|
bitfld.long 0x4 28. "PC7_NS,Protection context 7 non-secure." "0,1"
|
|
bitfld.long 0x4 27. "PC7_PW,Protection context 7 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 26. "PC7_PR,Protection context 7 privileged read enable." "0,1"
|
|
bitfld.long 0x4 25. "PC7_UW,Protection context 7 user write enable." "0,1"
|
|
rbitfld.long 0x4 24. "PC7_UR,Protection context 7 user read enable." "0,1"
|
|
bitfld.long 0x4 20. "PC6_NS,Protection context 6 non-secure." "0,1"
|
|
bitfld.long 0x4 19. "PC6_PW,Protection context 6 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 18. "PC6_PR,Protection context 6 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PC6_UW,Protection context 6 user write enable." "0,1"
|
|
rbitfld.long 0x4 16. "PC6_UR,Protection context 6 user read enable." "0,1"
|
|
bitfld.long 0x4 12. "PC5_NS,Protection context 5 non-secure." "0,1"
|
|
bitfld.long 0x4 11. "PC5_PW,Protection context 5 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 10. "PC5_PR,Protection context 5 privileged read enable." "0,1"
|
|
bitfld.long 0x4 9. "PC5_UW,Protection context 5 user write enable." "0,1"
|
|
rbitfld.long 0x4 8. "PC5_UR,Protection context 5 user read enable." "0,1"
|
|
bitfld.long 0x4 4. "PC4_NS,Protection context 4 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PC4_PW,Protection context 4 privileged write enable." "0,1"
|
|
rbitfld.long 0x4 2. "PC4_PR,Protection context 4 privileged read enable." "0,1"
|
|
bitfld.long 0x4 1. "PC4_UW,Protection context 4 user write enable." "0,1"
|
|
rbitfld.long 0x4 0. "PC4_UR,Protection context 4 user read enable." "0,1"
|
|
line.long 0x8 "MS_ATT2,Master attributes 2"
|
|
bitfld.long 0x8 28. "PC11_NS,Protection context 11 non-secure." "0,1"
|
|
bitfld.long 0x8 27. "PC11_PW,Protection context 11 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 26. "PC11_PR,Protection context 11 privileged read enable." "0,1"
|
|
bitfld.long 0x8 25. "PC11_UW,Protection context 11 user write enable." "0,1"
|
|
rbitfld.long 0x8 24. "PC11_UR,Protection context 11 user read enable." "0,1"
|
|
bitfld.long 0x8 20. "PC10_NS,Protection context 10 non-secure." "0,1"
|
|
bitfld.long 0x8 19. "PC10_PW,Protection context 10 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 18. "PC10_PR,Protection context 10 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PC10_UW,Protection context 10 user write enable." "0,1"
|
|
rbitfld.long 0x8 16. "PC10_UR,Protection context 10 user read enable." "0,1"
|
|
bitfld.long 0x8 12. "PC9_NS,Protection context 9 non-secure." "0,1"
|
|
bitfld.long 0x8 11. "PC9_PW,Protection context 9 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 10. "PC9_PR,Protection context 9 privileged read enable." "0,1"
|
|
bitfld.long 0x8 9. "PC9_UW,Protection context 9 user write enable." "0,1"
|
|
rbitfld.long 0x8 8. "PC9_UR,Protection context 9 user read enable." "0,1"
|
|
bitfld.long 0x8 4. "PC8_NS,Protection context 8 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PC8_PW,Protection context 8 privileged write enable." "0,1"
|
|
rbitfld.long 0x8 2. "PC8_PR,Protection context 8 privileged read enable." "0,1"
|
|
bitfld.long 0x8 1. "PC8_UW,Protection context 8 user write enable." "0,1"
|
|
rbitfld.long 0x8 0. "PC8_UR,Protection context 8 user read enable." "0,1"
|
|
line.long 0xC "MS_ATT3,Master attributes 3"
|
|
bitfld.long 0xC 28. "PC15_NS,Protection context 15 non-secure." "0,1"
|
|
bitfld.long 0xC 27. "PC15_PW,Protection context 15 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 26. "PC15_PR,Protection context 15 privileged read enable." "0,1"
|
|
bitfld.long 0xC 25. "PC15_UW,Protection context 15 user write enable." "0,1"
|
|
rbitfld.long 0xC 24. "PC15_UR,Protection context 15 user read enable." "0,1"
|
|
bitfld.long 0xC 20. "PC14_NS,Protection context 14 non-secure." "0,1"
|
|
bitfld.long 0xC 19. "PC14_PW,Protection context 14 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 18. "PC14_PR,Protection context 14 privileged read enable." "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PC14_UW,Protection context 14 user write enable." "0,1"
|
|
rbitfld.long 0xC 16. "PC14_UR,Protection context 14 user read enable." "0,1"
|
|
bitfld.long 0xC 12. "PC13_NS,Protection context 13 non-secure." "0,1"
|
|
bitfld.long 0xC 11. "PC13_PW,Protection context 13 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 10. "PC13_PR,Protection context 13 privileged read enable." "0,1"
|
|
bitfld.long 0xC 9. "PC13_UW,Protection context 13 user write enable." "0,1"
|
|
rbitfld.long 0xC 8. "PC13_UR,Protection context 13 user read enable." "0,1"
|
|
bitfld.long 0xC 4. "PC12_NS,Protection context 12 non-secure." "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PC12_PW,Protection context 12 privileged write enable." "0,1"
|
|
rbitfld.long 0xC 2. "PC12_PR,Protection context 12 privileged read enable." "0,1"
|
|
bitfld.long 0xC 1. "PC12_UW,Protection context 12 user write enable." "0,1"
|
|
rbitfld.long 0xC 0. "PC12_UR,Protection context 12 user read enable." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "PERI_PCLK (Peripheral interconnect - Peripheral Clock)"
|
|
base ad:0x40040000
|
|
repeat 2. (list 0x0 0x1)(list ad:0x40040000 ad:0x40042000)
|
|
tree "GR[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "DIV_CMD,Divider command"
|
|
bitfld.long 0x0 31. "ENABLE,Clock divider enable command (mutually exclusive with DISABLE). Typically SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled its integer and.." "0: Disable the divider using the DIV_CMD,1: Configure the divider's DIV_XXX_CTL register"
|
|
bitfld.long 0x0 30. "DISABLE,Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'." "0,1"
|
|
bitfld.long 0x0 24.--25. "PA_TYPE_SEL,Specifies the divider type of the divider to which phase alignment is performed for the clock enable command:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--23. 1. "PA_DIV_SEL,(PA_TYPE_SEL PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other even when they are.."
|
|
bitfld.long 0x0 8.--9. "TYPE_SEL,Specifies the divider type of the divider on which the command is performed:" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DIV_SEL,(TYPE_SEL DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed."
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xC00)++0x3
|
|
line.long 0x0 "CLOCK_CTL[$1],Clock control"
|
|
bitfld.long 0x0 8.--9. "TYPE_SEL,Specifies divider type:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DIV_SEL,Specifies one of the dividers of the divider type specified by TYPE_SEL."
|
|
repeat.end
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1000)++0x3
|
|
line.long 0x0 "DIV_8_CTL[$1],Divider control (for 8.0 divider)"
|
|
hexmask.long.byte 0x0 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1 256]. Note: this type of divider does NOT allow for a fractional division."
|
|
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
|
|
repeat.end
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1400)++0x3
|
|
line.long 0x0 "DIV_16_CTL[$1],Divider control (for 16.0 divider)"
|
|
hexmask.long.word 0x0 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1 65 536]. Note: this type of divider does NOT allow for a fractional division."
|
|
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
|
|
repeat.end
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1800)++0x3
|
|
line.long 0x0 "DIV_16_5_CTL[$1],Divider control (for 16.5 divider)"
|
|
hexmask.long.word 0x0 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1 65 536]. Note: combined with fractional division this divider type allows for a division in the range [1 65 536 31/32] in 1/32 increments."
|
|
hexmask.long.byte 0x0 3.--7. 1. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_pclk_root[i]' cycle longer than other clock periods."
|
|
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
|
|
repeat.end
|
|
repeat 255. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1C00)++0x3
|
|
line.long 0x0 "DIV_24_5_CTL[$1],Divider control (for 24.5 divider)"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1 16 777 216]. Note: combined with fractional division this divider type allows for a division in the range [1 16 777 216 31/32] in 1/32 increments."
|
|
hexmask.long.byte 0x0 3.--7. 1. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_pclk_root[i]' cycle longer than other clock periods."
|
|
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "PROT (Protection)"
|
|
base ad:0x40230000
|
|
tree "SMPU (SMPU)"
|
|
group.long 0x0++0x3F
|
|
line.long 0x0 "MS0_CTL,Master 0 protection context control"
|
|
hexmask.long.word 0x0 17.--31. 1. "PC_MASK_15_TO_1,Protection context mask for protection contexts '15' down to '1'. Bit PC_MASK_15_TO_1[i] indicates if the MPU MS_CTL.PC[3:0] protection context field can be set to the value 'i+1':"
|
|
rbitfld.long 0x0 16. "PC_MASK_0,Protection context mask for protection context '0'. This field is a constant '0':" "0,1"
|
|
bitfld.long 0x0 8.--9. "PRIO,Device wide bus arbitration priority setting ('0': highest priority '3': lowest priority)." "0,1,2,3"
|
|
bitfld.long 0x0 1. "NS,Security setting ('0': secure mode; '1': non-secure mode)." "0,1"
|
|
bitfld.long 0x0 0. "P,Privileged setting ('0': user mode; '1': privileged mode)." "0,1"
|
|
line.long 0x4 "MS1_CTL,Master 1 protection context control"
|
|
hexmask.long.word 0x4 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x4 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x4 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x4 1. "NS,See MS0_CTL.NS." "0,1"
|
|
bitfld.long 0x4 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x8 "MS2_CTL,Master 2 protection context control"
|
|
hexmask.long.word 0x8 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x8 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x8 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x8 1. "NS,See MS0_CTL.NS." "0,1"
|
|
bitfld.long 0x8 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0xC "MS3_CTL,Master 3 protection context control"
|
|
hexmask.long.word 0xC 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0xC 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0xC 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0xC 1. "NS,See MS0_CTL.NS." "0,1"
|
|
bitfld.long 0xC 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x10 "MS4_CTL,Master 4 protection context control"
|
|
hexmask.long.word 0x10 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x10 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x10 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x10 1. "NS,See MS0_CTL.NS." "0,1"
|
|
bitfld.long 0x10 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x14 "MS5_CTL,Master 5 protection context control"
|
|
hexmask.long.word 0x14 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x14 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x14 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x14 1. "NS,See MS0_CTL.NS." "0,1"
|
|
bitfld.long 0x14 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x18 "MS6_CTL,Master 6 protection context control"
|
|
hexmask.long.word 0x18 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x18 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x18 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x18 1. "NS,See MS0_CTL.NS." "0,1"
|
|
bitfld.long 0x18 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x1C "MS7_CTL,Master 7 protection context control"
|
|
hexmask.long.word 0x1C 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x1C 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x1C 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x1C 1. "NS,See MS0_CTL.NS." "0,1"
|
|
bitfld.long 0x1C 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x20 "MS8_CTL,Master 8 protection context control"
|
|
hexmask.long.word 0x20 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x20 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x20 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x20 1. "NS,See MS0_CTL.NS." "0,1"
|
|
bitfld.long 0x20 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x24 "MS9_CTL,Master 9 protection context control"
|
|
hexmask.long.word 0x24 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x24 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x24 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x24 1. "NS,See MS0_CTL.NS." "0,1"
|
|
bitfld.long 0x24 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x28 "MS10_CTL,Master 10 protection context control"
|
|
hexmask.long.word 0x28 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x28 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x28 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x28 1. "NS,See MS0_CTL.NS." "0,1"
|
|
bitfld.long 0x28 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x2C "MS11_CTL,Master 11 protection context control"
|
|
hexmask.long.word 0x2C 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x2C 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x2C 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x2C 1. "NS,See MS0_CTL.NS." "0,1"
|
|
bitfld.long 0x2C 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x30 "MS12_CTL,Master 12 protection context control"
|
|
hexmask.long.word 0x30 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x30 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x30 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x30 1. "NS,See MS0_CTL.NS." "0,1"
|
|
bitfld.long 0x30 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x34 "MS13_CTL,Master 13 protection context control"
|
|
hexmask.long.word 0x34 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x34 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x34 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x34 1. "NS,See MS0_CTL.NS." "0,1"
|
|
bitfld.long 0x34 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x38 "MS14_CTL,Master 14 protection context control"
|
|
hexmask.long.word 0x38 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x38 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x38 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x38 1. "NS,See MS0_CTL.NS." "0,1"
|
|
bitfld.long 0x38 0. "P,See MS0_CTL.P." "0,1"
|
|
line.long 0x3C "MS15_CTL,Master 15 protection context control"
|
|
hexmask.long.word 0x3C 17.--31. 1. "PC_MASK_15_TO_1,See MS0_CTL.PC_MASK_15_TO_1."
|
|
rbitfld.long 0x3C 16. "PC_MASK_0,See MS0_CTL.PC_MASK_0." "0,1"
|
|
bitfld.long 0x3C 8.--9. "PRIO,See MS0_CTL.PRIO" "0,1,2,3"
|
|
bitfld.long 0x3C 1. "NS,See MS0_CTL.NS." "0,1"
|
|
bitfld.long 0x3C 0. "P,See MS0_CTL.P." "0,1"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40232000 ad:0x40232040 ad:0x40232080 ad:0x402320C0 ad:0x40232100 ad:0x40232140 ad:0x40232180 ad:0x402321C0 ad:0x40232200 ad:0x40232240 ad:0x40232280 ad:0x402322C0 ad:0x40232300 ad:0x40232340 ad:0x40232380 ad:0x402323C0)
|
|
tree "SMPU_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "ADDR0,SMPU region address 0 (slave structure)"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR24,This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT0.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result some of the lesser significant address bits of.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "SUBREGION_DISABLE,This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:"
|
|
line.long 0x4 "ATT0,SMPU region attributes 0 (slave structure)"
|
|
bitfld.long 0x4 31. "ENABLED,Region enable:" "0,1"
|
|
bitfld.long 0x4 30. "PC_MATCH,This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the region size:"
|
|
hexmask.long.word 0x4 9.--23. 1. "PC_MASK_15_TO_1,This field specifies protection context identifier based access control."
|
|
rbitfld.long 0x4 8. "PC_MASK_0,This field specifies protection context identifier based access control for protection context '0'." "0,1"
|
|
bitfld.long 0x4 6. "NS,Non-secure:" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PX,Privileged execute enable:" "0,1"
|
|
bitfld.long 0x4 4. "PW,Privileged write enable:" "0,1"
|
|
bitfld.long 0x4 3. "PR,Privileged read enable:" "0,1"
|
|
bitfld.long 0x4 2. "UX,User execute enable:" "0,1"
|
|
bitfld.long 0x4 1. "UW,User write enable:" "0,1"
|
|
bitfld.long 0x4 0. "UR,User read enable:" "0,1"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "ADDR1,SMPU region address 1 (master structure)"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR24,This field specifies the most significant bits of the 32-bit address of an address region."
|
|
hexmask.long.byte 0x0 0.--7. 1. "SUBREGION_DISABLE,This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:"
|
|
group.long ($2+0x24)++0x3
|
|
line.long 0x0 "ATT1,SMPU region attributes 1 (master structure)"
|
|
bitfld.long 0x0 31. "ENABLED,Region enable:" "0,1"
|
|
bitfld.long 0x0 30. "PC_MATCH,This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process:" "0,1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "REGION_SIZE,This field specifies the region size:"
|
|
hexmask.long.word 0x0 9.--23. 1. "PC_MASK_15_TO_1,This field specifies protection context identifier based access control."
|
|
rbitfld.long 0x0 8. "PC_MASK_0,This field specifies protection context identifier based access control for protection context '0'." "0,1"
|
|
bitfld.long 0x0 6. "NS,Non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 5. "PX,Privileged execute enable:" "0,1"
|
|
bitfld.long 0x0 4. "PW,Privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 3. "PR,Privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 2. "UX,User execute enable:" "0,1"
|
|
bitfld.long 0x0 1. "UW,User write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "UR,User read enable:" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x40232400 ad:0x40232440 ad:0x40232480 ad:0x402324C0 ad:0x40232500 ad:0x40232540 ad:0x40232580 ad:0x402325C0 ad:0x40232600 ad:0x40232640 ad:0x40232680 ad:0x402326C0 ad:0x40232700 ad:0x40232740 ad:0x40232780 ad:0x402327C0)
|
|
tree "SMPU_STRUCT[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "ADDR0,SMPU region address 0 (slave structure)"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR24,This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT0.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result some of the lesser significant address bits of.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "SUBREGION_DISABLE,This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:"
|
|
line.long 0x4 "ATT0,SMPU region attributes 0 (slave structure)"
|
|
bitfld.long 0x4 31. "ENABLED,Region enable:" "0,1"
|
|
bitfld.long 0x4 30. "PC_MATCH,This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the region size:"
|
|
hexmask.long.word 0x4 9.--23. 1. "PC_MASK_15_TO_1,This field specifies protection context identifier based access control."
|
|
rbitfld.long 0x4 8. "PC_MASK_0,This field specifies protection context identifier based access control for protection context '0'." "0,1"
|
|
bitfld.long 0x4 6. "NS,Non-secure:" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PX,Privileged execute enable:" "0,1"
|
|
bitfld.long 0x4 4. "PW,Privileged write enable:" "0,1"
|
|
bitfld.long 0x4 3. "PR,Privileged read enable:" "0,1"
|
|
bitfld.long 0x4 2. "UX,User execute enable:" "0,1"
|
|
bitfld.long 0x4 1. "UW,User write enable:" "0,1"
|
|
bitfld.long 0x4 0. "UR,User read enable:" "0,1"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "ADDR1,SMPU region address 1 (master structure)"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR24,This field specifies the most significant bits of the 32-bit address of an address region."
|
|
hexmask.long.byte 0x0 0.--7. 1. "SUBREGION_DISABLE,This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:"
|
|
group.long ($2+0x24)++0x3
|
|
line.long 0x0 "ATT1,SMPU region attributes 1 (master structure)"
|
|
bitfld.long 0x0 31. "ENABLED,Region enable:" "0,1"
|
|
bitfld.long 0x0 30. "PC_MATCH,This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process:" "0,1"
|
|
hexmask.long.byte 0x0 24.--28. 1. "REGION_SIZE,This field specifies the region size:"
|
|
hexmask.long.word 0x0 9.--23. 1. "PC_MASK_15_TO_1,This field specifies protection context identifier based access control."
|
|
rbitfld.long 0x0 8. "PC_MASK_0,This field specifies protection context identifier based access control for protection context '0'." "0,1"
|
|
bitfld.long 0x0 6. "NS,Non-secure:" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 5. "PX,Privileged execute enable:" "0,1"
|
|
bitfld.long 0x0 4. "PW,Privileged write enable:" "0,1"
|
|
rbitfld.long 0x0 3. "PR,Privileged read enable:" "0,1"
|
|
rbitfld.long 0x0 2. "UX,User execute enable:" "0,1"
|
|
bitfld.long 0x0 1. "UW,User write enable:" "0,1"
|
|
rbitfld.long 0x0 0. "UR,User read enable:" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40234000 ad:0x40234400 ad:0x40234800 ad:0x40234C00 ad:0x40235000 ad:0x40235400 ad:0x40235800 ad:0x40235C00 ad:0x40236000 ad:0x40236400 ad:0x40236800 ad:0x40236C00 ad:0x40237000 ad:0x40237400 ad:0x40237800 ad:0x40237C00)
|
|
tree "MPU[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "MS_CTL,Master control"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PC_SAVED,Saved protection context. Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields."
|
|
hexmask.long.byte 0x0 0.--3. 1. "PC,Active protection context (PC). Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. In addition a write transfer with protection context '0' can change this field (protection.."
|
|
repeat 127. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "MS_CTL_READ_MIR[$1],Master control read mirror"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PC_SAVED,Read-only mirror of MS_CTL.PC_SAVED"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PC,Read-only mirror of MS_CTL.PC"
|
|
repeat.end
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list 0x200 0x220 0x240 0x260 0x280 0x2A0 0x2C0 0x2E0)
|
|
tree "MPU_STRUCT[$1]"
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "ADDR,MPU region address"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR24,This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result some of the lesser significant address bits of.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "SUBREGION_DISABLE,This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:"
|
|
line.long 0x4 "ATT,MPU region attrributes"
|
|
bitfld.long 0x4 31. "ENABLED,Region enable:" "0,1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REGION_SIZE,This field specifies the region size:"
|
|
bitfld.long 0x4 6. "NS,Non-secure:" "0,1"
|
|
bitfld.long 0x4 5. "PX,Privileged execute enable:" "0,1"
|
|
bitfld.long 0x4 4. "PW,Privileged write enable:" "0,1"
|
|
bitfld.long 0x4 3. "PR,Privileged read enable:" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "UX,User execute enable:" "0,1"
|
|
bitfld.long 0x4 1. "UW,User write enable:" "0,1"
|
|
bitfld.long 0x4 0. "UR,User read enable:" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "SCB (Serial Communications Block (SPI/UART/I2C))"
|
|
base ad:0x0
|
|
tree "SCB0"
|
|
base ad:0x40600000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,SCB block is enabled ('1') or not ('0'). The proper order in which to initialize SCB is as follows:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "EC_ACCESS,EC_ACCESS is used to enable I2CS_EC or SPIS_EC access to internal EZ memory." "0: disable clk_scb,1: enable clk_scb"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the internal CPU accesses to EZ memory coincide/collide this bit determines whether the CPU access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MEM_WIDTH,Determines the number of bits per FIFO data element." "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C) or slave selection detection logic (SPI)" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
|
|
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,Master ('1') or slave ('0') mode. In master mode transmission will commence on availability of data frames in the TX FIFO. In slave mode when selected and there is no data frame in the TX FIFO the slave will transmit all '1's. In both.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "SSEL_HOLD_DEL,Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MOSI bit and SELECT deactivation)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SSEL_SETUP_DEL,Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MOSI bit)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SSEL_POLARITY3,Slave select polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SSEL_POLARITY2,Slave select polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSEL_POLARITY1,Slave select polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SSEL_POLARITY0,Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SCLK_CONTINUOUS,Only applicable in master mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPOL,Indicates the clock polarity. This field together with the CPHA field indicates when MOSI data is driven and MISO data is captured:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPHA,Indicates the clock phase. This field together with the CPOL field indicates when MOSI data is driven and MISO data is captured:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "SPI_STATUS,SPI status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
|
|
newline
|
|
bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
|
|
bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
|
|
line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
|
|
bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "UART_CTRL,UART control"
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
|
|
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
|
|
bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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line.long 0x8 "UART_RX_CTRL,UART receiver control"
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bitfld.long 0x8 24. "BREAK_LEVEL,0: low level pulse detection like Break field in LIN protocol" "0: low level pulse detection,1: high level pulse detection"
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hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
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bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'. This functionality is intended.." "0,1"
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is.." "0,1"
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period." "0,1"
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails." "0,1"
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
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bitfld.long 0x8 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode parity checking is always enabled through hardware. In IrDA submode parity checking is always disabled through hardware." "0,1"
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bitfld.long 0x8 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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rgroup.long 0x4C++0x3
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line.long 0x0 "UART_RX_STATUS,UART receiver status"
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hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of SCB clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of SCB clock periods that constitute a bit period. This field has.."
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group.long 0x50++0x3
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line.long 0x0 "UART_FLOW_CTRL,UART flow control"
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bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0,1"
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0,1"
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is effectively disabled (may be useful for debug purposes)."
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group.long 0x60++0x3
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line.long 0x0 "I2C_CTRL,I2C control"
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bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself." "0,1"
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bitfld.long 0x0 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,This field is used during an address match or general call address in internally clocked mode" "0: clock stretching is performed,1: a received"
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0' clock stretching is used instead (till the receiver FIFO is no longer full)." "0,1"
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full." "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 SCB clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median.."
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 SCB clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median.."
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rgroup.long 0x64++0x3
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line.long 0x0 "I2C_STATUS,I2C status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the.."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 2. "I2CS_IC_BUSY,Indicates whether the internally clocked slave logic is being accessed by external I2C master." "0,1"
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bitfld.long 0x0 1. "I2C_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If SCB block is disabled BUS_BUSY is '0'. After.." "0,1"
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group.long 0x68++0xB
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line.long 0x0 "I2C_M_CMD,I2C master command"
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bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 3. "M_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative filter delay on SDA output to meet tHD_DAT parameter" "0,1,2,3"
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Enable for 50ns glitch filter on SCL input" "0,1"
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Enable for 50ns glitch filter on SDA input" "0,1"
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only valid.."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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wgroup.long 0x240++0x3
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
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hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
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group.long 0x300++0x7
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line.long 0x0 "RX_CTRL,Receiver control"
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bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only.."
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
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rgroup.long 0x308++0x3
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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group.long 0x310++0x3
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line.long 0x0 "RX_MATCH,Slave address and mask"
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hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the slave address bits take part in the matching. MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,Slave device address."
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rgroup.long 0x340++0x7
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
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hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
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rgroup.long 0xE00++0x3
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
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bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
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group.long 0xE80++0x3
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
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group.long 0xE88++0x3
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line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xE8C++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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|
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xEC0++0x3
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
|
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group.long 0xEC8++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xECC++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF00++0xB
|
|
line.long 0x0 "INTR_M,Master interrupt request"
|
|
bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
|
|
line.long 0x4 "INTR_M_SET,Master interrupt set request"
|
|
bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
|
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
|
line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. The Firmware may decide.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,I2C slave matching address received. If CTRL.ADDR_ACCEPT the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,I2C slave acknowledgement received. Set to '1' when the slave receives a ACK (typically after the slave transmitted TX data)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,I2C slave negative acknowledgement received. Set to '1' when the slave receives a NACK (typically after the slave transmitted TX data)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1' when event is detected. Write with.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when SCB is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,TX FIFO is not full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Parity error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Frame error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full RX FIFO. Note: in I2C mode the OVERFLOW is set when a data frame is received and the RX FIFO is full independent of whether it is ACK'd or NACK'd." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,RX FIFO is not empty." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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|
newline
|
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bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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|
newline
|
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bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
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|
newline
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bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
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|
tree.end
|
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tree "SCB1"
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base ad:0x40610000
|
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group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,SCB block is enabled ('1') or not ('0'). The proper order in which to initialize SCB is as follows:" "0,1"
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|
newline
|
|
bitfld.long 0x0 28. "EC_ACCESS,EC_ACCESS is used to enable I2CS_EC or SPIS_EC access to internal EZ memory." "0: disable clk_scb,1: enable clk_scb"
|
|
newline
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
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|
newline
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bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the internal CPU accesses to EZ memory coincide/collide this bit determines whether the CPU access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is.." "0,1"
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|
newline
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bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
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newline
|
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bitfld.long 0x0 14.--15. "MEM_WIDTH,Determines the number of bits per FIFO data element." "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1')." "0,1"
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|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block" "0,1"
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|
newline
|
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bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C) or slave selection detection logic (SPI)" "0,1"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
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|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
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|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
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|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
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|
rgroup.long 0xC++0x3
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|
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
|
|
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note:" "0,1"
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|
newline
|
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bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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|
newline
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hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,Master ('1') or slave ('0') mode. In master mode transmission will commence on availability of data frames in the TX FIFO. In slave mode when selected and there is no data frame in the TX FIFO the slave will transmit all '1's. In both.." "0,1"
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newline
|
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bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
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|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0,1"
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|
newline
|
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bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation)." "0,1"
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newline
|
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bitfld.long 0x0 13. "SSEL_HOLD_DEL,Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MOSI bit and SELECT deactivation)." "0,1"
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|
newline
|
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bitfld.long 0x0 12. "SSEL_SETUP_DEL,Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MOSI bit)." "0,1"
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|
newline
|
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bitfld.long 0x0 11. "SSEL_POLARITY3,Slave select polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SSEL_POLARITY2,Slave select polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSEL_POLARITY1,Slave select polarity." "0,1"
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|
newline
|
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bitfld.long 0x0 8. "SSEL_POLARITY0,Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes:" "0,1"
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|
newline
|
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bitfld.long 0x0 5. "SCLK_CONTINUOUS,Only applicable in master mode." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
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newline
|
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bitfld.long 0x0 3. "CPOL,Indicates the clock polarity. This field together with the CPHA field indicates when MOSI data is driven and MISO data is captured:" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "CPHA,Indicates the clock phase. This field together with the CPOL field indicates when MOSI data is driven and MISO data is captured:" "0,1"
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|
newline
|
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bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
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|
newline
|
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bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "SPI_STATUS,SPI status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
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|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
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|
newline
|
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bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
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|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
|
|
bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
|
|
line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
|
|
bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "UART_CTRL,UART control"
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
|
|
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
|
|
bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "UART_RX_CTRL,UART receiver control"
|
|
bitfld.long 0x8 24. "BREAK_LEVEL,0: low level pulse detection like Break field in LIN protocol" "0: low level pulse detection,1: high level pulse detection"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
|
|
newline
|
|
bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'. This functionality is intended.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode parity checking is always enabled through hardware. In IrDA submode parity checking is always disabled through hardware." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "UART_RX_STATUS,UART receiver status"
|
|
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of SCB clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of SCB clock periods that constitute a bit period. This field has.."
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
|
|
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is effectively disabled (may be useful for debug purposes)."
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "I2C_CTRL,I2C control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
|
|
newline
|
|
bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,This field is used during an address match or general call address in internally clocked mode" "0: clock stretching is performed,1: a received"
|
|
newline
|
|
bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0' clock stretching is used instead (till the receiver FIFO is no longer full)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 SCB clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 SCB clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median.."
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "I2C_STATUS,I2C status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1') as clock domain.."
|
|
newline
|
|
bitfld.long 0x0 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START REPEATED START STOP or an address this field is '0''." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START REPEATED START STOP or an address this field is '0''." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2CS_IC_BUSY,Indicates whether the internally clocked slave logic is being accessed by external I2C master." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and.." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If SCB block is disabled BUS_BUSY is '0'. After.." "0,1"
|
|
group.long 0x68++0xB
|
|
line.long 0x0 "I2C_M_CMD,I2C master command"
|
|
bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
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newline
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bitfld.long 0x0 3. "M_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'." "0,1"
|
|
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|
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bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
|
|
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
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|
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|
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
|
|
line.long 0x4 "I2C_S_CMD,I2C slave command"
|
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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|
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
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|
line.long 0x8 "I2C_CFG,I2C configuration"
|
|
bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative filter delay on SDA output to meet tHD_DAT parameter" "0,1,2,3"
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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newline
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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newline
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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newline
|
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Enable for 50ns glitch filter on SCL input" "0,1"
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|
newline
|
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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newline
|
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Enable for 50ns glitch filter on SDA input" "0,1"
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newline
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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|
group.long 0x200++0x7
|
|
line.long 0x0 "TX_CTRL,Transmitter control"
|
|
bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0,1"
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newline
|
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only valid.."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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|
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
|
|
rgroup.long 0x208++0x3
|
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
|
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
|
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wgroup.long 0x240++0x3
|
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
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|
hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
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|
group.long 0x300++0x7
|
|
line.long 0x0 "RX_CTRL,Receiver control"
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|
bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only.."
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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newline
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
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rgroup.long 0x308++0x3
|
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
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|
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
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newline
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
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|
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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group.long 0x310++0x3
|
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line.long 0x0 "RX_MATCH,Slave address and mask"
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hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the slave address bits take part in the matching. MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,Slave device address."
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rgroup.long 0x340++0x7
|
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
|
|
line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
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|
rgroup.long 0xE00++0x3
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
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bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
|
|
group.long 0xE80++0x3
|
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
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|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
|
|
group.long 0xE88++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xE8C++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
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group.long 0xEC0++0x3
|
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
|
|
group.long 0xEC8++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xECC++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF00++0xB
|
|
line.long 0x0 "INTR_M,Master interrupt request"
|
|
bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
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|
newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
|
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newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
|
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line.long 0x4 "INTR_M_SET,Master interrupt set request"
|
|
bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
|
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
|
line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. The Firmware may decide.." "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,I2C slave matching address received. If CTRL.ADDR_ACCEPT the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,I2C slave acknowledgement received. Set to '1' when the slave receives a ACK (typically after the slave transmitted TX data)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,I2C slave negative acknowledgement received. Set to '1' when the slave receives a NACK (typically after the slave transmitted TX data)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
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line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to.." "0,1"
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newline
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bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1' when event is detected. Write with.." "0,1"
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newline
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bitfld.long 0x0 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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newline
|
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bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
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newline
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bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when SCB is ready to transfer data and EMPTY is '1'." "0,1"
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newline
|
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bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
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newline
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bitfld.long 0x0 4. "EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
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newline
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bitfld.long 0x0 1. "NOT_FULL,TX FIFO is not full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
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newline
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bitfld.long 0x0 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
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line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
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bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
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bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
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line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
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line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier.." "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "PARITY_ERROR,Parity error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame.." "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "FRAME_ERROR,Frame error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error:" "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full RX FIFO. Note: in I2C mode the OVERFLOW is set when a data frame is received and the RX FIFO is full independent of whether it is ACK'd or NACK'd." "0,1"
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newline
|
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bitfld.long 0x0 3. "FULL,RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "NOT_EMPTY,RX FIFO is not empty." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TRIGGER,More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
tree "SCB2"
|
|
base ad:0x40620000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,SCB block is enabled ('1') or not ('0'). The proper order in which to initialize SCB is as follows:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "EC_ACCESS,EC_ACCESS is used to enable I2CS_EC or SPIS_EC access to internal EZ memory." "0: disable clk_scb,1: enable clk_scb"
|
|
newline
|
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the internal CPU accesses to EZ memory coincide/collide this bit determines whether the CPU access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is.." "0,1"
|
|
newline
|
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bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MEM_WIDTH,Determines the number of bits per FIFO data element." "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
|
|
newline
|
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bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C) or slave selection detection logic (SPI)" "0,1"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
|
|
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note:" "0,1"
|
|
newline
|
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bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,Master ('1') or slave ('0') mode. In master mode transmission will commence on availability of data frames in the TX FIFO. In slave mode when selected and there is no data frame in the TX FIFO the slave will transmit all '1's. In both.." "0,1"
|
|
newline
|
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bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
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newline
|
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
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newline
|
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0,1"
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|
newline
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bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation)." "0,1"
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bitfld.long 0x0 13. "SSEL_HOLD_DEL,Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MOSI bit and SELECT deactivation)." "0,1"
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bitfld.long 0x0 12. "SSEL_SETUP_DEL,Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MOSI bit)." "0,1"
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bitfld.long 0x0 11. "SSEL_POLARITY3,Slave select polarity." "0,1"
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bitfld.long 0x0 10. "SSEL_POLARITY2,Slave select polarity." "0,1"
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bitfld.long 0x0 9. "SSEL_POLARITY1,Slave select polarity." "0,1"
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bitfld.long 0x0 8. "SSEL_POLARITY0,Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes:" "0,1"
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bitfld.long 0x0 5. "SCLK_CONTINUOUS,Only applicable in master mode." "0,1"
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bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
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bitfld.long 0x0 3. "CPOL,Indicates the clock polarity. This field together with the CPHA field indicates when MOSI data is driven and MISO data is captured:" "0,1"
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bitfld.long 0x0 2. "CPHA,Indicates the clock phase. This field together with the CPOL field indicates when MOSI data is driven and MISO data is captured:" "0,1"
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bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
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bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "SPI_STATUS,SPI status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
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group.long 0x28++0x7
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line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
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bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
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line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
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bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
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group.long 0x40++0xB
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line.long 0x0 "UART_CTRL,UART control"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
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line.long 0x4 "UART_TX_CTRL,UART transmitter control"
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bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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line.long 0x8 "UART_RX_CTRL,UART receiver control"
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bitfld.long 0x8 24. "BREAK_LEVEL,0: low level pulse detection like Break field in LIN protocol" "0: low level pulse detection,1: high level pulse detection"
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hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
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bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'. This functionality is intended.." "0,1"
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is.." "0,1"
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period." "0,1"
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails." "0,1"
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
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bitfld.long 0x8 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode parity checking is always enabled through hardware. In IrDA submode parity checking is always disabled through hardware." "0,1"
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bitfld.long 0x8 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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rgroup.long 0x4C++0x3
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line.long 0x0 "UART_RX_STATUS,UART receiver status"
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hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of SCB clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of SCB clock periods that constitute a bit period. This field has.."
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group.long 0x50++0x3
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line.long 0x0 "UART_FLOW_CTRL,UART flow control"
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bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0,1"
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0,1"
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is effectively disabled (may be useful for debug purposes)."
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group.long 0x60++0x3
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line.long 0x0 "I2C_CTRL,I2C control"
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bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself." "0,1"
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bitfld.long 0x0 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,This field is used during an address match or general call address in internally clocked mode" "0: clock stretching is performed,1: a received"
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0' clock stretching is used instead (till the receiver FIFO is no longer full)." "0,1"
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full." "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 SCB clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median.."
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 SCB clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median.."
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rgroup.long 0x64++0x3
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line.long 0x0 "I2C_STATUS,I2C status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the.."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 2. "I2CS_IC_BUSY,Indicates whether the internally clocked slave logic is being accessed by external I2C master." "0,1"
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bitfld.long 0x0 1. "I2C_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If SCB block is disabled BUS_BUSY is '0'. After.." "0,1"
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group.long 0x68++0xB
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line.long 0x0 "I2C_M_CMD,I2C master command"
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bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 3. "M_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative filter delay on SDA output to meet tHD_DAT parameter" "0,1,2,3"
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Enable for 50ns glitch filter on SCL input" "0,1"
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Enable for 50ns glitch filter on SDA input" "0,1"
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only valid.."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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|
wgroup.long 0x240++0x3
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
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group.long 0x300++0x7
|
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line.long 0x0 "RX_CTRL,Receiver control"
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|
bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only.."
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
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|
rgroup.long 0x308++0x3
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
|
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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group.long 0x310++0x3
|
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line.long 0x0 "RX_MATCH,Slave address and mask"
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hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the slave address bits take part in the matching. MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,Slave device address."
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rgroup.long 0x340++0x7
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
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hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
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rgroup.long 0xE00++0x3
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
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bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
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group.long 0xE80++0x3
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
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group.long 0xE88++0x3
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line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xE8C++0x3
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
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bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xEC0++0x3
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
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group.long 0xEC8++0x3
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line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xECC++0x3
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line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
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bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xF00++0xB
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line.long 0x0 "INTR_M,Master interrupt request"
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bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
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newline
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
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bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
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bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
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newline
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bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
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newline
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
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line.long 0x4 "INTR_M_SET,Master interrupt set request"
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bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_M_MASK,Master interrupt mask"
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bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xF0C++0x3
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line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
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bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xF40++0xB
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line.long 0x0 "INTR_S,Slave interrupt request"
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bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
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newline
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bitfld.long 0x0 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred." "0,1"
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newline
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred." "0,1"
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newline
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. The Firmware may decide.." "0,1"
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newline
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bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
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newline
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,I2C slave matching address received. If CTRL.ADDR_ACCEPT the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
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newline
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bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
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newline
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bitfld.long 0x0 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
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newline
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bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
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newline
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bitfld.long 0x0 2. "I2C_ACK,I2C slave acknowledgement received. Set to '1' when the slave receives a ACK (typically after the slave transmitted TX data)." "0,1"
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newline
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bitfld.long 0x0 1. "I2C_NACK,I2C slave negative acknowledgement received. Set to '1' when the slave receives a NACK (typically after the slave transmitted TX data)." "0,1"
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newline
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
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line.long 0x4 "INTR_S_SET,Slave interrupt set request"
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bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
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bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xF4C++0x3
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line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
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bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
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line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to.." "0,1"
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newline
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bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1' when event is detected. Write with.." "0,1"
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newline
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bitfld.long 0x0 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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newline
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bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
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newline
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bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when SCB is ready to transfer data and EMPTY is '1'." "0,1"
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newline
|
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bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
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newline
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bitfld.long 0x0 4. "EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
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newline
|
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bitfld.long 0x0 1. "NOT_FULL,TX FIFO is not full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
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newline
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bitfld.long 0x0 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
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line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
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bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
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bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
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line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
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|
newline
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bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier.." "0,1"
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|
newline
|
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bitfld.long 0x0 9. "PARITY_ERROR,Parity error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame.." "0,1"
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|
newline
|
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bitfld.long 0x0 8. "FRAME_ERROR,Frame error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error:" "0,1"
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|
newline
|
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bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
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|
newline
|
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bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
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|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full RX FIFO. Note: in I2C mode the OVERFLOW is set when a data frame is received and the RX FIFO is full independent of whether it is ACK'd or NACK'd." "0,1"
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|
newline
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bitfld.long 0x0 3. "FULL,RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
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|
newline
|
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bitfld.long 0x0 2. "NOT_EMPTY,RX FIFO is not empty." "0,1"
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newline
|
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bitfld.long 0x0 0. "TRIGGER,More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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|
newline
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bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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|
newline
|
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bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
|
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bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
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newline
|
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bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
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tree.end
|
|
tree "SCB3"
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base ad:0x40630000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,SCB block is enabled ('1') or not ('0'). The proper order in which to initialize SCB is as follows:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "EC_ACCESS,EC_ACCESS is used to enable I2CS_EC or SPIS_EC access to internal EZ memory." "0: disable clk_scb,1: enable clk_scb"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
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newline
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bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the internal CPU accesses to EZ memory coincide/collide this bit determines whether the CPU access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is.." "0,1"
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newline
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bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
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newline
|
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bitfld.long 0x0 14.--15. "MEM_WIDTH,Determines the number of bits per FIFO data element." "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
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|
newline
|
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bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0,1"
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newline
|
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bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1')." "0,1"
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|
newline
|
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bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block" "0,1"
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|
newline
|
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bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C) or slave selection detection logic (SPI)" "0,1"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
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rgroup.long 0x4++0x3
|
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line.long 0x0 "STATUS,Generic status"
|
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bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
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group.long 0x8++0x3
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line.long 0x0 "CMD_RESP_CTRL,Command/response control"
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hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
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newline
|
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hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
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rgroup.long 0xC++0x3
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line.long 0x0 "CMD_RESP_STATUS,Command/response status"
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bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note:" "0,1"
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newline
|
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bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0,1"
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|
newline
|
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hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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group.long 0x20++0x3
|
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line.long 0x0 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,Master ('1') or slave ('0') mode. In master mode transmission will commence on availability of data frames in the TX FIFO. In slave mode when selected and there is no data frame in the TX FIFO the slave will transmit all '1's. In both.." "0,1"
|
|
newline
|
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bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
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newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
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|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "SSEL_HOLD_DEL,Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MOSI bit and SELECT deactivation)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SSEL_SETUP_DEL,Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MOSI bit)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SSEL_POLARITY3,Slave select polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SSEL_POLARITY2,Slave select polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSEL_POLARITY1,Slave select polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SSEL_POLARITY0,Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SCLK_CONTINUOUS,Only applicable in master mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPOL,Indicates the clock polarity. This field together with the CPHA field indicates when MOSI data is driven and MISO data is captured:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPHA,Indicates the clock phase. This field together with the CPOL field indicates when MOSI data is driven and MISO data is captured:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "SPI_STATUS,SPI status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
|
|
newline
|
|
bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
|
|
bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
|
|
line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
|
|
bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "UART_CTRL,UART control"
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
|
|
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
|
|
bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "UART_RX_CTRL,UART receiver control"
|
|
bitfld.long 0x8 24. "BREAK_LEVEL,0: low level pulse detection like Break field in LIN protocol" "0: low level pulse detection,1: high level pulse detection"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
|
|
newline
|
|
bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'. This functionality is intended.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode parity checking is always enabled through hardware. In IrDA submode parity checking is always disabled through hardware." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "UART_RX_STATUS,UART receiver status"
|
|
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of SCB clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of SCB clock periods that constitute a bit period. This field has.."
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
|
|
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0,1"
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0,1"
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is effectively disabled (may be useful for debug purposes)."
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group.long 0x60++0x3
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line.long 0x0 "I2C_CTRL,I2C control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself." "0,1"
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bitfld.long 0x0 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,This field is used during an address match or general call address in internally clocked mode" "0: clock stretching is performed,1: a received"
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0' clock stretching is used instead (till the receiver FIFO is no longer full)." "0,1"
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full." "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 SCB clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median.."
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 SCB clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median.."
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rgroup.long 0x64++0x3
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line.long 0x0 "I2C_STATUS,I2C status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the.."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 2. "I2CS_IC_BUSY,Indicates whether the internally clocked slave logic is being accessed by external I2C master." "0,1"
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bitfld.long 0x0 1. "I2C_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If SCB block is disabled BUS_BUSY is '0'. After.." "0,1"
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group.long 0x68++0xB
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line.long 0x0 "I2C_M_CMD,I2C master command"
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bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 3. "M_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative filter delay on SDA output to meet tHD_DAT parameter" "0,1,2,3"
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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newline
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Enable for 50ns glitch filter on SCL input" "0,1"
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newline
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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newline
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Enable for 50ns glitch filter on SDA input" "0,1"
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newline
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0,1"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only valid.."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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wgroup.long 0x240++0x3
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
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hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
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group.long 0x300++0x7
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line.long 0x0 "RX_CTRL,Receiver control"
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bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only.."
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
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rgroup.long 0x308++0x3
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
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newline
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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group.long 0x310++0x3
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line.long 0x0 "RX_MATCH,Slave address and mask"
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hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the slave address bits take part in the matching. MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,Slave device address."
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rgroup.long 0x340++0x7
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
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hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
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rgroup.long 0xE00++0x3
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
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bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
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group.long 0xE80++0x3
|
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
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group.long 0xE88++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xE8C++0x3
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
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group.long 0xEC0++0x3
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
|
|
group.long 0xEC8++0x3
|
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line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xECC++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF00++0xB
|
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line.long 0x0 "INTR_M,Master interrupt request"
|
|
bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
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newline
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bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
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newline
|
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bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
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bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
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newline
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
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line.long 0x4 "INTR_M_SET,Master interrupt set request"
|
|
bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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newline
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
|
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
|
line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. The Firmware may decide.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,I2C slave matching address received. If CTRL.ADDR_ACCEPT the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,I2C slave acknowledgement received. Set to '1' when the slave receives a ACK (typically after the slave transmitted TX data)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,I2C slave negative acknowledgement received. Set to '1' when the slave receives a NACK (typically after the slave transmitted TX data)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to.." "0,1"
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|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1' when event is detected. Write with.." "0,1"
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|
newline
|
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bitfld.long 0x0 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when SCB is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
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|
newline
|
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bitfld.long 0x0 4. "EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
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|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,TX FIFO is not full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
|
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line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Parity error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Frame error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full RX FIFO. Note: in I2C mode the OVERFLOW is set when a data frame is received and the RX FIFO is full independent of whether it is ACK'd or NACK'd." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,RX FIFO is not empty." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
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tree.end
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tree "SCB4"
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base ad:0x40640000
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group.long 0x0++0x3
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line.long 0x0 "CTRL,Generic control"
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bitfld.long 0x0 31. "ENABLED,SCB block is enabled ('1') or not ('0'). The proper order in which to initialize SCB is as follows:" "0,1"
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newline
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bitfld.long 0x0 28. "EC_ACCESS,EC_ACCESS is used to enable I2CS_EC or SPIS_EC access to internal EZ memory." "0: disable clk_scb,1: enable clk_scb"
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newline
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
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newline
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bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the internal CPU accesses to EZ memory coincide/collide this bit determines whether the CPU access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is.." "0,1"
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newline
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bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
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newline
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bitfld.long 0x0 14.--15. "MEM_WIDTH,Determines the number of bits per FIFO data element." "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
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newline
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bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0,1"
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newline
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bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1')." "0,1"
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newline
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bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block" "0,1"
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newline
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bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C) or slave selection detection logic (SPI)" "0,1"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
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rgroup.long 0x4++0x3
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line.long 0x0 "STATUS,Generic status"
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bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
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group.long 0x8++0x3
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line.long 0x0 "CMD_RESP_CTRL,Command/response control"
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hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
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newline
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hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
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rgroup.long 0xC++0x3
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line.long 0x0 "CMD_RESP_STATUS,Command/response status"
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bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note:" "0,1"
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newline
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bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0,1"
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newline
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hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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newline
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hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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group.long 0x20++0x3
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line.long 0x0 "SPI_CTRL,SPI control"
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bitfld.long 0x0 31. "MASTER_MODE,Master ('1') or slave ('0') mode. In master mode transmission will commence on availability of data frames in the TX FIFO. In slave mode when selected and there is no data frame in the TX FIFO the slave will transmit all '1's. In both.." "0,1"
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newline
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bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
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newline
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0,1"
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newline
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bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation)." "0,1"
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newline
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bitfld.long 0x0 13. "SSEL_HOLD_DEL,Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MOSI bit and SELECT deactivation)." "0,1"
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newline
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bitfld.long 0x0 12. "SSEL_SETUP_DEL,Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MOSI bit)." "0,1"
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newline
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bitfld.long 0x0 11. "SSEL_POLARITY3,Slave select polarity." "0,1"
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newline
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bitfld.long 0x0 10. "SSEL_POLARITY2,Slave select polarity." "0,1"
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newline
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bitfld.long 0x0 9. "SSEL_POLARITY1,Slave select polarity." "0,1"
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newline
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bitfld.long 0x0 8. "SSEL_POLARITY0,Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes:" "0,1"
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newline
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bitfld.long 0x0 5. "SCLK_CONTINUOUS,Only applicable in master mode." "0,1"
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newline
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bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
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newline
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bitfld.long 0x0 3. "CPOL,Indicates the clock polarity. This field together with the CPHA field indicates when MOSI data is driven and MISO data is captured:" "0,1"
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newline
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bitfld.long 0x0 2. "CPHA,Indicates the clock phase. This field together with the CPOL field indicates when MOSI data is driven and MISO data is captured:" "0,1"
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newline
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bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
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newline
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bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "SPI_STATUS,SPI status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
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newline
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
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newline
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bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
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newline
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bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
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group.long 0x28++0x7
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line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
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bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
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newline
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bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
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line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
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bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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newline
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
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newline
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
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group.long 0x40++0xB
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line.long 0x0 "UART_CTRL,UART control"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
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line.long 0x4 "UART_TX_CTRL,UART transmitter control"
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bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
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newline
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
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newline
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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newline
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bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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line.long 0x8 "UART_RX_CTRL,UART receiver control"
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bitfld.long 0x8 24. "BREAK_LEVEL,0: low level pulse detection like Break field in LIN protocol" "0: low level pulse detection,1: high level pulse detection"
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newline
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hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
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newline
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bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'. This functionality is intended.." "0,1"
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newline
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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newline
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is.." "0,1"
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newline
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period." "0,1"
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newline
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails." "0,1"
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newline
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
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newline
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bitfld.long 0x8 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode parity checking is always enabled through hardware. In IrDA submode parity checking is always disabled through hardware." "0,1"
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newline
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bitfld.long 0x8 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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newline
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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rgroup.long 0x4C++0x3
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line.long 0x0 "UART_RX_STATUS,UART receiver status"
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hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of SCB clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of SCB clock periods that constitute a bit period. This field has.."
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group.long 0x50++0x3
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line.long 0x0 "UART_FLOW_CTRL,UART flow control"
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bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0,1"
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newline
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0,1"
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newline
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0,1"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is effectively disabled (may be useful for debug purposes)."
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group.long 0x60++0x3
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line.long 0x0 "I2C_CTRL,I2C control"
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bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself." "0,1"
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newline
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bitfld.long 0x0 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')." "0,1"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
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newline
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
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newline
|
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,This field is used during an address match or general call address in internally clocked mode" "0: clock stretching is performed,1: a received"
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newline
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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newline
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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newline
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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newline
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0' clock stretching is used instead (till the receiver FIFO is no longer full)." "0,1"
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newline
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full." "0,1"
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newline
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 SCB clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median.."
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newline
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 SCB clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median.."
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rgroup.long 0x64++0x3
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line.long 0x0 "I2C_STATUS,I2C status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the.."
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newline
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1') as clock domain.."
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newline
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bitfld.long 0x0 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START REPEATED START STOP or an address this field is '0''." "0,1"
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newline
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bitfld.long 0x0 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START REPEATED START STOP or an address this field is '0''." "0,1"
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newline
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bitfld.long 0x0 2. "I2CS_IC_BUSY,Indicates whether the internally clocked slave logic is being accessed by external I2C master." "0,1"
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newline
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bitfld.long 0x0 1. "I2C_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and.." "0,1"
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newline
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If SCB block is disabled BUS_BUSY is '0'. After.." "0,1"
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group.long 0x68++0xB
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line.long 0x0 "I2C_M_CMD,I2C master command"
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bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
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newline
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bitfld.long 0x0 3. "M_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'." "0,1"
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newline
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bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
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newline
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
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newline
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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newline
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative filter delay on SDA output to meet tHD_DAT parameter" "0,1,2,3"
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newline
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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newline
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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newline
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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newline
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Enable for 50ns glitch filter on SCL input" "0,1"
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newline
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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newline
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Enable for 50ns glitch filter on SDA input" "0,1"
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newline
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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group.long 0x200++0x7
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|
line.long 0x0 "TX_CTRL,Transmitter control"
|
|
bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0,1"
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|
newline
|
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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|
newline
|
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only valid.."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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newline
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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|
newline
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
|
|
rgroup.long 0x208++0x3
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|
line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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|
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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newline
|
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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newline
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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|
wgroup.long 0x240++0x3
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|
line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
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|
hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
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|
group.long 0x300++0x7
|
|
line.long 0x0 "RX_CTRL,Receiver control"
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|
bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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|
newline
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only.."
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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newline
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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newline
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
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rgroup.long 0x308++0x3
|
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
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newline
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
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|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
|
|
group.long 0x310++0x3
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line.long 0x0 "RX_MATCH,Slave address and mask"
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hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the slave address bits take part in the matching. MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
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newline
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,Slave device address."
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rgroup.long 0x340++0x7
|
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
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hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
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rgroup.long 0xE00++0x3
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
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bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
|
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group.long 0xE80++0x3
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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|
newline
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
|
|
group.long 0xE88++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
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|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xE8C++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xEC0++0x3
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
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group.long 0xEC8++0x3
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line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xECC++0x3
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line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
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bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xF00++0xB
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line.long 0x0 "INTR_M,Master interrupt request"
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bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
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newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
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newline
|
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bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
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newline
|
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bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
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newline
|
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bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
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newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
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line.long 0x4 "INTR_M_SET,Master interrupt set request"
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bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
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bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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rgroup.long 0xF0C++0x3
|
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line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
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line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred." "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred." "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. The Firmware may decide.." "0,1"
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|
newline
|
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bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,I2C slave matching address received. If CTRL.ADDR_ACCEPT the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,I2C slave acknowledgement received. Set to '1' when the slave receives a ACK (typically after the slave transmitted TX data)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,I2C slave negative acknowledgement received. Set to '1' when the slave receives a NACK (typically after the slave transmitted TX data)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to.." "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1' when event is detected. Write with.." "0,1"
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|
newline
|
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bitfld.long 0x0 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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|
newline
|
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bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when SCB is ready to transfer data and EMPTY is '1'." "0,1"
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|
newline
|
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bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
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|
newline
|
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bitfld.long 0x0 4. "EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
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|
newline
|
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bitfld.long 0x0 1. "NOT_FULL,TX FIFO is not full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
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newline
|
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bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Parity error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame.." "0,1"
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|
newline
|
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bitfld.long 0x0 8. "FRAME_ERROR,Frame error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full RX FIFO. Note: in I2C mode the OVERFLOW is set when a data frame is received and the RX FIFO is full independent of whether it is ACK'd or NACK'd." "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "FULL,RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
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|
newline
|
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bitfld.long 0x0 2. "NOT_EMPTY,RX FIFO is not empty." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
tree "SCB5"
|
|
base ad:0x40650000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,SCB block is enabled ('1') or not ('0'). The proper order in which to initialize SCB is as follows:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "EC_ACCESS,EC_ACCESS is used to enable I2CS_EC or SPIS_EC access to internal EZ memory." "0: disable clk_scb,1: enable clk_scb"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the internal CPU accesses to EZ memory coincide/collide this bit determines whether the CPU access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is.." "0,1"
|
|
newline
|
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bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MEM_WIDTH,Determines the number of bits per FIFO data element." "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C) or slave selection detection logic (SPI)" "0,1"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
|
|
group.long 0x8++0x3
|
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line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
|
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rgroup.long 0xC++0x3
|
|
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
|
|
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,Master ('1') or slave ('0') mode. In master mode transmission will commence on availability of data frames in the TX FIFO. In slave mode when selected and there is no data frame in the TX FIFO the slave will transmit all '1's. In both.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "SSEL_HOLD_DEL,Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MOSI bit and SELECT deactivation)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SSEL_SETUP_DEL,Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MOSI bit)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SSEL_POLARITY3,Slave select polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SSEL_POLARITY2,Slave select polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSEL_POLARITY1,Slave select polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SSEL_POLARITY0,Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SCLK_CONTINUOUS,Only applicable in master mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPOL,Indicates the clock polarity. This field together with the CPHA field indicates when MOSI data is driven and MISO data is captured:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPHA,Indicates the clock phase. This field together with the CPOL field indicates when MOSI data is driven and MISO data is captured:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "SPI_STATUS,SPI status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
|
|
newline
|
|
bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
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group.long 0x28++0x7
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line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
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bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
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newline
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bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
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line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
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bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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newline
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
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|
newline
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
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group.long 0x40++0xB
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line.long 0x0 "UART_CTRL,UART control"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
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line.long 0x4 "UART_TX_CTRL,UART transmitter control"
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bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
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newline
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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line.long 0x8 "UART_RX_CTRL,UART receiver control"
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bitfld.long 0x8 24. "BREAK_LEVEL,0: low level pulse detection like Break field in LIN protocol" "0: low level pulse detection,1: high level pulse detection"
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hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
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bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'. This functionality is intended.." "0,1"
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is.." "0,1"
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period." "0,1"
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails." "0,1"
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newline
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
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bitfld.long 0x8 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode parity checking is always enabled through hardware. In IrDA submode parity checking is always disabled through hardware." "0,1"
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newline
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bitfld.long 0x8 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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rgroup.long 0x4C++0x3
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line.long 0x0 "UART_RX_STATUS,UART receiver status"
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hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of SCB clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of SCB clock periods that constitute a bit period. This field has.."
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group.long 0x50++0x3
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line.long 0x0 "UART_FLOW_CTRL,UART flow control"
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bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0,1"
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0,1"
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is effectively disabled (may be useful for debug purposes)."
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group.long 0x60++0x3
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line.long 0x0 "I2C_CTRL,I2C control"
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bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself." "0,1"
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bitfld.long 0x0 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
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newline
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,This field is used during an address match or general call address in internally clocked mode" "0: clock stretching is performed,1: a received"
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newline
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0' clock stretching is used instead (till the receiver FIFO is no longer full)." "0,1"
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full." "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 SCB clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median.."
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 SCB clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median.."
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rgroup.long 0x64++0x3
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line.long 0x0 "I2C_STATUS,I2C status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the.."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START REPEATED START STOP or an address this field is '0''." "0,1"
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newline
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bitfld.long 0x0 2. "I2CS_IC_BUSY,Indicates whether the internally clocked slave logic is being accessed by external I2C master." "0,1"
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newline
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bitfld.long 0x0 1. "I2C_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If SCB block is disabled BUS_BUSY is '0'. After.." "0,1"
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group.long 0x68++0xB
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line.long 0x0 "I2C_M_CMD,I2C master command"
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bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
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newline
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bitfld.long 0x0 3. "M_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'." "0,1"
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newline
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bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
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newline
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
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newline
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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newline
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative filter delay on SDA output to meet tHD_DAT parameter" "0,1,2,3"
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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newline
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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newline
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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newline
|
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Enable for 50ns glitch filter on SCL input" "0,1"
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newline
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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newline
|
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Enable for 50ns glitch filter on SDA input" "0,1"
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newline
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
|
|
bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0,1"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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newline
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only valid.."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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newline
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
|
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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|
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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newline
|
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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|
wgroup.long 0x240++0x3
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
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hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
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group.long 0x300++0x7
|
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line.long 0x0 "RX_CTRL,Receiver control"
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bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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newline
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only.."
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
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rgroup.long 0x308++0x3
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
|
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
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newline
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
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|
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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group.long 0x310++0x3
|
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line.long 0x0 "RX_MATCH,Slave address and mask"
|
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hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the slave address bits take part in the matching. MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,Slave device address."
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|
rgroup.long 0x340++0x7
|
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
|
|
line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
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|
hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
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|
rgroup.long 0xE00++0x3
|
|
line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
|
|
bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
|
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newline
|
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
|
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newline
|
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
|
|
group.long 0xE80++0x3
|
|
line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
|
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|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
|
|
group.long 0xE88++0x3
|
|
line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xE8C++0x3
|
|
line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xEC0++0x3
|
|
line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
|
|
group.long 0xEC8++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xECC++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF00++0xB
|
|
line.long 0x0 "INTR_M,Master interrupt request"
|
|
bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
|
|
line.long 0x4 "INTR_M_SET,Master interrupt set request"
|
|
bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
|
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
|
line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. The Firmware may decide.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,I2C slave matching address received. If CTRL.ADDR_ACCEPT the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,I2C slave acknowledgement received. Set to '1' when the slave receives a ACK (typically after the slave transmitted TX data)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,I2C slave negative acknowledgement received. Set to '1' when the slave receives a NACK (typically after the slave transmitted TX data)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1' when event is detected. Write with.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when SCB is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,TX FIFO is not full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Parity error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Frame error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
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newline
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bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
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newline
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bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full RX FIFO. Note: in I2C mode the OVERFLOW is set when a data frame is received and the RX FIFO is full independent of whether it is ACK'd or NACK'd." "0,1"
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newline
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bitfld.long 0x0 3. "FULL,RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
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newline
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bitfld.long 0x0 2. "NOT_EMPTY,RX FIFO is not empty." "0,1"
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newline
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bitfld.long 0x0 0. "TRIGGER,More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
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line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
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bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
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bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
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bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
rgroup.long 0xFCC++0x3
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line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
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tree.end
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tree "SCB6"
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base ad:0x40660000
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group.long 0x0++0x3
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line.long 0x0 "CTRL,Generic control"
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bitfld.long 0x0 31. "ENABLED,SCB block is enabled ('1') or not ('0'). The proper order in which to initialize SCB is as follows:" "0,1"
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newline
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bitfld.long 0x0 28. "EC_ACCESS,EC_ACCESS is used to enable I2CS_EC or SPIS_EC access to internal EZ memory." "0: disable clk_scb,1: enable clk_scb"
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newline
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
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newline
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bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the internal CPU accesses to EZ memory coincide/collide this bit determines whether the CPU access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is.." "0,1"
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newline
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bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
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newline
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bitfld.long 0x0 14.--15. "MEM_WIDTH,Determines the number of bits per FIFO data element." "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
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newline
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bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0,1"
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newline
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bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1')." "0,1"
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|
newline
|
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bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block" "0,1"
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newline
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bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C) or slave selection detection logic (SPI)" "0,1"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
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rgroup.long 0x4++0x3
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line.long 0x0 "STATUS,Generic status"
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bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
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group.long 0x8++0x3
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line.long 0x0 "CMD_RESP_CTRL,Command/response control"
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hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
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newline
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hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
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rgroup.long 0xC++0x3
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line.long 0x0 "CMD_RESP_STATUS,Command/response status"
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bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note:" "0,1"
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newline
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bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0,1"
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newline
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hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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newline
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hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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group.long 0x20++0x3
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line.long 0x0 "SPI_CTRL,SPI control"
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bitfld.long 0x0 31. "MASTER_MODE,Master ('1') or slave ('0') mode. In master mode transmission will commence on availability of data frames in the TX FIFO. In slave mode when selected and there is no data frame in the TX FIFO the slave will transmit all '1's. In both.." "0,1"
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newline
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bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
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newline
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0,1"
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newline
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bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation)." "0,1"
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newline
|
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bitfld.long 0x0 13. "SSEL_HOLD_DEL,Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MOSI bit and SELECT deactivation)." "0,1"
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newline
|
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bitfld.long 0x0 12. "SSEL_SETUP_DEL,Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MOSI bit)." "0,1"
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newline
|
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bitfld.long 0x0 11. "SSEL_POLARITY3,Slave select polarity." "0,1"
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newline
|
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bitfld.long 0x0 10. "SSEL_POLARITY2,Slave select polarity." "0,1"
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|
newline
|
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bitfld.long 0x0 9. "SSEL_POLARITY1,Slave select polarity." "0,1"
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newline
|
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bitfld.long 0x0 8. "SSEL_POLARITY0,Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes:" "0,1"
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newline
|
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bitfld.long 0x0 5. "SCLK_CONTINUOUS,Only applicable in master mode." "0,1"
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newline
|
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bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
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newline
|
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bitfld.long 0x0 3. "CPOL,Indicates the clock polarity. This field together with the CPHA field indicates when MOSI data is driven and MISO data is captured:" "0,1"
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newline
|
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bitfld.long 0x0 2. "CPHA,Indicates the clock phase. This field together with the CPOL field indicates when MOSI data is driven and MISO data is captured:" "0,1"
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newline
|
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bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
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newline
|
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bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
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|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "SPI_STATUS,SPI status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
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newline
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
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newline
|
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bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
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newline
|
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bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
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|
group.long 0x28++0x7
|
|
line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
|
|
bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
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|
newline
|
|
bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
|
|
line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
|
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bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
|
|
group.long 0x40++0xB
|
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line.long 0x0 "UART_CTRL,UART control"
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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|
newline
|
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
|
|
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
|
|
bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "UART_RX_CTRL,UART receiver control"
|
|
bitfld.long 0x8 24. "BREAK_LEVEL,0: low level pulse detection like Break field in LIN protocol" "0: low level pulse detection,1: high level pulse detection"
|
|
newline
|
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hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
|
|
newline
|
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bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'. This functionality is intended.." "0,1"
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newline
|
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
|
|
newline
|
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is.." "0,1"
|
|
newline
|
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode parity checking is always enabled through hardware. In IrDA submode parity checking is always disabled through hardware." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "UART_RX_STATUS,UART receiver status"
|
|
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of SCB clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of SCB clock periods that constitute a bit period. This field has.."
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
|
|
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is effectively disabled (may be useful for debug purposes)."
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "I2C_CTRL,I2C control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
|
|
newline
|
|
bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,This field is used during an address match or general call address in internally clocked mode" "0: clock stretching is performed,1: a received"
|
|
newline
|
|
bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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newline
|
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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|
newline
|
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0' clock stretching is used instead (till the receiver FIFO is no longer full)." "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 SCB clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median.."
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|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 SCB clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median.."
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rgroup.long 0x64++0x3
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line.long 0x0 "I2C_STATUS,I2C status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the.."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 2. "I2CS_IC_BUSY,Indicates whether the internally clocked slave logic is being accessed by external I2C master." "0,1"
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bitfld.long 0x0 1. "I2C_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If SCB block is disabled BUS_BUSY is '0'. After.." "0,1"
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group.long 0x68++0xB
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line.long 0x0 "I2C_M_CMD,I2C master command"
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bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 3. "M_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative filter delay on SDA output to meet tHD_DAT parameter" "0,1,2,3"
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Enable for 50ns glitch filter on SCL input" "0,1"
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Enable for 50ns glitch filter on SDA input" "0,1"
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only valid.."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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wgroup.long 0x240++0x3
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
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hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
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group.long 0x300++0x7
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line.long 0x0 "RX_CTRL,Receiver control"
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bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only.."
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
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rgroup.long 0x308++0x3
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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group.long 0x310++0x3
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line.long 0x0 "RX_MATCH,Slave address and mask"
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hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the slave address bits take part in the matching. MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,Slave device address."
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rgroup.long 0x340++0x7
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
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hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
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rgroup.long 0xE00++0x3
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
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bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
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group.long 0xE80++0x3
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
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group.long 0xE88++0x3
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line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xE8C++0x3
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
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bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xEC0++0x3
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
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group.long 0xEC8++0x3
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line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xECC++0x3
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line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
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bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xF00++0xB
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line.long 0x0 "INTR_M,Master interrupt request"
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bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
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bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
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bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
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bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
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line.long 0x4 "INTR_M_SET,Master interrupt set request"
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bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_M_MASK,Master interrupt mask"
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bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xF0C++0x3
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line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
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bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
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group.long 0xF40++0xB
|
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line.long 0x0 "INTR_S,Slave interrupt request"
|
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bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
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bitfld.long 0x0 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred." "0,1"
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred." "0,1"
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. The Firmware may decide.." "0,1"
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bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,I2C slave matching address received. If CTRL.ADDR_ACCEPT the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
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newline
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bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
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newline
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bitfld.long 0x0 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
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|
newline
|
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bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
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newline
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bitfld.long 0x0 2. "I2C_ACK,I2C slave acknowledgement received. Set to '1' when the slave receives a ACK (typically after the slave transmitted TX data)." "0,1"
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newline
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bitfld.long 0x0 1. "I2C_NACK,I2C slave negative acknowledgement received. Set to '1' when the slave receives a NACK (typically after the slave transmitted TX data)." "0,1"
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newline
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
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bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xF4C++0x3
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line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
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bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xF80++0xB
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line.long 0x0 "INTR_TX,Transmitter interrupt request"
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bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to.." "0,1"
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newline
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bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1' when event is detected. Write with.." "0,1"
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newline
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bitfld.long 0x0 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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newline
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bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
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newline
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bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when SCB is ready to transfer data and EMPTY is '1'." "0,1"
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newline
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bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
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bitfld.long 0x0 4. "EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
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newline
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bitfld.long 0x0 1. "NOT_FULL,TX FIFO is not full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
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newline
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bitfld.long 0x0 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
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line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
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bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
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bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xF8C++0x3
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line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
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bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
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newline
|
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bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xFC0++0xB
|
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line.long 0x0 "INTR_RX,Receiver interrupt request"
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bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
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newline
|
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bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier.." "0,1"
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newline
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bitfld.long 0x0 9. "PARITY_ERROR,Parity error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame.." "0,1"
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newline
|
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bitfld.long 0x0 8. "FRAME_ERROR,Frame error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error:" "0,1"
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newline
|
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bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
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newline
|
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bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
|
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newline
|
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bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full RX FIFO. Note: in I2C mode the OVERFLOW is set when a data frame is received and the RX FIFO is full independent of whether it is ACK'd or NACK'd." "0,1"
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newline
|
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bitfld.long 0x0 3. "FULL,RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
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newline
|
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bitfld.long 0x0 2. "NOT_EMPTY,RX FIFO is not empty." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TRIGGER,More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
|
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line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
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bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
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bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
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bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
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line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
tree "SCB7"
|
|
base ad:0x40670000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,SCB block is enabled ('1') or not ('0'). The proper order in which to initialize SCB is as follows:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "EC_ACCESS,EC_ACCESS is used to enable I2CS_EC or SPIS_EC access to internal EZ memory." "0: disable clk_scb,1: enable clk_scb"
|
|
newline
|
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
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newline
|
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bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the internal CPU accesses to EZ memory coincide/collide this bit determines whether the CPU access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is.." "0,1"
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newline
|
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bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
|
|
newline
|
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bitfld.long 0x0 14.--15. "MEM_WIDTH,Determines the number of bits per FIFO data element." "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
|
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newline
|
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bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1')." "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C) or slave selection detection logic (SPI)" "0,1"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
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rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
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newline
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hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
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rgroup.long 0xC++0x3
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line.long 0x0 "CMD_RESP_STATUS,Command/response status"
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bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note:" "0,1"
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bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0,1"
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hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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group.long 0x20++0x3
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line.long 0x0 "SPI_CTRL,SPI control"
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bitfld.long 0x0 31. "MASTER_MODE,Master ('1') or slave ('0') mode. In master mode transmission will commence on availability of data frames in the TX FIFO. In slave mode when selected and there is no data frame in the TX FIFO the slave will transmit all '1's. In both.." "0,1"
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bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0,1"
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bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation)." "0,1"
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bitfld.long 0x0 13. "SSEL_HOLD_DEL,Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MOSI bit and SELECT deactivation)." "0,1"
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bitfld.long 0x0 12. "SSEL_SETUP_DEL,Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MOSI bit)." "0,1"
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bitfld.long 0x0 11. "SSEL_POLARITY3,Slave select polarity." "0,1"
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bitfld.long 0x0 10. "SSEL_POLARITY2,Slave select polarity." "0,1"
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bitfld.long 0x0 9. "SSEL_POLARITY1,Slave select polarity." "0,1"
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bitfld.long 0x0 8. "SSEL_POLARITY0,Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes:" "0,1"
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bitfld.long 0x0 5. "SCLK_CONTINUOUS,Only applicable in master mode." "0,1"
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bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
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bitfld.long 0x0 3. "CPOL,Indicates the clock polarity. This field together with the CPHA field indicates when MOSI data is driven and MISO data is captured:" "0,1"
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bitfld.long 0x0 2. "CPHA,Indicates the clock phase. This field together with the CPOL field indicates when MOSI data is driven and MISO data is captured:" "0,1"
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bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
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bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "SPI_STATUS,SPI status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
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group.long 0x28++0x7
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line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
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bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
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line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
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bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
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group.long 0x40++0xB
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line.long 0x0 "UART_CTRL,UART control"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
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line.long 0x4 "UART_TX_CTRL,UART transmitter control"
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bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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line.long 0x8 "UART_RX_CTRL,UART receiver control"
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bitfld.long 0x8 24. "BREAK_LEVEL,0: low level pulse detection like Break field in LIN protocol" "0: low level pulse detection,1: high level pulse detection"
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hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
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bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'. This functionality is intended.." "0,1"
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is.." "0,1"
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period." "0,1"
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails." "0,1"
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
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bitfld.long 0x8 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode parity checking is always enabled through hardware. In IrDA submode parity checking is always disabled through hardware." "0,1"
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bitfld.long 0x8 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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rgroup.long 0x4C++0x3
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line.long 0x0 "UART_RX_STATUS,UART receiver status"
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hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of SCB clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of SCB clock periods that constitute a bit period. This field has.."
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group.long 0x50++0x3
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line.long 0x0 "UART_FLOW_CTRL,UART flow control"
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bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0,1"
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0,1"
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is effectively disabled (may be useful for debug purposes)."
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group.long 0x60++0x3
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line.long 0x0 "I2C_CTRL,I2C control"
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bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself." "0,1"
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bitfld.long 0x0 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,This field is used during an address match or general call address in internally clocked mode" "0: clock stretching is performed,1: a received"
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0' clock stretching is used instead (till the receiver FIFO is no longer full)." "0,1"
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full." "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 SCB clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median.."
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 SCB clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median.."
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rgroup.long 0x64++0x3
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line.long 0x0 "I2C_STATUS,I2C status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the.."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 2. "I2CS_IC_BUSY,Indicates whether the internally clocked slave logic is being accessed by external I2C master." "0,1"
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bitfld.long 0x0 1. "I2C_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If SCB block is disabled BUS_BUSY is '0'. After.." "0,1"
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group.long 0x68++0xB
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line.long 0x0 "I2C_M_CMD,I2C master command"
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bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 3. "M_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative filter delay on SDA output to meet tHD_DAT parameter" "0,1,2,3"
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Enable for 50ns glitch filter on SCL input" "0,1"
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Enable for 50ns glitch filter on SDA input" "0,1"
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only valid.."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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wgroup.long 0x240++0x3
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
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hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
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group.long 0x300++0x7
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line.long 0x0 "RX_CTRL,Receiver control"
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bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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newline
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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|
newline
|
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only.."
|
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
|
|
bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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|
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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|
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
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rgroup.long 0x308++0x3
|
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
|
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
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|
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
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|
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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group.long 0x310++0x3
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line.long 0x0 "RX_MATCH,Slave address and mask"
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hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the slave address bits take part in the matching. MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,Slave device address."
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rgroup.long 0x340++0x7
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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|
hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
|
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
|
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hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
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rgroup.long 0xE00++0x3
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
|
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bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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newline
|
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
|
|
group.long 0xE80++0x3
|
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
|
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
|
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
|
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group.long 0xE88++0x3
|
|
line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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rgroup.long 0xE8C++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
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group.long 0xEC0++0x3
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
|
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group.long 0xEC8++0x3
|
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line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xECC++0x3
|
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line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
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group.long 0xF00++0xB
|
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line.long 0x0 "INTR_M,Master interrupt request"
|
|
bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
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|
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|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
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|
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bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
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newline
|
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bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
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newline
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bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
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newline
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
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line.long 0x4 "INTR_M_SET,Master interrupt set request"
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bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
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bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
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line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
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line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
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newline
|
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bitfld.long 0x0 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred." "0,1"
|
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newline
|
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. The Firmware may decide.." "0,1"
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|
newline
|
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bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,I2C slave matching address received. If CTRL.ADDR_ACCEPT the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "I2C_ACK,I2C slave acknowledgement received. Set to '1' when the slave receives a ACK (typically after the slave transmitted TX data)." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "I2C_NACK,I2C slave negative acknowledgement received. Set to '1' when the slave receives a NACK (typically after the slave transmitted TX data)." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to.." "0,1"
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|
newline
|
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bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1' when event is detected. Write with.." "0,1"
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|
newline
|
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bitfld.long 0x0 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when SCB is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
|
|
newline
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bitfld.long 0x0 4. "EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
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newline
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bitfld.long 0x0 1. "NOT_FULL,TX FIFO is not full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
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newline
|
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bitfld.long 0x0 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
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line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
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bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
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bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xF8C++0x3
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line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xFC0++0xB
|
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line.long 0x0 "INTR_RX,Receiver interrupt request"
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bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
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newline
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bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier.." "0,1"
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newline
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bitfld.long 0x0 9. "PARITY_ERROR,Parity error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame.." "0,1"
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newline
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bitfld.long 0x0 8. "FRAME_ERROR,Frame error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error:" "0,1"
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newline
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bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
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newline
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bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
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newline
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bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full RX FIFO. Note: in I2C mode the OVERFLOW is set when a data frame is received and the RX FIFO is full independent of whether it is ACK'd or NACK'd." "0,1"
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newline
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bitfld.long 0x0 3. "FULL,RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
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newline
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bitfld.long 0x0 2. "NOT_EMPTY,RX FIFO is not empty." "0,1"
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newline
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bitfld.long 0x0 0. "TRIGGER,More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
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line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
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bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
|
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bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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newline
|
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bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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|
newline
|
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bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
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bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xFCC++0x3
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line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
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bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
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tree.end
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tree "SCB8"
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base ad:0x40680000
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group.long 0x0++0x3
|
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line.long 0x0 "CTRL,Generic control"
|
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bitfld.long 0x0 31. "ENABLED,SCB block is enabled ('1') or not ('0'). The proper order in which to initialize SCB is as follows:" "0,1"
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newline
|
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bitfld.long 0x0 28. "EC_ACCESS,EC_ACCESS is used to enable I2CS_EC or SPIS_EC access to internal EZ memory." "0: disable clk_scb,1: enable clk_scb"
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newline
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
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newline
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bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the internal CPU accesses to EZ memory coincide/collide this bit determines whether the CPU access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is.." "0,1"
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newline
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bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
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newline
|
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bitfld.long 0x0 14.--15. "MEM_WIDTH,Determines the number of bits per FIFO data element." "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
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newline
|
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bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0,1"
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newline
|
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bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1')." "0,1"
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newline
|
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bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block" "0,1"
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newline
|
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bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C) or slave selection detection logic (SPI)" "0,1"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
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rgroup.long 0x4++0x3
|
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line.long 0x0 "STATUS,Generic status"
|
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bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
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group.long 0x8++0x3
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line.long 0x0 "CMD_RESP_CTRL,Command/response control"
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hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
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newline
|
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hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
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rgroup.long 0xC++0x3
|
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line.long 0x0 "CMD_RESP_STATUS,Command/response status"
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bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note:" "0,1"
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newline
|
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bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0,1"
|
|
newline
|
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hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,Master ('1') or slave ('0') mode. In master mode transmission will commence on availability of data frames in the TX FIFO. In slave mode when selected and there is no data frame in the TX FIFO the slave will transmit all '1's. In both.." "0,1"
|
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newline
|
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bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
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newline
|
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
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newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "SSEL_HOLD_DEL,Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MOSI bit and SELECT deactivation)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SSEL_SETUP_DEL,Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MOSI bit)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SSEL_POLARITY3,Slave select polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SSEL_POLARITY2,Slave select polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSEL_POLARITY1,Slave select polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SSEL_POLARITY0,Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes:" "0,1"
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|
newline
|
|
bitfld.long 0x0 5. "SCLK_CONTINUOUS,Only applicable in master mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPOL,Indicates the clock polarity. This field together with the CPHA field indicates when MOSI data is driven and MISO data is captured:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPHA,Indicates the clock phase. This field together with the CPOL field indicates when MOSI data is driven and MISO data is captured:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "SPI_STATUS,SPI status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
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|
newline
|
|
bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
|
|
bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
|
|
line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
|
|
bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "UART_CTRL,UART control"
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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newline
|
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
|
|
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
|
|
bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "UART_RX_CTRL,UART receiver control"
|
|
bitfld.long 0x8 24. "BREAK_LEVEL,0: low level pulse detection like Break field in LIN protocol" "0: low level pulse detection,1: high level pulse detection"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
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newline
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bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'. This functionality is intended.." "0,1"
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is.." "0,1"
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period." "0,1"
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails." "0,1"
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
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bitfld.long 0x8 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode parity checking is always enabled through hardware. In IrDA submode parity checking is always disabled through hardware." "0,1"
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bitfld.long 0x8 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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rgroup.long 0x4C++0x3
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line.long 0x0 "UART_RX_STATUS,UART receiver status"
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hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of SCB clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of SCB clock periods that constitute a bit period. This field has.."
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group.long 0x50++0x3
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line.long 0x0 "UART_FLOW_CTRL,UART flow control"
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bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0,1"
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0,1"
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is effectively disabled (may be useful for debug purposes)."
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group.long 0x60++0x3
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line.long 0x0 "I2C_CTRL,I2C control"
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bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself." "0,1"
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bitfld.long 0x0 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,This field is used during an address match or general call address in internally clocked mode" "0: clock stretching is performed,1: a received"
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0' clock stretching is used instead (till the receiver FIFO is no longer full)." "0,1"
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full." "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 SCB clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median.."
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 SCB clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median.."
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rgroup.long 0x64++0x3
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line.long 0x0 "I2C_STATUS,I2C status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the.."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 2. "I2CS_IC_BUSY,Indicates whether the internally clocked slave logic is being accessed by external I2C master." "0,1"
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bitfld.long 0x0 1. "I2C_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If SCB block is disabled BUS_BUSY is '0'. After.." "0,1"
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group.long 0x68++0xB
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line.long 0x0 "I2C_M_CMD,I2C master command"
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bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 3. "M_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative filter delay on SDA output to meet tHD_DAT parameter" "0,1,2,3"
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Enable for 50ns glitch filter on SCL input" "0,1"
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Enable for 50ns glitch filter on SDA input" "0,1"
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only valid.."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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wgroup.long 0x240++0x3
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
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hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
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group.long 0x300++0x7
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line.long 0x0 "RX_CTRL,Receiver control"
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bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only.."
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
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rgroup.long 0x308++0x3
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
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|
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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group.long 0x310++0x3
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line.long 0x0 "RX_MATCH,Slave address and mask"
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hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the slave address bits take part in the matching. MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,Slave device address."
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rgroup.long 0x340++0x7
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
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hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
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rgroup.long 0xE00++0x3
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
|
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bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
|
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|
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
|
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|
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
|
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|
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
|
|
group.long 0xE80++0x3
|
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
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|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
|
|
group.long 0xE88++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xE8C++0x3
|
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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|
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|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
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|
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xEC0++0x3
|
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
|
|
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
|
|
group.long 0xEC8++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
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|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xECC++0x3
|
|
line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
|
|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF00++0xB
|
|
line.long 0x0 "INTR_M,Master interrupt request"
|
|
bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
|
|
line.long 0x4 "INTR_M_SET,Master interrupt set request"
|
|
bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
|
|
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
|
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF40++0xB
|
|
line.long 0x0 "INTR_S,Slave interrupt request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. The Firmware may decide.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,I2C slave matching address received. If CTRL.ADDR_ACCEPT the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,I2C slave acknowledgement received. Set to '1' when the slave receives a ACK (typically after the slave transmitted TX data)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,I2C slave negative acknowledgement received. Set to '1' when the slave receives a NACK (typically after the slave transmitted TX data)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
|
|
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
|
line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1' when event is detected. Write with.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when SCB is ready to transfer data and EMPTY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,TX FIFO is not full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
|
|
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Parity error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Frame error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full RX FIFO. Note: in I2C mode the OVERFLOW is set when a data frame is received and the RX FIFO is full independent of whether it is ACK'd or NACK'd." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,RX FIFO is not empty." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
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bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
rgroup.long 0xFCC++0x3
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line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
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bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
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tree.end
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tree "SCB9"
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base ad:0x40690000
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group.long 0x0++0x3
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line.long 0x0 "CTRL,Generic control"
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|
bitfld.long 0x0 31. "ENABLED,SCB block is enabled ('1') or not ('0'). The proper order in which to initialize SCB is as follows:" "0,1"
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newline
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bitfld.long 0x0 28. "EC_ACCESS,EC_ACCESS is used to enable I2CS_EC or SPIS_EC access to internal EZ memory." "0: disable clk_scb,1: enable clk_scb"
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newline
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
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newline
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bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the internal CPU accesses to EZ memory coincide/collide this bit determines whether the CPU access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is.." "0,1"
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newline
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bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
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newline
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bitfld.long 0x0 14.--15. "MEM_WIDTH,Determines the number of bits per FIFO data element." "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
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newline
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bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0,1"
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newline
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bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1')." "0,1"
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newline
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bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block" "0,1"
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newline
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bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C) or slave selection detection logic (SPI)" "0,1"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
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rgroup.long 0x4++0x3
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line.long 0x0 "STATUS,Generic status"
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bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
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group.long 0x8++0x3
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line.long 0x0 "CMD_RESP_CTRL,Command/response control"
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hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
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newline
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hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
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rgroup.long 0xC++0x3
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line.long 0x0 "CMD_RESP_STATUS,Command/response status"
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bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note:" "0,1"
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newline
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bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0,1"
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newline
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hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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newline
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hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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group.long 0x20++0x3
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line.long 0x0 "SPI_CTRL,SPI control"
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bitfld.long 0x0 31. "MASTER_MODE,Master ('1') or slave ('0') mode. In master mode transmission will commence on availability of data frames in the TX FIFO. In slave mode when selected and there is no data frame in the TX FIFO the slave will transmit all '1's. In both.." "0,1"
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newline
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bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
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newline
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
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newline
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0,1"
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newline
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bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation)." "0,1"
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newline
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bitfld.long 0x0 13. "SSEL_HOLD_DEL,Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MOSI bit and SELECT deactivation)." "0,1"
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newline
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bitfld.long 0x0 12. "SSEL_SETUP_DEL,Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MOSI bit)." "0,1"
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newline
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bitfld.long 0x0 11. "SSEL_POLARITY3,Slave select polarity." "0,1"
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newline
|
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bitfld.long 0x0 10. "SSEL_POLARITY2,Slave select polarity." "0,1"
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|
newline
|
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bitfld.long 0x0 9. "SSEL_POLARITY1,Slave select polarity." "0,1"
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newline
|
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bitfld.long 0x0 8. "SSEL_POLARITY0,Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes:" "0,1"
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newline
|
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bitfld.long 0x0 5. "SCLK_CONTINUOUS,Only applicable in master mode." "0,1"
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newline
|
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bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
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newline
|
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bitfld.long 0x0 3. "CPOL,Indicates the clock polarity. This field together with the CPHA field indicates when MOSI data is driven and MISO data is captured:" "0,1"
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newline
|
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bitfld.long 0x0 2. "CPHA,Indicates the clock phase. This field together with the CPOL field indicates when MOSI data is driven and MISO data is captured:" "0,1"
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newline
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bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
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newline
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bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "SPI_STATUS,SPI status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
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newline
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
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newline
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bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
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newline
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bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
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group.long 0x28++0x7
|
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line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
|
|
bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
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newline
|
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bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
|
|
line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
|
|
bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "UART_CTRL,UART control"
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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newline
|
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
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|
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
|
|
bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
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|
newline
|
|
bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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newline
|
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bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "UART_RX_CTRL,UART receiver control"
|
|
bitfld.long 0x8 24. "BREAK_LEVEL,0: low level pulse detection like Break field in LIN protocol" "0: low level pulse detection,1: high level pulse detection"
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|
newline
|
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hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
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newline
|
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bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'. This functionality is intended.." "0,1"
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newline
|
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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|
newline
|
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode parity checking is always enabled through hardware. In IrDA submode parity checking is always disabled through hardware." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "UART_RX_STATUS,UART receiver status"
|
|
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of SCB clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of SCB clock periods that constitute a bit period. This field has.."
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
|
|
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is effectively disabled (may be useful for debug purposes)."
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "I2C_CTRL,I2C control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
|
|
newline
|
|
bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,This field is used during an address match or general call address in internally clocked mode" "0: clock stretching is performed,1: a received"
|
|
newline
|
|
bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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|
newline
|
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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|
newline
|
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0' clock stretching is used instead (till the receiver FIFO is no longer full)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 SCB clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median.."
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|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 SCB clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median.."
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "I2C_STATUS,I2C status"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1') as clock domain.."
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newline
|
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bitfld.long 0x0 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START REPEATED START STOP or an address this field is '0''." "0,1"
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|
newline
|
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bitfld.long 0x0 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START REPEATED START STOP or an address this field is '0''." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2CS_IC_BUSY,Indicates whether the internally clocked slave logic is being accessed by external I2C master." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "I2C_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and.." "0,1"
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|
newline
|
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If SCB block is disabled BUS_BUSY is '0'. After.." "0,1"
|
|
group.long 0x68++0xB
|
|
line.long 0x0 "I2C_M_CMD,I2C master command"
|
|
bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "M_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative filter delay on SDA output to meet tHD_DAT parameter" "0,1,2,3"
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Enable for 50ns glitch filter on SCL input" "0,1"
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newline
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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newline
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Enable for 50ns glitch filter on SDA input" "0,1"
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only valid.."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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wgroup.long 0x240++0x3
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
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hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
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group.long 0x300++0x7
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line.long 0x0 "RX_CTRL,Receiver control"
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bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only.."
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
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rgroup.long 0x308++0x3
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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group.long 0x310++0x3
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line.long 0x0 "RX_MATCH,Slave address and mask"
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hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the slave address bits take part in the matching. MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,Slave device address."
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rgroup.long 0x340++0x7
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
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hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
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rgroup.long 0xE00++0x3
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
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bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
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group.long 0xE80++0x3
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
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group.long 0xE88++0x3
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line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xE8C++0x3
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
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bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xEC0++0x3
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
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group.long 0xEC8++0x3
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line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xECC++0x3
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line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
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bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xF00++0xB
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line.long 0x0 "INTR_M,Master interrupt request"
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bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
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bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
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newline
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bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
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newline
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bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
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newline
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
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line.long 0x4 "INTR_M_SET,Master interrupt set request"
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bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_M_MASK,Master interrupt mask"
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bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xF0C++0x3
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line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
|
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bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
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group.long 0xF40++0xB
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line.long 0x0 "INTR_S,Slave interrupt request"
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bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
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newline
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bitfld.long 0x0 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred." "0,1"
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newline
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred." "0,1"
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. The Firmware may decide.." "0,1"
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bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,I2C slave matching address received. If CTRL.ADDR_ACCEPT the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
|
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newline
|
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bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
|
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bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
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bitfld.long 0x0 2. "I2C_ACK,I2C slave acknowledgement received. Set to '1' when the slave receives a ACK (typically after the slave transmitted TX data)." "0,1"
|
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newline
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bitfld.long 0x0 1. "I2C_NACK,I2C slave negative acknowledgement received. Set to '1' when the slave receives a NACK (typically after the slave transmitted TX data)." "0,1"
|
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newline
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
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line.long 0x4 "INTR_S_SET,Slave interrupt set request"
|
|
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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newline
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
|
|
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF4C++0x3
|
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line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
|
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
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line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to.." "0,1"
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|
newline
|
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bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1' when event is detected. Write with.." "0,1"
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newline
|
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bitfld.long 0x0 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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|
newline
|
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bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
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newline
|
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bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when SCB is ready to transfer data and EMPTY is '1'." "0,1"
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newline
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bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
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newline
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bitfld.long 0x0 4. "EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
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newline
|
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bitfld.long 0x0 1. "NOT_FULL,TX FIFO is not full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
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line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
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bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
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line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier.." "0,1"
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|
newline
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bitfld.long 0x0 9. "PARITY_ERROR,Parity error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame.." "0,1"
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|
newline
|
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bitfld.long 0x0 8. "FRAME_ERROR,Frame error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error:" "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full RX FIFO. Note: in I2C mode the OVERFLOW is set when a data frame is received and the RX FIFO is full independent of whether it is ACK'd or NACK'd." "0,1"
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newline
|
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bitfld.long 0x0 3. "FULL,RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
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|
newline
|
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bitfld.long 0x0 2. "NOT_EMPTY,RX FIFO is not empty." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TRIGGER,More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
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bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
tree "SCB10"
|
|
base ad:0x406A0000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Generic control"
|
|
bitfld.long 0x0 31. "ENABLED,SCB block is enabled ('1') or not ('0'). The proper order in which to initialize SCB is as follows:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "EC_ACCESS,EC_ACCESS is used to enable I2CS_EC or SPIS_EC access to internal EZ memory." "0: disable clk_scb,1: enable clk_scb"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
|
|
newline
|
|
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the internal CPU accesses to EZ memory coincide/collide this bit determines whether the CPU access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is.." "0,1"
|
|
newline
|
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bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MEM_WIDTH,Determines the number of bits per FIFO data element." "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "EC_OP_MODE,This field specifies the clocking for the SCB block" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "EC_AM_MODE,This field specifies the clocking for the address matching (I2C) or slave selection detection logic (SPI)" "0,1"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Generic status"
|
|
bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
|
|
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers."
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. At the start of a read transfer this BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
|
|
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SPI_CTRL,SPI control"
|
|
bitfld.long 0x0 31. "MASTER_MODE,Master ('1') or slave ('0') mode. In master mode transmission will commence on availability of data frames in the TX FIFO. In slave mode when selected and there is no data frame in the TX FIFO the slave will transmit all '1's. In both.." "0,1"
|
|
newline
|
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bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "SSEL_HOLD_DEL,Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MOSI bit and SELECT deactivation)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SSEL_SETUP_DEL,Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MOSI bit)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SSEL_POLARITY3,Slave select polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SSEL_POLARITY2,Slave select polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSEL_POLARITY1,Slave select polarity." "0,1"
|
|
newline
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bitfld.long 0x0 8. "SSEL_POLARITY0,Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes:" "0,1"
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bitfld.long 0x0 5. "SCLK_CONTINUOUS,Only applicable in master mode." "0,1"
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bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
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bitfld.long 0x0 3. "CPOL,Indicates the clock polarity. This field together with the CPHA field indicates when MOSI data is driven and MISO data is captured:" "0,1"
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bitfld.long 0x0 2. "CPHA,Indicates the clock phase. This field together with the CPOL field indicates when MOSI data is driven and MISO data is captured:" "0,1"
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bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
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bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "SPI_STATUS,SPI status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
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group.long 0x28++0x7
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line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
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bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
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line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
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bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
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group.long 0x40++0xB
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line.long 0x0 "UART_CTRL,UART control"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)." "0: Loopback is not enabled,1: UART_TX is connected to UART_RX"
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line.long 0x4 "UART_TX_CTRL,UART transmitter control"
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bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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line.long 0x8 "UART_RX_CTRL,UART receiver control"
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bitfld.long 0x8 24. "BREAK_LEVEL,0: low level pulse detection like Break field in LIN protocol" "0: low level pulse detection,1: high level pulse detection"
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hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
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bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'. This functionality is intended.." "0,1"
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is.." "0,1"
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period." "0,1"
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails." "0,1"
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
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bitfld.long 0x8 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode parity checking is always enabled through hardware. In IrDA submode parity checking is always disabled through hardware." "0,1"
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bitfld.long 0x8 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of half bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
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rgroup.long 0x4C++0x3
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line.long 0x0 "UART_RX_STATUS,UART receiver status"
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hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of SCB clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of SCB clock periods that constitute a bit period. This field has.."
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group.long 0x50++0x3
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line.long 0x0 "UART_FLOW_CTRL,UART flow control"
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bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal by the UART transmitter:" "0,1"
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal" "0,1"
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal:" "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal is activated. By setting this field to '0' flow control is effectively disabled (may be useful for debug purposes)."
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group.long 0x60++0x3
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line.long 0x0 "I2C_CTRL,I2C control"
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bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself." "0,1"
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bitfld.long 0x0 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode." "0,1"
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,This field is used during an address match or general call address in internally clocked mode" "0: clock stretching is performed,1: a received"
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0' clock stretching is used instead (till the receiver FIFO is no longer full)." "0,1"
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full." "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 SCB clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median.."
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 SCB clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal median.."
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rgroup.long 0x64++0x3
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line.long 0x0 "I2C_STATUS,I2C status"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the.."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 2. "I2CS_IC_BUSY,Indicates whether the internally clocked slave logic is being accessed by external I2C master." "0,1"
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bitfld.long 0x0 1. "I2C_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If SCB block is disabled BUS_BUSY is '0'. After.." "0,1"
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group.long 0x68++0xB
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line.long 0x0 "I2C_M_CMD,I2C master command"
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bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 3. "M_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
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line.long 0x4 "I2C_S_CMD,I2C slave command"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
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line.long 0x8 "I2C_CFG,I2C configuration"
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bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative filter delay on SDA output to meet tHD_DAT parameter" "0,1,2,3"
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim settings for the 50ns delay filter on SDA output used to guarantee tHD_DAT I2C parameter. Default setting meets the I2C spec. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Enable for 50ns glitch filter on SCL input" "0,1"
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Enable for 50ns glitch filter on SDA input" "0,1"
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim settings for the 50ns glitch filter on the SDA input. Default setting meets the I2C glitch rejections specs. Programmability available if required" "0,1,2,3"
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group.long 0x200++0x7
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line.long 0x0 "TX_CTRL,Transmitter control"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only valid.."
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line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
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rgroup.long 0x208++0x3
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line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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wgroup.long 0x240++0x3
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line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
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hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
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group.long 0x300++0x7
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line.long 0x0 "RX_CTRL,Receiver control"
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bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 31]. For I2C the only.."
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line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
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bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
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rgroup.long 0x308++0x3
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line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
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hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
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group.long 0x310++0x3
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line.long 0x0 "RX_MATCH,Slave address and mask"
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hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the slave address bits take part in the matching. MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,Slave device address."
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rgroup.long 0x340++0x7
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line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
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hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
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line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
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hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
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rgroup.long 0xE00++0x3
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line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
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bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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newline
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
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group.long 0xE80++0x3
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line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
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group.long 0xE88++0x3
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line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xE8C++0x3
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line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
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|
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xEC0++0x3
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line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
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bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
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group.long 0xEC8++0x3
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line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
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bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xECC++0x3
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line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
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bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xF00++0xB
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line.long 0x0 "INTR_M,Master interrupt request"
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bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
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newline
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
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newline
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bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
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newline
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bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
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newline
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bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
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newline
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
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line.long 0x4 "INTR_M_SET,Master interrupt set request"
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bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_M_MASK,Master interrupt mask"
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bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long 0xF0C++0x3
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line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
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bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
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group.long 0xF40++0xB
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line.long 0x0 "INTR_S,Slave interrupt request"
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bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
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newline
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bitfld.long 0x0 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred." "0,1"
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newline
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred." "0,1"
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newline
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. The Firmware may decide.." "0,1"
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newline
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bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
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newline
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,I2C slave matching address received. If CTRL.ADDR_ACCEPT the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
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newline
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bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
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newline
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bitfld.long 0x0 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
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newline
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bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
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newline
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bitfld.long 0x0 2. "I2C_ACK,I2C slave acknowledgement received. Set to '1' when the slave receives a ACK (typically after the slave transmitted TX data)." "0,1"
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newline
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bitfld.long 0x0 1. "I2C_NACK,I2C slave negative acknowledgement received. Set to '1' when the slave receives a NACK (typically after the slave transmitted TX data)." "0,1"
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newline
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
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line.long 0x4 "INTR_S_SET,Slave interrupt set request"
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bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
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line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
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bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
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bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
newline
|
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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newline
|
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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rgroup.long 0xF4C++0x3
|
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line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
|
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bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
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newline
|
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
|
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newline
|
|
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xF80++0xB
|
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line.long 0x0 "INTR_TX,Transmitter interrupt request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to.." "0,1"
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newline
|
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bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1' when event is detected. Write with.." "0,1"
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newline
|
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bitfld.long 0x0 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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newline
|
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bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
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|
newline
|
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bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when SCB is ready to transfer data and EMPTY is '1'." "0,1"
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newline
|
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bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
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newline
|
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bitfld.long 0x0 4. "EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
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|
newline
|
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bitfld.long 0x0 1. "NOT_FULL,TX FIFO is not full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
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line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
|
|
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
|
|
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xF8C++0x3
|
|
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
|
|
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
group.long 0xFC0++0xB
|
|
line.long 0x0 "INTR_RX,Receiver interrupt request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Parity error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Frame error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,SW cannot get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full RX FIFO. Note: in I2C mode the OVERFLOW is set when a data frame is received and the RX FIFO is full independent of whether it is ACK'd or NACK'd." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,RX FIFO is not empty." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
|
|
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
|
|
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
|
|
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0xFCC++0x3
|
|
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
|
|
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "SDHC (SD/eMMC Host Controller)"
|
|
base ad:0x40460000
|
|
tree "CORE (MMIO for Synopsys Mobile Storage Host Controller IP)"
|
|
base ad:0x40461000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "SDMASA_R,SDMA System Address register"
|
|
hexmask.long 0x0 0.--31. 1. "BLOCKCNT_SDMASA,32-bit Block Count (SDMA System Address)"
|
|
group.word 0x4++0x3
|
|
line.word 0x0 "BLOCKSIZE_R,Block Size register"
|
|
bitfld.word 0x0 12.--14. "SDMA_BUF_BDARY,SDMA Buffer Boundary" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.word 0x0 0.--11. 1. "XFER_BLOCK_SIZE,Transfer Block Size"
|
|
line.word 0x2 "BLOCKCOUNT_R,16-bit Block Count register"
|
|
hexmask.word 0x2 0.--15. 1. "BLOCK_CNT,16-bit Block Count"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "ARGUMENT_R,Argument register"
|
|
hexmask.long 0x0 0.--31. 1. "ARGUMENT,Command Argument"
|
|
group.word 0xC++0x3
|
|
line.word 0x0 "XFER_MODE_R,Transfer Mode register"
|
|
bitfld.word 0x0 8. "RESP_INT_DISABLE,Response Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "RESP_ERR_CHK_ENABLE,Response Error Check Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "RESP_TYPE,Response Type R1/R5" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "MULTI_BLK_SEL,Multi/Single Block Select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "DATA_XFER_DIR,Data Transfer Direction Select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2.--3. "AUTO_CMD_ENABLE,Auto Command Enable" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 1. "BLOCK_COUNT_ENABLE,Block Count Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "DMA_ENABLE,DMA Enable" "0,1"
|
|
line.word 0x2 "CMD_R,Command register"
|
|
hexmask.word.byte 0x2 8.--13. 1. "CMD_INDEX,Command Index"
|
|
newline
|
|
bitfld.word 0x2 6.--7. "CMD_TYPE,Command Type" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x2 5. "DATA_PRESENT_SEL,Data Present Select" "0,1"
|
|
newline
|
|
bitfld.word 0x2 4. "CMD_IDX_CHK_ENABLE,Command Index Check Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 3. "CMD_CRC_CHK_ENABLE,Command CRC Check Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 2. "SUB_CMD_FLAG,Sub Command Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x2 0.--1. "RESP_TYPE_SELECT,Response Type Select" "0,1,2,3"
|
|
rgroup.long 0x10++0xF
|
|
line.long 0x0 "RESP01_R,Response Register 0/1"
|
|
hexmask.long 0x0 0.--31. 1. "RESP01,Command Response"
|
|
line.long 0x4 "RESP23_R,Response Register 2/3"
|
|
hexmask.long 0x4 0.--31. 1. "RESP23,Command Response"
|
|
line.long 0x8 "RESP45_R,Response Register 4/5"
|
|
hexmask.long 0x8 0.--31. 1. "RESP45,Command Response"
|
|
line.long 0xC "RESP67_R,Response Register 6/7"
|
|
hexmask.long 0xC 0.--31. 1. "RESP67,Command Response"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "BUF_DATA_R,Buffer Data Port Register"
|
|
hexmask.long 0x0 0.--31. 1. "BUF_DATA,Buffer Data"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "PSTATE_REG,Present State Register"
|
|
bitfld.long 0x0 28. "SUB_CMD_STAT,Sub Command Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "CMD_ISSU_ERR,Command Not Issued by Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "HOST_REG_VOL,Host Regulator Voltage Stable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "CMD_LINE_LVL,Command-Line Signal Level" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "DAT_3_0,DAT[3:0] Line Signal Level"
|
|
newline
|
|
bitfld.long 0x0 19. "WR_PROTECT_SW_LVL,Write Protect Switch Pin Level" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CARD_DETECT_PIN_LEVEL,Card Detect Pin Level" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "CARD_STABLE,Card Stable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CARD_INSERTED,Card Inserted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BUF_RD_ENABLE,Buffer Read Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "BUF_WR_ENABLE,Buffer Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RD_XFER_ACTIVE,Read Transfer Active" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "WR_XFER_ACTIVE,Write Transfer Active" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "DAT_7_4,DAT[7:4] Line Signal Level"
|
|
newline
|
|
bitfld.long 0x0 2. "DAT_LINE_ACTIVE,DAT Line Active (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CMD_INHIBIT_DAT,Command Inhibit (DAT)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMD_INHIBIT,Command Inhibit (CMD)" "0,1"
|
|
group.byte 0x28++0x3
|
|
line.byte 0x0 "HOST_CTRL1_R,Host Control 1 Register"
|
|
bitfld.byte 0x0 7. "CARD_DETECT_SIG_SEL,Card Detect Signal Selection" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 6. "CARD_DETECT_TEST_LVL,Card Detect Test Level" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 5. "EXT_DAT_XFER,Extended Data Transfer Width" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3.--4. "DMA_SEL,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.byte 0x0 2. "HIGH_SPEED_EN,High Speed Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "DAT_XFER_WIDTH,Data Transfer Width" "?,1: bit mode"
|
|
newline
|
|
bitfld.byte 0x0 0. "LED_CTRL,LED Control" "0,1"
|
|
line.byte 0x1 "PWR_CTRL_R,Power Control Register"
|
|
bitfld.byte 0x1 1.--3. "SD_BUS_VOL_VDD1,These bits are NON-operational (they can be written and read but they have no effect). In a generic HCI host these would select the card supply voltage. But for the applications targeted for this block it is assumed that the card.." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.byte 0x1 0. "SD_BUS_PWR_VDD1,SD Bus Power for VDD1" "0,1"
|
|
line.byte 0x2 "BGAP_CTRL_R,Block Gap Control Register"
|
|
bitfld.byte 0x2 3. "INT_AT_BGAP,Interrupt At Block Gap" "0,1"
|
|
newline
|
|
bitfld.byte 0x2 2. "RD_WAIT_CTRL,N/A" "0,1"
|
|
newline
|
|
bitfld.byte 0x2 1. "CONTINUE_REQ,Continue Request" "0,1"
|
|
newline
|
|
bitfld.byte 0x2 0. "STOP_BG_REQ,Stop At Block Gap Request" "0,1"
|
|
line.byte 0x3 "WUP_CTRL_R,Wakeup Control Register"
|
|
bitfld.byte 0x3 2. "WUP_CARD_REMOVAL,Wakeup Event Enable on SD Card Removal" "0,1"
|
|
newline
|
|
bitfld.byte 0x3 1. "WUP_CARD_INSERT,Wakeup Event Enable on SD Card Insertion" "0,1"
|
|
newline
|
|
bitfld.byte 0x3 0. "WUP_CARD_INT,Wakeup Event Enable on SDIO Card Interrupt (through DAT[1])." "0,1"
|
|
group.word 0x2C++0x1
|
|
line.word 0x0 "CLK_CTRL_R,Clock Control Register"
|
|
hexmask.word.byte 0x0 8.--15. 1. "FREQ_SEL,SDCLK Frequency Select"
|
|
newline
|
|
bitfld.word 0x0 6.--7. "UPPER_FREQ_SEL,These bits specify the upper 2 bits of 10-bit SDCLK" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 5. "CLK_GEN_SELECT,Clock Generator Select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "PLL_ENABLE,PLL Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "SD_CLK_EN,SD/eMMC Clock Enable" "0,1"
|
|
newline
|
|
rbitfld.word 0x0 1. "INTERNAL_CLK_STABLE,Internal Clock Stable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "INTERNAL_CLK_EN,Internal Clock Enable" "0,1"
|
|
group.byte 0x2E++0x1
|
|
line.byte 0x0 "TOUT_CTRL_R,Timeout Control Register"
|
|
hexmask.byte 0x0 0.--3. 1. "TOUT_CNT,N/A"
|
|
line.byte 0x1 "SW_RST_R,Software Reset Register"
|
|
bitfld.byte 0x1 2. "SW_RST_DAT,Software Reset For DAT line" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 1. "SW_RST_CMD,Software Reset For CMD line" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 0. "SW_RST_ALL,Software Reset For All" "0,1"
|
|
group.word 0x30++0xB
|
|
line.word 0x0 "NORMAL_INT_STAT_R,Normal Interrupt Status Register"
|
|
rbitfld.word 0x0 15. "ERR_INTERRUPT,Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x0 14. "CQE_EVENT,Command Queuing Event" "0,1"
|
|
newline
|
|
rbitfld.word 0x0 13. "FX_EVENT,FX Event" "0,1"
|
|
newline
|
|
rbitfld.word 0x0 8. "CARD_INTERRUPT,Card Interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "CARD_REMOVAL,Card Removal" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "CARD_INSERTION,Card Insertion" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "BUF_RD_READY,Buffer Read Ready" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "BUF_WR_READY,Buffer Write Ready" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "DMA_INTERRUPT,DMA Interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "BGAP_EVENT,Block Gap Event" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "XFER_COMPLETE,Transfer Complete" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "CMD_COMPLETE,Command Complete" "0,1"
|
|
line.word 0x2 "ERROR_INT_STAT_R,Error Interrupt Status Register"
|
|
bitfld.word 0x2 12. "BOOT_ACK_ERR,Boot Acknowledgement Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 11. "RESP_ERR,Response Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 10. "TUNING_ERR,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x2 9. "ADMA_ERR,ADMA Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 8. "AUTO_CMD_ERR,Auto CMD Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 7. "CUR_LMT_ERR,Current Limit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 6. "DATA_END_BIT_ERR,Data End Bit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 5. "DATA_CRC_ERR,Data CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 4. "DATA_TOUT_ERR,Data Timeout Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 3. "CMD_IDX_ERR,Command Index Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 2. "CMD_END_BIT_ERR,Command End Bit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "CMD_CRC_ERR,Command CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 0. "CMD_TOUT_ERR,Command Timeout Error" "0,1"
|
|
line.word 0x4 "NORMAL_INT_STAT_EN_R,Normal Interrupt Status Enable Register"
|
|
bitfld.word 0x4 14. "CQE_EVENT_STAT_EN,CQE Event Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 13. "FX_EVENT_STAT_EN,FX Event Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 12. "RE_TUNE_EVENT_STAT_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x4 11. "INT_C_STAT_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x4 10. "INT_B_STAT_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x4 9. "INT_A_STAT_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x4 8. "CARD_INTERRUPT_STAT_EN,Card Interrupt Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 7. "CARD_REMOVAL_STAT_EN,Card Removal Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 6. "CARD_INSERTION_STAT_EN,Card Insertion Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 5. "BUF_RD_READY_STAT_EN,Buffer Read Ready Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 4. "BUF_WR_READY_STAT_EN,Buffer Write Ready Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 3. "DMA_INTERRUPT_STAT_EN,DMA Interrupt Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 2. "BGAP_EVENT_STAT_EN,Block Gap Event Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 1. "XFER_COMPLETE_STAT_EN,Transfer Complete Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x4 0. "CMD_COMPLETE_STAT_EN,Command Complete Status Enable" "0,1"
|
|
line.word 0x6 "ERROR_INT_STAT_EN_R,Error Interrupt Status Enable Register"
|
|
bitfld.word 0x6 15. "VENDOR_ERR_STAT_EN3,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x6 14. "VENDOR_ERR_STAT_EN2,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x6 13. "VENDOR_ERR_STAT_EN1,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x6 12. "BOOT_ACK_ERR_STAT_EN,Boot Acknowledgment Error (eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x6 11. "RESP_ERR_STAT_EN,Response Error Status Enable (SD Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x6 10. "TUNING_ERR_STAT_EN,Tuning Error Status Enable (UHS-I Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x6 9. "ADMA_ERR_STAT_EN,ADMA Error Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x6 8. "AUTO_CMD_ERR_STAT_EN,Auto CMD Error Status Enable (SD/eMMC Mode only)." "0,1"
|
|
newline
|
|
bitfld.word 0x6 7. "CUR_LMT_ERR_STAT_EN,Current Limit Error Status Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x6 6. "DATA_END_BIT_ERR_STAT_EN,Data End Bit Error Status Enable (SD/eMMC Mode only)." "0,1"
|
|
newline
|
|
bitfld.word 0x6 5. "DATA_CRC_ERR_STAT_EN,Data CRC Error Status Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x6 4. "DATA_TOUT_ERR_STAT_EN,Data Timeout Error Status Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x6 3. "CMD_IDX_ERR_STAT_EN,Command Index Error Status Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x6 2. "CMD_END_BIT_ERR_STAT_EN,Command End Bit Error Status Enable (SD/eMMC Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x6 1. "CMD_CRC_ERR_STAT_EN,ommand CRC Error Status Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x6 0. "CMD_TOUT_ERR_STAT_EN,Command Timeout Error Status Enable (SD/eMMC Mode" "0,1"
|
|
line.word 0x8 "NORMAL_INT_SIGNAL_EN_R,Normal Interrupt Signal Enable Register"
|
|
bitfld.word 0x8 14. "CQE_EVENT_SIGNAL_EN,Command Queuing Engine Event Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x8 13. "FX_EVENT_SIGNAL_EN,FX Event Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x8 12. "RE_TUNE_EVENT_SIGNAL_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x8 11. "INT_C_SIGNAL_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x8 10. "INT_B_SIGNAL_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x8 9. "INT_A_SIGNAL_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x8 8. "CARD_INTERRUPT_SIGNAL_EN,Card Interrupt Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x8 7. "CARD_REMOVAL_SIGNAL_EN,Card Removal Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x8 6. "CARD_INSERTION_SIGNAL_EN,Card Insertion Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x8 5. "BUF_RD_READY_SIGNAL_EN,Buffer Read Ready Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x8 4. "BUF_WR_READY_SIGNAL_EN,Buffer Write Ready Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x8 3. "DMA_INTERRUPT_SIGNAL_EN,DMA Interrupt Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x8 2. "BGAP_EVENT_SIGNAL_EN,Block Gap Event Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x8 1. "XFER_COMPLETE_SIGNAL_EN,Transfer Complete Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x8 0. "CMD_COMPLETE_SIGNAL_EN,Command Complete Signal Enable" "0,1"
|
|
line.word 0xA "ERROR_INT_SIGNAL_EN_R,Error Interrupt Signal Enable Register"
|
|
bitfld.word 0xA 15. "VENDOR_ERR_SIGNAL_EN3,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0xA 14. "VENDOR_ERR_SIGNAL_EN2,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0xA 13. "VENDOR_ERR_SIGNAL_EN1,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0xA 12. "BOOT_ACK_ERR_SIGNAL_EN,Boot Acknowledgment Error (eMMC Mode only)." "0,1"
|
|
newline
|
|
bitfld.word 0xA 11. "RESP_ERR_SIGNAL_EN,Response Error Signal Enable (SD Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0xA 10. "TUNING_ERR_SIGNAL_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0xA 9. "ADMA_ERR_SIGNAL_EN,ADMA Error Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0xA 8. "AUTO_CMD_ERR_SIGNAL_EN,Auto CMD Error Signal Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0xA 7. "CUR_LMT_ERR_SIGNAL_EN,Current Limit Error Signal Enable" "0,1"
|
|
newline
|
|
bitfld.word 0xA 6. "DATA_END_BIT_ERR_SIGNAL_EN,Data End Bit Error Signal Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0xA 5. "DATA_CRC_ERR_SIGNAL_EN,Data CRC Error Signal Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0xA 4. "DATA_TOUT_ERR_SIGNAL_EN,Data Timeout Error Signal Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0xA 3. "CMD_IDX_ERR_SIGNAL_EN,Command Index Error Signal Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0xA 2. "CMD_END_BIT_ERR_SIGNAL_EN,Command End Bit Error Signal Enable (SD/eMMC Mode" "0,1"
|
|
newline
|
|
bitfld.word 0xA 1. "CMD_CRC_ERR_SIGNAL_EN,Command CRC Error Signal Enable (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0xA 0. "CMD_TOUT_ERR_SIGNAL_EN,Command Timeout Error Signal Enable (SD/eMMC Mode" "0,1"
|
|
rgroup.word 0x3C++0x1
|
|
line.word 0x0 "AUTO_CMD_STAT_R,Auto CMD Status Register"
|
|
bitfld.word 0x0 7. "CMD_NOT_ISSUED_AUTO_CMD12,Command Not Issued By Auto CMD12 Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "AUTO_CMD_RESP_ERR,Auto CMD Response Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "AUTO_CMD_IDX_ERR,Auto CMD Index Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "AUTO_CMD_EBIT_ERR,Auto CMD End Bit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "AUTO_CMD_CRC_ERR,Auto CMD CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "AUTO_CMD_TOUT_ERR,Auto CMD Timeout Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "AUTO_CMD12_NOT_EXEC,Auto CMD12 Not Executed" "0,1"
|
|
group.word 0x3E++0x1
|
|
line.word 0x0 "HOST_CTRL2_R,Host Control 2 Register"
|
|
bitfld.word 0x0 15. "PRESET_VAL_ENABLE,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x0 14. "ASYNC_INT_ENABLE,Asynchronous Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 13. "ADDRESSING,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x0 12. "HOST_VER4_ENABLE,Host Version 4 Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 11. "CMD23_ENABLE,CMD23 Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "ADMA2_LEN_MODE,ADMA2 Length Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x0 8. "UHS2_IF_ENABLE,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "SAMPLE_CLK_SEL,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "EXEC_TUNING,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4.--5. "DRV_STRENGTH_SEL,Driver Strength Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 3. "SIGNALING_EN,1.8V Signaling Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0.--2. "UHS_MODE_SEL,N/A" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x40++0xF
|
|
line.long 0x0 "CAPABILITIES1_R,Capabilities 1 Register - 0 to 31"
|
|
bitfld.long 0x0 30.--31. "SLOT_TYPE_R,Slot Type" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 29. "ASYNC_INT_SUPPORT,Asynchronous Interrupt Support (SD Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "SYS_ADDR_64_V3,64-bit System Address Support for V3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "SYS_ADDR_64_V4,64-bit System Address Support for V4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "VOLT_18,Voltage Support 1.8V" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "VOLT_30,Voltage Support 3.0V" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "VOLT_33,Voltage Support 3.3V" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "SUS_RES_SUPPORT,Suspense/Resume Support" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "SDMA_SUPPORT,SDMA Support" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "HIGH_SPEED_SUPPORT,High Speed Support" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "ADMA2_SUPPORT,ADMA2 Support" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "EMBEDDED_8_BIT,8-bit Support for Embedded Device" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "MAX_BLK_LEN,N/A" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "BASE_CLK_FREQ,Base Clock Frequency for SD clock"
|
|
newline
|
|
bitfld.long 0x0 7. "TOUT_CLK_UNIT,Timeout Clock Unit" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TOUT_CLK_FREQ,Timeout Clock Frequency"
|
|
line.long 0x4 "CAPABILITIES2_R,Capabilities Register - 32 to 63"
|
|
bitfld.long 0x4 28. "VDD2_18V_SUPPORT,1.8V VDD2 Support" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "ADMA3_SUPPORT,ADMA3 Support" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "CLK_MUL,Clock Multiplier"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "RE_TUNING_MODES,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 13. "USE_TUNING_SDR50,Use Tuning for SDR50 (UHS-I only)" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "RETUNE_CNT,N/A"
|
|
newline
|
|
bitfld.long 0x4 6. "DRV_TYPED,Driver Type D Support (UHS-I only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DRV_TYPEC,Driver Type C Support (UHS-I only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "DRV_TYPEA,Driver Type A Support (UHS-I only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "UHS2_SUPPORT,UHS-II Support (UHS-II only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DDR50_SUPPORT,DDR50 Support (UHS-I only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "SDR104_SUPPORT,SDR104 Support (UHS-I only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "SDR50_SUPPORT,SDR50 Support (UHS-I only)" "0,1"
|
|
line.long 0x8 "CURR_CAPABILITIES1_R,Current Capabilities Register - 0 to 31"
|
|
hexmask.long.byte 0x8 16.--23. 1. "MAX_CUR_18V,Maximum Current for 1.8V"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "MAX_CUR_30V,Maximum Current for 3.0V"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "MAX_CUR_33V,Maximum Current for 3.3V"
|
|
line.long 0xC "CURR_CAPABILITIES2_R,Maximum Current Capabilities Register - 32 to 63"
|
|
hexmask.long.byte 0xC 0.--7. 1. "MAX_CUR_VDD2_18V,Maximum Current for 1.8V VDD2"
|
|
wgroup.word 0x50++0x1
|
|
line.word 0x0 "FORCE_AUTO_CMD_STAT_R,Force Event Register for Auto CMD Error Status register"
|
|
bitfld.word 0x0 7. "FORCE_CMD_NOT_ISSUED_AUTO_CMD12,Force Event for Command Not Issued By Auto CMD12 Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "FORCE_AUTO_CMD_RESP_ERR,Force Event for Auto CMD Response Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "FORCE_AUTO_CMD_IDX_ERR,Force Event for Auto CMD Index Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "FORCE_AUTO_CMD_EBIT_ERR,Force Event for Auto CMD End Bit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "FORCE_AUTO_CMD_CRC_ERR,Force Event for Auto CMD CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "FORCE_AUTO_CMD_TOUT_ERR,Force Event for Auto CMD Timeout Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "FORCE_AUTO_CMD12_NOT_EXEC,Force Event for Auto CMD12 Not Executed" "0,1"
|
|
group.word 0x52++0x1
|
|
line.word 0x0 "FORCE_ERROR_INT_STAT_R,Force Event Register for Error Interrupt Status"
|
|
bitfld.word 0x0 15. "FORCE_VENDOR_ERR3,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x0 14. "FORCE_VENDOR_ERR2,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x0 13. "FORCE_VENDOR_ERR1,N/A" "0,1"
|
|
newline
|
|
bitfld.word 0x0 12. "FORCE_BOOT_ACK_ERR,Force Event for Boot Ack error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 11. "FORCE_RESP_ERR,Force Event for Response Error (SD Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "FORCE_TUNING_ERR,Force Event for Tuning Error (UHS-I Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "FORCE_ADMA_ERR,Force Event for ADMA Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 8. "FORCE_AUTO_CMD_ERR,Force Event for Auto CMD Error (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "FORCE_CUR_LMT_ERR,Force Event for Current Limit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "FORCE_DATA_END_BIT_ERR,Force Event for Data End Bit Error (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "FORCE_DATA_CRC_ERR,Force Event for Data CRC Error (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "FORCE_DATA_TOUT_ERR,Force Event for Data Timeout Error (SD/eMMC Mode only)" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "FORCE_CMD_IDX_ERR,Force Event for Command Index Error (SD/eMMC Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "FORCE_CMD_END_BIT_ERR,Force Event for Command End Bit Error (SD/eMMC Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "FORCE_CMD_CRC_ERR,Force Event for Command CRC Error (SD/eMMC Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "FORCE_CMD_TOUT_ERR,Force Event for Command Timeout Error (SD/eMMC Mode" "0,1"
|
|
rgroup.byte 0x54++0x0
|
|
line.byte 0x0 "ADMA_ERR_STAT_R,ADMA Error Status Register"
|
|
bitfld.byte 0x0 2. "ADMA_LEN_ERR,ADMA Length Mismatch Error States" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0.--1. "ADMA_ERR_STATES,ADMA Error States" "0,1,2,3"
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "ADMA_SA_LOW_R,ADMA System Address Register - Low"
|
|
hexmask.long 0x0 0.--31. 1. "ADMA_SA_LOW,ADMA System Address"
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "ADMA_ID_LOW_R,ADMA3 Integrated Descriptor Address Register - Low"
|
|
hexmask.long 0x0 0.--31. 1. "ADMA_ID_LOW,ADMA Integrated Descriptor Address"
|
|
rgroup.word 0xFE++0x1
|
|
line.word 0x0 "HOST_CNTRL_VERS_R,Host Controller Version"
|
|
hexmask.word.byte 0x0 8.--15. 1. "VENDOR_VERSION_NUM,N/A"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--7. 1. "SPEC_VERSION_NUM,N/A"
|
|
rgroup.long 0x180++0x7
|
|
line.long 0x0 "CQVER,Command Queuing Version register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "EMMC_VER_MAJOR,This bit indicates the eMMC major version (1st digit left of"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "EMMC_VER_MINOR,This bit indicates the eMMC minor version (1st digit right of"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "EMMC_VER_SUFFIX,This bit indicates the eMMC version suffix (2nd digit right of"
|
|
line.long 0x4 "CQCAP,Command Queuing Capabilities register"
|
|
bitfld.long 0x4 28. "CRYPTO_SUPPORT,Crypto Support" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "ITCFMUL,N/A"
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "ITCFVAL,Internal Timer Clock Frequency Value (ITCFVAL)"
|
|
group.long 0x188++0x1B
|
|
line.long 0x0 "CQCFG,Command Queuing Configuration register"
|
|
bitfld.long 0x0 12. "DCMD_EN,This bit indicates to the hardware whether the Task" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TASK_DESC_SIZE,Bit Value Description" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CR_GENERAL_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CQ_EN,Enable command queuing engine (CQE)." "0,1"
|
|
line.long 0x4 "CQCTL,Command Queuing Control register"
|
|
bitfld.long 0x4 8. "CLR_ALL_TASKS,Clear all tasks" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "HALT,Halt request and resume" "0,1"
|
|
line.long 0x8 "CQIS,Command Queuing Interrupt Status register"
|
|
bitfld.long 0x8 5. "ICCE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "GCE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "TCL,Task cleared interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "RED,Response error detected interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "TCC,Task complete interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "HAC,Halt complete interrupt" "0,1"
|
|
line.long 0xC "CQISE,Command Queuing Interrupt Status Enable register"
|
|
bitfld.long 0xC 5. "ICCE_STE,Invalid Crypto Configuration Error interrupt status enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "GCE_STE,General Crypto Error interrupt status enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "TCL_STE,Task cleared interrupt status enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "RED_STE,Response error detected interrupt status enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "TCC_STE,Task complete interrupt status enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "HAC_STE,Halt complete interrupt status enable" "0,1"
|
|
line.long 0x10 "CQISGE,Command Queuing Interrupt signal enable register"
|
|
bitfld.long 0x10 5. "ICCE_SGE,Invalid Crypto Configuration Error interrupt signal enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "GCE_SGE,General Crypto Error interrupt signal enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "TCL_SGE,Task cleared interrupt signal enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "RED_SGE,Response error detected interrupt signal enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "TCC_SGE,Task complete interrupt signal enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "HAC_SGE,Halt complete interrupt signal enable" "0,1"
|
|
line.long 0x14 "CQIC,Command Queuing Interrupt Coalescing register"
|
|
bitfld.long 0x14 31. "INTC_EN,Interrupt Coalescing Enable Bit" "0,1"
|
|
newline
|
|
rbitfld.long 0x14 20. "INTC_STAT,Interrupt Coalescing Status Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x14 16. "INTC_RST,Counter and Timer Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x14 15. "INTC_TH_WEN,Interrupt Coalescing Counter Threshold Write Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--12. 1. "INTC_TH,Interrupt Coalescing Counter Threshold filed"
|
|
newline
|
|
bitfld.long 0x14 7. "TOUT_VAL_WEN,When software writes 1 to this bit the value TOUT_VAL is" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--6. 1. "TOUT_VAL,Interrupt Coalescing Timeout Value"
|
|
line.long 0x18 "CQTDLBA,Command Queuing Task Descriptor List Base Address register"
|
|
hexmask.long 0x18 0.--31. 1. "TDLBA,This register stores the LSB bits (31:0) of the byte address of"
|
|
group.long 0x1A8++0x7
|
|
line.long 0x0 "CQTDBR,Command Queuing DoorBell register"
|
|
hexmask.long 0x0 0.--31. 1. "DBR,The software configures TDLBA and TDLBAU and enable"
|
|
line.long 0x4 "CQTCN,Command Queuing TaskClear Notification register"
|
|
hexmask.long 0x4 0.--31. 1. "TCN,Task Completion Notification"
|
|
rgroup.long 0x1B0++0x7
|
|
line.long 0x0 "CQDQS,Device queue status register"
|
|
hexmask.long 0x0 0.--31. 1. "DQS,Device Queue Status"
|
|
line.long 0x4 "CQDPT,Device pending tasks register"
|
|
hexmask.long 0x4 0.--31. 1. "DPT,Device-Pending Tasks"
|
|
group.long 0x1B8++0x3
|
|
line.long 0x0 "CQTCLR,Command Queuing DoorBell register"
|
|
hexmask.long 0x0 0.--31. 1. "TCLR,Writing 1 to bit n of this register orders CQE to clear a task"
|
|
group.long 0x1C0++0x7
|
|
line.long 0x0 "CQSSC1,CQ Send Status Configuration 1 register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SQSCMD_BLK_CNT,This field indicates when SQS CMD is sent while data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "SQSCMD_IDLE_TMR,This field configures the polling period to be used when"
|
|
line.long 0x4 "CQSSC2,CQ Send Status Configuration 2 register"
|
|
hexmask.long.word 0x4 0.--15. 1. "SQSCMD_RCA,This field provides CQE with the contents of the 16-bit RCA"
|
|
rgroup.long 0x1C8++0x3
|
|
line.long 0x0 "CQCRDCT,Command response for direct command register"
|
|
hexmask.long 0x0 0.--31. 1. "DCMD_RESP,This register contains the response of the command"
|
|
group.long 0x1D0++0x3
|
|
line.long 0x0 "CQRMEM,Command response mode error mask register"
|
|
hexmask.long 0x0 0.--31. 1. "RESP_ERR_MASK,The bits of this field are bit mapped to the device response."
|
|
rgroup.long 0x1D4++0xB
|
|
line.long 0x0 "CQTERRI,CQ Task Error Information register"
|
|
bitfld.long 0x0 31. "TRANS_ERR_FIELDS_VALID,This bit is updated when an error is detected while a data" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--28. 1. "TRANS_ERR_TASKID,This field captures the ID of the task that was executed and"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "TRANS_ERR_CMD_INDX,This field captures the index of the command that was"
|
|
newline
|
|
bitfld.long 0x0 15. "RESP_ERR_FIELDS_VALID,This bit is updated when an error is detected while a" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "RESP_ERR_TASKID,This field captures the ID of the task which was executed on"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "RESP_ERR_CMD_INDX,This field captures the index of the command that was"
|
|
line.long 0x4 "CQCRI,CQ Command response index"
|
|
hexmask.long.byte 0x4 0.--5. 1. "CMD_RESP_INDX,Last Command Response index"
|
|
line.long 0x8 "CQCRA,CQ Command response argument register"
|
|
hexmask.long 0x8 0.--31. 1. "CMD_RESP_ARG,Last Command Response argument"
|
|
rgroup.long 0x500++0x7
|
|
line.long 0x0 "MSHC_VER_ID_R,MSHC version"
|
|
hexmask.long 0x0 0.--31. 1. "MSHC_VER_ID,Current release number"
|
|
line.long 0x4 "MSHC_VER_TYPE_R,MSHC version type"
|
|
hexmask.long 0x4 0.--31. 1. "MSHC_VER_TYPE,Current release type"
|
|
group.byte 0x508++0x0
|
|
line.byte 0x0 "MSHC_CTRL_R,MSHC Control register"
|
|
bitfld.byte 0x0 4. "SW_CG_DIS,Internal clock gating disable control" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "CMD_CONFLICT_CHECK,Command conflict check" "0,1"
|
|
group.byte 0x510++0x0
|
|
line.byte 0x0 "MBIU_CTRL_R,MBIU Control register"
|
|
bitfld.byte 0x0 3. "BURST_INCR16_EN,INCR16 Burst" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "BURST_INCR8_EN,INCR8 Burst" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "BURST_INCR4_EN,INCR4 Burst" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "UNDEFL_INCR_EN,Undefined INCR Burst" "0,1"
|
|
group.word 0x52C++0x3
|
|
line.word 0x0 "EMMC_CTRL_R,eMMC Control register"
|
|
bitfld.word 0x0 10. "CQE_PREFETCH_DISABLE,Enable or Disable CQE's PREFETCH feature" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "CQE_ALGO_SEL,Scheduler algorithm selected for execution" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "EMMC_RST_N_OE,Output Enable (OE) control for EMMC Device Reset signal (card_emmc_reset_n)." "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "EMMC_RST_N,EMMC Device Reset signal control." "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "DISABLE_DATA_CRC_CHK,Disable Data CRC Check" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "CARD_IS_EMMC,eMMC Card present" "0,1"
|
|
line.word 0x2 "BOOT_CTRL_R,eMMC Boot Control register"
|
|
hexmask.word.byte 0x2 12.--15. 1. "BOOT_TOUT_CNT,N/A"
|
|
newline
|
|
bitfld.word 0x2 8. "BOOT_ACK_ENABLE,Boot Acknowledge Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 7. "VALIDATE_BOOT,Validate Mandatory Boot Enable bit" "0,1"
|
|
newline
|
|
bitfld.word 0x2 0. "MAN_BOOT_EN,Mandatory Boot Enable" "0,1"
|
|
rgroup.long 0x530++0x3
|
|
line.long 0x0 "GP_IN_R,General Purpose Input register"
|
|
bitfld.long 0x0 0. "GP_IN,It reflects the value of gp_in ports." "0,1"
|
|
group.long 0x534++0x3
|
|
line.long 0x0 "GP_OUT_R,General Purpose Output register"
|
|
bitfld.long 0x0 8.--9. "CARD_CLOCK_IN_DLY,Delay CARD_CLOCK input internally to optimally sample CMD/DAT; set according to interface mode:" "0: SD Default Speed,1: SD SDR25,?,?"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CARD_CLOCK_OUT_DLY,N/A" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 5. "IO_VOLT_SEL_OE,Active high output enable for the IO voltage selection signal (io_volt_sel) controlled through HOST_CTRL_2.SIGNALING_EN:" "0: disable OE to the io_volt_sel output,1: enable OE to the io_volt_sel output"
|
|
newline
|
|
bitfld.long 0x0 4. "CARD_IF_PWR_EN_OE,Active high output enable for the card interface power enable output (card_if_pwr_en) controlled through PWR_CTRL_R.SD_BUS_PWR_VDD1:" "0: disable OE to the card_if_pwr_en output,1: enable OE to the card_if_pwr_en output"
|
|
newline
|
|
bitfld.long 0x0 3. "CARD_CLOCK_OE,Active high output enable for the card clock output (clk_card) which is gated by CLK_CTRL_R.SD_CLK_EN:" "0: disable OE to the clk_card output,1: enable OE to the clk_card output"
|
|
newline
|
|
bitfld.long 0x0 2. "LED_CTRL_OE,Active high output enable for the LED output signal (led_ctrl) controlled through HOST_CTRL1_R.LED_CTRL:" "0: disable OE associated with the led_ctrl output,1: enable OE associated with the led_ctrl output"
|
|
newline
|
|
bitfld.long 0x0 1. "CARD_MECH_WRITE_PROT_EN,card_mech_write_prot despite its name is an active low signal (per the SD Host Controller Standard spec it is officially called SDWP#). Consider that in the following:" "0: Force card_mech_write_prot input to 0..,1: Allow card_mech_write_prot to work normally per.."
|
|
newline
|
|
bitfld.long 0x0 0. "CARD_DETECT_EN,0: Force card_detect_n input to 0" "0: Force card_detect_n input to 0,1: Normal card_detect_n operation allowing card.."
|
|
tree.end
|
|
base ad:0x40460000
|
|
tree "WRAP (MMIO at SDHC wrapper level)"
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTL,Top level wrapper control"
|
|
bitfld.long 0x0 31. "ENABLE,IP Enable:" "0: IP disabled,1: IP enabled"
|
|
tree.end
|
|
tree.end
|
|
tree "SMARTIO (Programmable IO Configuration)"
|
|
base ad:0x40320000
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40320000 ad:0x40320100 ad:0x40320200 ad:0x40320300 ad:0x40320400 ad:0x40320500 ad:0x40320600 ad:0x40320700 ad:0x40320800 ad:0x40320900 ad:0x40320A00 ad:0x40320B00 ad:0x40320C00 ad:0x40320D00 ad:0x40320E00 ad:0x40320F00)
|
|
tree "PRT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTL,Control register"
|
|
bitfld.long 0x0 31. "ENABLED,Enable for programmable IO. Should only be set to '1' when the programmable IO is completely configured:" "0,1"
|
|
bitfld.long 0x0 25. "PIPELINE_EN,Enable for pipeline register:" "0,1"
|
|
bitfld.long 0x0 24. "HLD_OVR,IO cell hold override functionality. In DeepSleep power mode the HSIOM holds the IO cell output and output enable signals if Active functionality is connected to the IO pads. This is undesirable if the SMARTIO is supposed to deliver DeepSleep.." "0,1"
|
|
hexmask.long.byte 0x0 8.--12. 1. "CLOCK_SRC,Clock ('clk_fabric') and reset ('rst_fabric_n') source selection:"
|
|
hexmask.long.byte 0x0 0.--7. 1. "BYPASS,Bypass of the programmable IO one bit for each IO pin: BYPASS[i] is for IO pin i. When ENABLED is '1' this field is used. When ENABLED is '0' this field is NOT used and SMARTIO fabric is always bypassed."
|
|
group.long ($2+0x10)++0x3
|
|
line.long 0x0 "SYNC_CTL,Synchronization control register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "CHIP_SYNC_EN,Synchronization of the chip input signals to 'clk_fabric' one bit for each input: CHIP_SYNC_EN[i] is for input i."
|
|
hexmask.long.byte 0x0 0.--7. 1. "IO_SYNC_EN,Synchronization of the IO pin input signals to 'clk_fabric' one bit for each IO pin: IO_SYNC_EN[i] is for IO pin i."
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "LUT_SEL[$1],LUT component input selection"
|
|
hexmask.long.byte 0x0 16.--19. 1. "LUT_TR2_SEL,LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL."
|
|
hexmask.long.byte 0x0 8.--11. 1. "LUT_TR1_SEL,LUT input signal 'tr1_in' source selection:"
|
|
hexmask.long.byte 0x0 0.--3. 1. "LUT_TR0_SEL,LUT input signal 'tr0_in' source selection:"
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "LUT_CTL[$1],LUT component control register"
|
|
bitfld.long 0x0 8.--9. "LUT_OPC,LUT opcode specifies the LUT operation:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "LUT,LUT configuration. Depending on the LUT opcode LUT_OPC the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in tr1_in tr2_in the LUT configuration is used to determine the LUT output signal and the next sequential.."
|
|
repeat.end
|
|
group.long ($2+0xC0)++0x7
|
|
line.long 0x0 "DU_SEL,Data unit component input selection"
|
|
bitfld.long 0x0 28.--29. "DU_DATA1_SEL,Data unit input data 'data1_in' source selection. Encoding is the same as for DU_DATA0_SEL." "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "DU_DATA0_SEL,Data unit input data 'data0_in' source selection:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "DU_TR2_SEL,Data unit input signal 'tr2_in' source selection. Encoding is the same as for DU_TR0_SEL."
|
|
hexmask.long.byte 0x0 8.--11. 1. "DU_TR1_SEL,Data unit input signal 'tr1_in' source selection. Encoding is the same as for DU_TR0_SEL."
|
|
hexmask.long.byte 0x0 0.--3. 1. "DU_TR0_SEL,Data unit input signal 'tr0_in' source selection:"
|
|
line.long 0x4 "DU_CTL,Data unit component control register"
|
|
hexmask.long.byte 0x4 8.--11. 1. "DU_OPC,Data unit opcode specifies the data unit operation:"
|
|
bitfld.long 0x4 0.--2. "DU_SIZE,Size/width of the data unit data operands (in bits) is DU_SIZE+1. E.g. if DU_SIZE is 7 the width is 8 bits." "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0xF0)++0x3
|
|
line.long 0x0 "DATA,Data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,Data unit input data source."
|
|
tree.end
|
|
repeat.end
|
|
repeat 2. (list 0x10 0x11)(list ad:0x40321000 ad:0x40321100)
|
|
tree "PRT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTL,Control register"
|
|
bitfld.long 0x0 31. "ENABLED,Enable for programmable IO. Should only be set to '1' when the programmable IO is completely configured:" "0,1"
|
|
bitfld.long 0x0 25. "PIPELINE_EN,Enable for pipeline register:" "0,1"
|
|
bitfld.long 0x0 24. "HLD_OVR,IO cell hold override functionality. In DeepSleep power mode the HSIOM holds the IO cell output and output enable signals if Active functionality is connected to the IO pads. This is undesirable if the SMARTIO is supposed to deliver DeepSleep.." "0,1"
|
|
hexmask.long.byte 0x0 8.--12. 1. "CLOCK_SRC,Clock ('clk_fabric') and reset ('rst_fabric_n') source selection:"
|
|
hexmask.long.byte 0x0 0.--7. 1. "BYPASS,Bypass of the programmable IO one bit for each IO pin: BYPASS[i] is for IO pin i. When ENABLED is '1' this field is used. When ENABLED is '0' this field is NOT used and SMARTIO fabric is always bypassed."
|
|
group.long ($2+0x10)++0x3
|
|
line.long 0x0 "SYNC_CTL,Synchronization control register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "CHIP_SYNC_EN,Synchronization of the chip input signals to 'clk_fabric' one bit for each input: CHIP_SYNC_EN[i] is for input i."
|
|
hexmask.long.byte 0x0 0.--7. 1. "IO_SYNC_EN,Synchronization of the IO pin input signals to 'clk_fabric' one bit for each IO pin: IO_SYNC_EN[i] is for IO pin i."
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "LUT_SEL[$1],LUT component input selection"
|
|
hexmask.long.byte 0x0 16.--19. 1. "LUT_TR2_SEL,LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL."
|
|
hexmask.long.byte 0x0 8.--11. 1. "LUT_TR1_SEL,LUT input signal 'tr1_in' source selection:"
|
|
hexmask.long.byte 0x0 0.--3. 1. "LUT_TR0_SEL,LUT input signal 'tr0_in' source selection:"
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "LUT_CTL[$1],LUT component control register"
|
|
bitfld.long 0x0 8.--9. "LUT_OPC,LUT opcode specifies the LUT operation:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "LUT,LUT configuration. Depending on the LUT opcode LUT_OPC the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in tr1_in tr2_in the LUT configuration is used to determine the LUT output signal and the next sequential.."
|
|
repeat.end
|
|
group.long ($2+0xC0)++0x7
|
|
line.long 0x0 "DU_SEL,Data unit component input selection"
|
|
bitfld.long 0x0 28.--29. "DU_DATA1_SEL,Data unit input data 'data1_in' source selection. Encoding is the same as for DU_DATA0_SEL." "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "DU_DATA0_SEL,Data unit input data 'data0_in' source selection:" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "DU_TR2_SEL,Data unit input signal 'tr2_in' source selection. Encoding is the same as for DU_TR0_SEL."
|
|
hexmask.long.byte 0x0 8.--11. 1. "DU_TR1_SEL,Data unit input signal 'tr1_in' source selection. Encoding is the same as for DU_TR0_SEL."
|
|
hexmask.long.byte 0x0 0.--3. 1. "DU_TR0_SEL,Data unit input signal 'tr0_in' source selection:"
|
|
line.long 0x4 "DU_CTL,Data unit component control register"
|
|
hexmask.long.byte 0x4 8.--11. 1. "DU_OPC,Data unit opcode specifies the data unit operation:"
|
|
bitfld.long 0x4 0.--2. "DU_SIZE,Size/width of the data unit data operands (in bits) is DU_SIZE+1. E.g. if DU_SIZE is 7 the width is 8 bits." "0,1,2,3,4,5,6,7"
|
|
group.long ($2+0xF0)++0x3
|
|
line.long 0x0 "DATA,Data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,Data unit input data source."
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "SMIF (Serial Memory Interface)"
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base ad:0x40420000
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group.long 0x0++0x3
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line.long 0x0 "CTL,Control"
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bitfld.long 0x0 31. "ENABLED,IP enable:" "0: N/A,1: N/A"
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newline
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bitfld.long 0x0 24. "BLOCK,Specifies what happens for MMIO interface read accesses to an empty RX data FIFO or to a full TX format/data FIFO. Note: the FIFOs can only be accessed in MMIO_MODE." "0: 0': Generate an AHB-Lite bus error. This option..,1: 1': Introduce wait states. This setting.."
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newline
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bitfld.long 0x0 22.--23. "SELECT_HOLD_DELAY,Specifies the duration between last 'spi_clk_out' edge to 'spi_select_out[]' becomes high/'1'):" "0,1,2,3"
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newline
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bitfld.long 0x0 20.--21. "SELECT_SETUP_DELAY,Specifies the duration between 'spi_select_out[]' becomes low/'0') to 1st 'spi_clk_out' edge:" "0,1,2,3"
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newline
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bitfld.long 0x0 16.--18. "DESELECT_DELAY,Specifies the minimum duration of SPI deselection ('spi_select_out[]' is high/'1') in between SPI transfers:" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x0 12.--14. "CLOCK_IF_RX_SEL,Specifies device interface receiver clock 'clk_if_rx' source. MISO data is captured on the rising edge of 'clk_if_rx' in SDR mode and on both edges of 'clk_if_rx' in DDR mode." "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x0 10.--11. "INT_CLOCK_CAPTURE_CYCLE,N/A" "0,1,2,3"
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newline
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bitfld.long 0x0 9. "INT_CLOCK_DL_ENABLED,Data Learning Enable for internal RX clock based on Data Learning Pattern. Only applies when CLOCK_IF_RX_SEL = [4..5] for selecting the internal clock based capture scheme and when DELAY_TAP_ENABLED = 1." "0,1"
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newline
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bitfld.long 0x0 8. "DELAY_TAP_ENABLED,Delay Line Tap Enable." "0,1"
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newline
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bitfld.long 0x0 5.--7. "DELAY_LINE_SEL,Specifies the delay line used for RX data capturing with" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x0 4. "CLOCK_IF_TX_SEL,Specifies device interface transmitter clock options." "0,1"
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newline
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bitfld.long 0x0 0. "XIP_MODE,Mode of operation." "0: '0': MMIO mode. Individual MMIO accesses to TX..,1: '1': XIP mode. eXecute-In-Place mode: incoming.."
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rgroup.long 0x4++0x3
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line.long 0x0 "STATUS,Status"
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bitfld.long 0x0 31. "BUSY,AHB Cache AXI interface cryptography XIP device interface or any other logic busy in the IP:" "0,1"
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group.long 0x10++0xB
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line.long 0x0 "INT_CLOCK_DELAY_TAP_SEL0,Internal Clocking Delay Tap Select Register 0"
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hexmask.long.byte 0x0 24.--31. 1. "DATA_BIT3,Delay line tap selection for data bit 3."
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newline
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hexmask.long.byte 0x0 16.--23. 1. "DATA_BIT2,Delay line tap selection for data bit 2."
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newline
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hexmask.long.byte 0x0 8.--15. 1. "DATA_BIT1,Delay line tap selection for data bit 1."
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newline
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hexmask.long.byte 0x0 0.--7. 1. "DATA_BIT0,Delay line tap selection for data bit 0."
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line.long 0x4 "INT_CLOCK_DELAY_TAP_SEL1,Internal Clocking Delay Tap Select Register 1"
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hexmask.long.byte 0x4 24.--31. 1. "DATA_BIT7,Delay line tap selection for data bit 7."
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newline
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hexmask.long.byte 0x4 16.--23. 1. "DATA_BIT6,Delay line tap selection for data bit 6."
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newline
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hexmask.long.byte 0x4 8.--15. 1. "DATA_BIT5,Delay line tap selection for data bit 5."
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newline
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hexmask.long.byte 0x4 0.--7. 1. "DATA_BIT4,Delay line tap selection for data bit 4."
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line.long 0x8 "DLP,Data Learning Pattern"
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hexmask.long.byte 0x8 0.--7. 1. "DLP,Data Learning Pattern"
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rgroup.long 0x20++0x7
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line.long 0x0 "DL_STATUS0,Data Learning Status Register 0"
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hexmask.long.byte 0x0 24.--31. 1. "DATA_BIT3,Number of delay line taps for data bit 3 with correctly captured DLP in last read transaction. Legal range: [0 255]."
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newline
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hexmask.long.byte 0x0 16.--23. 1. "DATA_BIT2,Number of delay line taps for data bit 2 with correctly captured DLP in last read transaction. Legal range: [0 255]."
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newline
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hexmask.long.byte 0x0 8.--15. 1. "DATA_BIT1,Number of delay line taps for data bit 1 with correctly captured DLP in last read transaction. Legal range: [0 255]."
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newline
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hexmask.long.byte 0x0 0.--7. 1. "DATA_BIT0,Number of delay line taps for data bit 0 with correctly captured DLP in last read transaction. Legal range: [0 255]."
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line.long 0x4 "DL_STATUS1,Data Learning Status Register 1"
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hexmask.long.byte 0x4 24.--31. 1. "DATA_BIT7,Number of delay line taps for data bit 7 with correctly captured DLP in last read transaction. Legal range: [0 255]."
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newline
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hexmask.long.byte 0x4 16.--23. 1. "DATA_BIT6,Number of delay line taps for data bit 6 with correctly captured DLP in last read transaction. Legal range: [0 255]."
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newline
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hexmask.long.byte 0x4 8.--15. 1. "DATA_BIT5,Number of delay line taps for data bit 5 with correctly captured DLP in last read transaction. Legal range: [0 255]."
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newline
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hexmask.long.byte 0x4 0.--7. 1. "DATA_BIT4,Number of delay line taps for data bit 4 with correctly captured DLP in last read transaction. Legal range: [0 255]."
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group.long 0x30++0x3
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line.long 0x0 "DELAY_TAP_SEL,Delay Tap Select Register"
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hexmask.long.byte 0x0 0.--7. 1. "SEL,Delay line tap selection in output / feedback clock based capture scheme (CLOCK_IF_RX_SEL = [0..3]) and RWDS capture scheme (CLOCK_IF_RX_SEL = [6..7]). This is used to shift the strobe signal into the data eye."
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rgroup.long 0x44++0x3
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line.long 0x0 "TX_CMD_FIFO_STATUS,Transmitter command FIFO status"
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hexmask.long.byte 0x0 0.--3. 1. "USED4,Number of entries that are used in the TX command FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0 8]."
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wgroup.long 0x50++0x3
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line.long 0x0 "TX_CMD_FIFO_WR,Transmitter command FIFO write"
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hexmask.long 0x0 0.--26. 1. "DATA27,N/A"
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group.long 0x80++0x3
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line.long 0x0 "TX_DATA_FIFO_CTL,Transmitter data FIFO control"
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bitfld.long 0x0 0.--2. "TX_TRIGGER_LEVEL,Determines when the TX data FIFO 'tr_tx_req' trigger is activated (trigger activation requires MMIO_MODE the trigger is NOT activated in XIP_MODE):" "0,1,2,3,4,5,6,7"
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rgroup.long 0x84++0x3
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line.long 0x0 "TX_DATA_FIFO_STATUS,Transmitter data FIFO status"
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hexmask.long.byte 0x0 0.--3. 1. "USED4,Number of entries that are used in the TX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0 8]."
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wgroup.long 0x90++0xF
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line.long 0x0 "TX_DATA_FIFO_WR1,Transmitter data FIFO write"
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hexmask.long.byte 0x0 0.--7. 1. "DATA0,TX data (written to TX data FIFO)."
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line.long 0x4 "TX_DATA_FIFO_WR2,Transmitter data FIFO write"
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hexmask.long.byte 0x4 8.--15. 1. "DATA1,TX data (written to TX data FIFO second byte)."
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newline
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hexmask.long.byte 0x4 0.--7. 1. "DATA0,TX data (written to TX data FIFO first byte)."
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line.long 0x8 "TX_DATA_FIFO_WR4,Transmitter data FIFO write"
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hexmask.long.byte 0x8 24.--31. 1. "DATA3,TX data (written to TX data FIFO fourth byte)."
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newline
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hexmask.long.byte 0x8 16.--23. 1. "DATA2,TX data (written to TX data FIFO third byte)."
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newline
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hexmask.long.byte 0x8 8.--15. 1. "DATA1,TX data (written to TX data FIFO second byte)."
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newline
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hexmask.long.byte 0x8 0.--7. 1. "DATA0,TX data (written to TX data FIFO first byte)."
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line.long 0xC "TX_DATA_FIFO_WR1ODD,Transmitter data FIFO write"
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hexmask.long.byte 0xC 0.--7. 1. "DATA0,TX data (written to TX data FIFO)."
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group.long 0xC0++0x3
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line.long 0x0 "RX_DATA_MMIO_FIFO_CTL,Receiver data MMIO FIFO control"
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bitfld.long 0x0 0.--2. "RX_TRIGGER_LEVEL,Determines when RX data FIFO 'tr_rx_req' trigger is activated (trigger activation requires MMIO_MODE the trigger is NOT activated in XIP_MODE):" "0,1,2,3,4,5,6,7"
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rgroup.long 0xC4++0x7
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line.long 0x0 "RX_DATA_MMIO_FIFO_STATUS,Receiver data MMIO FIFO status"
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hexmask.long.byte 0x0 0.--3. 1. "USED4,Number of entries that are used in the RX data MMIO FIFO (only available in MMIO_MODE). Legal range: [0 8]."
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line.long 0x4 "RX_DATA_FIFO_STATUS,Receiver data FIFO status"
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bitfld.long 0x4 8. "RX_SR_USED,Data available in RX Shift Register i.e. completely read from RX data FIFO (availabe in both XIP_MODE and MMIO_MODE)." "0,1"
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newline
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hexmask.long.byte 0x4 0.--4. 1. "USED5,Number of entries that are used in the RX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0 16]."
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rgroup.long 0xD0++0xB
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line.long 0x0 "RX_DATA_MMIO_FIFO_RD1,Receiver data MMIO FIFO read"
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hexmask.long.byte 0x0 0.--7. 1. "DATA0,RX data (read from RX data FIFO)."
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line.long 0x4 "RX_DATA_MMIO_FIFO_RD2,Receiver data MMIO FIFO read"
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hexmask.long.byte 0x4 8.--15. 1. "DATA1,RX data (read from RX data FIFO second byte)."
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newline
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hexmask.long.byte 0x4 0.--7. 1. "DATA0,RX data (read from RX data FIFO first byte)."
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line.long 0x8 "RX_DATA_MMIO_FIFO_RD4,Receiver data MMIO FIFO read"
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hexmask.long.byte 0x8 24.--31. 1. "DATA3,RX data (read from RX data FIFO fourth byte)."
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newline
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hexmask.long.byte 0x8 16.--23. 1. "DATA2,RX data (read from RX data FIFO third byte)."
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newline
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hexmask.long.byte 0x8 8.--15. 1. "DATA1,RX data (read from RX data FIFO second byte)."
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newline
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hexmask.long.byte 0x8 0.--7. 1. "DATA0,RX data (read from RX data FIFO first byte)."
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rgroup.long 0xE0++0x3
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line.long 0x0 "RX_DATA_MMIO_FIFO_RD1_SILENT,Receiver data MMIO FIFO silent read"
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hexmask.long.byte 0x0 0.--7. 1. "DATA0,RX data (read from RX data FIFO)."
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group.long 0x100++0x3
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line.long 0x0 "SLOW_CA_CTL,Slow cache control"
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bitfld.long 0x0 31. "ENABLED,Cache enable:" "0,1"
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newline
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bitfld.long 0x0 30. "PREF_EN,Prefetch enable:" "0,1"
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newline
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bitfld.long 0x0 24.--25. "SET_ADDR,this is for debug purpose only and should be hidden to customers in technical document" "0,1,2,3"
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newline
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bitfld.long 0x0 16.--17. "WAY,this is for debug purpose only and should be hidden to customers in technical document" "0,1,2,3"
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group.long 0x108++0x3
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line.long 0x0 "SLOW_CA_CMD,Slow cache command"
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bitfld.long 0x0 0. "INV,Cache and prefetch buffer invalidation." "0,1"
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group.long 0x180++0x3
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line.long 0x0 "FAST_CA_CTL,Fast cache control"
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bitfld.long 0x0 31. "ENABLED,See SLOW_CA_CTL.ENABLED." "0,1"
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newline
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bitfld.long 0x0 30. "PREF_EN,See SLOW_CA_CTL.PREF_EN." "0,1"
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newline
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bitfld.long 0x0 24.--25. "SET_ADDR,this is for debug purpose only and should be hidden to customers in technical document" "0,1,2,3"
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newline
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bitfld.long 0x0 16.--17. "WAY,this is for debug purpose only and should be hidden to customers in technical document" "0,1,2,3"
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group.long 0x188++0x3
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line.long 0x0 "FAST_CA_CMD,Fast cache command"
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bitfld.long 0x0 0. "INV,See SLOW_CA_CMD.INV." "0,1"
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group.long 0x200++0x3
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line.long 0x0 "CRYPTO_CMD,Cryptography Command"
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bitfld.long 0x0 0. "START,SW sets this field to '1' to start a AES-128 forward block cipher operation (on the address in CRYPTO_ADDR). HW sets this field to '0' to indicate that the operation has completed. Once completed the result of the operation can be read from.." "0,1"
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group.long 0x220++0xF
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line.long 0x0 "CRYPTO_INPUT0,Cryptography input 0"
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hexmask.long 0x0 0.--31. 1. "INPUT,Four Bytes of the plaintext PT[31:0] = CRYPTO_INPUT0.INPUT[31:0]."
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line.long 0x4 "CRYPTO_INPUT1,Cryptography input 1"
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hexmask.long 0x4 0.--31. 1. "INPUT,Four Bytes of the plaintext PT[63:32] = CRYPTO_INPUT1.INPUT[31:0]."
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line.long 0x8 "CRYPTO_INPUT2,Cryptography input 2"
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hexmask.long 0x8 0.--31. 1. "INPUT,Four Bytes of the plaintext PT[95:64] = CRYPTO_INPUT2.INPUT[31:0]."
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line.long 0xC "CRYPTO_INPUT3,Cryptography input 3"
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hexmask.long 0xC 0.--31. 1. "INPUT,Four Bytes of the plaintext PT[127:96] = CRYPTO_INPUT3.INPUT[31:0]."
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wgroup.long 0x240++0xF
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line.long 0x0 "CRYPTO_KEY0,Cryptography key 0"
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hexmask.long 0x0 0.--31. 1. "KEY,Four Bytes of the key KEY[31:0] = CRYPTO_KEY0.KEY[31:0]."
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line.long 0x4 "CRYPTO_KEY1,Cryptography key 1"
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hexmask.long 0x4 0.--31. 1. "KEY,Four Bytes of the key KEY[63:32] = CRYPTO_KEY1.KEY[31:0]."
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line.long 0x8 "CRYPTO_KEY2,Cryptography key 2"
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hexmask.long 0x8 0.--31. 1. "KEY,Four Bytes of the key KEY[95:64] = CRYPTO_KEY2.KEY[31:0]."
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line.long 0xC "CRYPTO_KEY3,Cryptography key 3"
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hexmask.long 0xC 0.--31. 1. "KEY,Four Bytes of the key KEY[127:96] = CRYPTO_KEY3.KEY[31:0]."
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group.long 0x260++0xF
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line.long 0x0 "CRYPTO_OUTPUT0,Cryptography output 0"
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hexmask.long 0x0 0.--31. 1. "OUTPUT,Four Bytes of the ciphertext CT[31:0] = CRYPTO_OUTPUT0.OUTPUT[31:0]."
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line.long 0x4 "CRYPTO_OUTPUT1,Cryptography output 1"
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hexmask.long 0x4 0.--31. 1. "OUTPUT,Four Bytes of the ciphertext CT[63:32] = CRYPTO_OUTPUT1.OUTPUT[31:0]."
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line.long 0x8 "CRYPTO_OUTPUT2,Cryptography output 2"
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hexmask.long 0x8 0.--31. 1. "OUTPUT,Four Bytes of the ciphertext CT[95:64] = CRYPTO_OUTPUT2.OUTPUT[31:0]."
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line.long 0xC "CRYPTO_OUTPUT3,Cryptography output 3"
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hexmask.long 0xC 0.--31. 1. "OUTPUT,Four Bytes of the ciphertext CT[127:96] = CRYPTO_OUTPUT3.OUTPUT[31:0]."
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group.long 0x300++0x3
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line.long 0x0 "CRC_CMD,CRC Command"
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bitfld.long 0x0 1. "CONTINUE,SW sets this field to '1' to continue a CRC calculation over the 64 CRC input bits provided in CRC_INPUT0 and CRC_INPUT1 using the current CRC output in CRC_OUTPUT as CRC feedback. HW sets this field to '0' to indicate that the operation has.." "0,1"
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newline
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bitfld.long 0x0 0. "START,SW sets this field to '1' to start a CRC calculation over the 64 CRC input bits provided in CRC_INPUT0 and CRC_INPUT1 using 0xFF as CRC feedback. HW sets this field to '0' to indicate that the operation has completed. Once completed the result of.." "0,1"
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group.long 0x320++0x7
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line.long 0x0 "CRC_INPUT0,CRC input 0"
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hexmask.long 0x0 0.--31. 1. "INPUT,Lower 32 input bits to the CRC engine."
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line.long 0x4 "CRC_INPUT1,CRC input 1"
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hexmask.long 0x4 0.--31. 1. "INPUT,Higher 32 input bits to the CRC engine."
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rgroup.long 0x340++0x3
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line.long 0x0 "CRC_OUTPUT,CRC output"
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hexmask.long.byte 0x0 0.--7. 1. "CRC_OUTPUT,CRC engine output."
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group.long 0x7C0++0xB
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line.long 0x0 "INTR,Interrupt register"
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bitfld.long 0x0 17. "FS_STATUS_ERROR,Functional Safety Status Error. A read transfer Functional Safety Status check failed (see definition in DEVICE_ver2.RD_CRC_CTL.STATUS_CHECK_MASK and DEVICE_ver2.RD_CRC_CTL.STATUS_CHECK_MASK_POL)." "0,1"
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newline
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bitfld.long 0x0 16. "CRC_ERROR,CRC Error. A read transfer data CRC check failed." "0,1"
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newline
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bitfld.long 0x0 12. "DL_WARNING,Data Learning Warning (for at least one input data line only 1 or 2 delay line taps resulted in a correct DLP capturing when CTL.INT_CLOCK_DL_ENABLED = 1)." "0,1"
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newline
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bitfld.long 0x0 8. "DL_FAIL,Data Learning Failed (no DLP match found on at least one of the input data lines when CTL.INT_CLOCK_DL_ENABLED = 1)." "0,1"
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newline
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bitfld.long 0x0 5. "RX_DATA_MMIO_FIFO_UNDERFLOW,Activated in MMIO mode on an AHB-Lite read transfer from the RX data MMIO FIFO (RX_DATA_MMIO_FIFO_RD1 RX_DATA_MMIO_FIFO_RD2 RX_DATA_MMIO_FIFO_RD4) with not enough entries available. Only activated for NON test bus.." "0,1"
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newline
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bitfld.long 0x0 4. "TX_DATA_FIFO_OVERFLOW,Activated in MMIO mode on an AHB-Lite write transfer to the TX data FIFO (TX_DATA_FIFO_WR1 TX_DATA_FIFO_WR2 TX_DATA_FIFO_WR4) with not enough free entries available." "0,1"
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newline
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bitfld.long 0x0 3. "TX_CMD_FIFO_OVERFLOW,Activated in MMIO mode on an AHB-Lite write transfer to the TX command FIFO (TX_CMD_FIFO_WR) with not enough free entries available." "0,1"
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newline
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bitfld.long 0x0 2. "XIP_ALIGNMENT_ERROR,Activated in XIP mode when:" "0,1"
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newline
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bitfld.long 0x0 1. "TR_RX_REQ,Activated in MMIO mode when a RX data FIFO trigger 'tr_rx_req' is activated." "0,1"
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newline
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bitfld.long 0x0 0. "TR_TX_REQ,Activated in MMIO mode when a TX data FIFO trigger 'tr_tx_req' is activated." "0,1"
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line.long 0x4 "INTR_SET,Interrupt set register"
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bitfld.long 0x4 17. "FS_STATUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 16. "CRC_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 12. "DL_WARNING,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 8. "DL_FAIL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 5. "RX_DATA_MMIO_FIFO_UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 4. "TX_DATA_FIFO_OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 3. "TX_CMD_FIFO_OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 2. "XIP_ALIGNMENT_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 1. "TR_RX_REQ,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x4 0. "TR_TX_REQ,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x8 17. "FS_STATUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 16. "CRC_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 12. "DL_WARNING,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 8. "DL_FAIL,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 5. "RX_DATA_MMIO_FIFO_UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 4. "TX_DATA_FIFO_OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 3. "TX_CMD_FIFO_OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 2. "XIP_ALIGNMENT_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 1. "TR_RX_REQ,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
|
|
bitfld.long 0x8 0. "TR_TX_REQ,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long 0x7CC++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked register"
|
|
bitfld.long 0x0 17. "FS_STATUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CRC_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "DL_WARNING,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DL_FAIL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RX_DATA_MMIO_FIFO_UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TX_DATA_FIFO_OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TX_CMD_FIFO_OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "XIP_ALIGNMENT_ERROR,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TR_RX_REQ,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TR_TX_REQ,Logical and of corresponding request and mask bits." "0,1"
|
|
repeat 2. (list 0x0 0x1)(list ad:0x40420800 ad:0x40420880)
|
|
tree "DEVICE[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTL,Control"
|
|
bitfld.long 0x0 31. "ENABLED,Device enable:" "0,1"
|
|
bitfld.long 0x0 30. "TOTAL_TIMEOUT_EN,Total transfer timeout enable." "0,1"
|
|
hexmask.long.word 0x0 16.--29. 1. "TOTAL_TIMEOUT,Total transfer timeout in clk_mem cycles."
|
|
newline
|
|
bitfld.long 0x0 15. "MERGE_EN,Continous transfer merge enable:" "0,1"
|
|
bitfld.long 0x0 12.--14. "MERGE_TIMEOUT,Continuous transfer merge timeout in clk_mem cycles. This limits the standby time of the memory interface i.e. the time the memory device is selected but no data is transferred." "0: Timeout after 1 clk_mem cycle. That means..,1: Timeout after 2^4 = 16 clk_mem cycles. At a..,2: Timeout after 2^8 = 256 clk_mem cycles. At a..,3: Timeout after 2^12 = 4096 clk_mem cycles. At a..,4: Timeout after 2^16 = 65536 clk_mem cycles. At a..,5: N/A,6: N/A,7: N/A"
|
|
bitfld.long 0x0 8.--9. "DATA_SEL,Specifies the connection of the IP's data lines (spi_data[0] ... spi_data[7]) to the device's data lines (SI/IO0 SO/IO1 IO2 IO3 IO4 IO5 IO6 IO7):" "0,1,2,3"
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|
newline
|
|
bitfld.long 0x0 4. "CRYPTO_EN,Cryptography on read/write accesses:" "0,1"
|
|
bitfld.long 0x0 0. "WR_EN,Write enable:" "0,1"
|
|
group.long ($2+0x8)++0x7
|
|
line.long 0x0 "ADDR,Device region base address"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "ADDR,Specifies the base address of the device region. If the device region is 2^m Bytes ADDR MUST be a multiple of 2^m."
|
|
line.long 0x4 "MASK,Device region mask"
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "MASK,Specifies the size of the device region. All '1' bits are used to compare the incoming transfer request address A[31:0] with the address as specified in ADDR.ADDR: Address A is in the device when (A[31:8] & MASK[31:8]) == ADDR.ADDR[31:8]."
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "ADDR_CTL,Address control"
|
|
bitfld.long 0x0 8. "DIV2,Specifies if the AHB-Lite bus transfer address is divided by 2 or not:" "0,1"
|
|
bitfld.long 0x0 0.--2. "SIZE3,N/A" "0,1,2,3,4,5,6,7"
|
|
rgroup.long ($2+0x30)++0x3
|
|
line.long 0x0 "RD_STATUS,Read status"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FS_STATUS,Provides the Functional Safety Status Register of the memory received with the last read transfer."
|
|
group.long ($2+0x40)++0x1B
|
|
line.long 0x0 "RD_CMD_CTL,Read command control"
|
|
bitfld.long 0x0 30.--31. "PRESENT2,Presence of command field:" "0,1,2,3"
|
|
bitfld.long 0x0 18. "DDR_MODE,Mode of transfer rate:" "0,1"
|
|
bitfld.long 0x0 16.--17. "WIDTH,Width of data transfer:" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CODEH,Command high byte code."
|
|
hexmask.long.byte 0x0 0.--7. 1. "CODE,Command byte code."
|
|
line.long 0x4 "RD_ADDR_CTL,Read address control"
|
|
bitfld.long 0x4 18. "DDR_MODE,Mode of transfer rate." "0,1"
|
|
bitfld.long 0x4 16.--17. "WIDTH,Width of transfer." "0,1,2,3"
|
|
line.long 0x8 "RD_MODE_CTL,Read mode control"
|
|
bitfld.long 0x8 30.--31. "PRESENT2,Presence of mode field:" "0,1,2,3"
|
|
bitfld.long 0x8 18. "DDR_MODE,Mode of transfer rate." "0,1"
|
|
bitfld.long 0x8 16.--17. "WIDTH,Width of transfer." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "CODEH,Mode high byte code."
|
|
hexmask.long.byte 0x8 0.--7. 1. "CODE,Mode byte code."
|
|
line.long 0xC "RD_DUMMY_CTL,Read dummy control"
|
|
bitfld.long 0xC 30.--31. "PRESENT2,Presence of dummy cycles:" "0,1,2,3"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SIZE5,Number of dummy cycles (minus 1):"
|
|
line.long 0x10 "RD_DATA_CTL,Read data control"
|
|
bitfld.long 0x10 18. "DDR_MODE,Mode of transfer rate." "0,1"
|
|
bitfld.long 0x10 16.--17. "WIDTH,Width of transfer." "0,1,2,3"
|
|
line.long 0x14 "RD_CRC_CTL,Read Bus CRC control"
|
|
bitfld.long 0x14 31. "DATA_CRC_PRESENT,Presence of data CRC field:" "0,1"
|
|
bitfld.long 0x14 30. "CMD_ADDR_CRC_PRESENT,Presence of command / address CRC field:" "0,1"
|
|
bitfld.long 0x14 28. "DATA_CRC_CHECK,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x14 27. "CMD_ADDR_CRC_INPUT,Specifies which fields are included in the command / address CRC generation." "0,1"
|
|
bitfld.long 0x14 26. "CMD_ADDR_CRC_DDR_MODE,Mode of transfer rate of command / address CRC field." "0,1"
|
|
bitfld.long 0x14 24.--25. "CMD_ADDR_CRC_WIDTH,Width of command / address CRC field." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x14 16.--23. 1. "DATA_CRC_INPUT_SIZE,Number of input data bytes for CRC generation (minus 1) i.e. number of data bytes over which the data CRC field is generated (minus 1):"
|
|
hexmask.long.byte 0x14 8.--15. 1. "STATUS_ERROR_POL,Specifies the polarity of the Functional Safety Status field bits. There is 1 polarity bit for each Functional Safety Status bit."
|
|
hexmask.long.byte 0x14 0.--7. 1. "STATUS_CHECK_MASK,Specifies which of the Functional Safety Status field bits are checked. There is 1 mask bit for each Functional Safety Status bit."
|
|
line.long 0x18 "RD_BOUND_CTL,Read boundary control"
|
|
bitfld.long 0x18 31. "PRESENT,Presence of first page boundary latency cycles:" "0,1"
|
|
bitfld.long 0x18 28. "SUBSEQ_BOUND_EN,Enable subsequent page boundary latency cycles." "0,1"
|
|
bitfld.long 0x18 20.--21. "SUB_PAGE_NR,Specifies the number of sub pages per page." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x18 16.--17. "SUB_PAGE_SIZE,Specifies the size of a memory sub page 'sub_page_size'." "0,1,2,3"
|
|
hexmask.long.byte 0x18 0.--4. 1. "SIZE5,Number of base latency cycles (minus 1) used for calculating the number of fist page boundary crossing latency cycles:"
|
|
group.long ($2+0x60)++0x17
|
|
line.long 0x0 "WR_CMD_CTL,Write command control"
|
|
bitfld.long 0x0 30.--31. "PRESENT2,Presence of command field:" "0,1,2,3"
|
|
bitfld.long 0x0 18. "DDR_MODE,Mode of transfer rate." "0,1"
|
|
bitfld.long 0x0 16.--17. "WIDTH,Width of transfer." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CODEH,Command high byte code."
|
|
hexmask.long.byte 0x0 0.--7. 1. "CODE,Command byte code."
|
|
line.long 0x4 "WR_ADDR_CTL,Write address control"
|
|
bitfld.long 0x4 18. "DDR_MODE,Mode of transfer rate." "0,1"
|
|
bitfld.long 0x4 16.--17. "WIDTH,Width of transfer." "0,1,2,3"
|
|
line.long 0x8 "WR_MODE_CTL,Write mode control"
|
|
bitfld.long 0x8 30.--31. "PRESENT2,Presence of mode field:" "0,1,2,3"
|
|
bitfld.long 0x8 18. "DDR_MODE,Mode of transfer rate." "0,1"
|
|
bitfld.long 0x8 16.--17. "WIDTH,Width of transfer." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "CODEH,Mode high byte code."
|
|
hexmask.long.byte 0x8 0.--7. 1. "CODE,Mode byte code."
|
|
line.long 0xC "WR_DUMMY_CTL,Write dummy control"
|
|
bitfld.long 0xC 30.--31. "PRESENT2,Presence of dummy cycles:" "0,1,2,3"
|
|
bitfld.long 0xC 17. "RWDS_EN,Read-Write-Data-Strobe Enable. Specifies whether the RWDS output signal should be driven starting in the last dummy cycle until DESELECT. This is needed for write transactions with byte masking via RWDS (e.g. Hyperbus)." "0,1"
|
|
hexmask.long.byte 0xC 0.--4. 1. "SIZE5,Number of dummy cycles (minus 1):"
|
|
line.long 0x10 "WR_DATA_CTL,Write data control"
|
|
bitfld.long 0x10 18. "DDR_MODE,Mode of transfer rate." "0,1"
|
|
bitfld.long 0x10 16.--17. "WIDTH,Width of transfer." "0,1,2,3"
|
|
line.long 0x14 "WR_CRC_CTL,Write Bus CRC control"
|
|
bitfld.long 0x14 31. "DATA_CRC_PRESENT,Presence of data CRC field:" "0,1"
|
|
bitfld.long 0x14 30. "CMD_ADDR_CRC_PRESENT,Presence of command / address CRC field:" "0,1"
|
|
bitfld.long 0x14 27. "CMD_ADDR_CRC_INPUT,Specifies which fields are included in the command / address CRC generation." "0,1"
|
|
newline
|
|
bitfld.long 0x14 26. "CMD_ADDR_CRC_DDR_MODE,Mode of transfer rate of command / address CRC field." "0,1"
|
|
bitfld.long 0x14 24.--25. "CMD_ADDR_CRC_WIDTH,Width of command / address CRC field." "0,1,2,3"
|
|
hexmask.long.byte 0x14 16.--23. 1. "DATA_CRC_INPUT_SIZE,Number of input data bytes for CRC generation (minus 1) i.e. number of data bytes over which the data CRC field is generated (minus 1):"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "SRSS (SRSS Core Registers)"
|
|
base ad:0x40260000
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x0 "PWR_LVD_STATUS,High Voltage / Low Voltage Detector (HVLVD) Status Register"
|
|
bitfld.long 0x0 0. "HVLVD1_OUT,HVLVD1 output." "0: below voltage threshold,1: above voltage threshold"
|
|
line.long 0x4 "PWR_LVD_STATUS2,High Voltage / Low Voltage Detector (HVLVD) Status Register #2"
|
|
bitfld.long 0x4 0. "HVLVD2_OUT,HVLVD2 output." "0: below voltage threshold,1: above voltage threshold"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x100)++0x3
|
|
line.long 0x0 "CLK_DSI_SELECT[$1],Clock DSI Select Register"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DSI_MUX,Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH<i> using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It.."
|
|
repeat.end
|
|
group.long 0x140++0xB
|
|
line.long 0x0 "CLK_OUTPUT_FAST,Fast Clock Output Select Register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "HFCLK_SEL1,Selects a HFCLK tree for use in fast clock output #1 logic"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "PATH_SEL1,Selects a clock path to use in fast clock output #1 logic."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "FAST_SEL1,Select signal for fast clock output #1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "HFCLK_SEL0,Selects a HFCLK tree for use in fast clock output #0"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "PATH_SEL0,Selects a clock path to use in fast clock output #0 logic."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "FAST_SEL0,Select signal for fast clock output #0"
|
|
line.long 0x4 "CLK_OUTPUT_SLOW,Slow Clock Output Select Register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "SLOW_SEL1,Select signal for slow clock output #1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "SLOW_SEL0,Select signal for slow clock output #0"
|
|
line.long 0x8 "CLK_CAL_CNT1,Clock Calibration Counter 1"
|
|
rbitfld.long 0x8 31. "CAL_COUNTER_DONE,Status bit indicating that the internal counter #1 is finished counting and CLK_CAL_CNT2.COUNTER stopped counting up" "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "CAL_COUNTER1,Down-counter clocked on fast clock output #0 (see CLK_OUTPUT_FAST). This register always reads as zero. Counting starts internally when this register is written with a nonzero value. CAL_COUNTER_DONE goes immediately low to indicate that.."
|
|
rgroup.long 0x14C++0x3
|
|
line.long 0x0 "CLK_CAL_CNT2,Clock Calibration Counter 2"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CAL_COUNTER2,Up-counter clocked on fast clock output #1 (see CLK_OUTPUT_FAST). When CLK_CAL_CNT1.CAL_COUNTER_DONE==1 the counter is stopped and can be read by SW. Do not read this value unless CAL_COUNTER_DONE==1. The expected final value is related.."
|
|
group.long 0x200++0xB
|
|
line.long 0x0 "SRSS_INTR,SRSS Interrupt Register"
|
|
bitfld.long 0x0 5. "CLK_CAL,Clock calibration counter is done. This field is reset during DEEPSLEEP mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "HVLVD2,Interrupt for low voltage detector HVLVD2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "HVLVD1,Interrupt for low voltage detector HVLVD1" "0,1"
|
|
line.long 0x4 "SRSS_INTR_SET,SRSS Interrupt Set Register"
|
|
bitfld.long 0x4 5. "CLK_CAL,Set interrupt for clock calibration counter done. This field is reset during DEEPSLEEP mode." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "HVLVD2,Set interrupt for low voltage detector HVLVD2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "HVLVD1,Set interrupt for low voltage detector HVLVD1" "0,1"
|
|
line.long 0x8 "SRSS_INTR_MASK,SRSS Interrupt Mask Register"
|
|
bitfld.long 0x8 5. "CLK_CAL,Mask for clock calibration done" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "HVLVD2,Mask for low voltage detector HVLVD2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "HVLVD1,Mask for low voltage detector HVLVD1" "0,1"
|
|
rgroup.long 0x20C++0x3
|
|
line.long 0x0 "SRSS_INTR_MASKED,SRSS Interrupt Masked Register"
|
|
bitfld.long 0x0 5. "CLK_CAL,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "HVLVD2,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "HVLVD1,Logical and of corresponding request and mask bits." "0,1"
|
|
rgroup.long 0x1000++0x3
|
|
line.long 0x0 "PWR_CTL,Power Mode Control"
|
|
bitfld.long 0x0 5. "LPM_READY,Indicates whether certain low power functions are ready. The low current circuits take longer to startup after XRES HIBERNATE wakeup or supply supervision reset wakeup than the normal mode circuits. HIBERNATE mode may be entered regardless.." "0: If a low power circuit operation is requested,1: Normal operation"
|
|
newline
|
|
bitfld.long 0x0 4. "DEBUG_SESSION,Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1)" "0: No debug session active,1: Debug session is active. Power modes behave.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "POWER_MODE,Current power mode of the device. Note that this field cannot be read in all power modes on actual silicon." "0: System is resetting.,1: At least one CPU is running.,2: No CPUs are running. Peripherals may be running.,3: Main high-frequency clock is off; low speed.."
|
|
group.long 0x1004++0x7
|
|
line.long 0x0 "PWR_CTL2,Power Mode Control 2"
|
|
bitfld.long 0x0 31. "PLL_LS_BYPASS,Bypass level shifter inside the PLL. Unused if no PLL is present in the product." "0: Do not bypass the level shifter,1: Bypass the level shifter"
|
|
newline
|
|
bitfld.long 0x0 28. "BGREF_LPMODE,Control the circuit-level power mode of the Bandgap Reference circuits." "0: Bandgap Reference circuits operate in higher..,1: Bandgap Reference circuits operate in low power"
|
|
newline
|
|
bitfld.long 0x0 27. "PORBOD_LPMODE,Control the power mode of the POR/BOD circuits. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset." "0: POR/BOD circuits operate in normal mode,1: POR/BOD circuits operate in low power mode"
|
|
newline
|
|
bitfld.long 0x0 26. "REFI_LPMODE,Control the power mode of the reference current generator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset." "0: Current reference generator operates in normal..,1: Current reference generator operates in low.."
|
|
newline
|
|
rbitfld.long 0x0 25. "REFI_OK,Indicates that the current reference is ready. Due to synchronization delays it may take two IMO clock cycles for hardware to clear this bit after asserting REFI_DIS=1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "REFI_DIS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "REFVBUF_LPMODE,Control the power mode of the 800mV voltage reference buffer. The value in this register is ignored and normal mode is used until LPM_READY==1." "0: Voltage Reference Buffer operates in normal mode,1: Voltage Reference Buffer operates in low power.."
|
|
newline
|
|
rbitfld.long 0x0 21. "REFVBUF_OK,Indicates that the voltage reference buffer is ready. Due to synchronization delays it may take two IMO clock cycles for hardware to clear this bit after asserting REFVBUF_DIS=1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "REFVBUF_DIS,Disable the voltage reference buffer. Firmware should only disable the buffer when there is no connected circuit that is using it. SRSS circuits that require it are the PLL and ECO. A particular product may have circuits outside the SRSS.." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 17. "REFV_OK,Indicates that the normal mode of the voltage reference is ready." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "REFV_DIS,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "NWELL_REG_DIS,Explicitly disable the Nwell regulator. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset." "0: Nwell Regulator is on,1: Nwell Regulator is explicitly disabled"
|
|
newline
|
|
bitfld.long 0x0 8. "RET_REG_DIS,Explicitly disable the Retention regulator. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset." "0: Retention Regulator is not explicitly disabled,1: Retention Regulator is explicitly disabled"
|
|
newline
|
|
bitfld.long 0x0 4. "DPSLP_REG_DIS,Explicity disable the DeepSleep regulator including circuits shared with the Active Regulator. This register must not be set except as part of a Cypress-provided sequence or API such as the PMIC case described below. This register is.." "0: DeepSleep Regulator is not explicitly disabled,1: DeepSleep Regulator is explicitly disabled"
|
|
newline
|
|
bitfld.long 0x0 2. "LINREG_LPMODE,Control the power mode of the Linear Regulator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset." "0: Linear Regulator operates in normal mode,1: Linear Regulator operates in low power mode"
|
|
newline
|
|
rbitfld.long 0x0 1. "LINREG_OK,Status of the linear Core Regulator." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "LINREG_DIS,Explicitly disable the linear Core Regulator. Write zero for Traveo II devices. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset." "0: Linear Core Regulator is not explicitly disabled,1: Linear Core Regulator is explicitly disabled"
|
|
line.long 0x4 "PWR_HIBERNATE,HIBERNATE Mode Register"
|
|
bitfld.long 0x4 31. "HIBERNATE,Firmware sets this bit to enter HIBERNATE mode. The system will enter HIBERNATE mode immediately after writing to this bit and will wakeup only in response to XRES or WAKEUP. Both UNLOCK and FREEZE must have been set correctly in a previous.." "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "HIBERNATE_DISABLE,Hibernate disable bit." "0: Normal operation,1: Further writes to this register are ignored"
|
|
newline
|
|
bitfld.long 0x4 29. "SENSE_MODE,Power mode when wakeups are sensitive. The default of this field is 0 for software compatibility with other products. It is recommended to set this field to 1 for new/updated software." "0: Wakeups are sensitive only during HIBERNATE mode,1: Wakeups are sensitive in HIBERNATE and higher.."
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hexmask.long.byte 0x4 24.--27. 1. "MASK_HIBPIN,Obsolete. Use PWR_HIB_WAKE_CTL.HIB_WAKE_SRC for new designs."
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hexmask.long.byte 0x4 20.--23. 1. "POLARITY_HIBPIN,Obsolete. Use PWR_HIB_WAKE_CTL2.HIB_WAKE_SRC for new designs."
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bitfld.long 0x4 19. "MASK_HIBWDT,Obsolete. Use PWR_HIB_WAKE_CTL.HIB_WAKE_WDT for new designs." "0,1"
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bitfld.long 0x4 18. "MASK_HIBALARM,Obsolete. Use PWR_HIB_WAKE_CTL.HIB_WAKE_RTC for new designs." "0,1"
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bitfld.long 0x4 17. "FREEZE,Firmware sets this bit to freeze the configuration mode and state of all GPIOs and SIOs in the system. When entering HIBERNATE mode the first write instructs DEEPSLEEP peripherals that they cannot ignore the upcoming freeze command. This.." "0,1"
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hexmask.long.byte 0x4 8.--15. 1. "UNLOCK,This byte must be set to 0x3A for FREEZE or HIBERNATE fields to operate. Any other value in this register will cause FREEZE/HIBERNATE to have no effect except as noted in the FREEZE description."
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hexmask.long.byte 0x4 0.--7. 1. "TOKEN,Contains a 8-bit token that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware to differentiate WAKEUP from a general RESET event. Note that waking up from HIBERNATE using XRES will reset this register."
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group.long 0x1010++0xB
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line.long 0x0 "PWR_BUCK_CTL,Buck Control Register"
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bitfld.long 0x0 31. "BUCK_OUT1_EN,Enable for vccbuck1 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset. The regulator takes up to 600us to charge the external.." "0,1"
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bitfld.long 0x0 30. "BUCK_EN,Master enable for buck converter. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset." "0,1"
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bitfld.long 0x0 0.--2. "BUCK_OUT1_SEL,Voltage output selection for vccbuck1 output. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset. When increasing the voltage it can take up to 200us for the output voltage to settle. When decreasing the.." "0,1,2,3,4,5,6,7"
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line.long 0x4 "PWR_BUCK_CTL2,Buck Control Register 2"
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bitfld.long 0x4 31. "BUCK_OUT2_EN,Enable for vccbuck2 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging this will increase the.." "0,1"
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bitfld.long 0x4 30. "BUCK_OUT2_HW_SEL,Hardware control for vccbuck2 output. When this bit is set the value in BUCK_OUT2_EN is ignored and a hardware signal is used instead. If the product has supporting hardware it can directly control the enable signal for vccbuck2." "0,1"
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bitfld.long 0x4 0.--2. "BUCK_OUT2_SEL,Voltage output selection for vccbuck2 output. When increasing the voltage it can take up to 200us for the output voltage to settle. When decreasing the voltage the settling time depends on the load current." "0,1,2,3,4,5,6,7"
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line.long 0x8 "PWR_SSV_CTL,Supply Supervision Control Register"
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bitfld.long 0x8 27. "OVDVCCD_ENABLE,Enable for OVD on vccd. This cannot be disabled during normal operation." "0,1"
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bitfld.long 0x8 24. "OVDVDDA_ENABLE,Enable for OVD on vdda." "0,1"
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bitfld.long 0x8 22.--23. "OVDVDDA_ACTION,Action taken when the OVD on vdda triggers." "0: No action,1: Generate a fault,2: Reset the chip,?"
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bitfld.long 0x8 20. "OVDVDDA_VSEL,Selects the voltage threshold for OVD on vdda. Ensure OVDVDDA_ENABLE==0 before changing this setting to prevent false triggers" "0: vddd>5,1: vddd>5"
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bitfld.long 0x8 19. "OVDVDDD_ENABLE,Enable for OVD on vddd. This cannot be disabled during normal operation." "0,1"
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bitfld.long 0x8 16. "OVDVDDD_VSEL,Selects the voltage threshold for OVD on vddd. The OVD does not reliably monitor the supply during the transition." "0: vddd>5,1: vddd>5"
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bitfld.long 0x8 11. "BODVCCD_ENABLE,Enable for BOD on vccd. This cannot be disabled during normal operation." "0,1"
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bitfld.long 0x8 8. "BODVDDA_ENABLE,Enable for BOD on vdda. BODVDDA_ACTION will be triggered when the BOD is disabled. If no action is desired when disabling firmware must first write BODVDDA_ACTION=NOTHING in a separate write cycle." "0,1"
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bitfld.long 0x8 6.--7. "BODVDDA_ACTION,Action taken when the BOD on vdda triggers." "0: No action,1: Generate a fault,2: Reset the chip,?"
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bitfld.long 0x8 4. "BODVDDA_VSEL,Selects the voltage threshold for BOD on vdda. Ensure BODVDDA_ENABLE==0 before changing this setting to prevent false triggers." "0: vdda<2,1: vdda<3"
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bitfld.long 0x8 3. "BODVDDD_ENABLE,Enable for BOD on vddd. This cannot be disabled during normal operation." "0,1"
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bitfld.long 0x8 0. "BODVDDD_VSEL,Selects the voltage threshold for BOD on vddd. The BOD does not reliably monitor the supply during the transition." "0: vddd<2,1: vddd<3"
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rgroup.long 0x101C++0x3
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line.long 0x0 "PWR_SSV_STATUS,Supply Supervision Status Register"
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bitfld.long 0x0 17. "OCD_DPSLP_REG_OK,OCD indicates the current drawn from the linear DeepSleep Regulator is ok. This will always read 1 because a detected over-current condition will reset the chip." "0,1"
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bitfld.long 0x0 16. "OCD_ACT_LINREG_OK,OCD indicates the current drawn from the linear Active Regulator is ok. This will always read 1 because a detected over-current condition will reset the chip." "0,1"
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bitfld.long 0x0 10. "OVDVCCD_OK,OVD indicates vccd is ok. This will always read 1 because a detected over-over-voltage condition will reset the chip." "0,1"
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bitfld.long 0x0 9. "OVDVDDA_OK,OVD indicates vdda is ok." "0,1"
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bitfld.long 0x0 8. "OVDVDDD_OK,OVD indicates vddd is ok. This will always read 1 because a detected over-voltage condition will reset the chip." "0,1"
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bitfld.long 0x0 2. "BODVCCD_OK,BOD indicates vccd is ok. This will always read 1 because a detected brownout will reset the chip." "0,1"
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bitfld.long 0x0 1. "BODVDDA_OK,BOD indicates vdda is ok." "0,1"
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bitfld.long 0x0 0. "BODVDDD_OK,BOD indicates vddd is ok. This will always read 1 because a detected brownout will reset the chip." "0,1"
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group.long 0x1020++0xB
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line.long 0x0 "PWR_LVD_CTL,High Voltage / Low Voltage Detector (HVLVD) Configuration Register"
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bitfld.long 0x0 18. "HVLVD1_ACTION,Action taken when the threshold is crossed in the programmed directions(s)" "0: Generate an interrupt,1: Generate a fault"
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bitfld.long 0x0 16.--17. "HVLVD1_EDGE_SEL,Sets which edge(s) will trigger an action when the threshold is crossed." "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
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bitfld.long 0x0 15. "HVLVD1_EN_HT,Enable HVLVD1 voltage monitor. This detector monitors vddd only. Do not change other HVLVD1 settings when enabled." "0,1"
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bitfld.long 0x0 14. "HVLVD1_DPSLP_EN_HT,Keep HVLVD1 voltage monitor enabled during DEEPSLEEP mode. This field is only used when HVLVD1_EN_HT==1." "0,1"
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hexmask.long.byte 0x0 8.--12. 1. "HVLVD1_TRIPSEL_HT,N/A"
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bitfld.long 0x0 7. "HVLVD1_EN,Enable HVLVD1 voltage monitor. HVLVD1 does not function during DEEPSLEEP but it automatically returns to its configured setting after DEEPSLEEP wakeup. Do not change other HVLVD1 settings when enabled." "0,1"
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bitfld.long 0x0 4.--6. "HVLVD1_SRCSEL,Source selection for HVLVD1" "0: Select VDDD,1: Select AMUXBUSA (VDDD branch),2: N/A,3: N/A,4: Select AMUXBUSB (VDDD branch),?,?,?"
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hexmask.long.byte 0x0 0.--3. 1. "HVLVD1_TRIPSEL,Threshold selection for HVLVD1. Disable the detector (HVLVD1_EN=0) before changing the threshold."
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line.long 0x4 "PWR_LVD_CTL2,High Voltage / Low Voltage Detector (HVLVD) Configuration Register #2"
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bitfld.long 0x4 18. "HVLVD2_ACTION,Action taken when the threshold is crossed in the programmed directions(s)" "0: Generate an interrupt,1: Generate a fault"
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bitfld.long 0x4 16.--17. "HVLVD2_EDGE_SEL,Sets which edge(s) will trigger an action when the threshold is crossed." "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
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bitfld.long 0x4 15. "HVLVD2_EN_HT,Enable HVLVD2 voltage monitor. This detector monitors vddd only. Do not change other HVLVD2 settings when enabled." "0,1"
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bitfld.long 0x4 14. "HVLVD2_DPSLP_EN_HT,Keep HVLVD2 voltage monitor enabled during DEEPSLEEP mode. This field is only used when HVLVD1_EN_HT==1." "0,1"
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hexmask.long.byte 0x4 8.--12. 1. "HVLVD2_TRIPSEL_HT,N/A"
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line.long 0x8 "PWR_REGHC_CTL,REGHC Control Register"
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bitfld.long 0x8 31. "REGHC_CONFIGURED,Indicates the REGHC has been configured. This is used to know if REGHC should be enabled in response to a debug power up request. It is recommended to not change REGHC settings after REGHC_CONFIGURED is set high because it can cause.." "0,1"
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bitfld.long 0x8 30. "REGHC_TRANS_USE_OCD,N/A" "0,1"
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hexmask.long.word 0x8 20.--29. 1. "REGHC_PMIC_STATUS_WAIT,Wait count in 4us steps after PMIC status ok. This is used by the hardware sequencer to allow additional settling time before disabling the internal regulator. The LSB is 32 IMO periods which results in a nominal LSB step of 4us."
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bitfld.long 0x8 19. "REGHC_PMIC_STATUS_POLARITY,The polarity used to trigger a reset action based on the PMIC status input. The reset system triggers a reset when the unmasked PMIC status matches this value." "0,1"
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bitfld.long 0x8 18. "REGHC_PMIC_STATUS_INEN,Input buffer enable for PMIC status input. Set this bit high to enable the input receiver." "0,1"
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bitfld.long 0x8 17. "REGHC_PMIC_CTL_POLARITY,Polarity used to enable the PMIC. The sequencer uses REGHC_PMIC_CTL_POLARITY to enable the PMIC and it uses the complement to disable the PMIC." "0,1"
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bitfld.long 0x8 16. "REGHC_PMIC_CTL_OUTEN,Output enable for PMIC enable pin. Set this bit high to enable the driver on this pin." "0,1"
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bitfld.long 0x8 12.--14. "REGHC_PMIC_RADJ,Reset voltage adjustment for PMIC as a factor (Vfbk/Vref) where Vfbk is the feedback voltage and Vref is the PMIC internal reference. The reset voltage adjustment circuit is enabled by the hardware sequencer if REGHC_PMIC_USE_RADJ=1." "0: Vfbk/Vref=1,1: Vfbk/Vref=1,2: Vfbk/Vref=1,3: Vfbk/Vref=1,4: Vfbk/Vref=1,5: Vfbk/Vref=1,6: Vfbk/Vref=1,7: Vfbk/Vref=1"
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bitfld.long 0x8 11. "REGHC_PMIC_USE_RADJ,Controls whether hardware sequencer enables reset voltage adjustment circuit when enabling a PMIC." "0,1"
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bitfld.long 0x8 10. "REGHC_PMIC_USE_LINREG,For REGHC external PMIC mode controls whether hardware sequencer keeps the internal Active Linear Regulator enabled to improve supply supervision of vccd. When using this feature if the PMIC fails to keep vccd above the internal.." "0: Internal Active Linear Regulator disabled after..,1: Internal Active Linear Regulator kept enabled"
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hexmask.long.byte 0x8 4.--8. 1. "REGHC_VADJ,Regulator output trim according to the formula vadj=(1.020V + REGHC_VADJ*0.005V) plus an offset described below. For example 0x1A=>1.15V (nominal)."
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bitfld.long 0x8 2.--3. "REGHC_PMIC_DRV_VOUT,Setting for DRV_VOUT pin for PMIC mode. See REGHC_VADJ for calculation of vadj." "0: DRV_VOUT=vccd*0,1: DRV_VOUT=vccd*0,2: DRV_VOUT=vccd*0,3: DRV_VOUT=vccd"
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bitfld.long 0x8 0. "REGHC_MODE,REGHC control mode:" "0: external transistor connected,1: external PMIC connected"
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rgroup.long 0x102C++0x3
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line.long 0x0 "PWR_REGHC_STATUS,REGHC Status Register"
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bitfld.long 0x0 31. "REGHC_SEQ_BUSY,Indicates the REGHC enable/disable sequencer is busy transitioning to/from REGHC." "0: Sequencer is not busy;,1: Sequencer is busy either enabling or disabling.."
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bitfld.long 0x0 12. "REGHC_PMIC_STATUS_OK,Indicates the PMIC status is ok. This includes polarity adjustment according to REGHC_PMIC_STATUS_POLARITY." "0: PMIC status is not ok or PMIC input buffer is..,1: PMIC status input buffer is enabled and.."
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bitfld.long 0x0 9. "REGHC_OV_OUT,N/A" "0,1"
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bitfld.long 0x0 8. "REGHC_UV_OUT,N/A" "0,1"
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bitfld.long 0x0 2. "REGHC_CKT_OK,Indicates the REGHC circuit is enabled and operating. It does not indicate that the voltage and current are within required limits for robust operation." "0: REGHC circuit is not ready,1: REGHC circuit is enabled and operating"
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bitfld.long 0x0 1. "REGHC_OCD_OK,Indicates the over-current detector is operating and the current drawn from REGHC is within limits. OCD is only a choice for transistor mode and it is disabled for PMIC mode." "0: Current measurement exceeds limit or detector is..,1: Current measurement within limit"
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bitfld.long 0x0 0. "REGHC_ENABLED,Indicates the state of the REGHC enable/disable sequencer. This bit is only valid when REGHC_SEQ_BUSY==0." "0: REGHC sequencer indicates REGHC is disabled,1: REGHC sequencer indicates REGHC is enabled"
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group.long 0x1030++0x3
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line.long 0x0 "PWR_REGHC_CTL2,REGHC Control Register 2"
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bitfld.long 0x0 31. "REGHC_EN,Enable REGHC. This bit will not set if REGHC_CONFIGURED==0. Use PWR_REGHC_STATUS.ENABLED to know the actual status of REGHC. It will differ from this bit in the following cases:" "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "REGHC_PMIC_STATUS_TIMEOUT,Timeout while waiting for REGHC_PMIC_STATUS_OK==1 when switching to PMIC."
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group.long 0x1038++0x3
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line.long 0x0 "PWR_REGHC_CTL4,REGHC Control Register 4"
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bitfld.long 0x0 31. "REGHC_PMIC_DPSLP,When operating in PMIC mode configures PMIC behavior during DEEPSLEEP." "0: Device operates from internal regulators during..,1: DEEPSLEEP transition does not change PMIC enable"
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bitfld.long 0x0 30. "REGHC_PMIC_VADJ_DIS,When operating in PMIC mode disables the VADJ circuitry. This can be used to decrease current consumption if the entire feedback network is outside the device." "0: Device generates VADJ when PMIC is enabled,1: Device does not generate VADJ"
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repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
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group.long ($2+0x1040)++0x3
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line.long 0x0 "PWR_HIB_DATA[$1],HIBERNATE Data Register"
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hexmask.long 0x0 0.--31. 1. "HIB_DATA,Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register."
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repeat.end
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group.long 0x10C0++0x3
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line.long 0x0 "PWR_PMIC_CTL,PMIC Control Register"
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bitfld.long 0x0 31. "PMIC_CONFIGURED,Indicates the PMIC has been configured. This is used to know if PMIC should be enabled in response to a debug power up request. Do not change PMIC settings after this bit is set high." "0,1"
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hexmask.long.word 0x0 20.--29. 1. "PMIC_STATUS_WAIT,Wait count in 4us steps after PMIC status ok. This is used by the hardware sequencer to allow additional settling time before disabling the internal regulator. The LSB is 32 IMO periods which results in a nominal LSB step of 4us."
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bitfld.long 0x0 19. "PMIC_STATUS_POLARITY,The polarity used to trigger a reset action based on the PMIC status input. The reset system triggers a reset when the unmasked PMIC status matches this value." "0,1"
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bitfld.long 0x0 18. "PMIC_STATUS_INEN,Input buffer enable for PMIC status input. Set this bit high to enable the input receiver." "0,1"
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bitfld.long 0x0 17. "PMIC_CTL_POLARITY,Polarity used to enable the PMIC. The sequencer uses PMIC_CTL_POLARITY to enable the PMIC and it uses the complement to disable the PMIC." "0,1"
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bitfld.long 0x0 16. "PMIC_CTL_OUTEN,Output enable for PMIC enable pin. Set this bit high to enable the driver on this pin." "0,1"
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bitfld.long 0x0 15. "PMIC_VADJ_BUF_EN,Analog buffer enable on voltage adjust output. Write this bit depending on the type of PMIC connected:" "0: Bypass buffer,1: Use analog buffer"
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bitfld.long 0x0 10. "PMIC_USE_LINREG,Controls whether hardware sequencer keeps the internal Active Linear Regulator enabled to improve supply supervision of vccd. When using this feature if the PMIC fails to keep vccd above the internal regulator target then the internal.." "0: Internal Active Linear Regulator disabled after..,1: Internal Active Linear Regulator kept enabled"
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hexmask.long.byte 0x0 4.--8. 1. "PMIC_VADJ,Voltage adjustment output setting. The lookup table in this field requires the proper setting in PMIC_VREF for the chosen PMIC. This field has no effect when PMIC_VREF selects no scaling. The feedback tap point is at a vccd pad inside the.."
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bitfld.long 0x0 2.--3. "PMIC_VREF,PMIC reference voltage setting. This selects the scaling factor used to generate the output voltage (vout) given the feedback voltage (vfb) for the chosen PMIC. For a PMIC that compares vfb to an internal reference voltage (vref) according to.." "0: Scale for vref=0,1: Scale for vref=0,2: Scale for vref=0,3: No scaling"
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rgroup.long 0x10C4++0x3
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line.long 0x0 "PWR_PMIC_STATUS,PMIC Status Register"
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bitfld.long 0x0 31. "PMIC_SEQ_BUSY,Indicates the PMIC enable/disable sequencer is busy transitioning to/from PMIC." "0: Sequencer is not busy;,1: Sequencer is busy either enabling or disabling.."
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bitfld.long 0x0 12. "PMIC_STATUS_OK,Indicates the PMIC status is ok. This includes polarity adjustment according to PMIC_STATUS_POLARITY." "0: PMIC status is not ok or PMIC input buffer is..,1: PMIC status input buffer is enabled and.."
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bitfld.long 0x0 0. "PMIC_ENABLED,Indicates the state of the PMIC enable/disable sequencer. This bit is only valid when PMIC_SEQ_BUSY==0." "0: PMIC sequencer indicates PMIC is disabled,1: PMIC sequencer indicates PMIC is enabled"
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group.long 0x10C8++0x3
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line.long 0x0 "PWR_PMIC_CTL2,PMIC Control Register 2"
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bitfld.long 0x0 31. "PMIC_EN,Enable PMIC. This bit will not set if PMIC_CONFIGURED==0. Use PWR_PMIC_STATUS.ENABLED to know the actual status of PMIC. It will differ from this bit in the following cases:" "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "PMIC_STATUS_TIMEOUT,Timeout while waiting for PMIC_STATUS_OK==1 when switching to PMIC."
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group.long 0x10D0++0x3
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line.long 0x0 "PWR_PMIC_CTL4,PMIC Control Register 4"
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bitfld.long 0x0 31. "PMIC_DPSLP,Configures PMIC behavior during DEEPSLEEP." "0: Device operates from internal regulators during..,1: DEEPSLEEP transition does not change PMIC enable"
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bitfld.long 0x0 30. "PMIC_VADJ_DIS,Disables the VADJ circuitry. This can be used to decrease current consumption if the entire feedback network is outside the device." "0: Device generates VADJ when PMIC is enabled,1: Device does not generate VADJ"
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group.long 0x10E0++0x7
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line.long 0x0 "PWR_HIB_WAKE_CTL,Hibernate Wakeup Mask Register"
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bitfld.long 0x0 31. "HIB_WAKE_WDT,When set HIBERNATE will wakeup for a pending WDT interrupt." "0,1"
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bitfld.long 0x0 30. "HIB_WAKE_RTC,When set HIBERNATE will wakeup for a pending RTC interrupt." "0,1"
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bitfld.long 0x0 29. "HIB_WAKE_CSV_BAK,When set HIBERNATE will wakeup for CSV_BAK detection." "0,1"
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hexmask.long.tbyte 0x0 0.--23. 1. "HIB_WAKE_SRC,When set HIBERNATE will wakeup for the assigned source The number and assignment of wakeup sources are product-specific."
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line.long 0x4 "PWR_HIB_WAKE_CTL2,Hibernate Wakeup Polarity Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "HIB_WAKE_SRC,Each bit selects the polarity for the corresponding HIBERNATE wakeup source. The number and assignment of wakeup sources are product-specific."
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group.long 0x10EC++0x3
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line.long 0x0 "PWR_HIB_WAKE_CAUSE,Hibernate Wakeup Cause Register"
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bitfld.long 0x0 31. "HIB_WAKE_WDT,Indicates WDT wakeup cause. The WDT interrupt must be cleared before this bit can be cleared." "0,1"
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bitfld.long 0x0 30. "HIB_WAKE_RTC,Indicates RTC wakeup cause. The RTC interrupt must be cleared before this bit can be cleared." "0,1"
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newline
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|
bitfld.long 0x0 29. "HIB_WAKE_CSV_BAK,Indicates CSV_BAK wakeup cause. The related fault must be handled before this bit can be cleared." "0,1"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "HIB_WAKE_SRC,Each bit indicates a HIBERNATE wakeup cause. The number and assigment of wakeup sources are product-specific. For each bit writing a 1 clears the cause flag."
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1200)++0x3
|
|
line.long 0x0 "CLK_PATH_SELECT[$1],Clock Path Select Register"
|
|
bitfld.long 0x0 0.--2. "PATH_MUX,Selects a source for clock PATH<i>. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. It takes four cycles of the originally selected clock to switch away.." "0: IMO - Internal R/C Oscillator,1: EXTCLK - External Clock Pin,2: ECO - External-Crystal Oscillator,3: ALTHF - Alternate High-Frequency clock input..,4: DSI_MUX - Output of DSI mux for this path. Using..,5: LPECO - Low-Power External-Crystal Oscillator,?,?"
|
|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1240)++0x3
|
|
line.long 0x0 "CLK_ROOT_SELECT[$1],Clock Root Select Register"
|
|
bitfld.long 0x0 31. "ENABLE,Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0 which cannot be disabled." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DIRECT_MUX,Direct selection mux that allows IMO to bypass most of the clock mux structure. For products with multiple regulators this mux can be used to reduce current without requiring significant reconfiguration of the clocking network. The.." "0: ROOT_MUX,1: Select ROOT_MUX selection"
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|
newline
|
|
bitfld.long 0x0 4.--5. "ROOT_DIV,Selects predivider value for this clock root and DSI input. This divider is after DIRECT_MUX. For products with DSI the output of this mux is routed to DSI for use as a signal. For products with clock supervision the output of this mux is.." "0: Transparent mode feed through selected clock..,1: Divide selected clock source by 2,2: Divide selected clock source by 4,3: Divide selected clock source by 8"
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|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "ROOT_MUX,Selects a clock path as the root of HFCLK<k> and for SRSS DSI input <k>. Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific) and the control and bypass mux selections of these are.."
|
|
repeat.end
|
|
tree "CSV_HF (Clock Supervisor (CSV) registers for Root clocks)"
|
|
base ad:0x40261400
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x40261400 ad:0x40261410 ad:0x40261420 ad:0x40261430 ad:0x40261440 ad:0x40261450 ad:0x40261460 ad:0x40261470)
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|
tree "CSV[$1]"
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|
base $2
|
|
group.long ($2)++0xB
|
|
line.long 0x0 "REF_CTL,Clock Supervision Reference Control"
|
|
bitfld.long 0x0 31. "CSV_EN,Enables clock supervision both frequency and loss." "0,1"
|
|
bitfld.long 0x0 30. "CSV_ACTION,Specifies the action taken when an anomaly is detected on the monitored clock. CSV in DeepSleep domain always do a Fault report (which also wakes up the system)." "0: Do a Fault report.,1: Cause a power reset. This should only be used.."
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|
hexmask.long.word 0x0 0.--15. 1. "STARTUP,Startup delay time -1 (in reference clock cycles) after enable or DeepSleep wakeup from reference clock start to monitored clock start."
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|
line.long 0x4 "REF_LIMIT,Clock Supervision Reference Limits"
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|
hexmask.long.word 0x4 16.--31. 1. "UPPER,Cycle time upper limit. Set the upper limit -1 in reference clock cycles before (or same time) the next monitored clock event must happen. If a monitored clock event does not happen before this limit is reached or does not happen at all (clock.."
|
|
hexmask.long.word 0x4 0.--15. 1. "LOWER,Cycle time lower limit. Set the lower limit -1 in reference clock cycles before the next monitored clock event is allowed to happen. If a monitored clock event happens before this limit is reached a CSV error is detected."
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|
line.long 0x8 "MON_CTL,Clock Supervision Monitor Control"
|
|
hexmask.long.word 0x8 0.--15. 1. "PERIOD,Period time. Set the Period -1 in monitored clock cycles before the next monitored clock event happens."
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
base ad:0x40260000
|
|
group.long 0x1500++0x3
|
|
newline
|
|
line.long 0x0 "CLK_SELECT,Clock selection register"
|
|
bitfld.long 0x0 15. "PUMP_ENABLE,N/A" "0,1"
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|
newline
|
|
bitfld.long 0x0 12.--14. "PUMP_DIV,N/A" "0: N/A,1: N/A,2: N/A,3: N/A,4: N/A,?,?,?"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "PUMP_SEL,N/A"
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|
newline
|
|
bitfld.long 0x0 0.--2. "LFCLK_SEL,Select source for LFCLK. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK.." "0: ILO0 - Internal Low-speed Oscillator #0.,1: WCO - Watch-Crystal Oscillator. Requires Backup..,2: ALTLF - Alternate Low-Frequency Clock.,3: PILO - Precision ILO. If present it works in..,4: ILO1 - Internal Low-speed Oscillator #1 if..,5: ECO_PRESCALER - External-Crystal Oscillator..,6: LPECO_PRESCALER - Low-Power External-Crystal..,?"
|
|
group.long 0x1508++0x7
|
|
line.long 0x0 "CLK_ILO0_CONFIG,ILO0 Configuration"
|
|
bitfld.long 0x0 31. "ENABLE,Master enable for ILO. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "ILO0_MON_ENABLE,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ILO0_BACKUP,This register indicates that ILO0 should stay enabled during XRES and HIBERNATE modes. If backup voltage domain is implemented on the product this bit also indicates if ILO0 should stay enabled through power-related resets on other.." "0: ILO0 turns off during XRES,1: ILO0 stays enabled"
|
|
line.long 0x4 "CLK_ILO1_CONFIG,ILO1 Configuration"
|
|
bitfld.long 0x4 31. "ENABLE,Master enable for ILO1." "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "ILO1_MON_ENABLE,N/A" "0,1"
|
|
group.long 0x1518++0xB
|
|
line.long 0x0 "CLK_IMO_CONFIG,IMO Configuration"
|
|
bitfld.long 0x0 31. "ENABLE,Master enable for IMO oscillator. This bit must be high at all times for all functions to work properly. Hardware will automatically disable the IMO during DEEPSLEEP HIBERNATE and XRES." "0,1"
|
|
line.long 0x4 "CLK_ECO_CONFIG,ECO Configuration Register"
|
|
bitfld.long 0x4 31. "ECO_EN,Master enable for ECO oscillator. Configure the settings in CLK_ECO_CONFIG2 to work with the selected crystal before enabling ECO." "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "ECO_DIV_ENABLE,ECO prescaler enable command (mutually exclusive with ECO_DIV_DISABLE). ECO Prescaler only works in ACTIVE and SLEEP modes. SW sets this field to '1' to enable the divider and HW sets this field to '0' to indicate that divider enabling.." "0: Disable the divider using the ECO_DIV_DISABLE..,1: Configure CLK_ECO_PRESCALE registers"
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|
newline
|
|
bitfld.long 0x4 27. "ECO_DIV_DISABLE,ECO prescaler disable command (mutually exclusive with ECO_DIV_ENABLE). SW sets this field to '1' and HW sets this field to '0'." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "AGC_EN,Automatic Gain Control (AGC) enable. When set the oscillation amplitude is controlled to the level selected by CLK_ECO_CONFIG2.ATRIM. When low the amplitude is not explicitly controlled and can be as high as the vddd supply. WARNING: use care.." "0,1"
|
|
line.long 0x8 "CLK_ECO_PRESCALE,ECO Prescaler Configuration Register"
|
|
hexmask.long.word 0x8 16.--25. 1. "ECO_INT_DIV,10-bit integer value allows for ECO frequencies up to 33.55MHz. Subtract one from the desired divide value when writing this field. For example to divide by 1 write ECO_INT_DIV=0. Do not change this setting when ECO Prescaler is enabled."
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "ECO_FRAC_DIV,8-bit fractional value sufficient to get prescaler output within the +/-65ppm calibration range. Do not change this setting when ECO Prescaler is enabled."
|
|
newline
|
|
rbitfld.long 0x8 0. "ECO_DIV_ENABLED,ECO prescaler enabled. HW sets this field to '1' as a result of an CLK_ECO_CONFIG.ECO_DIV_ENABLE command. HW sets this field to '0' as a result on a CLK_ECO_CONFIG.ECO_DIV_DISABLE command." "0,1"
|
|
rgroup.long 0x1524++0x3
|
|
line.long 0x0 "CLK_ECO_STATUS,ECO Status Register"
|
|
bitfld.long 0x0 1. "ECO_READY,Indicates the ECO internal oscillator circuit has had enough time to fully stabilize. This is the output of a counter since ECO was enabled and it does not check the ECO output. It is recommended to also confirm ECO_OK==1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ECO_OK,Indicates the ECO internal oscillator circuit has sufficient amplitude. It may not meet the PPM accuracy or duty cycle spec." "0,1"
|
|
group.long 0x1528++0x3
|
|
line.long 0x0 "CLK_PILO_CONFIG,Precision ILO Configuration Register"
|
|
bitfld.long 0x0 31. "PILO_EN,Enable PILO. When enabling PILO set PILO_EN=1 wait 1ms then PILO_RESET_N=1 and PILO_CLK_EN=1. When disabling PILO clear PILO_EN=0 PILO_RESET_N=0 and PLO_CLK_EN=0 in the same write cycle." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "PILO_RESET_N,Reset the PILO. See PILO_EN field for required sequencing." "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "PILO_CLK_EN,Enable the PILO clock output. See PILO_EN field for required sequencing." "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--9. 1. "PILO_FFREQ,Fine frequency trim allowing +/-250ppm accuracy with periodic calibration. The nominal step size of the LSB is 8Hz."
|
|
group.long 0x1530++0x17
|
|
line.long 0x0 "CLK_FLL_CONFIG,FLL Configuration Register"
|
|
bitfld.long 0x0 31. "FLL_ENABLE,Master enable for FLL. The FLL requires firmware sequencing when enabling and disabling. Hardware handles sequencing automatically when entering/exiting DEEPSLEEP." "0: Block is powered off,1: Block is powered on"
|
|
newline
|
|
bitfld.long 0x0 24. "FLL_OUTPUT_DIV,Control bits for Output divider. Set the divide value before enabling the FLL and do not change it while FLL is enabled." "0: no division,1: divide by 2"
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--17. 1. "FLL_MULT,Multiplier to determine CCO frequency in multiples of the frequency of the selected reference clock (Fref)."
|
|
line.long 0x4 "CLK_FLL_CONFIG2,FLL Configuration Register 2"
|
|
hexmask.long.byte 0x4 24.--31. 1. "UPDATE_TOL,Update tolerance sets the error threshold for when the FLL will update the CCO frequency settings. The update tolerance is the allowed difference between the count value for the ideal formula and the measured value. UPDATE_TOL should be less.."
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "LOCK_TOL,Lock tolerance sets the error threshold for when the FLL output is considered locked to the reference input. A high tolerance can be used to lock more quickly or allow less accuracy. The tolerance is the allowed difference between the count.."
|
|
newline
|
|
hexmask.long.word 0x4 0.--12. 1. "FLL_REF_DIV,Control bits for reference divider. Set the divide value before enabling the FLL and do not change it while FLL is enabled."
|
|
line.long 0x8 "CLK_FLL_CONFIG3,FLL Configuration Register 3"
|
|
bitfld.long 0x8 28.--29. "BYPASS_SEL,Bypass mux located just after FLL output. This register can be written while the FLL is enabled. When changing BYPASS_SEL do not turn off the reference clock or CCO clock for five cycles (whichever is slower). In case of disabling.." "0: Automatic using lock indicator. When unlocked..,1: Similar to AUTO except the clock is gated off..,2: Select FLL reference input (bypass mode).,3: Select FLL output. Ignores lock indicator."
|
|
newline
|
|
hexmask.long.word 0x8 8.--20. 1. "SETTLING_COUNT,Number of undivided reference clock cycles to wait after changing the CCO trim until the loop measurement restarts. A delay allows the CCO output to settle and gives a more accurate measurement. The default is tuned to an 8MHz reference.."
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "FLL_LF_PGAIN,FLL Loop Filter Gain Setting #2. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "FLL_LF_IGAIN,FLL Loop Filter Gain Setting #1. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN."
|
|
line.long 0xC "CLK_FLL_CONFIG4,FLL Configuration Register 4"
|
|
bitfld.long 0xC 31. "CCO_ENABLE,Enable the CCO. It is required to enable the CCO before using the FLL." "0: Block is powered off,1: Block is powered on"
|
|
newline
|
|
bitfld.long 0xC 30. "CCO_HW_UPDATE_DIS,Disable CCO frequency update by FLL hardware" "0: Hardware update of CCO settings is allowed,1: Hardware update of CCO settings is disabled"
|
|
newline
|
|
hexmask.long.word 0xC 16.--24. 1. "CCO_FREQ,CCO frequency code. This is updated by HW when the FLL is enabled. It can be manually updated to use the CCO in an open loop configuration. The meaning of each frequency code depends on the range."
|
|
newline
|
|
bitfld.long 0xC 8.--10. "CCO_RANGE,Frequency range of CCO" "0: Target frequency is in range [48 64) MHz,1: Target frequency is in range [64 85) MHz,2: Target frequency is in range [85 113) MHz,3: Target frequency is in range [113 150) MHz,4: Target frequency is in range [150 200] MHz,?,?,?"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CCO_LIMIT,Maximum CCO offset allowed (used to prevent FLL dynamics from selecting an CCO frequency that the logic cannot support)"
|
|
line.long 0x10 "CLK_FLL_STATUS,FLL Status Register"
|
|
rbitfld.long 0x10 2. "CCO_READY,This indicates that the CCO is internally settled and ready to use." "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "UNLOCK_OCCURRED,This bit sets whenever the FLL is enabled and goes out of lock. This bit stays set until cleared by firmware." "0,1"
|
|
newline
|
|
rbitfld.long 0x10 0. "LOCKED,FLL Lock Indicator" "0,1"
|
|
line.long 0x14 "CLK_ECO_CONFIG2,ECO Configuration Register 2"
|
|
bitfld.long 0x14 12.--14. "GTRIM,Gain Trim - Startup time." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x14 10.--11. "RTRIM,Feedback resistor Trim" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 8.--9. "FTRIM,Filter Trim - 3rd harmonic oscillation" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x14 4.--7. 1. "ATRIM,Amplitude trim. Sets maximum oscillation amplitude (Vp) to set the crystal drive level when ECO_CONFIG.AGC_EN=1. When AGC_EN=0 most values of this register are unused except as noted. WARNING: use care when setting this field because driving a.."
|
|
newline
|
|
bitfld.long 0x14 0.--2. "WDTRIM,Watch Dog Trim. Sets the minimum oscillation amplitude (Vp) for the crystal drive level. The minimum amplitude detector output is readable in CLK_ECO_STATUS.ECO_OK." "0: Vp > 0,1: Vp > 0,2: Vp > 0,3: Vp > 0,4: Vp > 0,5: Vp > 0,6: Vp > 0,7: Vp > 0"
|
|
repeat 15. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1600)++0x3
|
|
line.long 0x0 "CLK_PLL_CONFIG[$1],PLL Configuration Register"
|
|
bitfld.long 0x0 31. "ENABLE,Master enable for PLL. Setup FEEDBACK_DIV REFERENCE_DIV and OUTPUT_DIV at least one cycle before setting ENABLE=1." "0: Block is disabled,1: Block is enabled"
|
|
newline
|
|
bitfld.long 0x0 28.--29. "BYPASS_SEL,Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. When changing BYPASS_SEL do not turn off the reference clock or PLL clock for five cycles (whichever is slower)." "0: Automatic using lock indicator. When unlocked..,1: Similar to AUTO except the clock is gated off..,2: Select PLL reference input (bypass mode).,3: Select PLL output. Ignores lock indicator. If.."
|
|
newline
|
|
bitfld.long 0x0 27. "PLL_LF_MODE,VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled." "0: VCO frequency is [200MHz,1: VCO frequency is [170MHz"
|
|
newline
|
|
bitfld.long 0x0 25.--26. "LOCK_DELAY,N/A" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "OUTPUT_DIV,Control bits for Output divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "REFERENCE_DIV,Control bits for reference divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "FEEDBACK_DIV,Control bits for feedback divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
|
|
repeat.end
|
|
repeat 15. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1640)++0x3
|
|
line.long 0x0 "CLK_PLL_STATUS[$1],PLL Status Register"
|
|
bitfld.long 0x0 1. "UNLOCK_OCCURRED,This bit sets whenever the PLL Lock bit goes low and stays set until cleared by firmware." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 0. "LOCKED,PLL Lock Indicator" "0,1"
|
|
repeat.end
|
|
group.long 0x1700++0x3
|
|
line.long 0x0 "CSV_REF_SEL,Select CSV Reference clock for Active domain"
|
|
bitfld.long 0x0 0.--2. "REF_MUX,Selects a source for clock clk_ref_hf. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. It takes four cycles of the originally selected clock to switch.." "0: IMO - Internal R/C Oscillator,1: EXTCLK - External Clock Pin,2: ECO - External-Crystal Oscillator,3: ALTHF - Alternate High-Frequency clock input..,?,?,?,?"
|
|
tree "CSV_ILO (CSV registers for HVILO clock)"
|
|
base ad:0x40261730
|
|
tree "CSV (ILO0 clock DeepSleep domain Clock Supervisor registers)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "REF_CTL,Clock Supervision Reference Control"
|
|
bitfld.long 0x0 31. "CSV_EN,Enables clock supervision both frequency and loss." "0,1"
|
|
hexmask.long.word 0x0 0.--8. 1. "STARTUP,Startup delay time -1 (in reference clock cycles) after enable from reference clock start to monitored clock start."
|
|
line.long 0x4 "REF_LIMIT,Clock Supervision Reference Limits"
|
|
hexmask.long.byte 0x4 16.--23. 1. "UPPER,Cycle time upper limit. Set the upper limit -1 in reference clock cycles before (or same time) the next monitored clock event must happen. If a monitored clock event does not happen before this limit is reached or does not happen at all (clock.."
|
|
hexmask.long.byte 0x4 0.--7. 1. "LOWER,Cycle time lower limit. Set the lower limit -1 in reference clock cycles before the next monitored clock event is allowed to happen. If a monitored clock event happens before this limit is reached a CSV error is detected."
|
|
line.long 0x8 "MON_CTL,Clock Supervision Monitor Control"
|
|
hexmask.long.byte 0x8 0.--7. 1. "PERIOD,Period time. Set the Period -1 in monitored clock cycles before the next monitored clock event happens."
|
|
tree.end
|
|
tree.end
|
|
tree "CSV_LF (CSV registers for LF clock)"
|
|
base ad:0x40261720
|
|
tree "CSV (LF clock Clock Supervisor registers)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "REF_CTL,Clock Supervision Reference Control"
|
|
bitfld.long 0x0 31. "CSV_EN,Enables clock supervision both frequency and loss." "0,1"
|
|
hexmask.long.word 0x0 0.--8. 1. "STARTUP,Startup delay time -1 (in reference clock cycles) after enable from reference clock start to monitored clock start."
|
|
line.long 0x4 "REF_LIMIT,Clock Supervision Reference Limits"
|
|
hexmask.long.byte 0x4 16.--23. 1. "UPPER,Cycle time upper limit. Set the upper limit -1 in reference clock cycles before (or same time) the next monitored clock event must happen. If a monitored clock event does not happen before this limit is reached or does not happen at all (clock.."
|
|
hexmask.long.byte 0x4 0.--7. 1. "LOWER,Cycle time lower limit. Set the lower limit -1 in reference clock cycles before the next monitored clock event is allowed to happen. If a monitored clock event happens before this limit is reached a CSV error is detected."
|
|
line.long 0x8 "MON_CTL,Clock Supervision Monitor Control"
|
|
hexmask.long.byte 0x8 0.--7. 1. "PERIOD,Period time. Set the Period -1 in monitored clock cycles before the next monitored clock event happens."
|
|
tree.end
|
|
tree.end
|
|
tree "CSV_REF (CSV registers for the CSV Reference clock)"
|
|
base ad:0x40261710
|
|
tree "CSV (Active domain Clock Supervisor (CSV) registers for CSV Reference clock)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "REF_CTL,Clock Supervision Reference Control"
|
|
bitfld.long 0x0 31. "CSV_EN,Enables clock supervision both frequency and loss." "0,1"
|
|
bitfld.long 0x0 30. "CSV_ACTION,Specifies the action taken when an anomaly is detected on the monitored clock. CSV in DeepSleep domain always do a Fault report (which also wakes up the system)." "0: Do a Fault report.,1: Cause a power reset. This should only be used.."
|
|
hexmask.long.word 0x0 0.--15. 1. "STARTUP,Startup delay time -1 (in reference clock cycles) after enable or DeepSleep wakeup from reference clock start to monitored clock start."
|
|
line.long 0x4 "REF_LIMIT,Clock Supervision Reference Limits"
|
|
hexmask.long.word 0x4 16.--31. 1. "UPPER,Cycle time upper limit. Set the upper limit -1 in reference clock cycles before (or same time) the next monitored clock event must happen. If a monitored clock event does not happen before this limit is reached or does not happen at all (clock.."
|
|
hexmask.long.word 0x4 0.--15. 1. "LOWER,Cycle time lower limit. Set the lower limit -1 in reference clock cycles before the next monitored clock event is allowed to happen. If a monitored clock event happens before this limit is reached a CSV error is detected."
|
|
line.long 0x8 "MON_CTL,Clock Supervision Monitor Control"
|
|
hexmask.long.word 0x8 0.--15. 1. "PERIOD,Period time. Set the Period -1 in monitored clock cycles before the next monitored clock event happens."
|
|
tree.end
|
|
tree.end
|
|
base ad:0x40260000
|
|
group.long 0x1800++0x7
|
|
newline
|
|
line.long 0x0 "RES_CAUSE,Reset Cause Observation Register"
|
|
bitfld.long 0x0 30. "RESET_PORVDDD,Indicator that a POR occurred. This is a high-voltage cause bit and hardware clears the other bits when this one is set. It does not block further recording of other high-voltage causes." "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RESET_STRUCT_XRES,Structural reset was asserted. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware clears this bit during POR. This bit is not blocked by other HV cause bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RESET_PXRES,PXRES triggered. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware clears this bit during POR. This bit is not blocked by other HV cause bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "RESET_PMIC,PMIC status triggered a reset. PMIC_STATUS_TIMEOUT expiration will set this bit without issuing reset which will be observed by a subsequent WDT reset. If PMIC control is not present hardware will never set this bit. This is a.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RESET_OCD_REGHC,Overcurrent detection from REGHC (if present). REGHC_STATUS_TIMEOUT expiration will set this bit without issuing reset which will be observed by a subsequent WDT reset. If REGHC is not present hardware will never set this bit. This is.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "RESET_OCD_DPSLP_LINREG,Overcurrent detection on the internal VCCD supply when supplied by the DEEPSLEEP power mode linear regulator. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "RESET_OCD_ACT_LINREG,Overcurrent detection on the internal VCCD supply when supplied by the ACTIVE power mode linear regulator. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "RESET_OVDVCCD,Overvoltage detection on the internal core VCCD supply. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware clears this bit during POR." "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "RESET_OVDVDDA,Overvoltage detection on the external VDDA supply. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware clears this bit during POR." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "RESET_OVDVDDD,Overvoltage detection on the external VDDD supply. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware clears this bit during POR." "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RESET_BODVCCD,Internal VCCD core supply crossed the brown-out limit. Note that this detector will detect gross issues with the internal core supply but may not catch all brown-out conditions. Functional and timing supervision (CSV WDT) is provided to.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RESET_BODVDDA,External VDDA supply crossed the brown-out limit. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware clears this bit during POR." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RESET_BODVDDD,External VDDD supply crossed brown-out limit. Note that this cause will only be observable as long as the VDDD supply does not go below the POR (power on reset) detection limit. Below this limit it is not possible to reliably retain.." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RESET_XRES,External XRES pin was asserted. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware clears this bit during POR. This bit is not blocked by other HV cause bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RESET_MCWDT3,Multi-Counter Watchdog timer reset #3. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RESET_MCWDT2,Multi-Counter Watchdog timer reset #2. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RESET_MCWDT1,Multi-Counter Watchdog timer reset #1. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RESET_MCWDT0,Multi-Counter Watchdog timer reset #0. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RESET_SOFT,A CPU requested a system reset through it's SYSRESETREQ. This can be done via a debugger probe or in firmware. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RESET_TC_DBGRESET,Test controller or debugger asserted reset. Only resets debug domain. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RESET_DPSLP_FAULT,Fault logging system requested a reset from its DeepSleep logic. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RESET_ACT_FAULT,Fault logging system requested a reset from its Active logic. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RESET_WDT,A basic WatchDog Timer (WDT) reset has occurred since last power cycle. ULP products: This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above)." "0,1"
|
|
line.long 0x4 "RES_CAUSE2,Reset Cause Observation Register 2"
|
|
bitfld.long 0x4 16. "RESET_CSV_REF,Clock supervision logic requested a reset due to loss or frequency violation of the reference clock source that is used to monitor the other HF clock sources." "0,1"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "RESET_CSV_HF,Clock supervision logic requested a reset due to loss or frequency violation of a high-frequency clock. Each bit index K corresponds to a HFCLK<K>. Unimplemented clock bits return zero."
|
|
repeat 2. (list 0x0 0x1)(list ad:0x40261900 ad:0x40261910)
|
|
tree "CLK_PLL400M[$1]"
|
|
base $2
|
|
group.long ($2)++0xF
|
|
line.long 0x0 "CONFIG,400MHz PLL Configuration Register"
|
|
bitfld.long 0x0 31. "ENABLE,Master enable for PLL. Setup FEEDBACK_DIV REFERENCE_DIV and OUTPUT_DIV at least one cycle before setting ENABLE=1." "0: Block is disabled,1: Block is enabled"
|
|
bitfld.long 0x0 28.--29. "BYPASS_SEL,Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. When changing BYPASS_SEL do not turn off the reference clock or PLL clock for five cycles (whichever is slower)." "0: Automatic using lock indicator. When unlocked..,1: Similar to AUTO except the clock is gated off..,2: Select PLL reference input (bypass mode).,3: Select PLL output. Ignores lock indicator. If.."
|
|
bitfld.long 0x0 25.--26. "LOCK_DELAY,N/A" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "OUTPUT_DIV,Control bits for Output divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
|
|
hexmask.long.byte 0x0 8.--12. 1. "REFERENCE_DIV,Control bits for reference divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
|
|
hexmask.long.byte 0x0 0.--7. 1. "FEEDBACK_DIV,Control bits for feedback divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
|
|
line.long 0x4 "CONFIG2,400MHz PLL Configuration Register 2"
|
|
bitfld.long 0x4 31. "FRAC_EN,Enables fractional division mode. When using fractional division mode see CLK_PLL400M_CONFIG.LOCK_DELAY for an additional configuration requirement." "0,1"
|
|
bitfld.long 0x4 28.--30. "FRAC_DITHER_EN,N/A" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "FRAC_DIV,Control bits for fractional divider. This value is interpreted as a fraction of the PFD frequency i.e. fPFD * (FRAC_DIV/2^24). This field can be dynamically updated within the 1000ppm control limit. It takes up to 115 AHB cycles to transfer.."
|
|
line.long 0x8 "CONFIG3,400MHz PLL Configuration Register 3"
|
|
bitfld.long 0x8 31. "SSCG_EN,Enables spreading mode. When using spreading see CLK_PLL400M_CONFIG.LOCK_DELAY for an additional configuration requirement." "0,1"
|
|
bitfld.long 0x8 28. "SSCG_MODE,N/A" "0,1"
|
|
bitfld.long 0x8 24. "SSCG_DITHER_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16.--18. "SSCG_RATE,N/A" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x8 0.--9. 1. "SSCG_DEPTH,N/A"
|
|
line.long 0xC "STATUS,400MHz PLL Status Register"
|
|
bitfld.long 0xC 1. "UNLOCK_OCCURRED,This bit sets whenever the PLL Lock bit goes low and stays set until cleared by firmware." "0,1"
|
|
rbitfld.long 0xC 0. "LOCKED,PLL Lock Indicator" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 15. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE)(list ad:0x40261A00 ad:0x40261A20 ad:0x40261A40 ad:0x40261A60 ad:0x40261A80 ad:0x40261AA0 ad:0x40261AC0 ad:0x40261AE0 ad:0x40261B00 ad:0x40261B20 ad:0x40261B40 ad:0x40261B60 ad:0x40261B80 ad:0x40261BA0 ad:0x40261BC0)
|
|
tree "CLK_DPLL400M[$1]"
|
|
base $2
|
|
group.long ($2)++0xB
|
|
line.long 0x0 "CONFIG,400MHz Digital PLL Configuration Register"
|
|
bitfld.long 0x0 31. "ENABLE,Master enable for PLL. Setup FEEDBACK_DIV REFERENCE_DIV and OUTPUT_DIV at least one cycle before setting ENABLE=1." "0: Block is disabled,1: Block is enabled"
|
|
bitfld.long 0x0 28.--29. "BYPASS_SEL,Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. When changing BYPASS_SEL do not turn off the reference clock or PLL clock for five cycles (whichever is slower)." "0: Automatic using lock indicator. When unlocked..,1: Similar to AUTO except the clock is gated off..,2: Select PLL reference input (bypass mode).,3: Select PLL output. Ignores lock indicator. If.."
|
|
bitfld.long 0x0 25.--26. "LOCK_DELAY,N/A" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "OUTPUT_DIV,Control bits for Output divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
|
|
hexmask.long.byte 0x0 8.--12. 1. "REFERENCE_DIV,Control bits for reference divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
|
|
hexmask.long.byte 0x0 0.--7. 1. "FEEDBACK_DIV,Control bits for feedback divider. Set the divide value before enabling the PLL and do not change it while PLL is enabled."
|
|
line.long 0x4 "CONFIG2,400MHz Digital PLL Configuration Register 2"
|
|
bitfld.long 0x4 31. "FRAC_EN,Enables fractional division mode. When using fractional division mode see CLK_PLL400M_CONFIG.LOCK_DELAY for an additional configuration requirement." "0,1"
|
|
bitfld.long 0x4 28.--30. "FRAC_DITHER_EN,N/A" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "FRAC_DIV,Control bits for fractional divider. This value is interpreted as a fraction of the PFD frequency i.e. fPFD * (FRAC_DIV/2^24). This field can be dynamically updated within the 1000ppm control limit. It takes up to 115 AHB cycles to transfer.."
|
|
line.long 0x8 "CONFIG3,400MHz Digital PLL Configuration Register 3"
|
|
bitfld.long 0x8 31. "SSCG_EN,Enables spreading mode. When using spreading see CLK_PLL400M_CONFIG.LOCK_DELAY for an additional configuration requirement." "0,1"
|
|
bitfld.long 0x8 28. "SSCG_MODE,N/A" "0,1"
|
|
bitfld.long 0x8 24. "SSCG_DITHER_EN,N/A" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16.--18. "SSCG_RATE,N/A" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x8 0.--9. 1. "SSCG_DEPTH,N/A"
|
|
group.long ($2+0x10)++0x3
|
|
line.long 0x0 "STATUS,400MHz Digital PLL Status Register"
|
|
bitfld.long 0x0 1. "UNLOCK_OCCURRED,This bit sets whenever the PLL Lock bit goes low and stays set until cleared by firmware." "0,1"
|
|
rbitfld.long 0x0 0. "LOCKED,PLL Lock Indicator" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40260000
|
|
group.long 0x3014++0x3
|
|
line.long 0x0 "CLK_TRIM_ILO0_CTL,ILO0 Trim Register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "ILO0_MONTRIM,ILO0 internal monitor trim."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "ILO0_FTRIM,ILO0 frequency trims. LSB step size is 1.5 percent (typical) of the frequency."
|
|
group.long 0x3108++0x3
|
|
line.long 0x0 "PWR_TRIM_PWRSYS_CTL,Power System Trim Register"
|
|
bitfld.long 0x0 30.--31. "ACT_REG_BOOST,Controls the tradeoff between output current and internal operating current for the Active Regulator. The maximum output current depends on the silicon implementation but an application may limit its maximum current to less than that." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "ACT_REG_TRIM,Trim for the Active-Regulator. This sets the output voltage level. This register is only reset by XRES HIBERNATE wakeup or supply supervision reset. The nominal output voltage is vccd=812.5mV + ACT_REG_TRIM*12.5mV. The actual output.."
|
|
group.long 0x3114++0xB
|
|
line.long 0x0 "CLK_TRIM_PILO_CTL,PILO Trim Register"
|
|
bitfld.long 0x0 28.--30. "PILO_VTDIFF_TRIM,Trim for VT-DIFF output (internal power supply)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "PILO_ISLOPE_TRIM,Trim for beta-multiplier current slope" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--24. 1. "PILO_RES_TRIM,Trim for beta-multiplier branch current"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "PILO_NBIAS_TRIM,Trim for biasn by trimming sub-Vth NMOS width in beta-multiplier" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "PILO_COMP_TRIM,Trim for comparator bias current." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "PILO_OSC_TRIM,Trim for current in oscillator block." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "PILO_CFREQ,Coarse frequency trim to meet 32.768kHz +/-2 percent across PVT without calibration. The nominal step size of the LSB is 1kHz."
|
|
line.long 0x4 "CLK_TRIM_PILO_CTL2,PILO Trim Register 2"
|
|
hexmask.long.byte 0x4 16.--23. 1. "PILO_IREF_TRIM,Trim for current reference"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--12. 1. "PILO_IREFBM_TRIM,Trim for beta-multiplier current reference"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "PILO_VREF_TRIM,Trim for voltage reference"
|
|
line.long 0x8 "CLK_TRIM_PILO_CTL3,PILO Trim Register 3"
|
|
hexmask.long.word 0x8 0.--15. 1. "PILO_ENGOPT,Engineering options for PILO circuits"
|
|
group.long 0x3220++0x3
|
|
line.long 0x0 "CLK_TRIM_ILO1_CTL,ILO1 Trim Register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "ILO1_MONTRIM,ILO1 internal monitor trim."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "ILO1_FTRIM,ILO1 frequency trims. LSB step size is 1.5 percent (typical) of the frequency."
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40268000 ad:0x40268100 ad:0x40268200 ad:0x40268300)
|
|
tree "MCWDT[$1]"
|
|
base $2
|
|
repeat 2. (list 0x0 0x1)(list 0x0 0x20)
|
|
tree "CTR[$1]"
|
|
group.long ($2)++0x17
|
|
line.long 0x0 "CTL,MCWDT Subcounter Control Register"
|
|
bitfld.long 0x0 31. "ENABLE,Enable subcounter. May take up to 2 clk_lf cycles to take effect. When ENABLE changes from 1->0 the counter is cleared." "0: Counter is disabled,1: Counter is enabled"
|
|
rbitfld.long 0x0 0. "ENABLED,Indicates actual state of this subcounter. May lag ENABLE by up to two clk_lf cycles." "0,1"
|
|
line.long 0x4 "LOWER_LIMIT,MCWDT Subcounter Lower Limit Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "LOWER_LIMIT,Lower limit for this MCWDT subcounter. See LOWER_ACTION."
|
|
line.long 0x8 "UPPER_LIMIT,MCWDT Subcounter Upper Limit Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "UPPER_LIMIT,Upper limit for this MCWDT subcounter. See UPPER_ACTION."
|
|
line.long 0xC "WARN_LIMIT,MCWDT Subcounter Warn Limit Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "WARN_LIMIT,Warn limit for this MCWDT subcounter. See WARN_ACTION."
|
|
line.long 0x10 "CONFIG,MCWDT Subcounter Configuration Register"
|
|
bitfld.long 0x10 31. "DEBUG_RUN,Pauses/runs this counter while a debugger is connected. Other behaviors are unchanged during debugging including service configuration updates and enable/disable. Note it may take up to two clk_lf cycles for the counter to pause due to.." "0: When debugger connected,1: When debugger connected"
|
|
bitfld.long 0x10 30. "SLEEPDEEP_PAUSE,Pauses/runs this counter when the corresponding processor is in SLEEPDEEP. Note it may take up to two clk_lf cycles for the counter to pause and up to two clk_lf cycles for it to unpause due to internal synchronization. After wakeup .." "0: Counter runs normally regardless of processor mode,1: Counter pauses when corresponding processor is.."
|
|
newline
|
|
bitfld.long 0x10 28. "DEBUG_TRIGGER_EN,Enables the trigger input for this MCWDT to pause the counter during debug mode. To pause at a breakpoint while debugging configure the trigger matrix to connect the related CPU halted signal to the trigger input for this MCWDT and.." "0: Pauses the counter whenever a debug probe is..,1: Pauses the counter whenever a debug probe is.."
|
|
bitfld.long 0x10 12. "AUTO_SERVICE,Automatically service when the count value reaches WARN_LIMIT. This allows creation of a periodic interrupt if this counter is not needed as a watchdog. This field is ignored when LOWER_ACTION<>NOTHING or when UPPER_ACTION<>NOTHING." "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "WARN_ACTION,Action taken when the count value reaches WARN_LIMIT. The minimum setting to achieve a periodic interrupt is WARN_LIMIT==1. A setting of zero will trigger once but not periodically." "0: Do nothing,1: Trigger an interrupt."
|
|
bitfld.long 0x10 4.--5. "UPPER_ACTION,Action taken if this watchdog is not serviced before UPPER_LIMIT is reached. The counter stops counting when UPPER_LIMIT is reached regardless of UPPER_ACTION setting. UPPER_ACTION is ignored (i.e. treated as NOTHING) when a debugger is.." "0: Do nothing,1: Trigger a fault. For UPPER_LIMIT >= 2: The..,2: Trigger a fault. Further trigger a system-wide..,?"
|
|
newline
|
|
bitfld.long 0x10 0.--1. "LOWER_ACTION,Action taken if this watchdog is serviced before LOWER_LIMIT is reached. LOWER_ACTION is ignored (i.e. treated as NOTHING) when a debugger is connected and/or when the corresponding processor is in SLEEPDEEP." "0: Do nothing,1: Trigger a fault. It can take up to 3 clk_lf..,2: Trigger a fault. Further trigger a system-wide..,?"
|
|
line.long 0x14 "CNT,MCWDT Subcounter Count Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "CNT,Current value of subcounter for this MCWDT. This field may lag the actual count value by up to one clk_lf cycle due to internal synchronization. When this subcounter is disabled and unlocked the count value can be written for verification and.."
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40268000
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "CPU_SELECT,MCWDT CPU selection register"
|
|
bitfld.long 0x0 0.--1. "CPU_SEL,Assigns this MCWDT to a CPU. This selects which CPU SLEEPDEEP signal is used for SLEEPDEEP_PAUSE." "0,1,2,3"
|
|
group.long ($2+0x80)++0xB
|
|
line.long 0x0 "CTR2_CTL,MCWDT Subcounter 2 Control register"
|
|
bitfld.long 0x0 31. "ENABLE,Enable subcounter. May take up to 2 clk_lf cycles to take effect. When ENABLE changes from 1->0 the counter is cleared." "0: Counter is disabled,1: Counter is enabled"
|
|
rbitfld.long 0x0 0. "ENABLED,Indicates actual state of this subcounter. May lag ENABLE by up to two clk_lf cycles." "0,1"
|
|
line.long 0x4 "CTR2_CONFIG,MCWDT Subcounter 2 Configuration register"
|
|
bitfld.long 0x4 31. "DEBUG_RUN,Pauses/runs this counter while a debugger is connected. Other behaviors are unchanged during debugging including service configuration updates and enable/disable. Note it may take up to two clk_lf cycles for the counter to pause and another.." "0: When debugger connected,1: When debugger connected"
|
|
bitfld.long 0x4 30. "SLEEPDEEP_PAUSE,Pauses/runs this counter when the corresponding processor is in SLEEPDEEP. Note it may take up to two clk_lf cycles for the counter to pause and up to two clk_lf cycles for it to unpause due to internal synchronization." "0: Counter runs normally regardless of processor mode,1: Counter pauses when corresponding processor is.."
|
|
newline
|
|
bitfld.long 0x4 28. "DEBUG_TRIGGER_EN,Enables the trigger input for this MCWDT to pause the counter during debug mode. To pause at a breakpoint while debugging configure the trigger matrix to connect the related CPU halted signal to the trigger input for this MCWDT and.." "0: Pauses the counter whenever a debug probe is..,1: Pauses the counter whenever a debug probe is.."
|
|
hexmask.long.byte 0x4 16.--20. 1. "BITS,Bit to observe for a toggle:"
|
|
newline
|
|
bitfld.long 0x4 0. "ACTION,Action taken when the specified BIT toggles." "0: Do nothing,1: Trigger an interrupt"
|
|
line.long 0x8 "CTR2_CNT,MCWDT Subcounter 2 Count Register"
|
|
hexmask.long 0x8 0.--31. 1. "CNT2,Current value of subcounter 2 for this MCWDT. This field may lag the actual count value by up to one clk_lf cycle due to internal synchronization. When this subcounter is disabled and unlocked the count value can be written for verification and.."
|
|
group.long ($2+0x90)++0x7
|
|
line.long 0x0 "LOCK,MCWDT Lock Register"
|
|
bitfld.long 0x0 0.--1. "MCWDT_LOCK,Prohibits writing control and configuration registers related to this MCWDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock." "0: No effect,1: Clears bit 0,2: Clears bit 1,3: Sets both bits 0 and 1"
|
|
line.long 0x4 "SERVICE,MCWDT Service Register"
|
|
bitfld.long 0x4 1. "CTR1_SERVICE,Services subcounter 1. This resets the count value for subcounter 1 to zero. This may take up to three clk_lf cycles to take effect. Hardware clears this bit after necessary synchronization. To ensure a pending CTR1_SERVICE write is.." "0,1"
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|
bitfld.long 0x4 0. "CTR0_SERVICE,Services subcounter 0. This resets the count value for subcounter 0 to zero. This may take up to three clk_lf cycles to take effect. Hardware clears this bit after necessary synchronization. To ensure a pending CTR0_SERVICE write is.." "0,1"
|
|
group.long ($2+0xA0)++0xB
|
|
line.long 0x0 "INTR,MCWDT Interrupt Register"
|
|
bitfld.long 0x0 2. "CTR2_INT,MCWDT Interrupt Request for sub-counter 2. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware." "0,1"
|
|
bitfld.long 0x0 1. "CTR1_INT,MCWDT Interrupt Request for sub-counter 1. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CTR0_INT,MCWDT Interrupt Request for sub-counter 0. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware." "0,1"
|
|
line.long 0x4 "INTR_SET,MCWDT Interrupt Set Register"
|
|
bitfld.long 0x4 2. "CTR2_INT,Set interrupt for MCWDT_INT2" "0,1"
|
|
bitfld.long 0x4 1. "CTR1_INT,Set interrupt for MCWDT_INT1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CTR0_INT,Set interrupt for MCWDT_INT0" "0,1"
|
|
line.long 0x8 "INTR_MASK,MCWDT Interrupt Mask Register"
|
|
bitfld.long 0x8 2. "CTR2_INT,Interrupt Mask for sub-counter 2. The bit controls if the interrupt is forwarded to the CPU. The interrupt is blocked when the value of the bit is 0. The interrupt is forwarded if the value of the bit is 1." "0,1"
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|
bitfld.long 0x8 1. "CTR1_INT,Interrupt Mask for sub-counter 1 for warning interrupt. The bit controls if the interrupt is forwarded to the CPU. The interrupt is blocked when the value of the bit is 0. The interrupt is forwarded if the value of the bit is 1." "0,1"
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|
newline
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bitfld.long 0x8 0. "CTR0_INT,Interrupt Mask for sub-counter 0 for warning interrupt. The bit controls if the interrupt is forwarded to the CPU. The interrupt is blocked when the value of the bit is 0. The interrupt is forwarded if the value of the bit is 1." "0,1"
|
|
rgroup.long ($2+0xAC)++0x3
|
|
line.long 0x0 "INTR_MASKED,MCWDT Interrupt Masked Register"
|
|
bitfld.long 0x0 2. "CTR2_INT,Logical and of corresponding request and mask bits." "0,1"
|
|
bitfld.long 0x0 1. "CTR1_INT,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CTR0_INT,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0x4026C000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CTL,WDT Control Register"
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|
bitfld.long 0x0 31. "ENABLE,Enable watchdog. May take up to three clk_ilo0 cycles to take effect. When ENABLE changes from 1->0 the counter is cleared. Do not enter DEEPSLEEP or HIBERNATE mode if ENABLE<>ENABLED. This can be done by waiting until ENABLE==ENABLED.." "0: Counter is disabled,1: Counter is enabled"
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|
rbitfld.long 0x0 0. "ENABLED,Indicates actual state of watchdog. May lag ENABLE by up to three clk_ilo0 cycles." "0,1"
|
|
line.long 0x4 "LOWER_LIMIT,WDT Lower Limit Register"
|
|
hexmask.long 0x4 0.--31. 1. "LOWER_LIMIT,Lower limit for watchdog. See LOWER_ACTION."
|
|
line.long 0x8 "UPPER_LIMIT,WDT Upper Limit Register"
|
|
hexmask.long 0x8 0.--31. 1. "UPPER_LIMIT,Upper limit for watchdog. See UPPER_ACTION."
|
|
line.long 0xC "WARN_LIMIT,WDT Warn Limit Register"
|
|
hexmask.long 0xC 0.--31. 1. "WARN_LIMIT,Warn limit for watchdog. See WARN_ACTION."
|
|
line.long 0x10 "CONFIG,WDT Configuration Register"
|
|
bitfld.long 0x10 31. "DEBUG_RUN,Pauses/runs this counter while a debugger is connected. Other behaviors are unchanged during debugging including service configuration updates and enable/disable. Note it may take up to two clk_ilo0 cycles for the counter to pause and.." "0: When debugger connected,1: When debugger connected"
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|
bitfld.long 0x10 30. "HIB_PAUSE,Pauses/runs this counter when the system is in HIBERNATE. Note it may take up to two clk_ilo0 cycles for the counter to pause due to internal synchronization. After wakeup the LOWER_ACTION is ignored until after the first service. This.." "0: Counter behaves normally during HIBERNATE,1: Counter pauses during HIBERNATE"
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|
newline
|
|
bitfld.long 0x10 29. "DPSLP_PAUSE,Pauses/runs this counter when the system is in DEEPSLEEP. Note it may take up to two clk_ilo0 cycles for the counter to pause due to internal synchronization. During DEEPSLEEP wakeup the pause request is removed when clk_hf0 starts.." "0: Counter behaves normally during DEEPSLEEP,1: Counter pauses during DEEPSLEEP"
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bitfld.long 0x10 28. "DEBUG_TRIGGER_EN,Enables the trigger input for WDT to pause the counter during debug mode. To pause at a breakpoint while debugging configure the trigger matrix to connect the related CPU halted signal to the trigger input for this WDT and then set.." "0: Pauses the counter whenever a debug probe is..,1: Pauses the counter whenever a debug probe is.."
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newline
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bitfld.long 0x10 12. "AUTO_SERVICE,Automatically service when the count value reaches WARN_LIMIT. This allows creation of a periodic interrupt if this counter is not needed as a watchdog. This field is ignored when LOWER_ACTION<>NOTHING or when UPPER_ACTION<>NOTHING." "0,1"
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bitfld.long 0x10 8. "WARN_ACTION,Action taken when the count value reaches WARN_LIMIT. The minimum setting to achieve a periodic interrupt is WARN_LIMIT==1. A setting of zero will trigger once but not periodically." "0: Do nothing,1: Trigger an interrupt."
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|
newline
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bitfld.long 0x10 4. "UPPER_ACTION,Action taken if this watchdog is not serviced before UPPER_LIMIT is reached. The counter stops counting when UPPER_LIMIT is reached regardless of UPPER_ACTION setting. UPPER_ACTION is ignored (i.e. treated as NOTHING) when a debugger is.." "0: Do nothing,1: Trigger a reset."
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bitfld.long 0x10 0. "LOWER_ACTION,Action taken if this watchdog is serviced before LOWER_LIMIT is reached. LOWER_ACTION is ignored (i.e. treated as NOTHING) when a debugger is connected and/or when the chip is in DEEPSLEEP/HIBERNATE modes." "0: No action is triggered,1: The action is triggered on same edge when it.."
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|
line.long 0x14 "CNT,WDT Count Register"
|
|
hexmask.long 0x14 0.--31. 1. "CNT,Current value of subcounter for this WDT. This field may lag the actual count value by up to one clk_ilo0 cycle due to internal synchronization. When this subcounter is disabled and unlocked the count value can be written for verification and.."
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|
group.long 0x40++0x7
|
|
line.long 0x0 "LOCK,WDT Lock register"
|
|
bitfld.long 0x0 0.--1. "WDT_LOCK,Prohibits writing control and configuration registers related to this WDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock." "0: No effect,1: Clears bit 0,2: Clears bit 1,3: Sets both bits 0 and 1"
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|
line.long 0x4 "SERVICE,WDT Service register"
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|
bitfld.long 0x4 0. "SERVICE,Services the watchdog. This resets the count value to zero. This may take up to three clk_ilo0 cycle to take effect. Hardware clears this bit after necessary synchronization. To ensure a pending SERVICE write is reflected firmware should.." "0,1"
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|
group.long 0x50++0xB
|
|
line.long 0x0 "INTR,WDT Interrupt Register"
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|
bitfld.long 0x0 0. "WDT,WDT Interrupt Request. This bit is set as configured by WDT action and limits. Due to internal synchronization it takes up to 8 SYSCLK cycles to update after a W1C or reading this register and during this time AHB bus is stalled." "0,1"
|
|
line.long 0x4 "INTR_SET,WDT Interrupt Set Register"
|
|
bitfld.long 0x4 0. "WDT,Set interrupt." "0,1"
|
|
line.long 0x8 "INTR_MASK,WDT Interrupt Mask Register"
|
|
bitfld.long 0x8 0. "WDT,Mask for watchdog timer. Clearing this bit will not forward the interrupt to the CPU." "0,1"
|
|
rgroup.long 0x5C++0x3
|
|
line.long 0x0 "INTR_MASKED,WDT Interrupt Masked Register"
|
|
bitfld.long 0x0 0. "WDT,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "TCPWM (Timer/Counter/PWM)"
|
|
base ad:0x0
|
|
tree "TCPWM0"
|
|
base ad:0x40380000
|
|
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40380000 ad:0x40388000 ad:0x40390000)
|
|
tree "GRP[$1]"
|
|
base $2
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list 0x0 0x80 0x100 0x180 0x200 0x280 0x300 0x380 0x400 0x480 0x500 0x580 0x600 0x680 0x700 0x780)
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|
tree "CNT[$1]"
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTRL,Counter control register"
|
|
bitfld.long 0x0 31. "ENABLED,Counter enable." "0,1"
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|
newline
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bitfld.long 0x0 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode." "0,1"
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|
newline
|
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bitfld.long 0x0 24.--26. "MODE,Counter mode." "0: Timer mode,1: N/A,2: Capture mode,3: Quadrature mode Different encoding modes can be..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode."
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newline
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bitfld.long 0x0 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode." "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode. Input phiA.."
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newline
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bitfld.long 0x0 18. "ONE_SHOT,When '0' counter runs continuous. When '1' counter is turned off by hardware when a terminal count event is generated." "0,1"
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|
newline
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bitfld.long 0x0 16.--17. "UP_DOWN_MODE,Determines counter direction." "0: Count up (to PERIOD). An overflow event is..,1: Count down (to '0'). An underflow event is..,2: Count up (to PERIOD) then count down (to '0').,3: Count up (to PERIOD) then count down (to '0')."
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|
newline
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bitfld.long 0x0 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped." "0: The behavior is the same is in previous mxtcpwm..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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|
newline
|
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bitfld.long 0x0 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior:" "0,1"
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|
newline
|
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bitfld.long 0x0 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values. This field has a function in PWM and PWM_PR modes." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM and PWM_DT modes." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
|
|
newline
|
|
bitfld.long 0x0 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
|
|
rgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "STATUS,Counter status register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter. In PWM_DT mode this counter is used for dead time insertion."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field. In PWM_DT mode this counter is used for dead time insertion (8bit dead time counter or low byte of 16-bit dead time counter)."
|
|
newline
|
|
bitfld.long 0x0 15. "RUNNING,When '0' the counter is NOT running. When '1' the counter is running." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "LINE_OUT,Indicates the actual level of the PWM line output signal." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TR_START,Indicates the actual level of the selected start trigger." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TR_STOP,Indicates the actual level of the selected stop trigger." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TR_COUNT,Indicates the actual level of the selected count trigger." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DOWN,When '0' counter is counting up. When '1' counter is counting down. In QUAD mode this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented." "0,1"
|
|
group.long ($2+0x8)++0x3
|
|
line.long 0x0 "COUNTER,Counter count register"
|
|
hexmask.long 0x0 0.--31. 1. "COUNTER,16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running."
|
|
group.long ($2+0x10)++0x23
|
|
line.long 0x0 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x0 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
|
|
line.long 0x4 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x4 0.--31. 1. "CC,Additional buffer for counter CC register."
|
|
line.long 0x8 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x8 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
|
|
line.long 0xC "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0xC 0.--31. 1. "CC,Additional buffer for counter CC1 register."
|
|
line.long 0x10 "PERIOD,Counter period register"
|
|
hexmask.long 0x10 0.--31. 1. "PERIOD,Period value: upper value of the counter. When the counter should count for n cycles this field should be set to n-1."
|
|
line.long 0x14 "PERIOD_BUFF,Counter buffered period register"
|
|
hexmask.long 0x14 0.--31. 1. "PERIOD,Additional buffer for counter PERIOD register."
|
|
line.long 0x18 "LINE_SEL,Counter line selection register"
|
|
bitfld.long 0x18 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'. Default setting is the inverted PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
|
|
newline
|
|
bitfld.long 0x18 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'. Default setting is the PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
|
|
line.long 0x1C "LINE_SEL_BUFF,Counter buffered line selection register"
|
|
bitfld.long 0x1C 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x1C 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL." "0,1,2,3,4,5,6,7"
|
|
line.long 0x20 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x20 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain."
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|
newline
|
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hexmask.long.byte 0x20 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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|
newline
|
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hexmask.long.byte 0x20 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
|
|
group.long ($2+0x40)++0x17
|
|
line.long 0x0 "TR_CMD,Counter trigger command register"
|
|
bitfld.long 0x0 5. "CAPTURE1,SW capture 1 trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "START,SW start trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STOP,SW stop trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RELOAD,SW reload trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CAPTURE0,SW capture 0 trigger. When written with '1' a capture 0 trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled.." "0,1"
|
|
line.long 0x4 "TR_IN_SEL0,Counter input trigger selection register 0"
|
|
hexmask.long.byte 0x4 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger."
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger."
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger. Input trigger 0 is always '0' and input trigger 1 is always '1'. If existing the one-to-one trigger inputs 'tr_one_cnt_in' (different to each counter) are selected by.."
|
|
line.long 0x8 "TR_IN_SEL1,Counter input trigger selection register 1"
|
|
hexmask.long.byte 0x8 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger. In QUAD mode this is the second phase (phi B)."
|
|
line.long 0xC "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
|
|
bitfld.long 0xC 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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|
newline
|
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bitfld.long 0xC 8.--9. "START_EDGE,A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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|
newline
|
|
bitfld.long 0xC 6.--7. "STOP_EDGE,A stop event will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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|
newline
|
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bitfld.long 0xC 4.--5. "RELOAD_EDGE,A reload event will initialize the counter. When counting up the counter is initialized to '0'. When counting down the counter is initialized with PERIOD." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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|
newline
|
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bitfld.long 0xC 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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|
newline
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bitfld.long 0xC 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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line.long 0x10 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x10 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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line.long 0x14 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x14 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1. Default setting selects the compare match 0 event." "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
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bitfld.long 0x14 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0. Default setting selects the terminal count event." "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
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group.long ($2+0x70)++0xB
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line.long 0x0 "INTR,Interrupt request register"
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bitfld.long 0x0 2. "CC1_MATCH,Counter matches CC1 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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bitfld.long 0x0 1. "CC0_MATCH,Counter matches CC0 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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bitfld.long 0x0 0. "TC,Terminal count event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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line.long 0x4 "INTR_SET,Interrupt set request register"
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bitfld.long 0x4 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 0. "TC,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x8 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 0. "TC,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long ($2+0x7C)++0x3
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line.long 0x0 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x0 2. "CC1_MATCH,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "CC0_MATCH,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "TC,Logical and of corresponding request and mask bits." "0,1"
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tree.end
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repeat.end
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repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list 0x800 0x880 0x900 0x980 0xA00 0xA80 0xB00 0xB80 0xC00 0xC80 0xD00 0xD80 0xE00 0xE80 0xF00 0xF80)
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tree "CNT[$1]"
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group.long ($2)++0x3
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line.long 0x0 "CTRL,Counter control register"
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bitfld.long 0x0 31. "ENABLED,Counter enable." "0,1"
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bitfld.long 0x0 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode." "0,1"
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bitfld.long 0x0 24.--26. "MODE,Counter mode." "0: Timer mode,1: N/A,2: Capture mode,3: Quadrature mode Different encoding modes can be..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode."
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bitfld.long 0x0 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode." "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode. Input phiA.."
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bitfld.long 0x0 18. "ONE_SHOT,When '0' counter runs continuous. When '1' counter is turned off by hardware when a terminal count event is generated." "0,1"
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bitfld.long 0x0 16.--17. "UP_DOWN_MODE,Determines counter direction." "0: Count up (to PERIOD). An overflow event is..,1: Count down (to '0'). An underflow event is..,2: Count up (to PERIOD) then count down (to '0').,3: Count up (to PERIOD) then count down (to '0')."
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bitfld.long 0x0 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped." "0: The behavior is the same is in previous mxtcpwm..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x0 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior:" "0,1"
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bitfld.long 0x0 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events:" "0,1"
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bitfld.long 0x0 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')." "0,1"
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bitfld.long 0x0 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values. This field has a function in PWM and PWM_PR modes." "0,1"
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bitfld.long 0x0 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM and PWM_DT modes." "0,1"
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bitfld.long 0x0 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
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bitfld.long 0x0 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
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rgroup.long ($2+0x4)++0x3
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line.long 0x0 "STATUS,Counter status register"
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hexmask.long.byte 0x0 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter. In PWM_DT mode this counter is used for dead time insertion."
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hexmask.long.byte 0x0 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field. In PWM_DT mode this counter is used for dead time insertion (8bit dead time counter or low byte of 16-bit dead time counter)."
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bitfld.long 0x0 15. "RUNNING,When '0' the counter is NOT running. When '1' the counter is running." "0,1"
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bitfld.long 0x0 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal." "0,1"
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bitfld.long 0x0 10. "LINE_OUT,Indicates the actual level of the PWM line output signal." "0,1"
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bitfld.long 0x0 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger." "0,1"
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bitfld.long 0x0 8. "TR_START,Indicates the actual level of the selected start trigger." "0,1"
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bitfld.long 0x0 7. "TR_STOP,Indicates the actual level of the selected stop trigger." "0,1"
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bitfld.long 0x0 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger." "0,1"
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bitfld.long 0x0 5. "TR_COUNT,Indicates the actual level of the selected count trigger." "0,1"
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bitfld.long 0x0 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger." "0,1"
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bitfld.long 0x0 0. "DOWN,When '0' counter is counting up. When '1' counter is counting down. In QUAD mode this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented." "0,1"
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group.long ($2+0x8)++0x3
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line.long 0x0 "COUNTER,Counter count register"
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hexmask.long 0x0 0.--31. 1. "COUNTER,16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running."
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group.long ($2+0x10)++0x23
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line.long 0x0 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x0 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
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line.long 0x4 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x4 0.--31. 1. "CC,Additional buffer for counter CC register."
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line.long 0x8 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x8 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
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line.long 0xC "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0xC 0.--31. 1. "CC,Additional buffer for counter CC1 register."
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line.long 0x10 "PERIOD,Counter period register"
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hexmask.long 0x10 0.--31. 1. "PERIOD,Period value: upper value of the counter. When the counter should count for n cycles this field should be set to n-1."
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line.long 0x14 "PERIOD_BUFF,Counter buffered period register"
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hexmask.long 0x14 0.--31. 1. "PERIOD,Additional buffer for counter PERIOD register."
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line.long 0x18 "LINE_SEL,Counter line selection register"
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bitfld.long 0x18 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'. Default setting is the inverted PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
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bitfld.long 0x18 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'. Default setting is the PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
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line.long 0x1C "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x1C 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL." "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL." "0,1,2,3,4,5,6,7"
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line.long 0x20 "DT,Counter PWM dead time register"
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hexmask.long.word 0x20 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain."
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hexmask.long.byte 0x20 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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hexmask.long.byte 0x20 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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group.long ($2+0x40)++0x17
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line.long 0x0 "TR_CMD,Counter trigger command register"
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bitfld.long 0x0 5. "CAPTURE1,SW capture 1 trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 4. "START,SW start trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 3. "STOP,SW stop trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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newline
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bitfld.long 0x0 2. "RELOAD,SW reload trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 0. "CAPTURE0,SW capture 0 trigger. When written with '1' a capture 0 trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled.." "0,1"
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line.long 0x4 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x4 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger."
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hexmask.long.byte 0x4 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger."
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hexmask.long.byte 0x4 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger."
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hexmask.long.byte 0x4 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger. Input trigger 0 is always '0' and input trigger 1 is always '1'. If existing the one-to-one trigger inputs 'tr_one_cnt_in' (different to each counter) are selected by.."
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line.long 0x8 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x8 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger."
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hexmask.long.byte 0x8 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger. In QUAD mode this is the second phase (phi B)."
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line.long 0xC "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0xC 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 8.--9. "START_EDGE,A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 6.--7. "STOP_EDGE,A stop event will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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newline
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bitfld.long 0xC 4.--5. "RELOAD_EDGE,A reload event will initialize the counter. When counting up the counter is initialized to '0'. When counting down the counter is initialized with PERIOD." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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line.long 0x10 "TR_PWM_CTRL,Counter trigger PWM control register"
|
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bitfld.long 0x10 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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newline
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bitfld.long 0x10 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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newline
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bitfld.long 0x10 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
|
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line.long 0x14 "TR_OUT_SEL,Counter output trigger selection register"
|
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bitfld.long 0x14 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1. Default setting selects the compare match 0 event." "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
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bitfld.long 0x14 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0. Default setting selects the terminal count event." "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
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group.long ($2+0x70)++0xB
|
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line.long 0x0 "INTR,Interrupt request register"
|
|
bitfld.long 0x0 2. "CC1_MATCH,Counter matches CC1 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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bitfld.long 0x0 1. "CC0_MATCH,Counter matches CC0 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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newline
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bitfld.long 0x0 0. "TC,Terminal count event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
|
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line.long 0x4 "INTR_SET,Interrupt set request register"
|
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bitfld.long 0x4 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
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bitfld.long 0x4 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
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|
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bitfld.long 0x4 0. "TC,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x8 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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|
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bitfld.long 0x8 0. "TC,Mask bit for corresponding bit in interrupt request register." "0,1"
|
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rgroup.long ($2+0x7C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x0 2. "CC1_MATCH,Logical and of corresponding request and mask bits." "0,1"
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|
newline
|
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bitfld.long 0x0 1. "CC0_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TC,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F)(list 0x1000 0x1080 0x1100 0x1180 0x1200 0x1280 0x1300 0x1380 0x1400 0x1480 0x1500 0x1580 0x1600 0x1680 0x1700 0x1780)
|
|
tree "CNT[$1]"
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTRL,Counter control register"
|
|
bitfld.long 0x0 31. "ENABLED,Counter enable." "0,1"
|
|
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bitfld.long 0x0 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode." "0,1"
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bitfld.long 0x0 24.--26. "MODE,Counter mode." "0: Timer mode,1: N/A,2: Capture mode,3: Quadrature mode Different encoding modes can be..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode."
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bitfld.long 0x0 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode." "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode. Input phiA.."
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bitfld.long 0x0 18. "ONE_SHOT,When '0' counter runs continuous. When '1' counter is turned off by hardware when a terminal count event is generated." "0,1"
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bitfld.long 0x0 16.--17. "UP_DOWN_MODE,Determines counter direction." "0: Count up (to PERIOD). An overflow event is..,1: Count down (to '0'). An underflow event is..,2: Count up (to PERIOD) then count down (to '0').,3: Count up (to PERIOD) then count down (to '0')."
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bitfld.long 0x0 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped." "0: The behavior is the same is in previous mxtcpwm..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x0 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior:" "0,1"
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bitfld.long 0x0 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events:" "0,1"
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bitfld.long 0x0 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')." "0,1"
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bitfld.long 0x0 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values. This field has a function in PWM and PWM_PR modes." "0,1"
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bitfld.long 0x0 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM and PWM_DT modes." "0,1"
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bitfld.long 0x0 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
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bitfld.long 0x0 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
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rgroup.long ($2+0x4)++0x3
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line.long 0x0 "STATUS,Counter status register"
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hexmask.long.byte 0x0 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter. In PWM_DT mode this counter is used for dead time insertion."
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hexmask.long.byte 0x0 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field. In PWM_DT mode this counter is used for dead time insertion (8bit dead time counter or low byte of 16-bit dead time counter)."
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bitfld.long 0x0 15. "RUNNING,When '0' the counter is NOT running. When '1' the counter is running." "0,1"
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bitfld.long 0x0 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal." "0,1"
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bitfld.long 0x0 10. "LINE_OUT,Indicates the actual level of the PWM line output signal." "0,1"
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bitfld.long 0x0 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger." "0,1"
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bitfld.long 0x0 8. "TR_START,Indicates the actual level of the selected start trigger." "0,1"
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bitfld.long 0x0 7. "TR_STOP,Indicates the actual level of the selected stop trigger." "0,1"
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bitfld.long 0x0 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger." "0,1"
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bitfld.long 0x0 5. "TR_COUNT,Indicates the actual level of the selected count trigger." "0,1"
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bitfld.long 0x0 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger." "0,1"
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bitfld.long 0x0 0. "DOWN,When '0' counter is counting up. When '1' counter is counting down. In QUAD mode this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented." "0,1"
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group.long ($2+0x8)++0x3
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line.long 0x0 "COUNTER,Counter count register"
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hexmask.long 0x0 0.--31. 1. "COUNTER,16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running."
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group.long ($2+0x10)++0x23
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line.long 0x0 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x0 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
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line.long 0x4 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x4 0.--31. 1. "CC,Additional buffer for counter CC register."
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line.long 0x8 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x8 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
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line.long 0xC "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0xC 0.--31. 1. "CC,Additional buffer for counter CC1 register."
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line.long 0x10 "PERIOD,Counter period register"
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hexmask.long 0x10 0.--31. 1. "PERIOD,Period value: upper value of the counter. When the counter should count for n cycles this field should be set to n-1."
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line.long 0x14 "PERIOD_BUFF,Counter buffered period register"
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hexmask.long 0x14 0.--31. 1. "PERIOD,Additional buffer for counter PERIOD register."
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line.long 0x18 "LINE_SEL,Counter line selection register"
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bitfld.long 0x18 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'. Default setting is the inverted PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
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bitfld.long 0x18 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'. Default setting is the PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
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line.long 0x1C "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x1C 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL." "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL." "0,1,2,3,4,5,6,7"
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line.long 0x20 "DT,Counter PWM dead time register"
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hexmask.long.word 0x20 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain."
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hexmask.long.byte 0x20 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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hexmask.long.byte 0x20 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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group.long ($2+0x40)++0x17
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line.long 0x0 "TR_CMD,Counter trigger command register"
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bitfld.long 0x0 5. "CAPTURE1,SW capture 1 trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 4. "START,SW start trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 3. "STOP,SW stop trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 2. "RELOAD,SW reload trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 0. "CAPTURE0,SW capture 0 trigger. When written with '1' a capture 0 trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled.." "0,1"
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line.long 0x4 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x4 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger."
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hexmask.long.byte 0x4 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger."
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hexmask.long.byte 0x4 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger."
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hexmask.long.byte 0x4 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger. Input trigger 0 is always '0' and input trigger 1 is always '1'. If existing the one-to-one trigger inputs 'tr_one_cnt_in' (different to each counter) are selected by.."
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line.long 0x8 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x8 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger."
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hexmask.long.byte 0x8 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger. In QUAD mode this is the second phase (phi B)."
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line.long 0xC "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0xC 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 8.--9. "START_EDGE,A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 6.--7. "STOP_EDGE,A stop event will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 4.--5. "RELOAD_EDGE,A reload event will initialize the counter. When counting up the counter is initialized to '0'. When counting down the counter is initialized with PERIOD." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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line.long 0x10 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x10 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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line.long 0x14 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x14 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1. Default setting selects the compare match 0 event." "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
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bitfld.long 0x14 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0. Default setting selects the terminal count event." "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
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group.long ($2+0x70)++0xB
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line.long 0x0 "INTR,Interrupt request register"
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bitfld.long 0x0 2. "CC1_MATCH,Counter matches CC1 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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bitfld.long 0x0 1. "CC0_MATCH,Counter matches CC0 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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bitfld.long 0x0 0. "TC,Terminal count event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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line.long 0x4 "INTR_SET,Interrupt set request register"
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bitfld.long 0x4 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 0. "TC,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x8 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 0. "TC,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long ($2+0x7C)++0x3
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line.long 0x0 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x0 2. "CC1_MATCH,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "CC0_MATCH,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "TC,Logical and of corresponding request and mask bits." "0,1"
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tree.end
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repeat.end
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repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F)(list 0x1800 0x1880 0x1900 0x1980 0x1A00 0x1A80 0x1B00 0x1B80 0x1C00 0x1C80 0x1D00 0x1D80 0x1E00 0x1E80 0x1F00 0x1F80)
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tree "CNT[$1]"
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group.long ($2)++0x3
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line.long 0x0 "CTRL,Counter control register"
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bitfld.long 0x0 31. "ENABLED,Counter enable." "0,1"
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bitfld.long 0x0 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode." "0,1"
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bitfld.long 0x0 24.--26. "MODE,Counter mode." "0: Timer mode,1: N/A,2: Capture mode,3: Quadrature mode Different encoding modes can be..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode."
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bitfld.long 0x0 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode." "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode. Input phiA.."
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bitfld.long 0x0 18. "ONE_SHOT,When '0' counter runs continuous. When '1' counter is turned off by hardware when a terminal count event is generated." "0,1"
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bitfld.long 0x0 16.--17. "UP_DOWN_MODE,Determines counter direction." "0: Count up (to PERIOD). An overflow event is..,1: Count down (to '0'). An underflow event is..,2: Count up (to PERIOD) then count down (to '0').,3: Count up (to PERIOD) then count down (to '0')."
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bitfld.long 0x0 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped." "0: The behavior is the same is in previous mxtcpwm..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x0 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior:" "0,1"
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bitfld.long 0x0 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events:" "0,1"
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bitfld.long 0x0 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')." "0,1"
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bitfld.long 0x0 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values. This field has a function in PWM and PWM_PR modes." "0,1"
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bitfld.long 0x0 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM and PWM_DT modes." "0,1"
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bitfld.long 0x0 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
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bitfld.long 0x0 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
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rgroup.long ($2+0x4)++0x3
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line.long 0x0 "STATUS,Counter status register"
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hexmask.long.byte 0x0 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter. In PWM_DT mode this counter is used for dead time insertion."
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hexmask.long.byte 0x0 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field. In PWM_DT mode this counter is used for dead time insertion (8bit dead time counter or low byte of 16-bit dead time counter)."
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bitfld.long 0x0 15. "RUNNING,When '0' the counter is NOT running. When '1' the counter is running." "0,1"
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bitfld.long 0x0 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal." "0,1"
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bitfld.long 0x0 10. "LINE_OUT,Indicates the actual level of the PWM line output signal." "0,1"
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bitfld.long 0x0 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger." "0,1"
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bitfld.long 0x0 8. "TR_START,Indicates the actual level of the selected start trigger." "0,1"
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bitfld.long 0x0 7. "TR_STOP,Indicates the actual level of the selected stop trigger." "0,1"
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bitfld.long 0x0 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger." "0,1"
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bitfld.long 0x0 5. "TR_COUNT,Indicates the actual level of the selected count trigger." "0,1"
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bitfld.long 0x0 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger." "0,1"
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bitfld.long 0x0 0. "DOWN,When '0' counter is counting up. When '1' counter is counting down. In QUAD mode this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented." "0,1"
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group.long ($2+0x8)++0x3
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line.long 0x0 "COUNTER,Counter count register"
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hexmask.long 0x0 0.--31. 1. "COUNTER,16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running."
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group.long ($2+0x10)++0x23
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line.long 0x0 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x0 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
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line.long 0x4 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x4 0.--31. 1. "CC,Additional buffer for counter CC register."
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line.long 0x8 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x8 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
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line.long 0xC "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0xC 0.--31. 1. "CC,Additional buffer for counter CC1 register."
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line.long 0x10 "PERIOD,Counter period register"
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hexmask.long 0x10 0.--31. 1. "PERIOD,Period value: upper value of the counter. When the counter should count for n cycles this field should be set to n-1."
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line.long 0x14 "PERIOD_BUFF,Counter buffered period register"
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hexmask.long 0x14 0.--31. 1. "PERIOD,Additional buffer for counter PERIOD register."
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line.long 0x18 "LINE_SEL,Counter line selection register"
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bitfld.long 0x18 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'. Default setting is the inverted PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
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bitfld.long 0x18 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'. Default setting is the PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
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line.long 0x1C "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x1C 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL." "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL." "0,1,2,3,4,5,6,7"
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line.long 0x20 "DT,Counter PWM dead time register"
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hexmask.long.word 0x20 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain."
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hexmask.long.byte 0x20 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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hexmask.long.byte 0x20 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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group.long ($2+0x40)++0x17
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line.long 0x0 "TR_CMD,Counter trigger command register"
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bitfld.long 0x0 5. "CAPTURE1,SW capture 1 trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 4. "START,SW start trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 3. "STOP,SW stop trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 2. "RELOAD,SW reload trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 0. "CAPTURE0,SW capture 0 trigger. When written with '1' a capture 0 trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled.." "0,1"
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line.long 0x4 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x4 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger."
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hexmask.long.byte 0x4 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger."
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hexmask.long.byte 0x4 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger."
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hexmask.long.byte 0x4 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger. Input trigger 0 is always '0' and input trigger 1 is always '1'. If existing the one-to-one trigger inputs 'tr_one_cnt_in' (different to each counter) are selected by.."
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line.long 0x8 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x8 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger."
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hexmask.long.byte 0x8 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger. In QUAD mode this is the second phase (phi B)."
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line.long 0xC "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0xC 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 8.--9. "START_EDGE,A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 6.--7. "STOP_EDGE,A stop event will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 4.--5. "RELOAD_EDGE,A reload event will initialize the counter. When counting up the counter is initialized to '0'. When counting down the counter is initialized with PERIOD." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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line.long 0x10 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x10 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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line.long 0x14 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x14 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1. Default setting selects the compare match 0 event." "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
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bitfld.long 0x14 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0. Default setting selects the terminal count event." "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
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group.long ($2+0x70)++0xB
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line.long 0x0 "INTR,Interrupt request register"
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bitfld.long 0x0 2. "CC1_MATCH,Counter matches CC1 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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bitfld.long 0x0 1. "CC0_MATCH,Counter matches CC0 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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bitfld.long 0x0 0. "TC,Terminal count event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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line.long 0x4 "INTR_SET,Interrupt set request register"
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bitfld.long 0x4 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 0. "TC,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x8 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 0. "TC,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long ($2+0x7C)++0x3
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line.long 0x0 "INTR_MASKED,Interrupt masked request register"
|
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bitfld.long 0x0 2. "CC1_MATCH,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "CC0_MATCH,Logical and of corresponding request and mask bits." "0,1"
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|
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bitfld.long 0x0 0. "TC,Logical and of corresponding request and mask bits." "0,1"
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tree.end
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repeat.end
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repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F)(list 0x2000 0x2080 0x2100 0x2180 0x2200 0x2280 0x2300 0x2380 0x2400 0x2480 0x2500 0x2580 0x2600 0x2680 0x2700 0x2780)
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tree "CNT[$1]"
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group.long ($2)++0x3
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line.long 0x0 "CTRL,Counter control register"
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bitfld.long 0x0 31. "ENABLED,Counter enable." "0,1"
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bitfld.long 0x0 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode." "0,1"
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bitfld.long 0x0 24.--26. "MODE,Counter mode." "0: Timer mode,1: N/A,2: Capture mode,3: Quadrature mode Different encoding modes can be..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode."
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bitfld.long 0x0 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode." "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode. Input phiA.."
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bitfld.long 0x0 18. "ONE_SHOT,When '0' counter runs continuous. When '1' counter is turned off by hardware when a terminal count event is generated." "0,1"
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bitfld.long 0x0 16.--17. "UP_DOWN_MODE,Determines counter direction." "0: Count up (to PERIOD). An overflow event is..,1: Count down (to '0'). An underflow event is..,2: Count up (to PERIOD) then count down (to '0').,3: Count up (to PERIOD) then count down (to '0')."
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bitfld.long 0x0 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped." "0: The behavior is the same is in previous mxtcpwm..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x0 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior:" "0,1"
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bitfld.long 0x0 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events:" "0,1"
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bitfld.long 0x0 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')." "0,1"
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bitfld.long 0x0 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values. This field has a function in PWM and PWM_PR modes." "0,1"
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bitfld.long 0x0 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM and PWM_DT modes." "0,1"
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bitfld.long 0x0 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
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bitfld.long 0x0 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
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rgroup.long ($2+0x4)++0x3
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line.long 0x0 "STATUS,Counter status register"
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hexmask.long.byte 0x0 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter. In PWM_DT mode this counter is used for dead time insertion."
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hexmask.long.byte 0x0 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field. In PWM_DT mode this counter is used for dead time insertion (8bit dead time counter or low byte of 16-bit dead time counter)."
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bitfld.long 0x0 15. "RUNNING,When '0' the counter is NOT running. When '1' the counter is running." "0,1"
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|
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bitfld.long 0x0 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal." "0,1"
|
|
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|
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bitfld.long 0x0 10. "LINE_OUT,Indicates the actual level of the PWM line output signal." "0,1"
|
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|
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bitfld.long 0x0 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger." "0,1"
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|
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bitfld.long 0x0 8. "TR_START,Indicates the actual level of the selected start trigger." "0,1"
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bitfld.long 0x0 7. "TR_STOP,Indicates the actual level of the selected stop trigger." "0,1"
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|
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bitfld.long 0x0 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger." "0,1"
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|
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bitfld.long 0x0 5. "TR_COUNT,Indicates the actual level of the selected count trigger." "0,1"
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|
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bitfld.long 0x0 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger." "0,1"
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|
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bitfld.long 0x0 0. "DOWN,When '0' counter is counting up. When '1' counter is counting down. In QUAD mode this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented." "0,1"
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group.long ($2+0x8)++0x3
|
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line.long 0x0 "COUNTER,Counter count register"
|
|
hexmask.long 0x0 0.--31. 1. "COUNTER,16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running."
|
|
group.long ($2+0x10)++0x23
|
|
line.long 0x0 "CC0,Counter compare/capture 0 register"
|
|
hexmask.long 0x0 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
|
|
line.long 0x4 "CC0_BUFF,Counter buffered compare/capture 0 register"
|
|
hexmask.long 0x4 0.--31. 1. "CC,Additional buffer for counter CC register."
|
|
line.long 0x8 "CC1,Counter compare/capture 1 register"
|
|
hexmask.long 0x8 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
|
|
line.long 0xC "CC1_BUFF,Counter buffered compare/capture 1 register"
|
|
hexmask.long 0xC 0.--31. 1. "CC,Additional buffer for counter CC1 register."
|
|
line.long 0x10 "PERIOD,Counter period register"
|
|
hexmask.long 0x10 0.--31. 1. "PERIOD,Period value: upper value of the counter. When the counter should count for n cycles this field should be set to n-1."
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|
line.long 0x14 "PERIOD_BUFF,Counter buffered period register"
|
|
hexmask.long 0x14 0.--31. 1. "PERIOD,Additional buffer for counter PERIOD register."
|
|
line.long 0x18 "LINE_SEL,Counter line selection register"
|
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bitfld.long 0x18 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'. Default setting is the inverted PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
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bitfld.long 0x18 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'. Default setting is the PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
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line.long 0x1C "LINE_SEL_BUFF,Counter buffered line selection register"
|
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bitfld.long 0x1C 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL." "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL." "0,1,2,3,4,5,6,7"
|
|
line.long 0x20 "DT,Counter PWM dead time register"
|
|
hexmask.long.word 0x20 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain."
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hexmask.long.byte 0x20 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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hexmask.long.byte 0x20 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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group.long ($2+0x40)++0x17
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line.long 0x0 "TR_CMD,Counter trigger command register"
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bitfld.long 0x0 5. "CAPTURE1,SW capture 1 trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 4. "START,SW start trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 3. "STOP,SW stop trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 2. "RELOAD,SW reload trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 0. "CAPTURE0,SW capture 0 trigger. When written with '1' a capture 0 trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled.." "0,1"
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line.long 0x4 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x4 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger."
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hexmask.long.byte 0x4 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger."
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hexmask.long.byte 0x4 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger."
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hexmask.long.byte 0x4 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger. Input trigger 0 is always '0' and input trigger 1 is always '1'. If existing the one-to-one trigger inputs 'tr_one_cnt_in' (different to each counter) are selected by.."
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line.long 0x8 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x8 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger."
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hexmask.long.byte 0x8 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger. In QUAD mode this is the second phase (phi B)."
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line.long 0xC "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0xC 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 8.--9. "START_EDGE,A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 6.--7. "STOP_EDGE,A stop event will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 4.--5. "RELOAD_EDGE,A reload event will initialize the counter. When counting up the counter is initialized to '0'. When counting down the counter is initialized with PERIOD." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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line.long 0x10 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x10 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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line.long 0x14 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x14 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1. Default setting selects the compare match 0 event." "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
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bitfld.long 0x14 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0. Default setting selects the terminal count event." "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
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group.long ($2+0x70)++0xB
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line.long 0x0 "INTR,Interrupt request register"
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bitfld.long 0x0 2. "CC1_MATCH,Counter matches CC1 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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bitfld.long 0x0 1. "CC0_MATCH,Counter matches CC0 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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bitfld.long 0x0 0. "TC,Terminal count event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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line.long 0x4 "INTR_SET,Interrupt set request register"
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bitfld.long 0x4 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 0. "TC,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x8 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 0. "TC,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long ($2+0x7C)++0x3
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line.long 0x0 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x0 2. "CC1_MATCH,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "CC0_MATCH,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "TC,Logical and of corresponding request and mask bits." "0,1"
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tree.end
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repeat.end
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repeat 4. (list 0x50 0x51 0x52 0x53)(list 0x2800 0x2880 0x2900 0x2980)
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tree "CNT[$1]"
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group.long ($2)++0x3
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line.long 0x0 "CTRL,Counter control register"
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bitfld.long 0x0 31. "ENABLED,Counter enable." "0,1"
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bitfld.long 0x0 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode." "0,1"
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bitfld.long 0x0 24.--26. "MODE,Counter mode." "0: Timer mode,1: N/A,2: Capture mode,3: Quadrature mode Different encoding modes can be..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode."
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bitfld.long 0x0 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode." "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode. Input phiA.."
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bitfld.long 0x0 18. "ONE_SHOT,When '0' counter runs continuous. When '1' counter is turned off by hardware when a terminal count event is generated." "0,1"
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bitfld.long 0x0 16.--17. "UP_DOWN_MODE,Determines counter direction." "0: Count up (to PERIOD). An overflow event is..,1: Count down (to '0'). An underflow event is..,2: Count up (to PERIOD) then count down (to '0').,3: Count up (to PERIOD) then count down (to '0')."
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bitfld.long 0x0 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped." "0: The behavior is the same is in previous mxtcpwm..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x0 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior:" "0,1"
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bitfld.long 0x0 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events:" "0,1"
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bitfld.long 0x0 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')." "0,1"
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bitfld.long 0x0 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values. This field has a function in PWM and PWM_PR modes." "0,1"
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bitfld.long 0x0 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM and PWM_DT modes." "0,1"
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bitfld.long 0x0 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
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bitfld.long 0x0 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
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rgroup.long ($2+0x4)++0x3
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line.long 0x0 "STATUS,Counter status register"
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hexmask.long.byte 0x0 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter. In PWM_DT mode this counter is used for dead time insertion."
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hexmask.long.byte 0x0 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field. In PWM_DT mode this counter is used for dead time insertion (8bit dead time counter or low byte of 16-bit dead time counter)."
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bitfld.long 0x0 15. "RUNNING,When '0' the counter is NOT running. When '1' the counter is running." "0,1"
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bitfld.long 0x0 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal." "0,1"
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bitfld.long 0x0 10. "LINE_OUT,Indicates the actual level of the PWM line output signal." "0,1"
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bitfld.long 0x0 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger." "0,1"
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bitfld.long 0x0 8. "TR_START,Indicates the actual level of the selected start trigger." "0,1"
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bitfld.long 0x0 7. "TR_STOP,Indicates the actual level of the selected stop trigger." "0,1"
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bitfld.long 0x0 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger." "0,1"
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bitfld.long 0x0 5. "TR_COUNT,Indicates the actual level of the selected count trigger." "0,1"
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bitfld.long 0x0 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger." "0,1"
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bitfld.long 0x0 0. "DOWN,When '0' counter is counting up. When '1' counter is counting down. In QUAD mode this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented." "0,1"
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group.long ($2+0x8)++0x3
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line.long 0x0 "COUNTER,Counter count register"
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hexmask.long 0x0 0.--31. 1. "COUNTER,16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running."
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group.long ($2+0x10)++0x23
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line.long 0x0 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x0 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
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line.long 0x4 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x4 0.--31. 1. "CC,Additional buffer for counter CC register."
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line.long 0x8 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x8 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
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line.long 0xC "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0xC 0.--31. 1. "CC,Additional buffer for counter CC1 register."
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line.long 0x10 "PERIOD,Counter period register"
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hexmask.long 0x10 0.--31. 1. "PERIOD,Period value: upper value of the counter. When the counter should count for n cycles this field should be set to n-1."
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line.long 0x14 "PERIOD_BUFF,Counter buffered period register"
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hexmask.long 0x14 0.--31. 1. "PERIOD,Additional buffer for counter PERIOD register."
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line.long 0x18 "LINE_SEL,Counter line selection register"
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bitfld.long 0x18 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'. Default setting is the inverted PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
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bitfld.long 0x18 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'. Default setting is the PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
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line.long 0x1C "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x1C 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL." "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL." "0,1,2,3,4,5,6,7"
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line.long 0x20 "DT,Counter PWM dead time register"
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hexmask.long.word 0x20 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain."
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hexmask.long.byte 0x20 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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hexmask.long.byte 0x20 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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group.long ($2+0x40)++0x17
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line.long 0x0 "TR_CMD,Counter trigger command register"
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bitfld.long 0x0 5. "CAPTURE1,SW capture 1 trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 4. "START,SW start trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 3. "STOP,SW stop trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 2. "RELOAD,SW reload trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 0. "CAPTURE0,SW capture 0 trigger. When written with '1' a capture 0 trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled.." "0,1"
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line.long 0x4 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x4 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger."
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hexmask.long.byte 0x4 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger."
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hexmask.long.byte 0x4 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger."
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hexmask.long.byte 0x4 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger. Input trigger 0 is always '0' and input trigger 1 is always '1'. If existing the one-to-one trigger inputs 'tr_one_cnt_in' (different to each counter) are selected by.."
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line.long 0x8 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x8 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger."
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hexmask.long.byte 0x8 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger. In QUAD mode this is the second phase (phi B)."
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line.long 0xC "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0xC 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 8.--9. "START_EDGE,A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 6.--7. "STOP_EDGE,A stop event will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 4.--5. "RELOAD_EDGE,A reload event will initialize the counter. When counting up the counter is initialized to '0'. When counting down the counter is initialized with PERIOD." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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line.long 0x10 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x10 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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|
line.long 0x14 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x14 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1. Default setting selects the compare match 0 event." "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
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bitfld.long 0x14 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0. Default setting selects the terminal count event." "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
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group.long ($2+0x70)++0xB
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line.long 0x0 "INTR,Interrupt request register"
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bitfld.long 0x0 2. "CC1_MATCH,Counter matches CC1 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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bitfld.long 0x0 1. "CC0_MATCH,Counter matches CC0 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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bitfld.long 0x0 0. "TC,Terminal count event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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line.long 0x4 "INTR_SET,Interrupt set request register"
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bitfld.long 0x4 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 0. "TC,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x8 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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newline
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bitfld.long 0x8 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 0. "TC,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long ($2+0x7C)++0x3
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line.long 0x0 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x0 2. "CC1_MATCH,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 1. "CC0_MATCH,Logical and of corresponding request and mask bits." "0,1"
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newline
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bitfld.long 0x0 0. "TC,Logical and of corresponding request and mask bits." "0,1"
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tree.end
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repeat.end
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tree.end
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repeat.end
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tree.end
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tree "TCPWM1"
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base ad:0x40580000
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repeat 3. (list 0x0 0x1 0x2)(list ad:0x40580000 ad:0x40588000 ad:0x40590000)
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tree "GRP[$1]"
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base $2
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repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list 0x0 0x80 0x100 0x180 0x200 0x280 0x300 0x380 0x400 0x480 0x500 0x580 0x600 0x680 0x700 0x780)
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tree "CNT[$1]"
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group.long ($2)++0x3
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line.long 0x0 "CTRL,Counter control register"
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bitfld.long 0x0 31. "ENABLED,Counter enable." "0,1"
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bitfld.long 0x0 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode." "0,1"
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bitfld.long 0x0 24.--26. "MODE,Counter mode." "0: Timer mode,1: N/A,2: Capture mode,3: Quadrature mode Different encoding modes can be..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode."
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bitfld.long 0x0 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode." "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode. Input phiA.."
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bitfld.long 0x0 18. "ONE_SHOT,When '0' counter runs continuous. When '1' counter is turned off by hardware when a terminal count event is generated." "0,1"
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bitfld.long 0x0 16.--17. "UP_DOWN_MODE,Determines counter direction." "0: Count up (to PERIOD). An overflow event is..,1: Count down (to '0'). An underflow event is..,2: Count up (to PERIOD) then count down (to '0').,3: Count up (to PERIOD) then count down (to '0')."
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bitfld.long 0x0 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped." "0: The behavior is the same is in previous mxtcpwm..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x0 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior:" "0,1"
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bitfld.long 0x0 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events:" "0,1"
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bitfld.long 0x0 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')." "0,1"
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bitfld.long 0x0 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values. This field has a function in PWM and PWM_PR modes." "0,1"
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newline
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bitfld.long 0x0 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM and PWM_DT modes." "0,1"
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newline
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bitfld.long 0x0 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
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newline
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bitfld.long 0x0 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
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rgroup.long ($2+0x4)++0x3
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line.long 0x0 "STATUS,Counter status register"
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hexmask.long.byte 0x0 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter. In PWM_DT mode this counter is used for dead time insertion."
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hexmask.long.byte 0x0 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field. In PWM_DT mode this counter is used for dead time insertion (8bit dead time counter or low byte of 16-bit dead time counter)."
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bitfld.long 0x0 15. "RUNNING,When '0' the counter is NOT running. When '1' the counter is running." "0,1"
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bitfld.long 0x0 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal." "0,1"
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bitfld.long 0x0 10. "LINE_OUT,Indicates the actual level of the PWM line output signal." "0,1"
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newline
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bitfld.long 0x0 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger." "0,1"
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bitfld.long 0x0 8. "TR_START,Indicates the actual level of the selected start trigger." "0,1"
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|
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bitfld.long 0x0 7. "TR_STOP,Indicates the actual level of the selected stop trigger." "0,1"
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bitfld.long 0x0 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger." "0,1"
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newline
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bitfld.long 0x0 5. "TR_COUNT,Indicates the actual level of the selected count trigger." "0,1"
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bitfld.long 0x0 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger." "0,1"
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newline
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bitfld.long 0x0 0. "DOWN,When '0' counter is counting up. When '1' counter is counting down. In QUAD mode this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented." "0,1"
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group.long ($2+0x8)++0x3
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line.long 0x0 "COUNTER,Counter count register"
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hexmask.long 0x0 0.--31. 1. "COUNTER,16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running."
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group.long ($2+0x10)++0x23
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line.long 0x0 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x0 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
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line.long 0x4 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x4 0.--31. 1. "CC,Additional buffer for counter CC register."
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line.long 0x8 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x8 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
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line.long 0xC "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0xC 0.--31. 1. "CC,Additional buffer for counter CC1 register."
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line.long 0x10 "PERIOD,Counter period register"
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hexmask.long 0x10 0.--31. 1. "PERIOD,Period value: upper value of the counter. When the counter should count for n cycles this field should be set to n-1."
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line.long 0x14 "PERIOD_BUFF,Counter buffered period register"
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hexmask.long 0x14 0.--31. 1. "PERIOD,Additional buffer for counter PERIOD register."
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line.long 0x18 "LINE_SEL,Counter line selection register"
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bitfld.long 0x18 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'. Default setting is the inverted PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
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newline
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bitfld.long 0x18 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'. Default setting is the PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
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line.long 0x1C "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x1C 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL." "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x1C 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL." "0,1,2,3,4,5,6,7"
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line.long 0x20 "DT,Counter PWM dead time register"
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hexmask.long.word 0x20 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain."
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newline
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hexmask.long.byte 0x20 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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newline
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hexmask.long.byte 0x20 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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group.long ($2+0x40)++0x17
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line.long 0x0 "TR_CMD,Counter trigger command register"
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bitfld.long 0x0 5. "CAPTURE1,SW capture 1 trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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newline
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bitfld.long 0x0 4. "START,SW start trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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newline
|
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bitfld.long 0x0 3. "STOP,SW stop trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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newline
|
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bitfld.long 0x0 2. "RELOAD,SW reload trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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newline
|
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bitfld.long 0x0 0. "CAPTURE0,SW capture 0 trigger. When written with '1' a capture 0 trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled.." "0,1"
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line.long 0x4 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x4 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger."
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newline
|
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hexmask.long.byte 0x4 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger."
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newline
|
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hexmask.long.byte 0x4 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger."
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|
newline
|
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hexmask.long.byte 0x4 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger. Input trigger 0 is always '0' and input trigger 1 is always '1'. If existing the one-to-one trigger inputs 'tr_one_cnt_in' (different to each counter) are selected by.."
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line.long 0x8 "TR_IN_SEL1,Counter input trigger selection register 1"
|
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hexmask.long.byte 0x8 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger."
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newline
|
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hexmask.long.byte 0x8 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger. In QUAD mode this is the second phase (phi B)."
|
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line.long 0xC "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0xC 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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newline
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bitfld.long 0xC 8.--9. "START_EDGE,A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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newline
|
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bitfld.long 0xC 6.--7. "STOP_EDGE,A stop event will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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newline
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bitfld.long 0xC 4.--5. "RELOAD_EDGE,A reload event will initialize the counter. When counting up the counter is initialized to '0'. When counting down the counter is initialized with PERIOD." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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newline
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bitfld.long 0xC 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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newline
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bitfld.long 0xC 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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line.long 0x10 "TR_PWM_CTRL,Counter trigger PWM control register"
|
|
bitfld.long 0x10 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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newline
|
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bitfld.long 0x10 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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newline
|
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bitfld.long 0x10 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
|
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newline
|
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bitfld.long 0x10 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
|
|
line.long 0x14 "TR_OUT_SEL,Counter output trigger selection register"
|
|
bitfld.long 0x14 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1. Default setting selects the compare match 0 event." "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
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newline
|
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bitfld.long 0x14 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0. Default setting selects the terminal count event." "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
|
|
group.long ($2+0x70)++0xB
|
|
line.long 0x0 "INTR,Interrupt request register"
|
|
bitfld.long 0x0 2. "CC1_MATCH,Counter matches CC1 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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newline
|
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bitfld.long 0x0 1. "CC0_MATCH,Counter matches CC0 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TC,Terminal count event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x4 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TC,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x8 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
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bitfld.long 0x8 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TC,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long ($2+0x7C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x0 2. "CC1_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC0_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TC,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list 0x800 0x880 0x900 0x980 0xA00 0xA80 0xB00 0xB80 0xC00 0xC80 0xD00 0xD80 0xE00 0xE80 0xF00 0xF80)
|
|
tree "CNT[$1]"
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CTRL,Counter control register"
|
|
bitfld.long 0x0 31. "ENABLED,Counter enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "MODE,Counter mode." "0: Timer mode,1: N/A,2: Capture mode,3: Quadrature mode Different encoding modes can be..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode."
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|
newline
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bitfld.long 0x0 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode." "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode. Input phiA.."
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bitfld.long 0x0 18. "ONE_SHOT,When '0' counter runs continuous. When '1' counter is turned off by hardware when a terminal count event is generated." "0,1"
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bitfld.long 0x0 16.--17. "UP_DOWN_MODE,Determines counter direction." "0: Count up (to PERIOD). An overflow event is..,1: Count down (to '0'). An underflow event is..,2: Count up (to PERIOD) then count down (to '0').,3: Count up (to PERIOD) then count down (to '0')."
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bitfld.long 0x0 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped." "0: The behavior is the same is in previous mxtcpwm..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x0 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior:" "0,1"
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bitfld.long 0x0 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events:" "0,1"
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bitfld.long 0x0 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')." "0,1"
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bitfld.long 0x0 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values. This field has a function in PWM and PWM_PR modes." "0,1"
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bitfld.long 0x0 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM and PWM_DT modes." "0,1"
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bitfld.long 0x0 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
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bitfld.long 0x0 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
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rgroup.long ($2+0x4)++0x3
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line.long 0x0 "STATUS,Counter status register"
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hexmask.long.byte 0x0 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter. In PWM_DT mode this counter is used for dead time insertion."
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hexmask.long.byte 0x0 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field. In PWM_DT mode this counter is used for dead time insertion (8bit dead time counter or low byte of 16-bit dead time counter)."
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bitfld.long 0x0 15. "RUNNING,When '0' the counter is NOT running. When '1' the counter is running." "0,1"
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bitfld.long 0x0 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal." "0,1"
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bitfld.long 0x0 10. "LINE_OUT,Indicates the actual level of the PWM line output signal." "0,1"
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bitfld.long 0x0 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger." "0,1"
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bitfld.long 0x0 8. "TR_START,Indicates the actual level of the selected start trigger." "0,1"
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bitfld.long 0x0 7. "TR_STOP,Indicates the actual level of the selected stop trigger." "0,1"
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bitfld.long 0x0 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger." "0,1"
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bitfld.long 0x0 5. "TR_COUNT,Indicates the actual level of the selected count trigger." "0,1"
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bitfld.long 0x0 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger." "0,1"
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bitfld.long 0x0 0. "DOWN,When '0' counter is counting up. When '1' counter is counting down. In QUAD mode this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented." "0,1"
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group.long ($2+0x8)++0x3
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line.long 0x0 "COUNTER,Counter count register"
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hexmask.long 0x0 0.--31. 1. "COUNTER,16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running."
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group.long ($2+0x10)++0x23
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line.long 0x0 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x0 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
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line.long 0x4 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x4 0.--31. 1. "CC,Additional buffer for counter CC register."
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line.long 0x8 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x8 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
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line.long 0xC "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0xC 0.--31. 1. "CC,Additional buffer for counter CC1 register."
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line.long 0x10 "PERIOD,Counter period register"
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hexmask.long 0x10 0.--31. 1. "PERIOD,Period value: upper value of the counter. When the counter should count for n cycles this field should be set to n-1."
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line.long 0x14 "PERIOD_BUFF,Counter buffered period register"
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hexmask.long 0x14 0.--31. 1. "PERIOD,Additional buffer for counter PERIOD register."
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line.long 0x18 "LINE_SEL,Counter line selection register"
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bitfld.long 0x18 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'. Default setting is the inverted PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
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bitfld.long 0x18 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'. Default setting is the PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
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line.long 0x1C "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x1C 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL." "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL." "0,1,2,3,4,5,6,7"
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line.long 0x20 "DT,Counter PWM dead time register"
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hexmask.long.word 0x20 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain."
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hexmask.long.byte 0x20 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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hexmask.long.byte 0x20 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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group.long ($2+0x40)++0x17
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line.long 0x0 "TR_CMD,Counter trigger command register"
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bitfld.long 0x0 5. "CAPTURE1,SW capture 1 trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 4. "START,SW start trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 3. "STOP,SW stop trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 2. "RELOAD,SW reload trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 0. "CAPTURE0,SW capture 0 trigger. When written with '1' a capture 0 trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled.." "0,1"
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line.long 0x4 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x4 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger."
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hexmask.long.byte 0x4 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger."
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hexmask.long.byte 0x4 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger."
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hexmask.long.byte 0x4 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger. Input trigger 0 is always '0' and input trigger 1 is always '1'. If existing the one-to-one trigger inputs 'tr_one_cnt_in' (different to each counter) are selected by.."
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line.long 0x8 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x8 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger."
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hexmask.long.byte 0x8 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger. In QUAD mode this is the second phase (phi B)."
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line.long 0xC "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0xC 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 8.--9. "START_EDGE,A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 6.--7. "STOP_EDGE,A stop event will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 4.--5. "RELOAD_EDGE,A reload event will initialize the counter. When counting up the counter is initialized to '0'. When counting down the counter is initialized with PERIOD." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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line.long 0x10 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x10 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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line.long 0x14 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x14 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1. Default setting selects the compare match 0 event." "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
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bitfld.long 0x14 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0. Default setting selects the terminal count event." "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
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group.long ($2+0x70)++0xB
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line.long 0x0 "INTR,Interrupt request register"
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bitfld.long 0x0 2. "CC1_MATCH,Counter matches CC1 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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bitfld.long 0x0 1. "CC0_MATCH,Counter matches CC0 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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bitfld.long 0x0 0. "TC,Terminal count event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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line.long 0x4 "INTR_SET,Interrupt set request register"
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bitfld.long 0x4 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 0. "TC,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x8 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 0. "TC,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long ($2+0x7C)++0x3
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line.long 0x0 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x0 2. "CC1_MATCH,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "CC0_MATCH,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "TC,Logical and of corresponding request and mask bits." "0,1"
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tree.end
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repeat.end
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repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F)(list 0x1000 0x1080 0x1100 0x1180 0x1200 0x1280 0x1300 0x1380 0x1400 0x1480 0x1500 0x1580 0x1600 0x1680 0x1700 0x1780)
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tree "CNT[$1]"
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group.long ($2)++0x3
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line.long 0x0 "CTRL,Counter control register"
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bitfld.long 0x0 31. "ENABLED,Counter enable." "0,1"
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bitfld.long 0x0 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode." "0,1"
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bitfld.long 0x0 24.--26. "MODE,Counter mode." "0: Timer mode,1: N/A,2: Capture mode,3: Quadrature mode Different encoding modes can be..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode."
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bitfld.long 0x0 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode." "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode. Input phiA.."
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bitfld.long 0x0 18. "ONE_SHOT,When '0' counter runs continuous. When '1' counter is turned off by hardware when a terminal count event is generated." "0,1"
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bitfld.long 0x0 16.--17. "UP_DOWN_MODE,Determines counter direction." "0: Count up (to PERIOD). An overflow event is..,1: Count down (to '0'). An underflow event is..,2: Count up (to PERIOD) then count down (to '0').,3: Count up (to PERIOD) then count down (to '0')."
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bitfld.long 0x0 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped." "0: The behavior is the same is in previous mxtcpwm..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x0 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior:" "0,1"
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bitfld.long 0x0 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events:" "0,1"
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bitfld.long 0x0 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')." "0,1"
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bitfld.long 0x0 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values. This field has a function in PWM and PWM_PR modes." "0,1"
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bitfld.long 0x0 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM and PWM_DT modes." "0,1"
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bitfld.long 0x0 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
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bitfld.long 0x0 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
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rgroup.long ($2+0x4)++0x3
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line.long 0x0 "STATUS,Counter status register"
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hexmask.long.byte 0x0 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter. In PWM_DT mode this counter is used for dead time insertion."
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hexmask.long.byte 0x0 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field. In PWM_DT mode this counter is used for dead time insertion (8bit dead time counter or low byte of 16-bit dead time counter)."
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bitfld.long 0x0 15. "RUNNING,When '0' the counter is NOT running. When '1' the counter is running." "0,1"
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bitfld.long 0x0 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal." "0,1"
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bitfld.long 0x0 10. "LINE_OUT,Indicates the actual level of the PWM line output signal." "0,1"
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bitfld.long 0x0 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger." "0,1"
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bitfld.long 0x0 8. "TR_START,Indicates the actual level of the selected start trigger." "0,1"
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bitfld.long 0x0 7. "TR_STOP,Indicates the actual level of the selected stop trigger." "0,1"
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bitfld.long 0x0 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger." "0,1"
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bitfld.long 0x0 5. "TR_COUNT,Indicates the actual level of the selected count trigger." "0,1"
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bitfld.long 0x0 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger." "0,1"
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bitfld.long 0x0 0. "DOWN,When '0' counter is counting up. When '1' counter is counting down. In QUAD mode this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented." "0,1"
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group.long ($2+0x8)++0x3
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line.long 0x0 "COUNTER,Counter count register"
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hexmask.long 0x0 0.--31. 1. "COUNTER,16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running."
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group.long ($2+0x10)++0x23
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line.long 0x0 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x0 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
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line.long 0x4 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x4 0.--31. 1. "CC,Additional buffer for counter CC register."
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line.long 0x8 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x8 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
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line.long 0xC "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0xC 0.--31. 1. "CC,Additional buffer for counter CC1 register."
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line.long 0x10 "PERIOD,Counter period register"
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hexmask.long 0x10 0.--31. 1. "PERIOD,Period value: upper value of the counter. When the counter should count for n cycles this field should be set to n-1."
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line.long 0x14 "PERIOD_BUFF,Counter buffered period register"
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hexmask.long 0x14 0.--31. 1. "PERIOD,Additional buffer for counter PERIOD register."
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line.long 0x18 "LINE_SEL,Counter line selection register"
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bitfld.long 0x18 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'. Default setting is the inverted PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
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bitfld.long 0x18 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'. Default setting is the PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
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line.long 0x1C "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x1C 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL." "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL." "0,1,2,3,4,5,6,7"
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line.long 0x20 "DT,Counter PWM dead time register"
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hexmask.long.word 0x20 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain."
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hexmask.long.byte 0x20 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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hexmask.long.byte 0x20 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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group.long ($2+0x40)++0x17
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line.long 0x0 "TR_CMD,Counter trigger command register"
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bitfld.long 0x0 5. "CAPTURE1,SW capture 1 trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 4. "START,SW start trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 3. "STOP,SW stop trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 2. "RELOAD,SW reload trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 0. "CAPTURE0,SW capture 0 trigger. When written with '1' a capture 0 trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled.." "0,1"
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line.long 0x4 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x4 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger."
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hexmask.long.byte 0x4 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger."
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hexmask.long.byte 0x4 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger."
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hexmask.long.byte 0x4 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger. Input trigger 0 is always '0' and input trigger 1 is always '1'. If existing the one-to-one trigger inputs 'tr_one_cnt_in' (different to each counter) are selected by.."
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line.long 0x8 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x8 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger."
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hexmask.long.byte 0x8 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger. In QUAD mode this is the second phase (phi B)."
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line.long 0xC "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0xC 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 8.--9. "START_EDGE,A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 6.--7. "STOP_EDGE,A stop event will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 4.--5. "RELOAD_EDGE,A reload event will initialize the counter. When counting up the counter is initialized to '0'. When counting down the counter is initialized with PERIOD." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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line.long 0x10 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x10 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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line.long 0x14 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x14 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1. Default setting selects the compare match 0 event." "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
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bitfld.long 0x14 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0. Default setting selects the terminal count event." "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
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group.long ($2+0x70)++0xB
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line.long 0x0 "INTR,Interrupt request register"
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bitfld.long 0x0 2. "CC1_MATCH,Counter matches CC1 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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bitfld.long 0x0 1. "CC0_MATCH,Counter matches CC0 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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bitfld.long 0x0 0. "TC,Terminal count event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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line.long 0x4 "INTR_SET,Interrupt set request register"
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bitfld.long 0x4 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 0. "TC,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x8 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 0. "TC,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long ($2+0x7C)++0x3
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line.long 0x0 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x0 2. "CC1_MATCH,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "CC0_MATCH,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "TC,Logical and of corresponding request and mask bits." "0,1"
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tree.end
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repeat.end
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repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F)(list 0x1800 0x1880 0x1900 0x1980 0x1A00 0x1A80 0x1B00 0x1B80 0x1C00 0x1C80 0x1D00 0x1D80 0x1E00 0x1E80 0x1F00 0x1F80)
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tree "CNT[$1]"
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group.long ($2)++0x3
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line.long 0x0 "CTRL,Counter control register"
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bitfld.long 0x0 31. "ENABLED,Counter enable." "0,1"
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bitfld.long 0x0 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode." "0,1"
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bitfld.long 0x0 24.--26. "MODE,Counter mode." "0: Timer mode,1: N/A,2: Capture mode,3: Quadrature mode Different encoding modes can be..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode."
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bitfld.long 0x0 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode." "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode. Input phiA.."
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bitfld.long 0x0 18. "ONE_SHOT,When '0' counter runs continuous. When '1' counter is turned off by hardware when a terminal count event is generated." "0,1"
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bitfld.long 0x0 16.--17. "UP_DOWN_MODE,Determines counter direction." "0: Count up (to PERIOD). An overflow event is..,1: Count down (to '0'). An underflow event is..,2: Count up (to PERIOD) then count down (to '0').,3: Count up (to PERIOD) then count down (to '0')."
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bitfld.long 0x0 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped." "0: The behavior is the same is in previous mxtcpwm..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x0 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior:" "0,1"
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bitfld.long 0x0 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events:" "0,1"
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bitfld.long 0x0 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')." "0,1"
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bitfld.long 0x0 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values. This field has a function in PWM and PWM_PR modes." "0,1"
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bitfld.long 0x0 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM and PWM_DT modes." "0,1"
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bitfld.long 0x0 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
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bitfld.long 0x0 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
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rgroup.long ($2+0x4)++0x3
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line.long 0x0 "STATUS,Counter status register"
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hexmask.long.byte 0x0 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter. In PWM_DT mode this counter is used for dead time insertion."
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hexmask.long.byte 0x0 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field. In PWM_DT mode this counter is used for dead time insertion (8bit dead time counter or low byte of 16-bit dead time counter)."
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bitfld.long 0x0 15. "RUNNING,When '0' the counter is NOT running. When '1' the counter is running." "0,1"
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bitfld.long 0x0 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal." "0,1"
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bitfld.long 0x0 10. "LINE_OUT,Indicates the actual level of the PWM line output signal." "0,1"
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bitfld.long 0x0 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger." "0,1"
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bitfld.long 0x0 8. "TR_START,Indicates the actual level of the selected start trigger." "0,1"
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bitfld.long 0x0 7. "TR_STOP,Indicates the actual level of the selected stop trigger." "0,1"
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bitfld.long 0x0 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger." "0,1"
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bitfld.long 0x0 5. "TR_COUNT,Indicates the actual level of the selected count trigger." "0,1"
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bitfld.long 0x0 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger." "0,1"
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bitfld.long 0x0 0. "DOWN,When '0' counter is counting up. When '1' counter is counting down. In QUAD mode this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented." "0,1"
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group.long ($2+0x8)++0x3
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line.long 0x0 "COUNTER,Counter count register"
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hexmask.long 0x0 0.--31. 1. "COUNTER,16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running."
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group.long ($2+0x10)++0x23
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line.long 0x0 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x0 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
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line.long 0x4 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x4 0.--31. 1. "CC,Additional buffer for counter CC register."
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line.long 0x8 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x8 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
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line.long 0xC "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0xC 0.--31. 1. "CC,Additional buffer for counter CC1 register."
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line.long 0x10 "PERIOD,Counter period register"
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hexmask.long 0x10 0.--31. 1. "PERIOD,Period value: upper value of the counter. When the counter should count for n cycles this field should be set to n-1."
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line.long 0x14 "PERIOD_BUFF,Counter buffered period register"
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hexmask.long 0x14 0.--31. 1. "PERIOD,Additional buffer for counter PERIOD register."
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line.long 0x18 "LINE_SEL,Counter line selection register"
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bitfld.long 0x18 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'. Default setting is the inverted PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
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bitfld.long 0x18 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'. Default setting is the PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
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line.long 0x1C "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x1C 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL." "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL." "0,1,2,3,4,5,6,7"
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line.long 0x20 "DT,Counter PWM dead time register"
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hexmask.long.word 0x20 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain."
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hexmask.long.byte 0x20 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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hexmask.long.byte 0x20 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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group.long ($2+0x40)++0x17
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line.long 0x0 "TR_CMD,Counter trigger command register"
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bitfld.long 0x0 5. "CAPTURE1,SW capture 1 trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 4. "START,SW start trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 3. "STOP,SW stop trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 2. "RELOAD,SW reload trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 0. "CAPTURE0,SW capture 0 trigger. When written with '1' a capture 0 trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled.." "0,1"
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line.long 0x4 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x4 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger."
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hexmask.long.byte 0x4 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger."
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hexmask.long.byte 0x4 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger."
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hexmask.long.byte 0x4 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger. Input trigger 0 is always '0' and input trigger 1 is always '1'. If existing the one-to-one trigger inputs 'tr_one_cnt_in' (different to each counter) are selected by.."
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line.long 0x8 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x8 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger."
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hexmask.long.byte 0x8 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger. In QUAD mode this is the second phase (phi B)."
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line.long 0xC "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0xC 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 8.--9. "START_EDGE,A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 6.--7. "STOP_EDGE,A stop event will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 4.--5. "RELOAD_EDGE,A reload event will initialize the counter. When counting up the counter is initialized to '0'. When counting down the counter is initialized with PERIOD." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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line.long 0x10 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x10 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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line.long 0x14 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x14 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1. Default setting selects the compare match 0 event." "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
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bitfld.long 0x14 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0. Default setting selects the terminal count event." "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
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group.long ($2+0x70)++0xB
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line.long 0x0 "INTR,Interrupt request register"
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bitfld.long 0x0 2. "CC1_MATCH,Counter matches CC1 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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bitfld.long 0x0 1. "CC0_MATCH,Counter matches CC0 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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bitfld.long 0x0 0. "TC,Terminal count event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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line.long 0x4 "INTR_SET,Interrupt set request register"
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bitfld.long 0x4 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 0. "TC,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x8 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 0. "TC,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long ($2+0x7C)++0x3
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line.long 0x0 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x0 2. "CC1_MATCH,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "CC0_MATCH,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "TC,Logical and of corresponding request and mask bits." "0,1"
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tree.end
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repeat.end
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repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F)(list 0x2000 0x2080 0x2100 0x2180 0x2200 0x2280 0x2300 0x2380 0x2400 0x2480 0x2500 0x2580 0x2600 0x2680 0x2700 0x2780)
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tree "CNT[$1]"
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group.long ($2)++0x3
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line.long 0x0 "CTRL,Counter control register"
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bitfld.long 0x0 31. "ENABLED,Counter enable." "0,1"
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bitfld.long 0x0 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode." "0,1"
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bitfld.long 0x0 24.--26. "MODE,Counter mode." "0: Timer mode,1: N/A,2: Capture mode,3: Quadrature mode Different encoding modes can be..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode."
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bitfld.long 0x0 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode." "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode. Input phiA.."
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bitfld.long 0x0 18. "ONE_SHOT,When '0' counter runs continuous. When '1' counter is turned off by hardware when a terminal count event is generated." "0,1"
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bitfld.long 0x0 16.--17. "UP_DOWN_MODE,Determines counter direction." "0: Count up (to PERIOD). An overflow event is..,1: Count down (to '0'). An underflow event is..,2: Count up (to PERIOD) then count down (to '0').,3: Count up (to PERIOD) then count down (to '0')."
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bitfld.long 0x0 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped." "0: The behavior is the same is in previous mxtcpwm..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x0 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior:" "0,1"
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bitfld.long 0x0 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events:" "0,1"
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bitfld.long 0x0 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')." "0,1"
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bitfld.long 0x0 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values. This field has a function in PWM and PWM_PR modes." "0,1"
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bitfld.long 0x0 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM and PWM_DT modes." "0,1"
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bitfld.long 0x0 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
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bitfld.long 0x0 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
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rgroup.long ($2+0x4)++0x3
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line.long 0x0 "STATUS,Counter status register"
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hexmask.long.byte 0x0 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter. In PWM_DT mode this counter is used for dead time insertion."
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hexmask.long.byte 0x0 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field. In PWM_DT mode this counter is used for dead time insertion (8bit dead time counter or low byte of 16-bit dead time counter)."
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bitfld.long 0x0 15. "RUNNING,When '0' the counter is NOT running. When '1' the counter is running." "0,1"
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bitfld.long 0x0 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal." "0,1"
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bitfld.long 0x0 10. "LINE_OUT,Indicates the actual level of the PWM line output signal." "0,1"
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bitfld.long 0x0 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger." "0,1"
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bitfld.long 0x0 8. "TR_START,Indicates the actual level of the selected start trigger." "0,1"
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bitfld.long 0x0 7. "TR_STOP,Indicates the actual level of the selected stop trigger." "0,1"
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bitfld.long 0x0 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger." "0,1"
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bitfld.long 0x0 5. "TR_COUNT,Indicates the actual level of the selected count trigger." "0,1"
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bitfld.long 0x0 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger." "0,1"
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bitfld.long 0x0 0. "DOWN,When '0' counter is counting up. When '1' counter is counting down. In QUAD mode this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented." "0,1"
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group.long ($2+0x8)++0x3
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line.long 0x0 "COUNTER,Counter count register"
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hexmask.long 0x0 0.--31. 1. "COUNTER,16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running."
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group.long ($2+0x10)++0x23
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line.long 0x0 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x0 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
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line.long 0x4 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x4 0.--31. 1. "CC,Additional buffer for counter CC register."
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line.long 0x8 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x8 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
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line.long 0xC "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0xC 0.--31. 1. "CC,Additional buffer for counter CC1 register."
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line.long 0x10 "PERIOD,Counter period register"
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hexmask.long 0x10 0.--31. 1. "PERIOD,Period value: upper value of the counter. When the counter should count for n cycles this field should be set to n-1."
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line.long 0x14 "PERIOD_BUFF,Counter buffered period register"
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hexmask.long 0x14 0.--31. 1. "PERIOD,Additional buffer for counter PERIOD register."
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line.long 0x18 "LINE_SEL,Counter line selection register"
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bitfld.long 0x18 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'. Default setting is the inverted PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
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bitfld.long 0x18 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'. Default setting is the PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
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line.long 0x1C "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x1C 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL." "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL." "0,1,2,3,4,5,6,7"
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line.long 0x20 "DT,Counter PWM dead time register"
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hexmask.long.word 0x20 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain."
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hexmask.long.byte 0x20 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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hexmask.long.byte 0x20 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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group.long ($2+0x40)++0x17
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line.long 0x0 "TR_CMD,Counter trigger command register"
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bitfld.long 0x0 5. "CAPTURE1,SW capture 1 trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 4. "START,SW start trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 3. "STOP,SW stop trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 2. "RELOAD,SW reload trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 0. "CAPTURE0,SW capture 0 trigger. When written with '1' a capture 0 trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled.." "0,1"
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line.long 0x4 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x4 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger."
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hexmask.long.byte 0x4 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger."
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hexmask.long.byte 0x4 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger."
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hexmask.long.byte 0x4 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger. Input trigger 0 is always '0' and input trigger 1 is always '1'. If existing the one-to-one trigger inputs 'tr_one_cnt_in' (different to each counter) are selected by.."
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line.long 0x8 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x8 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger."
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hexmask.long.byte 0x8 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger. In QUAD mode this is the second phase (phi B)."
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line.long 0xC "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0xC 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 8.--9. "START_EDGE,A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 6.--7. "STOP_EDGE,A stop event will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 4.--5. "RELOAD_EDGE,A reload event will initialize the counter. When counting up the counter is initialized to '0'. When counting down the counter is initialized with PERIOD." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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line.long 0x10 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x10 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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line.long 0x14 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x14 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1. Default setting selects the compare match 0 event." "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
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bitfld.long 0x14 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0. Default setting selects the terminal count event." "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
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group.long ($2+0x70)++0xB
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line.long 0x0 "INTR,Interrupt request register"
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bitfld.long 0x0 2. "CC1_MATCH,Counter matches CC1 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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bitfld.long 0x0 1. "CC0_MATCH,Counter matches CC0 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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bitfld.long 0x0 0. "TC,Terminal count event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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line.long 0x4 "INTR_SET,Interrupt set request register"
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bitfld.long 0x4 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 0. "TC,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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line.long 0x8 "INTR_MASK,Interrupt mask register"
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bitfld.long 0x8 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 0. "TC,Mask bit for corresponding bit in interrupt request register." "0,1"
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rgroup.long ($2+0x7C)++0x3
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line.long 0x0 "INTR_MASKED,Interrupt masked request register"
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bitfld.long 0x0 2. "CC1_MATCH,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "CC0_MATCH,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "TC,Logical and of corresponding request and mask bits." "0,1"
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tree.end
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repeat.end
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repeat 4. (list 0x50 0x51 0x52 0x53)(list 0x2800 0x2880 0x2900 0x2980)
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tree "CNT[$1]"
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group.long ($2)++0x3
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line.long 0x0 "CTRL,Counter control register"
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bitfld.long 0x0 31. "ENABLED,Counter enable." "0,1"
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bitfld.long 0x0 30. "DBG_FREEZE_EN,Specifies the counter behavior in debug mode." "0,1"
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bitfld.long 0x0 24.--26. "MODE,Counter mode." "0: Timer mode,1: N/A,2: Capture mode,3: Quadrature mode Different encoding modes can be..,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,7: Shift register mode."
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bitfld.long 0x0 20.--21. "QUAD_ENCODING_MODE,In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode." "0: X1 encoding (QUAD mode) This encoding is..,1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),3: Up / Down rotary counting mode. Input phiA.."
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bitfld.long 0x0 18. "ONE_SHOT,When '0' counter runs continuous. When '1' counter is turned off by hardware when a terminal count event is generated." "0,1"
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bitfld.long 0x0 16.--17. "UP_DOWN_MODE,Determines counter direction." "0: Count up (to PERIOD). An overflow event is..,1: Count down (to '0'). An underflow event is..,2: Count up (to PERIOD) then count down (to '0').,3: Count up (to PERIOD) then count down (to '0')."
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bitfld.long 0x0 12.--13. "PWM_DISABLE_MODE,Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped." "0: The behavior is the same is in previous mxtcpwm..,1: When the counter is disabled the PWM outputs..,2: When the counter is disabled the PWM outputs..,3: When the counter is disabled the PWM outputs.."
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bitfld.long 0x0 10. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior:" "0,1"
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bitfld.long 0x0 9. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events:" "0,1"
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bitfld.long 0x0 8. "PWM_IMM_KILL,Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter')." "0,1"
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bitfld.long 0x0 7. "CC1_MATCH_DOWN_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 6. "CC1_MATCH_UP_EN,Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 5. "CC0_MATCH_DOWN_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 4. "CC0_MATCH_UP_EN,Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode." "0,1"
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bitfld.long 0x0 3. "AUTO_RELOAD_LINE_SEL,Specifies switching of the LINE_SEL and LINE_BUFF_SEL values. This field has a function in PWM and PWM_PR modes." "0,1"
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bitfld.long 0x0 2. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM and PWM_DT modes." "0,1"
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bitfld.long 0x0 1. "AUTO_RELOAD_CC1,Specifies switching of the CC1 and buffered CC1 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
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bitfld.long 0x0 0. "AUTO_RELOAD_CC0,Specifies switching of the CC0 and buffered CC0 values. This field has a function in TIMER QUAD (QUAD_RANGE0_CMP QUAD_RANGE1_CMP range modes) SR PWM PWM_DT and PWM_PR modes." "0: never switch,?"
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rgroup.long ($2+0x4)++0x3
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line.long 0x0 "STATUS,Counter status register"
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hexmask.long.byte 0x0 24.--31. 1. "DT_CNT_H,High byte of 16-bit dead time counter. In PWM_DT mode this counter is used for dead time insertion."
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hexmask.long.byte 0x0 16.--23. 1. "DT_CNT_L,Generic 8-bit counter field. In PWM_DT mode this counter is used for dead time insertion (8bit dead time counter or low byte of 16-bit dead time counter)."
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bitfld.long 0x0 15. "RUNNING,When '0' the counter is NOT running. When '1' the counter is running." "0,1"
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bitfld.long 0x0 11. "LINE_COMPL_OUT,Indicates the actual level of the complementary PWM line output signal." "0,1"
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bitfld.long 0x0 10. "LINE_OUT,Indicates the actual level of the PWM line output signal." "0,1"
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bitfld.long 0x0 9. "TR_CAPTURE1,Indicates the actual level of the selected capture 1 trigger." "0,1"
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bitfld.long 0x0 8. "TR_START,Indicates the actual level of the selected start trigger." "0,1"
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bitfld.long 0x0 7. "TR_STOP,Indicates the actual level of the selected stop trigger." "0,1"
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bitfld.long 0x0 6. "TR_RELOAD,Indicates the actual level of the selected reload trigger." "0,1"
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bitfld.long 0x0 5. "TR_COUNT,Indicates the actual level of the selected count trigger." "0,1"
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bitfld.long 0x0 4. "TR_CAPTURE0,Indicates the actual level of the selected capture 0 trigger." "0,1"
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bitfld.long 0x0 0. "DOWN,When '0' counter is counting up. When '1' counter is counting down. In QUAD mode this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented." "0,1"
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group.long ($2+0x8)++0x3
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line.long 0x0 "COUNTER,Counter count register"
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hexmask.long 0x0 0.--31. 1. "COUNTER,16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running."
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group.long ($2+0x10)++0x23
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line.long 0x0 "CC0,Counter compare/capture 0 register"
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hexmask.long 0x0 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
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line.long 0x4 "CC0_BUFF,Counter buffered compare/capture 0 register"
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hexmask.long 0x4 0.--31. 1. "CC,Additional buffer for counter CC register."
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line.long 0x8 "CC1,Counter compare/capture 1 register"
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hexmask.long 0x8 0.--31. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
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line.long 0xC "CC1_BUFF,Counter buffered compare/capture 1 register"
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hexmask.long 0xC 0.--31. 1. "CC,Additional buffer for counter CC1 register."
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line.long 0x10 "PERIOD,Counter period register"
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hexmask.long 0x10 0.--31. 1. "PERIOD,Period value: upper value of the counter. When the counter should count for n cycles this field should be set to n-1."
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line.long 0x14 "PERIOD_BUFF,Counter buffered period register"
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hexmask.long 0x14 0.--31. 1. "PERIOD,Additional buffer for counter PERIOD register."
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line.long 0x18 "LINE_SEL,Counter line selection register"
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bitfld.long 0x18 4.--6. "COMPL_OUT_SEL,Selects the source for the output signal 'line_compl_out'. Default setting is the inverted PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_compl_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
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bitfld.long 0x18 0.--2. "OUT_SEL,Selects the source for the output signal 'line_out'. Default setting is the PWM signal 'line'. Other settings are useful for Stepper Motor Control." "0: fixed '0',1: fixed '1',2: PWM signal 'line',3: inverted PWM signal 'line',4: The output 'line_out' is not driven by the..,5: N/A,6: N/A,7: N/A"
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line.long 0x1C "LINE_SEL_BUFF,Counter buffered line selection register"
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bitfld.long 0x1C 4.--6. "COMPL_OUT_SEL,Buffer for LINE_SEL.COMPL.OUT_SEL." "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C 0.--2. "OUT_SEL,Buffer for LINE_SEL.OUT_SEL." "0,1,2,3,4,5,6,7"
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line.long 0x20 "DT,Counter PWM dead time register"
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hexmask.long.word 0x20 16.--31. 1. "DT_LINE_COMPL_OUT,In PWM_DT mode this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain."
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hexmask.long.byte 0x20 8.--15. 1. "DT_LINE_OUT_H,In PWM_DT mode this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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hexmask.long.byte 0x20 0.--7. 1. "DT_LINE_OUT_L,In PWM_DT mode this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain."
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group.long ($2+0x40)++0x17
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line.long 0x0 "TR_CMD,Counter trigger command register"
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bitfld.long 0x0 5. "CAPTURE1,SW capture 1 trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 4. "START,SW start trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 3. "STOP,SW stop trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 2. "RELOAD,SW reload trigger. For HW behavior see COUNTER_CAPTURE0 field." "0,1"
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bitfld.long 0x0 0. "CAPTURE0,SW capture 0 trigger. When written with '1' a capture 0 trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled.." "0,1"
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line.long 0x4 "TR_IN_SEL0,Counter input trigger selection register 0"
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hexmask.long.byte 0x4 24.--31. 1. "STOP_SEL,Selects one of the 256 input triggers as a stop trigger."
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hexmask.long.byte 0x4 16.--23. 1. "RELOAD_SEL,Selects one of the 256 input triggers as a reload trigger."
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hexmask.long.byte 0x4 8.--15. 1. "COUNT_SEL,Selects one of the 256 input triggers as a count trigger."
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hexmask.long.byte 0x4 0.--7. 1. "CAPTURE0_SEL,Selects one of the up to 256 input triggers as a capture0 trigger. Input trigger 0 is always '0' and input trigger 1 is always '1'. If existing the one-to-one trigger inputs 'tr_one_cnt_in' (different to each counter) are selected by.."
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line.long 0x8 "TR_IN_SEL1,Counter input trigger selection register 1"
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hexmask.long.byte 0x8 8.--15. 1. "CAPTURE1_SEL,Selects one of the 256 input triggers as a capture 1 trigger."
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hexmask.long.byte 0x8 0.--7. 1. "START_SEL,Selects one of the 256 input triggers as a start trigger. In QUAD mode this is the second phase (phi B)."
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line.long 0xC "TR_IN_EDGE_SEL,Counter input trigger edge selection register"
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bitfld.long 0xC 10.--11. "CAPTURE1_EDGE,A capture 1 event will copy the counter value into the CC1 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 8.--9. "START_EDGE,A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 6.--7. "STOP_EDGE,A stop event will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 4.--5. "RELOAD_EDGE,A reload event will initialize the counter. When counting up the counter is initialized to '0'. When counting down the counter is initialized with PERIOD." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0xC 0.--1. "CAPTURE0_EDGE,A capture 0 event will copy the counter value into the CC0 register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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line.long 0x10 "TR_PWM_CTRL,Counter trigger PWM control register"
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bitfld.long 0x10 6.--7. "CC1_MATCH_MODE,Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x10 0.--1. "CC0_MATCH_MODE,Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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line.long 0x14 "TR_OUT_SEL,Counter output trigger selection register"
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bitfld.long 0x14 4.--6. "OUT1,Selects one of the internal events to generate the output trigger 1. Default setting selects the compare match 0 event." "0: Overflow event,1: Underflow event,2: Terminal count event,3: Compare match 0 event (default selection),4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
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bitfld.long 0x14 0.--2. "OUT0,Selects one of the internal events to generate the output trigger 0. Default setting selects the terminal count event." "0: Overflow event,1: Underflow event,2: Terminal count event (default selection),3: Compare match 0 event,4: Compare match 1 event,5: PWM output signal 'line_out',6: N/A,7: Output trigger disabled."
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group.long ($2+0x70)++0xB
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line.long 0x0 "INTR,Interrupt request register"
|
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bitfld.long 0x0 2. "CC1_MATCH,Counter matches CC1 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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bitfld.long 0x0 1. "CC0_MATCH,Counter matches CC0 register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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bitfld.long 0x0 0. "TC,Terminal count event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
|
|
line.long 0x4 "INTR_SET,Interrupt set request register"
|
|
bitfld.long 0x4 2. "CC1_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
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|
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bitfld.long 0x4 1. "CC0_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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|
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|
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bitfld.long 0x4 0. "TC,Write with '1' to set corresponding bit in interrupt request register." "0,1"
|
|
line.long 0x8 "INTR_MASK,Interrupt mask register"
|
|
bitfld.long 0x8 2. "CC1_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
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|
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|
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bitfld.long 0x8 1. "CC0_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
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|
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bitfld.long 0x8 0. "TC,Mask bit for corresponding bit in interrupt request register." "0,1"
|
|
rgroup.long ($2+0x7C)++0x3
|
|
line.long 0x0 "INTR_MASKED,Interrupt masked request register"
|
|
bitfld.long 0x0 2. "CC1_MATCH,Logical and of corresponding request and mask bits." "0,1"
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|
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|
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bitfld.long 0x0 1. "CC0_MATCH,Logical and of corresponding request and mask bits." "0,1"
|
|
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|
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bitfld.long 0x0 0. "TC,Logical and of corresponding request and mask bits." "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
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tree.end
|
|
AUTOINDENT.OFF
|