6143 lines
430 KiB
Plaintext
6143 lines
430 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: Cortex-M85 On-Chip Peripherals
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; @Props: Released
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; @Author: NEJ, KRZ
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; @Changelog: 2022-01-18 NEJ
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; 2022-11-15 KRZ
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; @Manufacturer: ARM - ARM Ltd.
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; @Doc: arm_olympus_trm_101924_0001_04_en.pdf (Rev. r0p1, 2021-11-15)
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; Olympus_AT640_and_Olympus_with_FPU_AT641_Software_Developer_Errata_Notice_v3.0.pdf (Rev. 3.0, 2021-11-11)
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; DDI0553B_r_armv8m_arm.pdf (Rev. B.r, 2021-12-17)
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; @Core: Cortex-M85
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: percortexm85.per 17410 2024-01-29 13:10:56Z kwisniewski $
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ASSERT VERSION.BUILD.BASE()>=80109.
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sif PER.isNOTIFICATION()
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base AVM:0x00000000
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wgroup AVM:0x00++0
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textline " Peripheral File Notification - "
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button "show missing files" "DIALOG.MESSAGE ""Please check your installation for the possibly missing files:""+CONV.CHAR(0xa)+PER.NOTIFICATION.MISSINGFILES()"
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textline " ---------------------------------------------------------------"
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textline " The peripheral file for this SoC cannot be displayed. "
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textline " Possible reasons are: "
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textline " - it is missing in the local installation or under development "
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textline " - it is confidential "
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textline " "
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textline " As fallback only the core registers are shown. "
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textline " Please check www.lauterbach.com/scripts.html "
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textline " or contact support@lauterbach.com . "
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textline " "
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endif
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x13
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 27. " DISCRITAXIRUW ,Disable critical AXI read under write" "No,Yes"
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bitfld.long 0x00 15. " DISCRITAXIRUR ,Disable critical AXI read-under-read" "No,Yes"
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bitfld.long 0x00 14. " EVENTBUSEN ,Enable EVENTBUS output" "Disabled,Enabled"
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newline
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bitfld.long 0x00 13. " EVENTBUSEN_S ,Enable Secure-only EVENTBUSEN" "Disabled,Enabled"
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bitfld.long 0x00 12. " DISITMATBFLUSH ,Disables ITM and DWT ATB flush" "No,Yes"
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bitfld.long 0x00 11. " DISNWAMODE ,Disable no write allocate mode" "No,Yes"
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newline
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bitfld.long 0x00 10. " FPEXCODIS ,Disables FPU exception outputs" "No,Yes"
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line.long 0x04 "CPPWR,Coprocessor Power Control Register"
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bitfld.long 0x04 23. " SUS11 ,State unknown secure only" "Both states,Secure only"
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bitfld.long 0x04 22. " SU11 ,State UNKNOWN 11" "Not permitted,Permitted"
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bitfld.long 0x04 21. " SUS10 ,State unknown secure only" "Both states,Secure only"
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newline
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bitfld.long 0x04 20. " SU10 ,This bit indicates and allows modification of whether the state associated with the floating point unit is permitted to become UNKNOWN" "Not permitted,Permitted"
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bitfld.long 0x04 15. " SUS7 ,State unknown secure only" "Both states,Secure only"
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bitfld.long 0x04 14. " SU7 ,This bit indicates and allows modification of whether the state associated with the coprocessor 7 is permitted to become UNKNOWN" "Not permitted,Permitted"
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newline
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bitfld.long 0x04 13. " SUS6 ,State unknown secure only" "Both states,Secure only"
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bitfld.long 0x04 12. " SU6 ,This bit indicates and allows modification of whether the state associated with the coprocessor 6 is permitted to become UNKNOWN" "Not permitted,Permitted"
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bitfld.long 0x04 11. " SUS5 ,State unknown secure only" "Both states,Secure only"
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newline
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bitfld.long 0x04 10. " SU5 ,This bit indicates and allows modification of whether the state associated with the coprocessor 5 is permitted to become UNKNOWN" "Not permitted,Permitted"
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bitfld.long 0x04 9. " SUS4 ,State unknown secure only" "Both states,Secure only"
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bitfld.long 0x04 8. " SU4 ,This bit indicates and allows modification of whether the state associated with the coprocessor 4 is permitted to become UNKNOWN" "Not permitted,Permitted"
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newline
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bitfld.long 0x04 7. " SUS3 ,State unknown secure only" "Both states,Secure only"
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bitfld.long 0x04 6. " SU3 ,This bit indicates and allows modification of whether the state associated with the coprocessor 3 is permitted to become UNKNOWN" "Not permitted,Permitted"
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bitfld.long 0x04 5. " SUS2 ,State unknown secure only" "Both states,Secure only"
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newline
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bitfld.long 0x04 4. " SU2 ,This bit indicates and allows modification of whether the state associated with the coprocessor 2 is permitted to become UNKNOWN" "Not permitted,Permitted"
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bitfld.long 0x04 3. " SUS1 ,State unknown secure only" "Both states,Secure only"
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bitfld.long 0x04 2. " SU1 ,This bit indicates and allows modification of whether the state associated with the coprocessor 1 is permitted to become UNKNOWN" "Not permitted,Permitted"
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newline
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bitfld.long 0x04 1. " SUS0 ,State unknown secure only" "Both states,Secure only"
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bitfld.long 0x04 0. " SU0 ,This bit indicates and allows modification of whether the state associated with the coprocessor 0 is permitted to become UNKNOWN" "Not permitted,Permitted"
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line.long 0x08 "SYST_CSR,SysTick Control and Status Register"
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bitfld.long 0x08 16. " COUNTFLAG ,Counter flag" "Not counted,Counted"
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bitfld.long 0x08 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x08 1. " TICKINT ,Tick interrupt" "No SysTick,SysTick"
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newline
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bitfld.long 0x08 0. " ENABLE ,SysTick enable" "Disabled,Enabled"
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line.long 0x0C "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x0C 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x10 "SYST_CVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x10 0.--23. 1. " CURRENT ,Current counter value"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPUID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Indicates implementer"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Olympus r0p1,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8-M w/ Main extension"
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newline
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "Reserved,Olympus r0p1,?..."
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control and State Register"
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setclrfld.long 0x00 31. 0x00 31. 0x00 30. " PENDNMI_SET/CLR ,On writes allows the NMI exception to be set as pending. On reads indicates whether the NMI exception is pending" "Not pending,Pending"
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setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSV_SET/CLR ,On writes allows the PendSV exception for the selected security state to be set as pending on reads indicates whether the PendSV for the selected security state exception is pending" "Not pending,Pending"
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setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDST_SET/CLR ,On writes sets the SysTick exception as pending on reads indicates the current state of the exception" "Not pending,Pending"
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newline
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bitfld.long 0x00 24. " STTNS ,Controls whether in a single SysTick implementation the SysTick is secure or non-secure" "Secure,Non-secure"
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rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
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rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt generated by the NVIC is pending" "Not pending,Pending"
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newline
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rhexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt"
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rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
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rhexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector key"
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rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian"
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bitfld.long 0x08 14. " PRIS ,Prioritize secure exceptions" "Disabled,Enabled"
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newline
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bitfld.long 0x08 13. " BFHFNMINS ,BusFault HardFault and NMI non-secure enable" "Disabled,Enabled"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping group priority field bits/subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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bitfld.long 0x08 5. " IESB ,Implicit ESB enable" "Disabled,Enabled"
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newline
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bitfld.long 0x08 4. " DIT ,Data Independent Timing" "Not guaranteed,Guaranteed"
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bitfld.long 0x08 3. " SYSRESETREQS ,System reset request secure only" "Both states,Secure only"
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bitfld.long 0x08 2. " SYSRESETREQ ,System reset request" "Not requested,Requested"
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newline
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 3. " SLEEPDEEPS ,Controls whether the SLEEPDEEP bit is only accessible from the secure state" "Both states,Secure only"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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newline
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether on an exit from an ISR that returns to the base level of execution priority the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration and Control Register"
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bitfld.long 0x10 20. " TRD ,Thread reentrancy disabled. Enables checking for exception stack frame integrity signatures on SG instructions" "Disabled,Enabled"
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bitfld.long 0x10 19. " LOB ,Loop and branch info cache enable" "Disabled,Enabled"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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newline
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 10. " STKOFHFNMIGN ,Controls the effect of a stack limit violation while executing at a requested priority less than 0" "Not ignored,Ignored"
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newline
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bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise bus faults on handlers running at a requested priority less than 0" "Not ignored,Ignored"
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bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled"
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bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
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newline
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
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line.long 0x14 "SHPR1,System Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of system handler 7 SecureFault"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6 UsageFault"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5 BusFault"
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newline
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4 MemManage"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11 SVCall"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of system handler 15 SysTick"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of system handler 14 PendSV"
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of system handler 12 DebugMonitor"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 21. " HARDFAULTPENDED ,HardFault exception status" "Not pending,Pending"
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bitfld.long 0x20 20. " SECUREFAULTPENDED ,SecureFault exception status" "Not pending,Pending"
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bitfld.long 0x20 19. " SECUREFAULTENA ,SecureFault exception enable" "Disabled,Enabled"
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newline
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bitfld.long 0x20 18. " USGFAULTENA ,UsageFault exception enable" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,BusFault exception enable" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,MemManage exception enable" "Disabled,Enabled"
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newline
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall exception status" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault exception status" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage exception status" "Not pending,Pending"
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newline
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault exception status" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick exception status" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV exception status" "Not active,Active"
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newline
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bitfld.long 0x20 8. " MONITORACT ,Monitor exception status" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall exception status" "Not active,Active"
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bitfld.long 0x20 5. " NMIACT ,NMI exception status" "Not active,Active"
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newline
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bitfld.long 0x20 4. " SECUREFAULTACT ,SecureFault exception status" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault exception status" "Not active,Active"
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bitfld.long 0x20 2. " HARDFAULTACT ,HardFault exception status for the selected security state" "Not active,Active"
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newline
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault exception status" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage exception status" "Not active,Active"
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group.byte 0xD28++0x01
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line.byte 0x00 "MMFSR,MemManage Fault Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address valid flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,Stacking access violations" "Not occurred,Occurred"
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newline
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstacking access violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data access violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction access violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address valid flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault (exception entry)" "Not occurred,Occurred"
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newline
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault (exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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newline
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x01
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line.word 0x00 "UFSR,UsageFault Status Register"
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eventfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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eventfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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eventfld.word 0x00 4. " STKOF ,Stack overflow error" "No error,Error"
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newline
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eventfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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eventfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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eventfld.word 0x00 1. " INVSTATE ,Invalid combination of EPSR and instruction" "No error,Error"
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newline
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eventfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x0F
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line.long 0x00 "HFSR,HardFault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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eventfld.long 0x04 5. " PMU ,PMU event" "Not occurred,Occurred"
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eventfld.long 0x04 4. " EXTERNAL ,Eternal event" "Not occurred,Occurred"
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eventfld.long 0x04 3. " VCATCH ,Vector catch event" "Not occurred,Occurred"
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newline
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eventfld.long 0x04 2. " DWTTRAP ,Watchpoint event" "Not occurred,Occurred"
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eventfld.long 0x04 1. " BKPT ,Breakpoint event" "Not occurred,Occurred"
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eventfld.long 0x04 0. " HALTED ,Halt or step event" "Not occurred,Occurred"
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line.long 0x08 "MMFAR,MemManage Fault Address Register"
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line.long 0x0C "BFAR,BusFault Address Register"
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if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD28))&0x700)==0x700)
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group.long 0xD3C++0x03
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line.long 0x00 "AFSR,Auxiliary Fault Status Register"
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bitfld.long 0x00 30. " FPOISON ,Fetch fault caused by RPOISON or TEBRx.POISON" "Not occurred,Occurred"
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bitfld.long 0x00 29. " FTGU ,Fetch fault caused by TCM gate unit (TGU) security violation" "Not occurred,Occurred"
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bitfld.long 0x00 28. " FECC ,Fetch fault caused by uncorrectable error correcting code (ECC) error" "Not occurred,Occurred"
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newline
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bitfld.long 0x00 27. " FMAXITYPE ,AXI response that caused the fetch fault" "SLVERR,DECERR"
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bitfld.long 0x00 24. " FMAXI ,Fetch fault on master AXI interface" "Not occurred,Occurred"
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bitfld.long 0x00 22. " FDTCM ,Fetch fault on data tightly coupled memory (DTCM) interface" "Not occurred,Occurred"
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newline
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bitfld.long 0x00 21. " FITCM ,Fetch fault on instruction tightly coupled memory (ITCM) interface" "Not occurred,Occurred"
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bitfld.long 0x00 19. " PPOISON ,Precise fault caused by RPOISON or TEBRx.POISON" "Not occurred,Occurred"
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bitfld.long 0x00 18. " PTGU ,Precise fault caused by TGU security violation" "Not occurred,Occurred"
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newline
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bitfld.long 0x00 17. " PECC ,Precise fault caused by uncorrectable ECC error" "Not occurred,Occurred"
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bitfld.long 0x00 16. " PMAXITYPE ,AXI response that caused the precise fault" "SLVERR,DECERR"
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bitfld.long 0x00 15. " PIPPB ,Precise fault on internal private peripheral bus (IPPB) interface" "Not occurred,Occurred"
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newline
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bitfld.long 0x00 14. " PEPPB ,Precise fault on external private peripheral bus (EPPB) interface" "Not occurred,Occurred"
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bitfld.long 0x00 13. " PMAXI ,Precise fault on M-AXI interface" "Not occurred,Occurred"
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bitfld.long 0x00 12. " PPAHB ,Precise fault on peripheral AHB (P-AHB) interface" "Not occurred,Occurred"
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newline
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bitfld.long 0x00 11. " PDTCM ,Precise fault on DTCM interface" "Not occurred,Occurred"
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bitfld.long 0x00 10. " PITCM ,Precise fault on ITCM interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " IPOISON ,Imprecise BusFault because of RPOISON" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 7. " IECC ,Imprecise fault caused by uncorrectable ECC error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " IMAXITYPE ,AXI response that caused the imprecise fault" "SLVERR,DECERR"
|
|
bitfld.long 0x00 4. " IEPPB ,Imprecise fault on EPPB interface" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 3. " IMAXI ,Imprecise fault on M-AXI interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " IPAHB ,Imprecise fault on P-AHB interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " IDTCM ,Imprecise fault on DTCM interface" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 0. " IITCM ,Imprecise fault on ITCM interface" "Not occurred,Occurred"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD28))&0x700)==0x600)
|
|
group.long 0xD3C++0x03
|
|
line.long 0x00 "AFSR,Auxiliary Fault Status Register"
|
|
bitfld.long 0x00 19. " PPOISON ,Precise fault caused by RPOISON or TEBRx.POISON" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " PTGU ,Precise fault caused by TGU security violation" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " PECC ,Precise fault caused by uncorrectable ECC error" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 16. " PMAXITYPE ,AXI response that caused the precise fault" "SLVERR,DECERR"
|
|
bitfld.long 0x00 15. " PIPPB ,Precise fault on internal private peripheral bus (IPPB) interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " PEPPB ,Precise fault on external private peripheral bus (EPPB) interface" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 13. " PMAXI ,Precise fault on M-AXI interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " PPAHB ,Precise fault on peripheral AHB (P-AHB) interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 11. " PDTCM ,Precise fault on DTCM interface" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 10. " PITCM ,Precise fault on ITCM interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " IPOISON ,Imprecise BusFault because of RPOISON" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " IECC ,Imprecise fault caused by uncorrectable ECC error" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 6. " IMAXITYPE ,AXI response that caused the imprecise fault" "SLVERR,DECERR"
|
|
bitfld.long 0x00 4. " IEPPB ,Imprecise fault on EPPB interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " IMAXI ,Imprecise fault on M-AXI interface" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 2. " IPAHB ,Imprecise fault on P-AHB interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " IDTCM ,Imprecise fault on DTCM interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " IITCM ,Imprecise fault on ITCM interface" "Not occurred,Occurred"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD28))&0x700)==0x500)
|
|
group.long 0xD3C++0x03
|
|
line.long 0x00 "AFSR,Auxiliary Fault Status Register"
|
|
bitfld.long 0x00 30. " FPOISON ,Fetch fault caused by RPOISON or TEBRx.POISON" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " FTGU ,Fetch fault caused by TCM gate unit (TGU) security violation" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " FECC ,Fetch fault caused by uncorrectable error correcting code (ECC) error" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 27. " FMAXITYPE ,AXI response that caused the fetch fault" "SLVERR,DECERR"
|
|
bitfld.long 0x00 24. " FMAXI ,Fetch fault on master AXI interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " FDTCM ,Fetch fault on data tightly coupled memory (DTCM) interface" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 21. " FITCM ,Fetch fault on instruction tightly coupled memory (ITCM) interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " IPOISON ,Imprecise BusFault because of RPOISON" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " IECC ,Imprecise fault caused by uncorrectable ECC error" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 6. " IMAXITYPE ,AXI response that caused the imprecise fault" "SLVERR,DECERR"
|
|
bitfld.long 0x00 4. " IEPPB ,Imprecise fault on EPPB interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " IMAXI ,Imprecise fault on M-AXI interface" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 2. " IPAHB ,Imprecise fault on P-AHB interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " IDTCM ,Imprecise fault on DTCM interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " IITCM ,Imprecise fault on ITCM interface" "Not occurred,Occurred"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD28))&0x700)==0x400)
|
|
group.long 0xD3C++0x03
|
|
line.long 0x00 "AFSR,Auxiliary Fault Status Register"
|
|
bitfld.long 0x00 9. " IPOISON ,Imprecise BusFault because of RPOISON" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " IECC ,Imprecise fault caused by uncorrectable ECC error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " IMAXITYPE ,AXI response that caused the imprecise fault" "SLVERR,DECERR"
|
|
newline
|
|
bitfld.long 0x00 4. " IEPPB ,Imprecise fault on EPPB interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " IMAXI ,Imprecise fault on M-AXI interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " IPAHB ,Imprecise fault on P-AHB interface" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 1. " IDTCM ,Imprecise fault on DTCM interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " IITCM ,Imprecise fault on ITCM interface" "Not occurred,Occurred"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD28))&0x700)==0x300)
|
|
group.long 0xD3C++0x03
|
|
line.long 0x00 "AFSR,Auxiliary Fault Status Register"
|
|
bitfld.long 0x00 30. " FPOISON ,Fetch fault caused by RPOISON or TEBRx.POISON" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " FTGU ,Fetch fault caused by TCM gate unit (TGU) security violation" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " FECC ,Fetch fault caused by uncorrectable error correcting code (ECC) error" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 27. " FMAXITYPE ,AXI response that caused the fetch fault" "SLVERR,DECERR"
|
|
bitfld.long 0x00 24. " FMAXI ,Fetch fault on master AXI interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " FDTCM ,Fetch fault on data tightly coupled memory (DTCM) interface" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 21. " FITCM ,Fetch fault on instruction tightly coupled memory (ITCM) interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 19. " PPOISON ,Precise fault caused by RPOISON or TEBRx.POISON" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " PTGU ,Precise fault caused by TGU security violation" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 17. " PECC ,Precise fault caused by uncorrectable ECC error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " PMAXITYPE ,AXI response that caused the precise fault" "SLVERR,DECERR"
|
|
bitfld.long 0x00 15. " PIPPB ,Precise fault on internal private peripheral bus (IPPB) interface" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 14. " PEPPB ,Precise fault on external private peripheral bus (EPPB) interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " PMAXI ,Precise fault on M-AXI interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " PPAHB ,Precise fault on peripheral AHB (P-AHB) interface" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 11. " PDTCM ,Precise fault on DTCM interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " PITCM ,Precise fault on ITCM interface" "Not occurred,Occurred"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD28))&0x700)==0x200)
|
|
group.long 0xD3C++0x03
|
|
line.long 0x00 "AFSR,Auxiliary Fault Status Register"
|
|
bitfld.long 0x00 19. " PPOISON ,Precise fault caused by RPOISON or TEBRx.POISON" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " PTGU ,Precise fault caused by TGU security violation" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " PECC ,Precise fault caused by uncorrectable ECC error" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 16. " PMAXITYPE ,AXI response that caused the precise fault" "SLVERR,DECERR"
|
|
bitfld.long 0x00 15. " PIPPB ,Precise fault on internal private peripheral bus (IPPB) interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " PEPPB ,Precise fault on external private peripheral bus (EPPB) interface" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 13. " PMAXI ,Precise fault on M-AXI interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " PPAHB ,Precise fault on peripheral AHB (P-AHB) interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 11. " PDTCM ,Precise fault on DTCM interface" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 10. " PITCM ,Precise fault on ITCM interface" "Not occurred,Occurred"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD28))&0x700)==0x100)
|
|
group.long 0xD3C++0x03
|
|
line.long 0x00 "AFSR,Auxiliary Fault Status Register"
|
|
bitfld.long 0x00 30. " FPOISON ,Fetch fault caused by RPOISON or TEBRx.POISON" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " FTGU ,Fetch fault caused by TCM gate unit (TGU) security violation" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " FECC ,Fetch fault caused by uncorrectable error correcting code (ECC) error" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 27. " FMAXITYPE ,AXI response that caused the fetch fault" "SLVERR,DECERR"
|
|
bitfld.long 0x00 24. " FMAXI ,Fetch fault on master AXI interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " FDTCM ,Fetch fault on data tightly coupled memory (DTCM) interface" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 21. " FITCM ,Fetch fault on instruction tightly coupled memory (ITCM) interface" "Not occurred,Occurred"
|
|
else
|
|
group.long 0xD3C++0x03
|
|
line.long 0x00 "AFSR,Auxiliary Fault Status Register"
|
|
endif
|
|
group.long 0xD88++0x07
|
|
line.long 0x00 "CPACR,Coprocessor Access Control Register"
|
|
bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Denied,Privileged,Reserved,Full"
|
|
newline
|
|
bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Denied,Privileged,Reserved,Full"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Denied,Privileged,Reserved,Full"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Denied,Privileged,Reserved,Full"
|
|
line.long 0x04 "NSACR,Non-secure Access Control Register"
|
|
bitfld.long 0x04 11. " CP11 ,Enables non-secure access to coprocessor CP11" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " CP10 ,Enables non-secure access to coprocessor CP10" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " CP7 ,Enables non-secure access to coprocessor CP7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 6. " CP6 ,Enables non-secure access to coprocessor CP6" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " CP5 ,Enables non-secure access to coprocessor CP5" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " CP4 ,Enables non-secure access to coprocessor CP4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " CP3 ,Enables non-secure access to coprocessor CP3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CP2 ,Enables non-secure access to coprocessor CP2" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CP1 ,Enables non-secure access to coprocessor CP1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " CP0 ,Enables non-secure access to coprocessor CP0" "Disabled,Enabled"
|
|
wgroup.long 0xF00++0x03
|
|
line.long 0x00 "STIR,Software Triggered Interrupt Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be pended"
|
|
wgroup.long 0x10700++0x03
|
|
line.long 0x00 "CFGINFOSEL,Processor Configuration Information Selection Register"
|
|
rgroup.long 0x10704++0x03
|
|
line.long 0x00 "CFGINFORD,Processor Configuration Information Read Data Register"
|
|
group.long 0x10004++0x03
|
|
line.long 0x00 "PFCR,Prefetcher Control Register"
|
|
bitfld.long 0x00 7. " DIS_NLP ,Disables Next Line Prefetch mode" "No,Yes"
|
|
bitfld.long 0x00 0. " ENABLE ,Prefetcher enable" "Disabled,Enabled"
|
|
width 10.
|
|
tree "Memory System"
|
|
rgroup.long 0xD78++0x03
|
|
line.long 0x00 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 30.--31. " ICB ,Inner cache boundary" "Not disclosed,?..."
|
|
bitfld.long 0x00 27.--29. " LOUU ,Level of unification uniprocessor" "Not implemented,Level 1,?..."
|
|
bitfld.long 0x00 24.--26. " LOC ,Level of coherency" "Not implemented,Level 1,?..."
|
|
newline
|
|
bitfld.long 0x00 21.--23. " LOUIS ,Level of unification inner shareable" "Not implemented,Level 1,?..."
|
|
bitfld.long 0x00 0.--2. " CL1 ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..."
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD7C))&0xE0000000)==0x80000000)
|
|
rgroup.long 0xD7C++0x03
|
|
line.long 0x00 "CTR,Cache Type Register"
|
|
bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,Reserved,Reserved,Reserved,Cache,?..."
|
|
bitfld.long 0x00 24.--27. " CWG ,Cache write-back granule" "No Cache,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,?..."
|
|
bitfld.long 0x00 20.--23. " ERG ,Exclusives reservation granule" "Not provided,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0xD7C++0x03
|
|
line.long 0x00 "CTR,Cache Type Register"
|
|
bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,Reserved,Reserved,Reserved,Cache,?..."
|
|
endif
|
|
rgroup.long 0xD80++0x03
|
|
line.long 0x00 "CCSIDR,Current Cache Size ID Register"
|
|
bitfld.long 0x00 31. " WT ,Indicates support available for write-through" "Reserved,Supported"
|
|
bitfld.long 0x00 30. " WB ,Indicates support available for write-back" "Reserved,Supported"
|
|
bitfld.long 0x00 29. " RA ,Indicates support available for read allocation" "Reserved,Supported"
|
|
newline
|
|
bitfld.long 0x00 28. " WA ,Indicates support available for write allocation" "Reserved,Supported"
|
|
hexmask.long.word 0x00 13.--27. 0x20 " NUMSETS ,Indicates the number of sets as (number of sets) - 1"
|
|
hexmask.long.word 0x00 3.--12. 0x08 " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "Reserved,32 bytes,?..."
|
|
group.long 0xD84++0x03
|
|
line.long 0x00 "CSSELR,Cache Size Selection Register"
|
|
rbitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,?..."
|
|
bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data,Instruction"
|
|
wgroup.long 0xF50++0x03
|
|
line.long 0x00 "ICIALLU,I-Cache Invalidate All To PoU"
|
|
wgroup.long 0xF58++0x1F
|
|
line.long 0x00 "ICIMVAU,I-Cache Invalidate By MVA To PoU"
|
|
line.long 0x04 "DCIMVAC,D-Cache Invalidate By MVA To PoC"
|
|
line.long 0x08 "DCISW,D-Cache Invalidate By Set-Way"
|
|
hexmask.long 0x08 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
|
|
bitfld.long 0x08 1.--3. " LEVEL ,Cache level to operate on minus 1" "L1,L2,L3,L4,L5,L6,L7,L8"
|
|
line.long 0x0C "DCCMVAU,D-Cache Clean By MVA To PoU"
|
|
line.long 0x10 "DCCMVAC,D-Cache Clean By MVA To PoC"
|
|
line.long 0x14 "DCCSW,D-Cache Clean By Set-Way"
|
|
hexmask.long 0x14 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
|
|
bitfld.long 0x14 1.--3. " LEVEL ,Cache level to operate on minus" "L1,L2,L3,L4,L5,L6,L7,L8"
|
|
line.long 0x18 "DCCIMVAC,D-Cache Clean And Invalidate By MVA To PoC"
|
|
line.long 0x1C "DCCISW,D-Cache Clean And Invalidate By Set-Way"
|
|
hexmask.long 0x1C 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
|
|
bitfld.long 0x1C 1.--3. " LEVEL ,Cache level to operate on minus" "L1,L2,L3,L4,L5,L6,L7,L8"
|
|
group.long 0x10010++0x0B
|
|
line.long 0x00 "ITCMCR,Instruction TCM Control Register"
|
|
rbitfld.long 0x00 3.--6. " SZ ,TCM size" "Not implemented,Reserved,Reserved,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB"
|
|
bitfld.long 0x00 0. " EN ,TCM enable" "Disabled,Enabled"
|
|
line.long 0x04 "DTCMCR,Data TCM Control Register"
|
|
rbitfld.long 0x04 3.--6. " SZ ,TCM size" "Not implemented,Reserved,Reserved,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB"
|
|
bitfld.long 0x04 0. " EN ,TCM enable" "Disabled,Enabled"
|
|
line.long 0x08 "PAHBCR,P-AHB Control Register"
|
|
rbitfld.long 0x08 1.--3. " SZ ,P-AHB size" "Disabled,64 MB,128 MB,256 MB,512 MB,?..."
|
|
bitfld.long 0x08 0. " EN ,P-AHB enable" "Disabled,Enabled"
|
|
repeat 2. (increment 0x10100 0x04) (increment 0. 1.)
|
|
group.long $1++0x03
|
|
line.long 0x00 "IEBR$2,Instruction Cache Error Bank Register $2"
|
|
bitfld.long 0x00 30.--31. " SWDEF ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 16. " BANK ,Indicates which RAM bank to use" "Tag,Data"
|
|
bitfld.long 0x00 15. " LOC_WAY ,Indicates the location in instruction cache RAM (way)" "0,1"
|
|
newline
|
|
hexmask.long.word 0x00 5.--14. 0x20 " LOC_INDEX ,Indicates the location in instruction cache RAM (index)"
|
|
bitfld.long 0x00 2.--4. " LOC_OFFSET ,Indicates the location in instruction cache RAM (offset)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
repeat.end
|
|
repeat 2. (increment 0x10110 0x04) (increment 0. 1.)
|
|
group.long $1++0x03
|
|
line.long 0x00 "DEBR$2,Data Cache Error Bank Register $2"
|
|
bitfld.long 0x00 30.--31. " SWDEF ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TYPE ,Indicates the error type" "Single-bit,Multi-bit"
|
|
bitfld.long 0x00 16. " BANK ,Indicates which RAM bank to use" "Tag,Data"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " LOC_WAY ,Indicates the location in instruction cache RAM (way)" "0,1,2,3"
|
|
hexmask.long.word 0x00 5.--13. 0x20 " LOC_INDEX ,Indicates the location in instruction cache RAM (index)"
|
|
bitfld.long 0x00 2.--4. " LOC_OFFSET ,Indicates the location in instruction cache RAM (offset)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
repeat.end
|
|
repeat 2. (increment 0x10120 0x04) (increment 0. 1.)
|
|
group.long $1++0x03
|
|
line.long 0x00 "TEBR$2,TCM Error Bank Register $2"
|
|
bitfld.long 0x00 30.--31. " SWDEF ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 28. " POISON ,Indicates whether a BusFault is generated or not" "Not generated,Generated"
|
|
bitfld.long 0x00 27. " TYPE ,Indicates the error type" "Single-bit,Multi-bit"
|
|
newline
|
|
bitfld.long 0x00 24.--26. " BANK ,Indicates which RAM bank to use" "DTCM0,DTCM1,DTCM2,DTCM3,ITCM,?..."
|
|
hexmask.long.tbyte 0x00 3.--23. 0x08 " LOCATION ,Indicates the location in data cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
repeat.end
|
|
group.long 0x10000++0x03
|
|
line.long 0x00 "MSCR,Memory System Control Register"
|
|
rbitfld.long 0x00 17. " CPWRDN ,Data and instruction caches powered down or automatic invalidation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DCCLEAN ,Data cache contains any dirty lines" "Contained,Not contained"
|
|
bitfld.long 0x00 13. " ICACTIVE ,L1 instruction cache is active" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 12. " DCACTIVE ,L1 data cache is active" "Not active,Active"
|
|
bitfld.long 0x00 3. " EVECCFAULT ,Enables asynchronous BusFault exceptions when data is lost on evictions" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FORCEWT ,Enables forced write-through in the L1 data cache" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 1. " ECCEN ,Indicates whether error correcting code is present and enabled" "Disabled,Enabled"
|
|
newline
|
|
rgroup.long 0x10200++0x07
|
|
line.long 0x00 "DCADCRR,Direct Cache Access Data Cache Read Register"
|
|
bitfld.long 0x00 23.--25. " STATUS ,Clean or dirty transient and outer attributes of the cache line" "Clean/transient/unknown,Clean/not transient/unknown,Dirty/not transient/Non-cacheable,Dirty/Not transient/Non-cacheable/W-back/W-allocate,Dirty/not transient/W-back/no W-allocate,Dirty/not transient/W-through/W-allocate,Dirty/Not transient/W-through/no W-allocate,?..."
|
|
newline
|
|
bitfld.long 0x00 22. " VALID ,Valid state of the data cache line entry" "Not valid,Valid"
|
|
hexmask.long.tbyte 0x00 0.--21. 0x01 " TAG ,Tag address"
|
|
line.long 0x04 "DCAICRR,Direct Cache Access Instruction Cache Read Register"
|
|
bitfld.long 0x04 21. " VALID ,Valid state of the instruction cache line" "Not valid,Valid"
|
|
hexmask.long.tbyte 0x04 0.--20. 0x01 " TAG ,Tag address"
|
|
newline
|
|
group.long 0x10210++0x07
|
|
line.long 0x00 "DCADCLR,Direct Cache Access Location Register"
|
|
rbitfld.long 0x00 30.--31. " WAY ,Cache way" "0,1,2,3"
|
|
rhexmask.long.word 0x00 5.--13. 0x20 " SET ,Set index"
|
|
rbitfld.long 0x00 2.--4. " OFFSET ,Data offset" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 0. " RAMTYPE ,RAM type" "Tag,Data"
|
|
line.long 0x04 "DCAICLR,Direct Cache Access Location Register"
|
|
rbitfld.long 0x04 30. " WAY ,Cache way" "0,1"
|
|
rhexmask.long.word 0x04 5.--14. 0x20 " SET ,Set index"
|
|
rbitfld.long 0x04 2.--4. " OFFSET ,Data offset" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x04 0. " RAMTYPE ,RAM type" "Tag,Data"
|
|
tree.end
|
|
tree "Feature Registers"
|
|
rgroup.long 0xD40++0x37
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " RAS ,Identifies which version of the RAS architecture is implemented" "Reserved,Reserved,Version 1,?..."
|
|
bitfld.long 0x00 4.--7. " STATE1 ,T32 instruction set support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
|
|
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" "Reserved,Reserved,2-stack,?..."
|
|
bitfld.long 0x04 4.--7. " SECURITY ,Security support" "Not implemented,Implemented,Reserved,Implemented with state handling,?..."
|
|
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x08 28.--31. " UDE ,Unprivileged debug extension" "Not implemented,Implemented,?..."
|
|
bitfld.long 0x08 20.--23. " MPROFDBG ,M-profile debug indicates the supported M-profile debug architecture" "Not supported,Reserved,ARMv8-M Debug architecture,?..."
|
|
line.long 0x0C "ID_AFR0,Auxiliary Feature Register 0"
|
|
line.long 0x10 "ID_MMFR0,Memory Model Feature Register 0"
|
|
bitfld.long 0x10 20.--23. " AUXREG ,Indicates the support for auxiliary registers" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " TCM ,Indicates the support for tightly coupled memory (TCM)" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "1 level,2 levels,?..."
|
|
newline
|
|
bitfld.long 0x10 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,HW coherency,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ignored"
|
|
bitfld.long 0x10 4.--7. " PMSASUP ,Indicates support for a PMSA" "Reserved,Reserved,Reserved,Reserved,PMSAv8,?..."
|
|
line.long 0x14 "ID_MMFR1,Memory Model Feature Register 1"
|
|
line.long 0x18 "ID_MMFR2,Memory Model Feature Register 2"
|
|
bitfld.long 0x18 24.--27. " WFISTALL ,Indicates the support for wait for interrupt (WFI) stalling" "Not supported,Supported,?..."
|
|
line.long 0x1C "ID_MMFR3,Memory Model Feature Register 3"
|
|
bitfld.long 0x1C 8.--11. " BPMAINT ,Indicates the supported branch predictor maintenance" "Not supported,Supported,?..."
|
|
bitfld.long 0x1C 4.--7. " CMAINTSW ,Indicates the supported cache maintenance operations by set/way" "Not supported,Supported,?..."
|
|
bitfld.long 0x1C 0.--3. " CMAINTVA ,Indicates the supported cache maintenance operations by virtual-address" "Not supported,Supported,?..."
|
|
line.long 0x20 "ID_ISAR0,Instruction Set Attribute Register 0"
|
|
bitfld.long 0x20 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Reserved,SDIV/UDIV,?..."
|
|
bitfld.long 0x20 20.--23. " DEBUG ,Indicates the supported debug instructions" "Reserved,BKPT,?..."
|
|
bitfld.long 0x20 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,Reserved,Reserved,Reserved,Supported,?..."
|
|
newline
|
|
bitfld.long 0x20 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Reserved,CBNZ/CBZ,Reserved,CBNZ/CBZ with looping,?..."
|
|
bitfld.long 0x20 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Reserved,BFC/BFI/SBFX/UBFX,?..."
|
|
bitfld.long 0x20 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Reserved,CLZ supported,?..."
|
|
line.long 0x24 "ID_ISAR1,Instruction Set Attribute Register 1"
|
|
bitfld.long 0x24 24.--27. " INTERWORK ,Indicates the supported interworking instructions" "Reserved,Reserved,BX/BLX,?..."
|
|
bitfld.long 0x24 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Reserved,ADDW/MOVW/MOVT/SUBW,?..."
|
|
bitfld.long 0x24 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Reserved,IT,?..."
|
|
newline
|
|
bitfld.long 0x24 12.--15. " EXTEND ,Indicates the supported extend instructions" "Reserved,Basic,Extended,?..."
|
|
line.long 0x28 "ID_ISAR2,Instruction Set Attributes Register 2"
|
|
bitfld.long 0x28 28.--31. " REVERSAL ,Indicates the supported reversal instructions" "Reserved,Reserved,REV/REV16/REVSH/RBIT,?..."
|
|
bitfld.long 0x28 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Reserved,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
|
|
bitfld.long 0x28 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Reserved,SMULL/SMLAL,Reserved,SMULL/SMLAL/DSP,?..."
|
|
newline
|
|
bitfld.long 0x28 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Reserved,Reserved,MUL/MLA/MLS,?..."
|
|
bitfld.long 0x28 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
|
|
bitfld.long 0x28 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Reserved,Reserved,Reserved,PLD/PLI,?..."
|
|
newline
|
|
bitfld.long 0x28 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Reserved,Reserved,Load-acquire/Store-release/Exclusive,?..."
|
|
line.long 0x2C "ID_ISAR3,Instruction Set Attributes Register 3"
|
|
bitfld.long 0x2C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Reserved,Supported,?..."
|
|
bitfld.long 0x2C 20.--23. " T32COPY ,Indicates the supported non flag-setting MOV instructions" "Reserved,Supported,?..."
|
|
bitfld.long 0x2C 16.--19. " TABBRANCH ,Indicates the supported table branch instructions" "Reserved,TBB/TBH,?..."
|
|
newline
|
|
bitfld.long 0x2C 12.--15. " SYNCHPRIM ,Indicates the supported table branch instructions" "Reserved,Supported,?..."
|
|
bitfld.long 0x2C 8.--11. " SVC ,Indicates the supported SVC instructions" "Reserved,SVC,?..."
|
|
bitfld.long 0x2C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Reserved,Supported,Reserved,Extended,?..."
|
|
newline
|
|
bitfld.long 0x2C 0.--3. " SATURATE ,Indicates the supported saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB/Q-bit,?..."
|
|
line.long 0x30 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x30 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Reserved,CPS/MRS/MSR,?..."
|
|
bitfld.long 0x30 20.--23. " SYNCHPRIMFRAC ,Indicate the implemented synchronization primitive instructions" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x30 16.--19. " BARRIER ,Indicates the supported barrier instructions" "Reserved,CSDB/DMB/DSB/ISB/PSSBB/SSBB,?..."
|
|
newline
|
|
bitfld.long 0x30 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Reserved,Supported,?..."
|
|
bitfld.long 0x30 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x30 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Reserved,Reserved,Supported,?..."
|
|
line.long 0x34 "ID_ISAR5,Instruction Set Attributes Register 5"
|
|
bitfld.long 0x34 20.--23. " PACBTI ,Pointer authentication algorithm" "Not implemented,QARMA5,Implementation defined,Reserved,QARMA3,?..."
|
|
tree.end
|
|
newline
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DDEVARCH,CoreSight Device Architecture Register"
|
|
hexmask.long.word 0x00 21.--31. 0x20 " ARCHITECT ,Component architect"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Reserved,Present"
|
|
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "M-Profile V3.0,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "Reserved,Reserved,M-Profile V3.0,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
|
rgroup.long 0xFCC++0x03
|
|
line.long 0x00 "DDEVTYPE,SCS Device Type Register"
|
|
bitfld.long 0x00 4.--7. " SUB ,Component sub-type" "Other,?..."
|
|
bitfld.long 0x00 0.--3. " MAJOR ,CoreSight major type" "Miscellaneous,?..."
|
|
rgroup.long 0xCFC++0x03
|
|
line.long 0x00 "REVIDR,Revision ID Register"
|
|
width 8.
|
|
tree "Peripheral Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "DPIDR0,CoreSight Peripheral ID Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PART_NUM[7:0] ,Part number bits[7:0]"
|
|
line.long 0x04 "DPIDR1,CoreSight Peripheral ID Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PART_NUM[11:8] ,Part number bits[11:8]"
|
|
line.long 0x08 "DPIDR2,CoreSight Peripheral ID Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " REVISION ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "DPIDR3,CoreSight Peripheral ID Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " REVAND ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x0F
|
|
line.long 0x00 "DPIDR4,CoreSight Peripheral ID Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " COUNT ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
line.long 0x04 "DPIDR5,CoreSight Peripheral ID Register 5"
|
|
line.long 0x08 "DPIDR6,CoreSight Peripheral ID Register 6"
|
|
line.long 0x0C "DPIDR7,CoreSight Peripheral ID Register 7"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "DCIDR0,CoreSight Component ID Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "DCIDR1,CoreSight Component ID Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component identification preamble"
|
|
line.long 0x08 "DCIDR2,CoreSight Component ID Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0C "DCIDR3,CoreSight Component ID Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 12.
|
|
tree "Reliability, Availability, and Serviceability"
|
|
base (CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))-0x9000)
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ERRFR0,RAS Error Record Feature"
|
|
bitfld.long 0x00 8.--9. " UE ,Enable uncorrected error" "Reserved,Enabled,?..."
|
|
bitfld.long 0x00 0.--1. " ED ,Error reporting and logging" "Reserved,Enabled,?..."
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "ERRCTRL0,RAS Error Record Control Register 0"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ERRSTATUS0,RAS Error Record Primary Status Register"
|
|
eventfld.long 0x00 31. " AV ,Address valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " V ,Status valid" "Not valid,Valid"
|
|
eventfld.long 0x00 29. " UE ,Uncorrected errors" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x00 28. " ER ,BusFault caused by RAS" "Not occurred,Occurred"
|
|
eventfld.long 0x00 27. " OF ,RAS event has occurred since the last time ERRSTATUS0.V was cleared" "At most one,At least two"
|
|
eventfld.long 0x00 26. " MV ,Miscellaneous registers valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " CE ,Corrected errors" "Not detected,Reserved,Detected,?..."
|
|
eventfld.long 0x00 23. " DE ,Deferred errors" "No deferred,Deferred"
|
|
bitfld.long 0x00 20.--21. " UET ,Uncorrectable error type" "UC,Reserved,Reserved,UER"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code"
|
|
rgroup.long 0x18++0x07
|
|
line.long 0x00 "ERRADDR0,RAS Error Record Address Register"
|
|
line.long 0x04 "ERRADDR20,RAS Error Record Address Register"
|
|
bitfld.long 0x04 30. " SI ,Security information incorrect" "Reserved,Not valid"
|
|
bitfld.long 0x04 29. " AI ,Address incorrect" "Valid,Not valid"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "ERRMISC00,RAS Error Record Miscellaneous Register 00"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "ERRMISC10,RAS Error Record Miscellaneous Register 10"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Indicates the type of RAS event logged" "L1 instruction,L1 data,By processor,S-AHB"
|
|
hgroup.long 0x28++0x03
|
|
hide.long 0x00 "ERRMISC20,RAS Error Record Miscellaneous Register 20"
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "ERRMISC30,RAS Error Record Miscellaneous Register 30"
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "ERRMISC40,RAS Error Record Miscellaneous Register 40"
|
|
hgroup.long 0x34++0x03
|
|
hide.long 0x00 "ERRMISC50,RAS Error Record Miscellaneous Register 50"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "ERRMISC60,RAS Error Record Miscellaneous Register 60"
|
|
hgroup.long 0x3C++0x03
|
|
hide.long 0x00 "ERRMISC70,RAS Error Record Miscellaneous Register 70"
|
|
rgroup.long 0xE00++0x03
|
|
line.long 0x00 "ERRGSR0,RAS Fault Group Status Register"
|
|
bitfld.long 0x00 0. " ERR0 ,Error record 0 valid" "Not valid,Valid"
|
|
rgroup.long 0xFC8++0x03
|
|
line.long 0x00 "ERRDEVID,RAS Error Record Device ID Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " NUM ,Maximum error record index+1"
|
|
group.long 0x9F04++0x03
|
|
line.long 0x00 "RFSR,RAS Fault Status Register"
|
|
eventfld.long 0x00 31. " VALID ,Indicates whether the register is valid" "Not valid,Valid"
|
|
bitfld.long 0x00 16.--30. " IS ,Implementation-defined syndrome" "L1 instruction,L1 data,TCM ECC,?..."
|
|
bitfld.long 0x00 0.--1. " UET ,Error type" "Uncontainable,Reserved,Reserved,Recoverable"
|
|
tree.end
|
|
tree "TCM Security Gate"
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
group.long 0x10500++0x07
|
|
line.long 0x00 "ITGU_CTRL,ITGU Control Register"
|
|
bitfld.long 0x00 1. " DEREN ,Enable slave AHB error response for TGU fault" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DBFEN ,Enable data side BusFault for TGU fault" "Disabled,Enabled"
|
|
line.long 0x04 "ITGU_CFG,ITGU Configuration Register"
|
|
bitfld.long 0x04 31. " PRESENT ,This field determines if the TGU is present" "Not present,Present"
|
|
bitfld.long 0x04 8.--11. " NUMBLKS ,Number of TCM blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " BLKSZ ,TGU block size in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 16. (increment 0x10510 0x04) (increment 0. 1.)
|
|
group.long $1++0x03
|
|
line.long 0x00 "ITGU_LUT$2,ITGU Look Up Table Register $2"
|
|
bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
repeat.end
|
|
group.long 0x10500++0x07
|
|
line.long 0x00 "DTGU_CTRL,ITGU Control Register"
|
|
bitfld.long 0x00 1. " DEREN ,Enable slave AHB error response for TGU fault" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DBFEN ,Enable data side BusFault for TGU fault" "Disabled,Enabled"
|
|
line.long 0x04 "DTGU_CFG,ITGU Configuration Register"
|
|
bitfld.long 0x04 31. " PRESENT ,This field determines if the TGU is present" "Not present,Present"
|
|
bitfld.long 0x04 8.--11. " NUMBLKS ,Number of TCM blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " BLKSZ ,TGU block size in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 16. (increment 0x10510 0x04) (increment 0. 1.)
|
|
group.long $1++0x03
|
|
line.long 0x00 "DTGU_LUT$2,ITGU Look Up Table Register $2"
|
|
bitfld.long 0x00 31. " BLK31 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " BLK30 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " BLK29 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 28. " BLK28 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 27. " BLK27 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " BLK26 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 25. " BLK25 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " BLK24 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 23. " BLK23 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 22. " BLK22 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " BLK21 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " BLK20 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 19. " BLK19 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " BLK18 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " BLK17 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 16. " BLK16 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 15. " BLK15 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " BLK14 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 13. " BLK13 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " BLK12 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 11. " BLK11 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 10. " BLK10 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " BLK9 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " BLK8 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 7. " BLK7 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " BLK6 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " BLK5 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 4. " BLK4 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 3. " BLK3 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " BLK2 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 1. " BLK1 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " BLK0 ,Implemented block security mapping bit options" "Secure,Non-secure"
|
|
repeat.end
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 13.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU"
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,?..."
|
|
group.long 0xD94++0x07
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
line.long 0x04 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0x0
|
|
group.long 0xD9C++0x07 "Region 0"
|
|
saveindex 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted"
|
|
line.long 0x04 "MPU_RLAR0,MPU Region Attribute And Size Register 0"
|
|
hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted"
|
|
bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveindex 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveindex 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RLAR0,MPU Region Attribute And Size Register 0"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0x1
|
|
group.long 0xD9C++0x07 "Region 1"
|
|
saveindex 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted"
|
|
line.long 0x04 "MPU_RLAR1,MPU Region Attribute And Size Register 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted"
|
|
bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveindex 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveindex 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RLAR1,MPU Region Attribute And Size Register 1"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0x2
|
|
group.long 0xD9C++0x07 "Region 2"
|
|
saveindex 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted"
|
|
line.long 0x04 "MPU_RLAR2,MPU Region Attribute And Size Register 2"
|
|
hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted"
|
|
bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveindex 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveindex 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RLAR2,MPU Region Attribute And Size Register 2"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0x3
|
|
group.long 0xD9C++0x07 "Region 3"
|
|
saveindex 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted"
|
|
line.long 0x04 "MPU_RLAR3,MPU Region Attribute And Size Register 3"
|
|
hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted"
|
|
bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveindex 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveindex 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RLAR3,MPU Region Attribute And Size Register 3"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0x4
|
|
group.long 0xD9C++0x07 "Region 4"
|
|
saveindex 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted"
|
|
line.long 0x04 "MPU_RLAR4,MPU Region Attribute And Size Register 4"
|
|
hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted"
|
|
bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveindex 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveindex 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RLAR4,MPU Region Attribute And Size Register 4"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0x5
|
|
group.long 0xD9C++0x07 "Region 5"
|
|
saveindex 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted"
|
|
line.long 0x04 "MPU_RLAR5,MPU Region Attribute And Size Register 5"
|
|
hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted"
|
|
bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveindex 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveindex 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RLAR5,MPU Region Attribute And Size Register 5"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0x6
|
|
group.long 0xD9C++0x07 "Region 6"
|
|
saveindex 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted"
|
|
line.long 0x04 "MPU_RLAR6,MPU Region Attribute And Size Register 6"
|
|
hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted"
|
|
bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveindex 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveindex 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RLAR6,MPU Region Attribute And Size Register 6"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0x7
|
|
group.long 0xD9C++0x07 "Region 7"
|
|
saveindex 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted"
|
|
line.long 0x04 "MPU_RLAR7,MPU Region Attribute And Size Register 7"
|
|
hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted"
|
|
bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveindex 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveindex 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RLAR7,MPU Region Attribute And Size Register 7"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0x8
|
|
group.long 0xD9C++0x07 "Region 8"
|
|
saveindex 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted"
|
|
line.long 0x04 "MPU_RLAR8,MPU Region Attribute And Size Register 8"
|
|
hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted"
|
|
bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveindex 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveindex 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RLAR8,MPU Region Attribute And Size Register 8"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0x9
|
|
group.long 0xD9C++0x07 "Region 9"
|
|
saveindex 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted"
|
|
line.long 0x04 "MPU_RLAR9,MPU Region Attribute And Size Register 9"
|
|
hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted"
|
|
bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveindex 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveindex 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RLAR9,MPU Region Attribute And Size Register 9"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0xA
|
|
group.long 0xD9C++0x07 "Region 10"
|
|
saveindex 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted"
|
|
line.long 0x04 "MPU_RLAR10,MPU Region Attribute And Size Register 10"
|
|
hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted"
|
|
bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveindex 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveindex 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RLAR10,MPU Region Attribute And Size Register 10"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0xB
|
|
group.long 0xD9C++0x07 "Region 11"
|
|
saveindex 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted"
|
|
line.long 0x04 "MPU_RLAR11,MPU Region Attribute And Size Register 11"
|
|
hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted"
|
|
bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveindex 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveindex 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RLAR11,MPU Region Attribute And Size Register 11"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0xC
|
|
group.long 0xD9C++0x07 "Region 12"
|
|
saveindex 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted"
|
|
line.long 0x04 "MPU_RLAR12,MPU Region Attribute And Size Register 12"
|
|
hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted"
|
|
bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveindex 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveindex 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RLAR12,MPU Region Attribute And Size Register 12"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0xD
|
|
group.long 0xD9C++0x07 "Region 13"
|
|
saveindex 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted"
|
|
line.long 0x04 "MPU_RLAR13,MPU Region Attribute And Size Register 13"
|
|
hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted"
|
|
bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveindex 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveindex 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RLAR13,MPU Region Attribute And Size Register 13"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0xE
|
|
group.long 0xD9C++0x07 "Region 14"
|
|
saveindex 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted"
|
|
line.long 0x04 "MPU_RLAR14,MPU Region Attribute And Size Register 14"
|
|
hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted"
|
|
bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveindex 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveindex 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RLAR14,MPU Region Attribute And Size Register 14"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xFF00)>>8)>0xF
|
|
group.long 0xD9C++0x07 "Region 15"
|
|
saveindex 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted"
|
|
line.long 0x04 "MPU_RLAR15,MPU Region Attribute And Size Register 15"
|
|
hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted"
|
|
bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveindex 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveindex 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RLAR15,MPU Region Attribute And Size Register 15"
|
|
endif
|
|
tree.end
|
|
newline
|
|
repeat 3. (increment 0xDA4 0x08)(increment 1. 1.)
|
|
group.long $1++0x07
|
|
line.long 0x00 "MPU_RBAR_A$2,MPU Region Base Address Register Alias $2"
|
|
hexmask.long 0x00 5.--31. 0x20 " BASE ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for normal memory" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Permitted,Not Permitted"
|
|
line.long 0x04 "MPU_RLAR_A$2,MPU Region Limit Address Register Alias $2"
|
|
hexmask.long 0x04 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x04 4. " PXN ,Privileged execute never" "Permitted,Not permitted"
|
|
bitfld.long 0x04 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 0. " EN ,Enable" "Disabled,Enabled"
|
|
repeat.end
|
|
newline
|
|
group.long 0xDC0++0x07
|
|
line.long 0x00 "MPU_MAIR0,MPU Memory Attribute Indirection Register 0"
|
|
bitfld.long 0x00 28.--31. " ATTR3H ,Attribute 3 High. Outer memory attributes for MPU regions with an AttrIndex of 3" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x00 24.--27. " ATTR3L ,Attribute 3 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 3 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " ATTR2H ,Attribute 2 High. Outer memory attributes for MPU regions with an AttrIndex of 2" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x00 16.--19. " ATTR2L ,Attribute 2 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 2 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " ATTR1H ,Attribute 1 High. Outer memory attributes for MPU regions with an AttrIndex of 1" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x00 8.--11. " ATTR1L ,Attribute 1 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 1 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " ATTR0H ,Attribute 0 High. Outer memory attributes for MPU regions with an AttrIndex of 0" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x00 0.--3. " ATTR0L ,Attribute 0 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 0 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
line.long 0x04 "MPU_MAIR1,MPU Memory Attribute Indirection Register 1"
|
|
bitfld.long 0x04 28.--31. " ATTR7H ,Attribute 7 High. Outer memory attributes for MPU regions with an AttrIndex of 7" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x04 24.--27. " ATTR7L ,Attribute 7 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 7 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
newline
|
|
bitfld.long 0x04 20.--23. " ATTR6H ,Attribute 6 High. Outer memory attributes for MPU regions with an AttrIndex of 6" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x04 16.--19. " ATTR6L ,Attribute 6 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 6 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
newline
|
|
bitfld.long 0x04 12.--15. " ATTR5H ,Attribute 5 High. Outer memory attributes for MPU regions with an AttrIndex of 5" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x04 8.--11. " ATTR5L ,Attribute 5 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 5 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " ATTR4H ,Attribute 4 High. Outer memory attributes for MPU regions with an AttrIndex of 4" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x04 0.--3. " ATTR4L ,Attribute 4 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 4 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Security Attribution Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 11.
|
|
group.long 0xDD0++0x03
|
|
line.long 0x00 "SAU_CTRL,SAU Control Register"
|
|
bitfld.long 0x00 1. " ALLNS ,When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or secure" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the SAU" "Disabled,Enabled"
|
|
rgroup.long 0xDD4++0x03
|
|
line.long 0x00 "SAU_TYPE,SAU Type Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SREGION ,The number of implemented SAU regions"
|
|
group.long 0xDD8++0x03
|
|
line.long 0x00 "SAU_RNR,SAU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SAU_RNR ,Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR"
|
|
tree "SAU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x0
|
|
group.long 0xDDC++0x07 "Region 0"
|
|
saveindex 0xDD8 %l 0x0
|
|
line.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " BADDR ,Base address of the region"
|
|
line.long 0x04 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
hexmask.long 0x04 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x04 1. " NSC ,Controls whether non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x04 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 0 (not implemented)"
|
|
saveindex 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hgroup.long 0xDE0++0x03
|
|
saveindex 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x1
|
|
group.long 0xDDC++0x07 "Region 1"
|
|
saveindex 0xDD8 %l 0x1
|
|
line.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " BADDR ,Base address of the region"
|
|
line.long 0x04 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x04 1. " NSC ,Controls whether non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x04 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 1 (not implemented)"
|
|
saveindex 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hgroup.long 0xDE0++0x03
|
|
saveindex 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x2
|
|
group.long 0xDDC++0x07 "Region 2"
|
|
saveindex 0xDD8 %l 0x2
|
|
line.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " BADDR ,Base address of the region"
|
|
line.long 0x04 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
hexmask.long 0x04 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x04 1. " NSC ,Controls whether non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x04 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 2 (not implemented)"
|
|
saveindex 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hgroup.long 0xDE0++0x03
|
|
saveindex 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x3
|
|
group.long 0xDDC++0x07 "Region 3"
|
|
saveindex 0xDD8 %l 0x3
|
|
line.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " BADDR ,Base address of the region"
|
|
line.long 0x04 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
hexmask.long 0x04 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x04 1. " NSC ,Controls whether non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x04 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 3 (not implemented)"
|
|
saveindex 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hgroup.long 0xDE0++0x03
|
|
saveindex 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x4
|
|
group.long 0xDDC++0x07 "Region 4"
|
|
saveindex 0xDD8 %l 0x4
|
|
line.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " BADDR ,Base address of the region"
|
|
line.long 0x04 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
hexmask.long 0x04 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x04 1. " NSC ,Controls whether non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x04 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 4 (not implemented)"
|
|
saveindex 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hgroup.long 0xDE0++0x03
|
|
saveindex 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x5
|
|
group.long 0xDDC++0x07 "Region 5"
|
|
saveindex 0xDD8 %l 0x5
|
|
line.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " BADDR ,Base address of the region"
|
|
line.long 0x04 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
hexmask.long 0x04 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x04 1. " NSC ,Controls whether non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x04 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 5 (not implemented)"
|
|
saveindex 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hgroup.long 0xDE0++0x03
|
|
saveindex 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x6
|
|
group.long 0xDDC++0x07 "Region 6"
|
|
saveindex 0xDD8 %l 0x6
|
|
line.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " BADDR ,Base address of the region"
|
|
line.long 0x04 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
hexmask.long 0x04 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x04 1. " NSC ,Controls whether non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x04 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 6 (not implemented)"
|
|
saveindex 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hgroup.long 0xDE0++0x03
|
|
saveindex 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x7
|
|
group.long 0xDDC++0x07 "Region 7"
|
|
saveindex 0xDD8 %l 0x7
|
|
line.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " BADDR ,Base address of the region"
|
|
line.long 0x04 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
hexmask.long 0x04 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x04 1. " NSC ,Controls whether non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x04 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 7 (not implemented)"
|
|
saveindex 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hgroup.long 0xDE0++0x03
|
|
saveindex 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
endif
|
|
tree.end
|
|
newline
|
|
group.long 0xDE4++0x07
|
|
line.long 0x00 "SFSR,Secure Fault Status Register"
|
|
bitfld.long 0x00 7. " LSERR ,Lazy state error flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " SFARVALID ,Secure fault address valid" "Not valid,Valid"
|
|
bitfld.long 0x00 5. " LSPERR ,Lazy state preservation error flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 4. " INVTRAN ,Invalid transition flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " AUVIOL ,Attribution unit violation flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " INVER ,Invalid exception return flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 1. " INVIS ,Invalid integrity signature flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " INVEP ,Invalid entry point" "Not occurred,Occurred"
|
|
line.long 0x04 "SFAR,Secure Fault Address Register"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Control Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total number of interrupt lines in groups of 32" "0-31,0-63,0-95,0-127,0-159,0-191,0-223,0-255,0-287,0-319,0-351,0-383,0-415,0-447,0-479,?..."
|
|
wgroup.long 0x10400++0x03
|
|
line.long 0x00 "EVENTSPR,Event Set Pending Register"
|
|
bitfld.long 0x00 2. " EDBGREQ ,External debug request has occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " NMI ,Non-maskable interrupt has occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " EVENT ,RXEV event has occurred" "Not occurred,Occurred"
|
|
rgroup.long 0x10480++0x03
|
|
line.long 0x00 "EVENTMASKA,Wake-Up Event Mask Register"
|
|
bitfld.long 0x00 2. " EDBGREQ ,Mask for external debug request" "0,1"
|
|
bitfld.long 0x00 1. " NMI ,Mask for non-maskable interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " EVENT ,RXEV event has occurred while WFE sleep" "Not occurred,Occurred"
|
|
repeat 15. (increment 0x10484 0x04) (increment 0. 1.)
|
|
rgroup.long $1++0x03
|
|
line.long 0x00 "EVENTMASK$2,Wake-up Event Mask Register $2"
|
|
repeat.end
|
|
width 24.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA63 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA62 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA61 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA60 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA59 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA58 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA57 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA56 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA55 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA54 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA53 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA52 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA51 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA50 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA49 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA48 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA47 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA46 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA45 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA44 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA43 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA42 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA41 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA40 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA39 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA38 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA37 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA36 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA35 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA34 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA33 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA32 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x104++0x03
|
|
hide.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA95 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA94 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA93 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA92 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA91 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA90 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA89 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA88 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA87 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA86 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA85 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA84 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA83 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA82 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA81 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA80 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA79 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA78 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA77 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA76 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA75 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA74 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA73 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA72 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA71 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA70 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA69 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA68 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA67 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA66 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA65 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA64 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x108++0x03
|
|
hide.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA127 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA126 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA125 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA124 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA123 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA122 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA121 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA120 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA119 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA118 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA117 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA116 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA115 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA114 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA113 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA112 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA111 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA110 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA109 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA108 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA107 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA106 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA105 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA104 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA103 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA102 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA101 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA100 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA99 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA98 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA97 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA96 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x10C++0x03
|
|
hide.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA159 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA158 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA157 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA156 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA155 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA154 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA153 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA152 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA151 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA150 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA149 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA148 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA147 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA146 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA145 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA144 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA143 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA142 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA141 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA140 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA139 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA138 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA137 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA136 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA135 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA134 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA133 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA132 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA131 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA130 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA129 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA128 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x110++0x03
|
|
hide.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA191 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA190 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA189 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA188 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA187 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA186 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA185 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA184 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA183 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA182 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA181 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA180 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA179 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA178 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA177 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA176 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA175 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA174 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA173 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA172 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA171 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA170 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA169 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA168 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA167 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA166 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA165 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA164 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA163 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA162 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA161 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA160 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x114++0x03
|
|
hide.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA223 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA222 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA221 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA220 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA219 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA218 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA217 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA216 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA215 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA214 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA213 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA212 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA211 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA210 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA209 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA208 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA207 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA206 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA205 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA204 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA203 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA202 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA201 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA200 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA199 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA198 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA197 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA196 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA195 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA194 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA193 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA192 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x118++0x03
|
|
hide.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA255 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA254 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA253 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA252 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA251 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA250 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA249 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA248 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA247 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA246 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA245 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA244 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA243 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA242 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA241 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA240 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA239 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA238 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA237 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA236 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA235 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA234 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA233 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA232 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA231 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA230 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA229 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA228 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA227 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA226 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA225 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA224 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x11C++0x03
|
|
hide.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA287 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA286 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA285 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA284 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA283 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA282 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA281 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA280 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA279 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA278 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA277 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA276 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA275 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA274 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA273 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA272 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA271 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA270 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA269 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA268 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA267 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA266 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA265 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA264 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA263 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA262 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA261 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA260 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA259 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA258 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA257 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA256 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x120++0x03
|
|
hide.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA319 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA318 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA317 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA316 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA315 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA314 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA313 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA312 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA311 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA310 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA309 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA308 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA307 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA306 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA305 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA304 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA303 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA302 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA301 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA300 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA299 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA298 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA297 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA296 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA295 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA294 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA293 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA292 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA291 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA290 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA289 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA288 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x124++0x03
|
|
hide.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA351 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA350 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA349 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA348 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA347 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA346 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA345 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA344 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA343 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA342 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA341 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA340 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA339 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA338 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA337 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA336 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA335 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA334 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA333 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA332 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA331 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA330 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA329 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA328 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA327 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA326 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA325 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA324 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA323 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA322 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA321 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA320 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x128++0x03
|
|
hide.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA383 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA382 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA381 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA380 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA379 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA378 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA377 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA376 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA375 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA374 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA373 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA372 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA371 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA370 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA369 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA368 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA367 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA366 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA365 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA364 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA363 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA362 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA361 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA360 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA359 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA358 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA357 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA356 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA355 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA354 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA353 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA352 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x12C++0x03
|
|
hide.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA415 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA414 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA413 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA412 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA411 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA410 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA409 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA408 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA407 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA406 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA405 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA404 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA403 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA402 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA401 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA400 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA399 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA398 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA397 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA396 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA395 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA394 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA393 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA392 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA391 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA390 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA389 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA388 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA387 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA386 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA385 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA384 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x130++0x03
|
|
hide.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA447 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA446 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA445 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA444 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA443 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA442 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA441 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA440 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA439 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA438 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA437 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA436 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA435 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA434 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA433 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA432 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA431 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA430 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA429 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA428 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA427 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA426 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA425 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA424 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA423 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA422 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA421 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA420 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA419 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA418 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA417 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA416 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x134++0x03
|
|
hide.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA479 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA478 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA477 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA476 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA475 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA474 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA473 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA472 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA471 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA470 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA469 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA468 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA467 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA466 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA465 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA464 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA463 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA462 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA461 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA460 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA459 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA458 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA457 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA456 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA455 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA454 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA453 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA452 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA451 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA450 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA449 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA448 ,Interrupt set/clear enable bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x138++0x03
|
|
hide.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
width 24.
|
|
tree "Interrupt Pending Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN63 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN62 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN61 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN60 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN59 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN58 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN57 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN56 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN55 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN54 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN53 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN52 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN51 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN50 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN49 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN48 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN47 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN46 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN45 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN44 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN43 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN42 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN41 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN40 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN39 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN38 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN37 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN36 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN35 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN34 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN33 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN32 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x204++0x03
|
|
hide.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN95 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN94 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN93 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN92 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN91 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN90 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN89 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN88 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN87 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN86 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN85 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN84 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN83 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN82 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN81 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN80 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN79 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN78 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN77 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN76 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN75 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN74 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN73 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN72 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN71 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN70 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN69 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN68 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN67 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN66 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN65 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN64 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x208++0x03
|
|
hide.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN127 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN126 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN125 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN124 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN123 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN122 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN121 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN120 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN119 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN118 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN117 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN116 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN115 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN114 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN113 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN112 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN111 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN110 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN109 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN108 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN107 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN106 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN105 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN104 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN103 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN102 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN101 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN100 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN99 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN98 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN97 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN96 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x20C++0x03
|
|
hide.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN159 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN158 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN157 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN156 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN155 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN154 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN153 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN152 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN151 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN150 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN149 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN148 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN147 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN146 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN145 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN144 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN143 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN142 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN141 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN140 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN139 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN138 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN137 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN136 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN135 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN134 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN133 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN132 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN131 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN130 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN129 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN128 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x210++0x03
|
|
hide.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN191 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN190 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN189 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN188 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN187 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN186 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN185 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN184 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN183 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN182 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN181 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN180 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN179 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN178 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN177 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN176 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN175 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN174 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN173 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN172 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN171 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN170 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN169 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN168 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN167 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN166 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN165 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN164 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN163 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN162 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN161 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN160 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x214++0x03
|
|
hide.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN223 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN222 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN221 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN220 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN219 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN218 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN217 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN216 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN215 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN214 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN213 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN212 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN211 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN210 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN209 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN208 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN207 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN206 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN205 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN204 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN203 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN202 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN201 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN200 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN199 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN198 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN197 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN196 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN195 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN194 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN193 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN192 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x218++0x03
|
|
hide.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN255 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN254 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN253 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN252 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN251 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN250 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN249 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN248 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN247 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN246 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN245 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN244 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN243 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN242 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN241 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN240 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN239 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN238 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN237 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN236 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN235 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN234 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN233 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN232 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN231 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN230 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN229 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN228 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN227 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN226 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN225 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN224 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x21C++0x03
|
|
hide.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN287 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN286 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN285 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN284 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN283 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN282 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN281 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN280 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN279 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN278 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN277 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN276 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN275 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN274 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN273 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN272 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN271 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN270 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN269 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN268 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN267 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN266 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN265 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN264 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN263 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN262 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN261 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN260 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN259 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN258 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN257 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN256 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x220++0x03
|
|
hide.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN319 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN318 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN317 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN316 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN315 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN314 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN313 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN312 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN311 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN310 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN309 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN308 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN307 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN306 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN305 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN304 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN303 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN302 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN301 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN300 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN299 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN298 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN297 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN296 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN295 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN294 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN293 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN292 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN291 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN290 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN289 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN288 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x224++0x03
|
|
hide.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN351 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN350 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN349 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN348 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN347 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN346 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN345 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN344 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN343 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN342 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN341 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN340 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN339 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN338 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN337 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN336 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN335 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN334 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN333 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN332 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN331 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN330 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN329 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN328 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN327 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN326 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN325 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN324 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN323 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN322 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN321 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN320 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x228++0x03
|
|
hide.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN383 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN382 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN381 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN380 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN379 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN378 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN377 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN376 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN375 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN374 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN373 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN372 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN371 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN370 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN369 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN368 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN367 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN366 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN365 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN364 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN363 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN362 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN361 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN360 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN359 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN358 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN357 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN356 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN355 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN354 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN353 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN352 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x22C++0x03
|
|
hide.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN415 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN414 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN413 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN412 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN411 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN410 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN409 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN408 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN407 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN406 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN405 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN404 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN403 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN402 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN401 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN400 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN399 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN398 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN397 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN396 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN395 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN394 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN393 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN392 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN391 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN390 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN389 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN388 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN387 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN386 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN385 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN384 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x230++0x03
|
|
hide.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN447 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN446 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN445 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN444 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN443 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN442 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN441 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN440 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN439 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN438 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN437 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN436 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN435 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN434 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN433 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN432 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN431 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN430 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN429 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN428 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN427 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN426 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN425 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN424 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN423 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN422 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN421 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN420 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN419 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN418 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN417 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN416 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x234++0x03
|
|
hide.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN479 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN478 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN477 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN476 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN475 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN474 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN473 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN472 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN471 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN470 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN469 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN468 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN467 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN466 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN465 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN464 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN463 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN462 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN461 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN460 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN459 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN458 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN457 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN456 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN455 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN454 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN453 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN452 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN451 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN450 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN449 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN448 ,Interrupt set/clear pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x238++0x03
|
|
hide.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
width 11.
|
|
tree "Interrupt Active Bit Registers"
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE0,Active Bit Register 0"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt active flag" "Not active,Active"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE63 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE62 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE61 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE60 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE59 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE58 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 25. " ACTIVE57 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE56 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE55 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE54 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE53 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE52 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 19. " ACTIVE51 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE50 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE49 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE48 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE47 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE46 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 13. " ACTIVE45 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE44 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE43 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE42 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE41 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE40 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 7. " ACTIVE39 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE38 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE37 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE36 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE35 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE34 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 1. " ACTIVE33 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE32 ,Interrupt active flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x304++0x03
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
rgroup.long 0x308++0x03
|
|
line.long 0x00 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x00 31. " ACTIVE95 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE94 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE93 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE92 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE91 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE90 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 25. " ACTIVE89 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE88 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE87 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE86 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE85 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE84 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 19. " ACTIVE83 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE82 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE81 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE80 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE79 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE78 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 13. " ACTIVE77 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE76 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE75 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE74 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE73 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE72 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 7. " ACTIVE71 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE70 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE69 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE68 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE67 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE66 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 1. " ACTIVE65 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE64 ,Interrupt active flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x308++0x03
|
|
hide.long 0x00 "ACTIVE2,Active Bit Register 2"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
rgroup.long 0x30C++0x03
|
|
line.long 0x00 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x00 31. " ACTIVE127 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE126 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE125 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE124 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE123 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE122 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 25. " ACTIVE121 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE120 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE119 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE118 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE117 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE116 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 19. " ACTIVE115 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE114 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE113 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE112 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE111 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE110 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 13. " ACTIVE109 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE108 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE107 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE106 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE105 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE104 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 7. " ACTIVE103 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE102 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE101 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE100 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE99 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE98 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 1. " ACTIVE97 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE96 ,Interrupt active flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x30C++0x03
|
|
hide.long 0x00 "ACTIVE3,Active Bit Register 3"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
rgroup.long 0x310++0x03
|
|
line.long 0x00 "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x00 31. " ACTIVE159 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE158 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE157 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE156 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE155 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE154 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 25. " ACTIVE153 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE152 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE151 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE150 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE149 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE148 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 19. " ACTIVE147 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE146 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE145 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE144 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE143 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE142 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 13. " ACTIVE141 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE140 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE139 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE138 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE137 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE136 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 7. " ACTIVE135 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE134 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE133 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE132 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE131 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE130 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 1. " ACTIVE129 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE128 ,Interrupt active flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x310++0x03
|
|
hide.long 0x00 "ACTIVE4,Active Bit Register 4"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
rgroup.long 0x314++0x03
|
|
line.long 0x00 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x00 31. " ACTIVE191 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE190 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE189 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE188 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE187 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE186 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 25. " ACTIVE185 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE184 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE183 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE182 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE181 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE180 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 19. " ACTIVE179 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE178 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE177 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE176 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE175 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE174 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 13. " ACTIVE173 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE172 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE171 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE170 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE169 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE168 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 7. " ACTIVE167 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE166 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE165 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE164 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE163 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE162 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 1. " ACTIVE161 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE160 ,Interrupt active flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x314++0x03
|
|
hide.long 0x00 "ACTIVE5,Active Bit Register 5"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
rgroup.long 0x318++0x03
|
|
line.long 0x00 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x00 31. " ACTIVE223 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE222 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE221 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE220 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE219 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE218 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 25. " ACTIVE217 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE216 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE215 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE214 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE213 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE212 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 19. " ACTIVE211 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE210 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE209 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE208 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE207 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE206 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 13. " ACTIVE205 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE204 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE203 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE202 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE201 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE200 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 7. " ACTIVE199 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE198 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE197 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE196 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE195 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE194 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 1. " ACTIVE193 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE192 ,Interrupt active flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x318++0x03
|
|
hide.long 0x00 "ACTIVE6,Active Bit Register 6"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
rgroup.long 0x31C++0x03
|
|
line.long 0x00 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x00 31. " ACTIVE255 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE254 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE253 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE252 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE251 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE250 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 25. " ACTIVE249 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE248 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE247 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE246 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE245 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE244 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 19. " ACTIVE243 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE242 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE241 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE240 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE239 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE238 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 13. " ACTIVE237 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE236 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE235 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE234 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE233 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE232 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 7. " ACTIVE231 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE230 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE229 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE228 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE227 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE226 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 1. " ACTIVE225 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE224 ,Interrupt active flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x31C++0x03
|
|
hide.long 0x00 "ACTIVE7,Active Bit Register 7"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
|
|
rgroup.long 0x320++0x03
|
|
line.long 0x00 "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x00 31. " ACTIVE287 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE286 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE285 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE284 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE283 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE282 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 25. " ACTIVE281 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE280 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE279 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE278 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE277 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE276 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 19. " ACTIVE275 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE274 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE273 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE272 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE271 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE270 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 13. " ACTIVE269 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE268 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE267 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE266 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE265 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE264 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 7. " ACTIVE263 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE262 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE261 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE260 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE259 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE258 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 1. " ACTIVE257 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE256 ,Interrupt active flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x320++0x03
|
|
hide.long 0x00 "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
|
|
rgroup.long 0x324++0x03
|
|
line.long 0x00 "ACTIVE9,Active Bit Register 9"
|
|
bitfld.long 0x00 31. " ACTIVE319 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE318 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE317 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE316 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE315 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE314 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 25. " ACTIVE313 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE312 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE311 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE310 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE309 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE308 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 19. " ACTIVE307 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE306 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE305 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE304 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE303 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE302 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 13. " ACTIVE301 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE300 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE299 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE298 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE297 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE296 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 7. " ACTIVE295 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE294 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE293 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE292 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE291 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE290 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 1. " ACTIVE289 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE288 ,Interrupt active flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x324++0x03
|
|
hide.long 0x00 "ACTIVE9,Active Bit Register 9"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
|
|
rgroup.long 0x328++0x03
|
|
line.long 0x00 "ACTIVE10,Active Bit Register 10"
|
|
bitfld.long 0x00 31. " ACTIVE351 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE350 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE349 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE348 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE347 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE346 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 25. " ACTIVE345 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE344 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE343 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE342 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE341 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE340 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 19. " ACTIVE339 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE338 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE337 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE336 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE335 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE334 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 13. " ACTIVE333 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE332 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE331 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE330 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE329 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE328 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 7. " ACTIVE327 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE326 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE325 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE324 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE323 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE322 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 1. " ACTIVE321 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE320 ,Interrupt active flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x328++0x03
|
|
hide.long 0x00 "ACTIVE10,Active Bit Register 10"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
|
|
rgroup.long 0x32C++0x03
|
|
line.long 0x00 "ACTIVE11,Active Bit Register 11"
|
|
bitfld.long 0x00 31. " ACTIVE383 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE382 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE381 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE380 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE379 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE378 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 25. " ACTIVE377 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE376 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE375 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE374 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE373 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE372 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 19. " ACTIVE371 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE370 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE369 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE368 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE367 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE366 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 13. " ACTIVE365 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE364 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE363 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE362 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE361 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE360 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 7. " ACTIVE359 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE358 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE357 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE356 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE355 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE354 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 1. " ACTIVE353 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE352 ,Interrupt active flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x32C++0x03
|
|
hide.long 0x00 "ACTIVE11,Active Bit Register 11"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
|
|
rgroup.long 0x330++0x03
|
|
line.long 0x00 "ACTIVE12,Active Bit Register 12"
|
|
bitfld.long 0x00 31. " ACTIVE415 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE414 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE413 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE412 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE411 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE410 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 25. " ACTIVE409 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE408 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE407 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE406 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE405 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE404 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 19. " ACTIVE403 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE402 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE401 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE400 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE399 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE398 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 13. " ACTIVE397 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE396 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE395 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE394 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE393 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE392 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 7. " ACTIVE391 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE390 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE389 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE388 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE387 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE386 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 1. " ACTIVE385 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE384 ,Interrupt active flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x330++0x03
|
|
hide.long 0x00 "ACTIVE12,Active Bit Register 12"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
|
|
rgroup.long 0x334++0x03
|
|
line.long 0x00 "ACTIVE13,Active Bit Register 13"
|
|
bitfld.long 0x00 31. " ACTIVE447 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE446 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE445 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE444 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE443 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE442 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 25. " ACTIVE441 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE440 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE439 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE438 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE437 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE436 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 19. " ACTIVE435 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE434 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE433 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE432 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE431 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE430 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 13. " ACTIVE429 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE428 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE427 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE426 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE425 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE424 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 7. " ACTIVE423 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE422 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE421 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE420 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE419 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE418 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 1. " ACTIVE417 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE416 ,Interrupt active flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x334++0x03
|
|
hide.long 0x00 "ACTIVE13,Active Bit Register 13"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
|
|
rgroup.long 0x338++0x03
|
|
line.long 0x00 "ACTIVE14,Active Bit Register 14"
|
|
bitfld.long 0x00 31. " ACTIVE479 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE478 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE477 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE476 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE475 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE474 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 25. " ACTIVE473 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE472 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE471 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE470 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE469 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE468 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 19. " ACTIVE467 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE466 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE465 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE464 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE463 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE462 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 13. " ACTIVE461 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE460 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE459 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE458 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE457 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE456 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 7. " ACTIVE455 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE454 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE453 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE452 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE451 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE450 ,Interrupt active flag" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 1. " ACTIVE449 ,Interrupt active flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE448 ,Interrupt active flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x338++0x03
|
|
hide.long 0x00 "ACTIVE14,Active Bit Register 14"
|
|
endif
|
|
tree.end
|
|
width 13.
|
|
tree "Interrupt Target Non-Secure Registers"
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "NVIC_ITNS0,Interrupt Target Non-Secure Register 0"
|
|
bitfld.long 0x00 31. " ITNS31 ,Interrupt targets non-secure 31" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS30 ,Interrupt targets non-secure 30" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS29 ,Interrupt targets non-secure 29" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 28. " ITNS28 ,Interrupt targets non-secure 28" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS27 ,Interrupt targets non-secure 27" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS26 ,Interrupt targets non-secure 26" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 25. " ITNS25 ,Interrupt targets non-secure 25" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS24 ,Interrupt targets non-secure 24" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS23 ,Interrupt targets non-secure 23" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 22. " ITNS22 ,Interrupt targets non-secure 22" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS21 ,Interrupt targets non-secure 21" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS20 ,Interrupt targets non-secure 20" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 19. " ITNS19 ,Interrupt targets non-secure 19" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS18 ,Interrupt targets non-secure 18" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS17 ,Interrupt targets non-secure 17" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 16. " ITNS16 ,Interrupt targets non-secure 16" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS15 ,Interrupt targets non-secure 15" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS14 ,Interrupt targets non-secure 14" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 13. " ITNS13 ,Interrupt targets non-secure 13" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS12 ,Interrupt targets non-secure 12" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS11 ,Interrupt targets non-secure 11" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 10. " ITNS10 ,Interrupt targets non-secure 10" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS9 ,Interrupt targets non-secure 9" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS8 ,Interrupt targets non-secure 8" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 7. " ITNS7 ,Interrupt targets non-secure 7" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS6 ,Interrupt targets non-secure 6" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS5 ,Interrupt targets non-secure 5" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 4. " ITNS4 ,Interrupt targets non-secure 4" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS3 ,Interrupt targets non-secure 3" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS2 ,Interrupt targets non-secure 2" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 1. " ITNS1 ,Interrupt targets non-secure 1" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS0 ,Interrupt targets non-secure 0" "Secure,Non-secure"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x384++0x03
|
|
line.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
|
|
bitfld.long 0x00 31. " ITNS63 ,Interrupt targets non-secure 63" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS62 ,Interrupt targets non-secure 62" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS61 ,Interrupt targets non-secure 61" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 28. " ITNS60 ,Interrupt targets non-secure 60" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS59 ,Interrupt targets non-secure 59" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS58 ,Interrupt targets non-secure 58" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 25. " ITNS57 ,Interrupt targets non-secure 57" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS56 ,Interrupt targets non-secure 56" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS55 ,Interrupt targets non-secure 55" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 22. " ITNS54 ,Interrupt targets non-secure 54" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS53 ,Interrupt targets non-secure 53" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS52 ,Interrupt targets non-secure 52" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 19. " ITNS51 ,Interrupt targets non-secure 51" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS50 ,Interrupt targets non-secure 50" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS49 ,Interrupt targets non-secure 49" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 16. " ITNS48 ,Interrupt targets non-secure 48" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS47 ,Interrupt targets non-secure 47" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS46 ,Interrupt targets non-secure 46" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 13. " ITNS45 ,Interrupt targets non-secure 45" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS44 ,Interrupt targets non-secure 44" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS43 ,Interrupt targets non-secure 43" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 10. " ITNS42 ,Interrupt targets non-secure 42" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS41 ,Interrupt targets non-secure 41" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS40 ,Interrupt targets non-secure 40" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 7. " ITNS39 ,Interrupt targets non-secure 39" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS38 ,Interrupt targets non-secure 38" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS37 ,Interrupt targets non-secure 37" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 4. " ITNS36 ,Interrupt targets non-secure 36" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS35 ,Interrupt targets non-secure 35" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS34 ,Interrupt targets non-secure 34" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 1. " ITNS33 ,Interrupt targets non-secure 33" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS32 ,Interrupt targets non-secure 32" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x384++0x03
|
|
hide.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x388++0x03
|
|
line.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
|
|
bitfld.long 0x00 31. " ITNS95 ,Interrupt targets non-secure 95" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS94 ,Interrupt targets non-secure 94" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS93 ,Interrupt targets non-secure 93" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 28. " ITNS92 ,Interrupt targets non-secure 92" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS91 ,Interrupt targets non-secure 91" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS90 ,Interrupt targets non-secure 90" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 25. " ITNS89 ,Interrupt targets non-secure 89" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS88 ,Interrupt targets non-secure 88" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS87 ,Interrupt targets non-secure 87" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 22. " ITNS86 ,Interrupt targets non-secure 86" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS85 ,Interrupt targets non-secure 85" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS84 ,Interrupt targets non-secure 84" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 19. " ITNS83 ,Interrupt targets non-secure 83" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS82 ,Interrupt targets non-secure 82" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS81 ,Interrupt targets non-secure 81" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 16. " ITNS80 ,Interrupt targets non-secure 80" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS79 ,Interrupt targets non-secure 79" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS78 ,Interrupt targets non-secure 78" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 13. " ITNS77 ,Interrupt targets non-secure 77" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS76 ,Interrupt targets non-secure 76" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS75 ,Interrupt targets non-secure 75" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 10. " ITNS74 ,Interrupt targets non-secure 74" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS73 ,Interrupt targets non-secure 73" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS72 ,Interrupt targets non-secure 72" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 7. " ITNS71 ,Interrupt targets non-secure 71" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS70 ,Interrupt targets non-secure 70" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS69 ,Interrupt targets non-secure 69" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 4. " ITNS68 ,Interrupt targets non-secure 68" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS67 ,Interrupt targets non-secure 67" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS66 ,Interrupt targets non-secure 66" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 1. " ITNS65 ,Interrupt targets non-secure 65" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS64 ,Interrupt targets non-secure 64" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x388++0x03
|
|
hide.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x38C++0x03
|
|
line.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
|
|
bitfld.long 0x00 31. " ITNS127 ,Interrupt targets non-secure 127" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS126 ,Interrupt targets non-secure 126" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS125 ,Interrupt targets non-secure 125" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 28. " ITNS124 ,Interrupt targets non-secure 124" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS123 ,Interrupt targets non-secure 123" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS122 ,Interrupt targets non-secure 122" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 25. " ITNS121 ,Interrupt targets non-secure 121" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS120 ,Interrupt targets non-secure 120" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS119 ,Interrupt targets non-secure 119" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 22. " ITNS118 ,Interrupt targets non-secure 118" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS117 ,Interrupt targets non-secure 117" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS116 ,Interrupt targets non-secure 116" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 19. " ITNS115 ,Interrupt targets non-secure 115" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS114 ,Interrupt targets non-secure 114" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS113 ,Interrupt targets non-secure 113" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 16. " ITNS112 ,Interrupt targets non-secure 112" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS111 ,Interrupt targets non-secure 111" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS110 ,Interrupt targets non-secure 110" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 13. " ITNS109 ,Interrupt targets non-secure 109" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS108 ,Interrupt targets non-secure 108" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS107 ,Interrupt targets non-secure 107" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 10. " ITNS106 ,Interrupt targets non-secure 106" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS105 ,Interrupt targets non-secure 105" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS104 ,Interrupt targets non-secure 104" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 7. " ITNS103 ,Interrupt targets non-secure 103" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS102 ,Interrupt targets non-secure 102" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS101 ,Interrupt targets non-secure 101" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 4. " ITNS100 ,Interrupt targets non-secure 100" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS99 ,Interrupt targets non-secure 99" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS98 ,Interrupt targets non-secure 98" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 1. " ITNS97 ,Interrupt targets non-secure 97" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS96 ,Interrupt targets non-secure 96" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x38C++0x03
|
|
hide.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
|
|
bitfld.long 0x00 31. " ITNS159 ,Interrupt targets non-secure 159" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS158 ,Interrupt targets non-secure 158" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS157 ,Interrupt targets non-secure 157" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 28. " ITNS156 ,Interrupt targets non-secure 156" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS155 ,Interrupt targets non-secure 155" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS154 ,Interrupt targets non-secure 154" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 25. " ITNS153 ,Interrupt targets non-secure 153" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS152 ,Interrupt targets non-secure 152" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS151 ,Interrupt targets non-secure 151" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 22. " ITNS150 ,Interrupt targets non-secure 150" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS149 ,Interrupt targets non-secure 149" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS148 ,Interrupt targets non-secure 148" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 19. " ITNS147 ,Interrupt targets non-secure 147" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS146 ,Interrupt targets non-secure 146" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS145 ,Interrupt targets non-secure 145" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 16. " ITNS144 ,Interrupt targets non-secure 144" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS143 ,Interrupt targets non-secure 143" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS142 ,Interrupt targets non-secure 142" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 13. " ITNS141 ,Interrupt targets non-secure 141" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS140 ,Interrupt targets non-secure 140" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS139 ,Interrupt targets non-secure 139" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 10. " ITNS138 ,Interrupt targets non-secure 138" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS137 ,Interrupt targets non-secure 137" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS136 ,Interrupt targets non-secure 136" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 7. " ITNS135 ,Interrupt targets non-secure 135" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS134 ,Interrupt targets non-secure 134" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS133 ,Interrupt targets non-secure 133" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 4. " ITNS132 ,Interrupt targets non-secure 132" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS131 ,Interrupt targets non-secure 131" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS130 ,Interrupt targets non-secure 130" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 1. " ITNS129 ,Interrupt targets non-secure 129" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS128 ,Interrupt targets non-secure 128" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x390++0x03
|
|
hide.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
|
|
bitfld.long 0x00 31. " ITNS191 ,Interrupt targets non-secure 191" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS190 ,Interrupt targets non-secure 190" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS189 ,Interrupt targets non-secure 189" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 28. " ITNS188 ,Interrupt targets non-secure 188" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS187 ,Interrupt targets non-secure 187" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS186 ,Interrupt targets non-secure 186" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 25. " ITNS185 ,Interrupt targets non-secure 185" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS184 ,Interrupt targets non-secure 184" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS183 ,Interrupt targets non-secure 183" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 22. " ITNS182 ,Interrupt targets non-secure 182" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS181 ,Interrupt targets non-secure 181" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS180 ,Interrupt targets non-secure 180" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 19. " ITNS179 ,Interrupt targets non-secure 179" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS178 ,Interrupt targets non-secure 178" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS177 ,Interrupt targets non-secure 177" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 16. " ITNS176 ,Interrupt targets non-secure 176" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS175 ,Interrupt targets non-secure 175" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS174 ,Interrupt targets non-secure 174" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 13. " ITNS173 ,Interrupt targets non-secure 173" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS172 ,Interrupt targets non-secure 172" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS171 ,Interrupt targets non-secure 171" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 10. " ITNS170 ,Interrupt targets non-secure 170" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS169 ,Interrupt targets non-secure 169" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS168 ,Interrupt targets non-secure 168" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 7. " ITNS167 ,Interrupt targets non-secure 167" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS166 ,Interrupt targets non-secure 166" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS165 ,Interrupt targets non-secure 165" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 4. " ITNS164 ,Interrupt targets non-secure 164" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS163 ,Interrupt targets non-secure 163" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS162 ,Interrupt targets non-secure 162" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 1. " ITNS161 ,Interrupt targets non-secure 161" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS160 ,Interrupt targets non-secure 160" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x394++0x03
|
|
hide.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x398++0x03
|
|
line.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
|
|
bitfld.long 0x00 31. " ITNS223 ,Interrupt targets non-secure 223" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS222 ,Interrupt targets non-secure 222" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS221 ,Interrupt targets non-secure 221" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 28. " ITNS220 ,Interrupt targets non-secure 220" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS219 ,Interrupt targets non-secure 219" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS218 ,Interrupt targets non-secure 218" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 25. " ITNS217 ,Interrupt targets non-secure 217" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS216 ,Interrupt targets non-secure 216" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS215 ,Interrupt targets non-secure 215" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 22. " ITNS214 ,Interrupt targets non-secure 214" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS213 ,Interrupt targets non-secure 213" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS212 ,Interrupt targets non-secure 212" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 19. " ITNS211 ,Interrupt targets non-secure 211" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS210 ,Interrupt targets non-secure 210" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS209 ,Interrupt targets non-secure 209" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 16. " ITNS208 ,Interrupt targets non-secure 208" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS207 ,Interrupt targets non-secure 207" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS206 ,Interrupt targets non-secure 206" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 13. " ITNS205 ,Interrupt targets non-secure 205" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS204 ,Interrupt targets non-secure 204" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS203 ,Interrupt targets non-secure 203" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 10. " ITNS202 ,Interrupt targets non-secure 202" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS201 ,Interrupt targets non-secure 201" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS200 ,Interrupt targets non-secure 200" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 7. " ITNS199 ,Interrupt targets non-secure 199" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS198 ,Interrupt targets non-secure 198" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS197 ,Interrupt targets non-secure 197" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 4. " ITNS196 ,Interrupt targets non-secure 196" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS195 ,Interrupt targets non-secure 195" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS194 ,Interrupt targets non-secure 194" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 1. " ITNS193 ,Interrupt targets non-secure 193" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS192 ,Interrupt targets non-secure 192" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x398++0x03
|
|
hide.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x39C++0x03
|
|
line.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
|
|
bitfld.long 0x00 31. " ITNS255 ,Interrupt targets non-secure 255" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS254 ,Interrupt targets non-secure 254" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS253 ,Interrupt targets non-secure 253" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 28. " ITNS252 ,Interrupt targets non-secure 252" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS251 ,Interrupt targets non-secure 251" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS250 ,Interrupt targets non-secure 250" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 25. " ITNS249 ,Interrupt targets non-secure 249" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS248 ,Interrupt targets non-secure 248" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS247 ,Interrupt targets non-secure 247" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 22. " ITNS246 ,Interrupt targets non-secure 246" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS245 ,Interrupt targets non-secure 245" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS244 ,Interrupt targets non-secure 244" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 19. " ITNS243 ,Interrupt targets non-secure 243" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS242 ,Interrupt targets non-secure 242" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS241 ,Interrupt targets non-secure 241" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 16. " ITNS240 ,Interrupt targets non-secure 240" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS239 ,Interrupt targets non-secure 239" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS238 ,Interrupt targets non-secure 238" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 13. " ITNS237 ,Interrupt targets non-secure 237" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS236 ,Interrupt targets non-secure 236" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS235 ,Interrupt targets non-secure 235" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 10. " ITNS234 ,Interrupt targets non-secure 234" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS233 ,Interrupt targets non-secure 233" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS232 ,Interrupt targets non-secure 232" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 7. " ITNS231 ,Interrupt targets non-secure 231" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS230 ,Interrupt targets non-secure 230" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS229 ,Interrupt targets non-secure 229" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 4. " ITNS228 ,Interrupt targets non-secure 228" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS227 ,Interrupt targets non-secure 227" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS226 ,Interrupt targets non-secure 226" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 1. " ITNS225 ,Interrupt targets non-secure 225" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS224 ,Interrupt targets non-secure 224" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x39C++0x03
|
|
hide.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
|
|
group.long 0x3A0++0x03
|
|
line.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8"
|
|
bitfld.long 0x00 31. " ITNS287 ,Interrupt targets non-secure 287" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS286 ,Interrupt targets non-secure 286" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS285 ,Interrupt targets non-secure 285" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 28. " ITNS284 ,Interrupt targets non-secure 284" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS283 ,Interrupt targets non-secure 283" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS282 ,Interrupt targets non-secure 282" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 25. " ITNS281 ,Interrupt targets non-secure 281" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS280 ,Interrupt targets non-secure 280" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS279 ,Interrupt targets non-secure 279" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 22. " ITNS278 ,Interrupt targets non-secure 278" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS277 ,Interrupt targets non-secure 277" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS276 ,Interrupt targets non-secure 276" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 19. " ITNS275 ,Interrupt targets non-secure 275" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS274 ,Interrupt targets non-secure 274" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS273 ,Interrupt targets non-secure 273" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 16. " ITNS272 ,Interrupt targets non-secure 272" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS271 ,Interrupt targets non-secure 271" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS270 ,Interrupt targets non-secure 270" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 13. " ITNS269 ,Interrupt targets non-secure 269" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS268 ,Interrupt targets non-secure 268" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS267 ,Interrupt targets non-secure 267" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 10. " ITNS266 ,Interrupt targets non-secure 266" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS265 ,Interrupt targets non-secure 265" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS264 ,Interrupt targets non-secure 264" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 7. " ITNS263 ,Interrupt targets non-secure 263" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS262 ,Interrupt targets non-secure 262" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS261 ,Interrupt targets non-secure 261" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 4. " ITNS260 ,Interrupt targets non-secure 260" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS259 ,Interrupt targets non-secure 259" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS258 ,Interrupt targets non-secure 258" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 1. " ITNS257 ,Interrupt targets non-secure 257" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS256 ,Interrupt targets non-secure 256" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3A0++0x03
|
|
hide.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
|
|
group.long 0x3A4++0x03
|
|
line.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9"
|
|
bitfld.long 0x00 31. " ITNS319 ,Interrupt targets non-secure 319" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS318 ,Interrupt targets non-secure 318" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS317 ,Interrupt targets non-secure 317" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 28. " ITNS316 ,Interrupt targets non-secure 316" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS315 ,Interrupt targets non-secure 315" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS314 ,Interrupt targets non-secure 314" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 25. " ITNS313 ,Interrupt targets non-secure 313" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS312 ,Interrupt targets non-secure 312" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS311 ,Interrupt targets non-secure 311" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 22. " ITNS310 ,Interrupt targets non-secure 310" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS309 ,Interrupt targets non-secure 309" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS308 ,Interrupt targets non-secure 308" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 19. " ITNS307 ,Interrupt targets non-secure 307" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS306 ,Interrupt targets non-secure 306" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS305 ,Interrupt targets non-secure 305" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 16. " ITNS304 ,Interrupt targets non-secure 304" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS303 ,Interrupt targets non-secure 303" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS302 ,Interrupt targets non-secure 302" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 13. " ITNS301 ,Interrupt targets non-secure 301" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS300 ,Interrupt targets non-secure 300" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS299 ,Interrupt targets non-secure 299" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 10. " ITNS298 ,Interrupt targets non-secure 298" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS297 ,Interrupt targets non-secure 297" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS296 ,Interrupt targets non-secure 296" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 7. " ITNS295 ,Interrupt targets non-secure 295" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS294 ,Interrupt targets non-secure 294" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS293 ,Interrupt targets non-secure 293" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 4. " ITNS292 ,Interrupt targets non-secure 292" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS291 ,Interrupt targets non-secure 291" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS290 ,Interrupt targets non-secure 290" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 1. " ITNS289 ,Interrupt targets non-secure 289" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS288 ,Interrupt targets non-secure 288" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3A4++0x03
|
|
hide.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
|
|
group.long 0x3A8++0x03
|
|
line.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10"
|
|
bitfld.long 0x00 31. " ITNS351 ,Interrupt targets non-secure 351" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS350 ,Interrupt targets non-secure 350" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS349 ,Interrupt targets non-secure 349" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 28. " ITNS348 ,Interrupt targets non-secure 348" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS347 ,Interrupt targets non-secure 347" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS346 ,Interrupt targets non-secure 346" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 25. " ITNS345 ,Interrupt targets non-secure 345" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS344 ,Interrupt targets non-secure 344" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS343 ,Interrupt targets non-secure 343" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 22. " ITNS342 ,Interrupt targets non-secure 342" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS341 ,Interrupt targets non-secure 341" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS340 ,Interrupt targets non-secure 340" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 19. " ITNS339 ,Interrupt targets non-secure 339" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS338 ,Interrupt targets non-secure 338" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS337 ,Interrupt targets non-secure 337" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 16. " ITNS336 ,Interrupt targets non-secure 336" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS335 ,Interrupt targets non-secure 335" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS334 ,Interrupt targets non-secure 334" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 13. " ITNS333 ,Interrupt targets non-secure 333" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS332 ,Interrupt targets non-secure 332" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS331 ,Interrupt targets non-secure 331" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 10. " ITNS330 ,Interrupt targets non-secure 330" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS329 ,Interrupt targets non-secure 329" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS328 ,Interrupt targets non-secure 328" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 7. " ITNS327 ,Interrupt targets non-secure 327" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS326 ,Interrupt targets non-secure 326" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS325 ,Interrupt targets non-secure 325" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 4. " ITNS324 ,Interrupt targets non-secure 324" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS323 ,Interrupt targets non-secure 323" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS322 ,Interrupt targets non-secure 322" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 1. " ITNS321 ,Interrupt targets non-secure 321" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS320 ,Interrupt targets non-secure 320" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3A8++0x03
|
|
hide.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
|
|
group.long 0x3AC++0x03
|
|
line.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11"
|
|
bitfld.long 0x00 31. " ITNS383 ,Interrupt targets non-secure 383" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS382 ,Interrupt targets non-secure 382" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS381 ,Interrupt targets non-secure 381" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 28. " ITNS380 ,Interrupt targets non-secure 380" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS379 ,Interrupt targets non-secure 379" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS378 ,Interrupt targets non-secure 378" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 25. " ITNS377 ,Interrupt targets non-secure 377" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS376 ,Interrupt targets non-secure 376" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS375 ,Interrupt targets non-secure 375" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 22. " ITNS374 ,Interrupt targets non-secure 374" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS373 ,Interrupt targets non-secure 373" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS372 ,Interrupt targets non-secure 372" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 19. " ITNS371 ,Interrupt targets non-secure 371" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS370 ,Interrupt targets non-secure 370" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS369 ,Interrupt targets non-secure 369" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 16. " ITNS368 ,Interrupt targets non-secure 368" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS367 ,Interrupt targets non-secure 367" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS366 ,Interrupt targets non-secure 366" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 13. " ITNS365 ,Interrupt targets non-secure 365" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS364 ,Interrupt targets non-secure 364" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS363 ,Interrupt targets non-secure 363" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 10. " ITNS362 ,Interrupt targets non-secure 362" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS361 ,Interrupt targets non-secure 361" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS360 ,Interrupt targets non-secure 360" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 7. " ITNS359 ,Interrupt targets non-secure 359" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS358 ,Interrupt targets non-secure 358" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS357 ,Interrupt targets non-secure 357" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 4. " ITNS356 ,Interrupt targets non-secure 356" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS355 ,Interrupt targets non-secure 355" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS354 ,Interrupt targets non-secure 354" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 1. " ITNS353 ,Interrupt targets non-secure 353" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS352 ,Interrupt targets non-secure 352" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3AC++0x03
|
|
hide.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
|
|
group.long 0x3B0++0x03
|
|
line.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12"
|
|
bitfld.long 0x00 31. " ITNS415 ,Interrupt targets non-secure 415" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS414 ,Interrupt targets non-secure 414" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS413 ,Interrupt targets non-secure 413" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 28. " ITNS412 ,Interrupt targets non-secure 412" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS411 ,Interrupt targets non-secure 411" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS410 ,Interrupt targets non-secure 410" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 25. " ITNS409 ,Interrupt targets non-secure 409" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS408 ,Interrupt targets non-secure 408" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS407 ,Interrupt targets non-secure 407" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 22. " ITNS406 ,Interrupt targets non-secure 406" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS405 ,Interrupt targets non-secure 405" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS404 ,Interrupt targets non-secure 404" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 19. " ITNS403 ,Interrupt targets non-secure 403" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS402 ,Interrupt targets non-secure 402" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS401 ,Interrupt targets non-secure 401" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 16. " ITNS400 ,Interrupt targets non-secure 400" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS399 ,Interrupt targets non-secure 399" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS398 ,Interrupt targets non-secure 398" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 13. " ITNS397 ,Interrupt targets non-secure 397" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS396 ,Interrupt targets non-secure 396" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS395 ,Interrupt targets non-secure 395" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 10. " ITNS394 ,Interrupt targets non-secure 394" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS393 ,Interrupt targets non-secure 393" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS392 ,Interrupt targets non-secure 392" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 7. " ITNS391 ,Interrupt targets non-secure 391" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS390 ,Interrupt targets non-secure 390" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS389 ,Interrupt targets non-secure 389" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 4. " ITNS388 ,Interrupt targets non-secure 388" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS387 ,Interrupt targets non-secure 387" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS386 ,Interrupt targets non-secure 386" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 1. " ITNS385 ,Interrupt targets non-secure 385" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS384 ,Interrupt targets non-secure 384" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3B0++0x03
|
|
hide.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
|
|
group.long 0x3B4++0x03
|
|
line.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13"
|
|
bitfld.long 0x00 31. " ITNS447 ,Interrupt targets non-secure 447" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS446 ,Interrupt targets non-secure 446" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS445 ,Interrupt targets non-secure 445" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 28. " ITNS444 ,Interrupt targets non-secure 444" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS443 ,Interrupt targets non-secure 443" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS442 ,Interrupt targets non-secure 442" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 25. " ITNS441 ,Interrupt targets non-secure 441" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS440 ,Interrupt targets non-secure 440" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS439 ,Interrupt targets non-secure 439" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 22. " ITNS438 ,Interrupt targets non-secure 438" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS437 ,Interrupt targets non-secure 437" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS436 ,Interrupt targets non-secure 436" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 19. " ITNS435 ,Interrupt targets non-secure 435" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS434 ,Interrupt targets non-secure 434" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS433 ,Interrupt targets non-secure 433" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 16. " ITNS432 ,Interrupt targets non-secure 432" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS431 ,Interrupt targets non-secure 431" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS430 ,Interrupt targets non-secure 430" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 13. " ITNS429 ,Interrupt targets non-secure 429" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS428 ,Interrupt targets non-secure 428" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS427 ,Interrupt targets non-secure 427" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 10. " ITNS426 ,Interrupt targets non-secure 426" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS425 ,Interrupt targets non-secure 425" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS424 ,Interrupt targets non-secure 424" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 7. " ITNS423 ,Interrupt targets non-secure 423" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS422 ,Interrupt targets non-secure 422" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS421 ,Interrupt targets non-secure 421" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 4. " ITNS420 ,Interrupt targets non-secure 420" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS419 ,Interrupt targets non-secure 419" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS418 ,Interrupt targets non-secure 418" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 1. " ITNS417 ,Interrupt targets non-secure 417" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS416 ,Interrupt targets non-secure 416" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3B4++0x03
|
|
hide.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
|
|
group.long 0x3B8++0x03
|
|
line.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14"
|
|
bitfld.long 0x00 31. " ITNS479 ,Interrupt targets non-secure 479" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS478 ,Interrupt targets non-secure 478" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS477 ,Interrupt targets non-secure 477" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 28. " ITNS476 ,Interrupt targets non-secure 476" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS475 ,Interrupt targets non-secure 475" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS474 ,Interrupt targets non-secure 474" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 25. " ITNS473 ,Interrupt targets non-secure 473" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS472 ,Interrupt targets non-secure 472" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS471 ,Interrupt targets non-secure 471" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 22. " ITNS470 ,Interrupt targets non-secure 470" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS469 ,Interrupt targets non-secure 469" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS468 ,Interrupt targets non-secure 468" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 19. " ITNS467 ,Interrupt targets non-secure 467" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS466 ,Interrupt targets non-secure 466" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS465 ,Interrupt targets non-secure 465" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 16. " ITNS464 ,Interrupt targets non-secure 464" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS463 ,Interrupt targets non-secure 463" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS462 ,Interrupt targets non-secure 462" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 13. " ITNS461 ,Interrupt targets non-secure 461" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS460 ,Interrupt targets non-secure 460" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS459 ,Interrupt targets non-secure 459" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 10. " ITNS458 ,Interrupt targets non-secure 458" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS457 ,Interrupt targets non-secure 457" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS456 ,Interrupt targets non-secure 456" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 7. " ITNS455 ,Interrupt targets non-secure 455" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS454 ,Interrupt targets non-secure 454" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS453 ,Interrupt targets non-secure 453" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 4. " ITNS452 ,Interrupt targets non-secure 452" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS451 ,Interrupt targets non-secure 451" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS450 ,Interrupt targets non-secure 450" "Secure,Non-secure"
|
|
newline
|
|
bitfld.long 0x00 1. " ITNS449 ,Interrupt targets non-secure 449" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS448 ,Interrupt targets non-secure 448" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3B8++0x03
|
|
hide.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "IPR0 ,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_3 ,Interrupt 3 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_2 ,Interrupt 2 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_1 ,Interrupt 1 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_0 ,Interrupt 0 priority"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "IPR1 ,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_7 ,Interrupt 7 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_6 ,Interrupt 6 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_5 ,Interrupt 5 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_4 ,Interrupt 4 priority"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "IPR2 ,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_11 ,Interrupt 11 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_10 ,Interrupt 10 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_9 ,Interrupt 9 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_8 ,Interrupt 8 priority"
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "IPR3 ,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_15 ,Interrupt 15 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_14 ,Interrupt 14 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_13 ,Interrupt 13 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_12 ,Interrupt 12 priority"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "IPR4 ,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_19 ,Interrupt 19 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_18 ,Interrupt 18 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_17 ,Interrupt 17 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_16 ,Interrupt 16 priority"
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "IPR5 ,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_23 ,Interrupt 23 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_22 ,Interrupt 22 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_21 ,Interrupt 21 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_20 ,Interrupt 20 priority"
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "IPR6 ,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_27 ,Interrupt 27 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_26 ,Interrupt 26 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_25 ,Interrupt 25 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_24 ,Interrupt 24 priority"
|
|
group.long 0x41C++0x03
|
|
line.long 0x00 "IPR7 ,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_31 ,Interrupt 31 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_30 ,Interrupt 30 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_29 ,Interrupt 29 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_28 ,Interrupt 28 priority"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_35 ,Interrupt 35 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_34 ,Interrupt 34 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_33 ,Interrupt 33 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_32 ,Interrupt 32 priority"
|
|
group.long 0x424++0x03
|
|
line.long 0x00 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_39 ,Interrupt 39 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_38 ,Interrupt 38 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_37 ,Interrupt 37 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_36 ,Interrupt 36 priority"
|
|
group.long 0x428++0x03
|
|
line.long 0x00 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_43 ,Interrupt 43 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_42 ,Interrupt 42 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_41 ,Interrupt 41 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_40 ,Interrupt 40 priority"
|
|
group.long 0x42C++0x03
|
|
line.long 0x00 "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_47 ,Interrupt 47 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_46 ,Interrupt 46 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_45 ,Interrupt 45 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_44 ,Interrupt 44 priority"
|
|
group.long 0x430++0x03
|
|
line.long 0x00 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_51 ,Interrupt 51 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_50 ,Interrupt 50 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_49 ,Interrupt 49 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_48 ,Interrupt 48 priority"
|
|
group.long 0x434++0x03
|
|
line.long 0x00 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_55 ,Interrupt 55 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_54 ,Interrupt 54 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_53 ,Interrupt 53 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_52 ,Interrupt 52 priority"
|
|
group.long 0x438++0x03
|
|
line.long 0x00 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_59 ,Interrupt 59 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_58 ,Interrupt 58 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_57 ,Interrupt 57 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_56 ,Interrupt 56 priority"
|
|
group.long 0x43C++0x03
|
|
line.long 0x00 "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_63 ,Interrupt 63 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_62 ,Interrupt 62 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_61 ,Interrupt 61 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_60 ,Interrupt 60 priority"
|
|
else
|
|
repeat 8. (increment 0x420 0x04)(increment 8. 1.)
|
|
hgroup.long $1++0x03
|
|
hide.long 0x00 "IPR$2,Interrupt Priority Register"
|
|
repeat.end
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_67 ,Interrupt 67 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_66 ,Interrupt 66 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_65 ,Interrupt 65 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_64 ,Interrupt 64 priority"
|
|
group.long 0x444++0x03
|
|
line.long 0x00 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_71 ,Interrupt 71 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_70 ,Interrupt 70 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_69 ,Interrupt 69 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_68 ,Interrupt 68 priority"
|
|
group.long 0x448++0x03
|
|
line.long 0x00 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_75 ,Interrupt 75 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_74 ,Interrupt 74 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_73 ,Interrupt 73 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_72 ,Interrupt 72 priority"
|
|
group.long 0x44C++0x03
|
|
line.long 0x00 "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_79 ,Interrupt 79 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_78 ,Interrupt 78 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_77 ,Interrupt 77 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_76 ,Interrupt 76 priority"
|
|
group.long 0x450++0x03
|
|
line.long 0x00 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_83 ,Interrupt 83 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_82 ,Interrupt 82 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_81 ,Interrupt 81 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_80 ,Interrupt 80 priority"
|
|
group.long 0x454++0x03
|
|
line.long 0x00 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_87 ,Interrupt 87 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_86 ,Interrupt 86 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_85 ,Interrupt 85 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_84 ,Interrupt 84 priority"
|
|
group.long 0x458++0x03
|
|
line.long 0x00 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_91 ,Interrupt 91 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_90 ,Interrupt 90 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_89 ,Interrupt 89 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_88 ,Interrupt 88 priority"
|
|
group.long 0x45C++0x03
|
|
line.long 0x00 "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_95 ,Interrupt 95 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_94 ,Interrupt 94 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_93 ,Interrupt 93 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_92 ,Interrupt 92 priority"
|
|
else
|
|
repeat 8. (increment 0x440 0x04)(increment 16. 1.)
|
|
hgroup.long $1++0x03
|
|
hide.long 0x00 "IPR$2,Interrupt Priority Register"
|
|
repeat.end
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x460++0x03
|
|
line.long 0x00 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_99 ,Interrupt 99 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_98 ,Interrupt 98 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_97 ,Interrupt 97 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_96 ,Interrupt 96 priority"
|
|
group.long 0x464++0x03
|
|
line.long 0x00 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_103 ,Interrupt 103 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_102 ,Interrupt 102 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_101 ,Interrupt 101 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_100 ,Interrupt 100 priority"
|
|
group.long 0x468++0x03
|
|
line.long 0x00 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_107 ,Interrupt 107 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_106 ,Interrupt 106 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_105 ,Interrupt 105 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_104 ,Interrupt 104 priority"
|
|
group.long 0x46C++0x03
|
|
line.long 0x00 "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_111 ,Interrupt 111 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_110 ,Interrupt 110 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_109 ,Interrupt 109 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_108 ,Interrupt 108 priority"
|
|
group.long 0x470++0x03
|
|
line.long 0x00 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_115 ,Interrupt 115 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_114 ,Interrupt 114 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_113 ,Interrupt 113 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_112 ,Interrupt 112 priority"
|
|
group.long 0x474++0x03
|
|
line.long 0x00 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_119 ,Interrupt 119 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_118 ,Interrupt 118 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_117 ,Interrupt 117 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_116 ,Interrupt 116 priority"
|
|
group.long 0x478++0x03
|
|
line.long 0x00 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_123 ,Interrupt 123 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_122 ,Interrupt 122 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_121 ,Interrupt 121 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_120 ,Interrupt 120 priority"
|
|
group.long 0x47C++0x03
|
|
line.long 0x00 "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_127 ,Interrupt 127 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_126 ,Interrupt 126 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_125 ,Interrupt 125 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_124 ,Interrupt 124 priority"
|
|
else
|
|
repeat 8. (increment 0x460 0x04)(increment 24. 1.)
|
|
hgroup.long $1++0x03
|
|
hide.long 0x00 "IPR$2,Interrupt Priority Register"
|
|
repeat.end
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_131 ,Interrupt 131 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_130 ,Interrupt 130 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_129 ,Interrupt 129 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_128 ,Interrupt 128 priority"
|
|
group.long 0x484++0x03
|
|
line.long 0x00 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_135 ,Interrupt 135 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_134 ,Interrupt 134 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_133 ,Interrupt 133 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_132 ,Interrupt 132 priority"
|
|
group.long 0x488++0x03
|
|
line.long 0x00 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_139 ,Interrupt 139 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_138 ,Interrupt 138 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_137 ,Interrupt 137 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_136 ,Interrupt 136 priority"
|
|
group.long 0x48C++0x03
|
|
line.long 0x00 "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_143 ,Interrupt 143 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_142 ,Interrupt 142 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_141 ,Interrupt 141 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_140 ,Interrupt 140 priority"
|
|
group.long 0x490++0x03
|
|
line.long 0x00 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_147 ,Interrupt 147 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_146 ,Interrupt 146 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_145 ,Interrupt 145 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_144 ,Interrupt 144 priority"
|
|
group.long 0x494++0x03
|
|
line.long 0x00 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_151 ,Interrupt 151 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_150 ,Interrupt 150 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_149 ,Interrupt 149 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_148 ,Interrupt 148 priority"
|
|
group.long 0x498++0x03
|
|
line.long 0x00 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_155 ,Interrupt 155 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_154 ,Interrupt 154 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_153 ,Interrupt 153 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_152 ,Interrupt 152 priority"
|
|
group.long 0x49C++0x03
|
|
line.long 0x00 "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_159 ,Interrupt 159 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_158 ,Interrupt 158 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_157 ,Interrupt 157 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_156 ,Interrupt 156 priority"
|
|
else
|
|
repeat 8. (increment 0x480 0x04)(increment 32. 1.)
|
|
hgroup.long $1++0x03
|
|
hide.long 0x00 "IPR$2,Interrupt Priority Register"
|
|
repeat.end
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x4A0++0x03
|
|
line.long 0x00 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_163 ,Interrupt 163 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_162 ,Interrupt 162 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_161 ,Interrupt 161 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_160 ,Interrupt 160 priority"
|
|
group.long 0x4A4++0x03
|
|
line.long 0x00 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_167 ,Interrupt 167 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_166 ,Interrupt 166 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_165 ,Interrupt 165 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_164 ,Interrupt 164 priority"
|
|
group.long 0x4A8++0x03
|
|
line.long 0x00 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_171 ,Interrupt 171 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_170 ,Interrupt 170 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_169 ,Interrupt 169 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_168 ,Interrupt 168 priority"
|
|
group.long 0x4AC++0x03
|
|
line.long 0x00 "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_175 ,Interrupt 175 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_174 ,Interrupt 174 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_173 ,Interrupt 173 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_172 ,Interrupt 172 priority"
|
|
group.long 0x4B0++0x03
|
|
line.long 0x00 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_179 ,Interrupt 179 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_178 ,Interrupt 178 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_177 ,Interrupt 177 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_176 ,Interrupt 176 priority"
|
|
group.long 0x4B4++0x03
|
|
line.long 0x00 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_183 ,Interrupt 183 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_182 ,Interrupt 182 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_181 ,Interrupt 181 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_180 ,Interrupt 180 priority"
|
|
group.long 0x4B8++0x03
|
|
line.long 0x00 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_187 ,Interrupt 187 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_186 ,Interrupt 186 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_185 ,Interrupt 185 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_184 ,Interrupt 184 priority"
|
|
group.long 0x4BC++0x03
|
|
line.long 0x00 "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_191 ,Interrupt 191 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_190 ,Interrupt 190 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_189 ,Interrupt 189 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_188 ,Interrupt 188 priority"
|
|
else
|
|
repeat 8. (increment 0x4A0 0x04)(increment 40. 1.)
|
|
hgroup.long $1++0x03
|
|
hide.long 0x00 "IPR$2,Interrupt Priority Register"
|
|
repeat.end
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x4C0++0x03
|
|
line.long 0x00 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_195 ,Interrupt 195 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_194 ,Interrupt 194 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_193 ,Interrupt 193 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_192 ,Interrupt 192 priority"
|
|
group.long 0x4C4++0x03
|
|
line.long 0x00 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_199 ,Interrupt 199 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_198 ,Interrupt 198 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_197 ,Interrupt 197 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_196 ,Interrupt 196 priority"
|
|
group.long 0x4C8++0x03
|
|
line.long 0x00 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_203 ,Interrupt 203 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_202 ,Interrupt 202 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_201 ,Interrupt 201 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_200 ,Interrupt 200 priority"
|
|
group.long 0x4CC++0x03
|
|
line.long 0x00 "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_207 ,Interrupt 207 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_206 ,Interrupt 206 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_205 ,Interrupt 205 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_204 ,Interrupt 204 priority"
|
|
group.long 0x4D0++0x03
|
|
line.long 0x00 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_211 ,Interrupt 211 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_210 ,Interrupt 210 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_209 ,Interrupt 209 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_208 ,Interrupt 208 priority"
|
|
group.long 0x4D4++0x03
|
|
line.long 0x00 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_215 ,Interrupt 215 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_214 ,Interrupt 214 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_213 ,Interrupt 213 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_212 ,Interrupt 212 priority"
|
|
group.long 0x4D8++0x03
|
|
line.long 0x00 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_219 ,Interrupt 219 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_218 ,Interrupt 218 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_217 ,Interrupt 217 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_216 ,Interrupt 216 priority"
|
|
group.long 0x4DC++0x03
|
|
line.long 0x00 "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_223 ,Interrupt 223 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_222 ,Interrupt 222 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_221 ,Interrupt 221 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_220 ,Interrupt 220 priority"
|
|
else
|
|
repeat 8. (increment 0x4C0 0x04)(increment 48. 1.)
|
|
hgroup.long $1++0x03
|
|
hide.long 0x00 "IPR$2,Interrupt Priority Register"
|
|
repeat.end
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x4E0++0x03
|
|
line.long 0x00 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_227 ,Interrupt 227 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_226 ,Interrupt 226 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_225 ,Interrupt 225 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_224 ,Interrupt 224 priority"
|
|
group.long 0x4E4++0x03
|
|
line.long 0x00 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_231 ,Interrupt 231 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_230 ,Interrupt 230 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_229 ,Interrupt 229 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_228 ,Interrupt 228 priority"
|
|
group.long 0x4E8++0x03
|
|
line.long 0x00 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_235 ,Interrupt 235 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_234 ,Interrupt 234 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_233 ,Interrupt 233 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_232 ,Interrupt 232 priority"
|
|
group.long 0x4EC++0x03
|
|
line.long 0x00 "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_239 ,Interrupt 239 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_238 ,Interrupt 238 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_237 ,Interrupt 237 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_236 ,Interrupt 236 priority"
|
|
group.long 0x4F0++0x03
|
|
line.long 0x00 "IPR60,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_243 ,Interrupt 243 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_242 ,Interrupt 242 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_241 ,Interrupt 241 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_240 ,Interrupt 240 priority"
|
|
group.long 0x4F4++0x03
|
|
line.long 0x00 "IPR61,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_247 ,Interrupt 247 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_246 ,Interrupt 246 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_245 ,Interrupt 245 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_244 ,Interrupt 244 priority"
|
|
group.long 0x4F8++0x03
|
|
line.long 0x00 "IPR62,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_251 ,Interrupt 251 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_250 ,Interrupt 250 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_249 ,Interrupt 249 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_248 ,Interrupt 248 priority"
|
|
group.long 0x4FC++0x03
|
|
line.long 0x00 "IPR63,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_255 ,Interrupt 255 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_254 ,Interrupt 254 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_253 ,Interrupt 253 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_252 ,Interrupt 252 priority"
|
|
else
|
|
repeat 8. (increment 0x4E0 0x04)(increment 56. 1.)
|
|
hgroup.long $1++0x03
|
|
hide.long 0x00 "IPR$2,Interrupt Priority Register"
|
|
repeat.end
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "IPR64,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_259 ,Interrupt 259 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_258 ,Interrupt 258 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_257 ,Interrupt 257 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_256 ,Interrupt 256 priority"
|
|
group.long 0x504++0x03
|
|
line.long 0x00 "IPR65,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_263 ,Interrupt 263 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_262 ,Interrupt 262 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_261 ,Interrupt 261 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_260 ,Interrupt 260 priority"
|
|
group.long 0x508++0x03
|
|
line.long 0x00 "IPR66,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_267 ,Interrupt 267 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_266 ,Interrupt 266 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_265 ,Interrupt 265 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_264 ,Interrupt 264 priority"
|
|
group.long 0x50C++0x03
|
|
line.long 0x00 "IPR67,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_271 ,Interrupt 271 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_270 ,Interrupt 270 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_269 ,Interrupt 269 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_268 ,Interrupt 268 priority"
|
|
group.long 0x510++0x03
|
|
line.long 0x00 "IPR68,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_275 ,Interrupt 275 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_274 ,Interrupt 274 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_273 ,Interrupt 273 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_272 ,Interrupt 272 priority"
|
|
group.long 0x514++0x03
|
|
line.long 0x00 "IPR69,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_279 ,Interrupt 279 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_278 ,Interrupt 278 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_277 ,Interrupt 277 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_276 ,Interrupt 276 priority"
|
|
group.long 0x518++0x03
|
|
line.long 0x00 "IPR70,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_283 ,Interrupt 283 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_282 ,Interrupt 282 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_281 ,Interrupt 281 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_280 ,Interrupt 280 priority"
|
|
group.long 0x51C++0x03
|
|
line.long 0x00 "IPR71,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_287 ,Interrupt 287 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_286 ,Interrupt 286 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_285 ,Interrupt 285 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_284 ,Interrupt 284 priority"
|
|
else
|
|
repeat 8. (increment 0x500 0x04)(increment 64. 1.)
|
|
hgroup.long $1++0x03
|
|
hide.long 0x00 "IPR$2,Interrupt Priority Register"
|
|
repeat.end
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
|
|
group.long 0x520++0x03
|
|
line.long 0x00 "IPR72,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_291 ,Interrupt 291 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_290 ,Interrupt 290 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_289 ,Interrupt 289 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_288 ,Interrupt 288 priority"
|
|
group.long 0x524++0x03
|
|
line.long 0x00 "IPR73,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_295 ,Interrupt 295 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_294 ,Interrupt 294 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_293 ,Interrupt 293 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_292 ,Interrupt 292 priority"
|
|
group.long 0x528++0x03
|
|
line.long 0x00 "IPR74,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_299 ,Interrupt 299 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_298 ,Interrupt 298 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_297 ,Interrupt 297 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_296 ,Interrupt 296 priority"
|
|
group.long 0x52C++0x03
|
|
line.long 0x00 "IPR75,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_303 ,Interrupt 303 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_302 ,Interrupt 302 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_301 ,Interrupt 301 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_300 ,Interrupt 300 priority"
|
|
group.long 0x530++0x03
|
|
line.long 0x00 "IPR76,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_307 ,Interrupt 307 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_306 ,Interrupt 306 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_305 ,Interrupt 305 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_304 ,Interrupt 304 priority"
|
|
group.long 0x534++0x03
|
|
line.long 0x00 "IPR77,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_311 ,Interrupt 311 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_310 ,Interrupt 310 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_309 ,Interrupt 309 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_308 ,Interrupt 308 priority"
|
|
group.long 0x538++0x03
|
|
line.long 0x00 "IPR78,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_315 ,Interrupt 315 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_314 ,Interrupt 314 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_313 ,Interrupt 313 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_312 ,Interrupt 312 priority"
|
|
group.long 0x53C++0x03
|
|
line.long 0x00 "IPR79,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_319 ,Interrupt 319 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_318 ,Interrupt 318 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_317 ,Interrupt 317 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_316 ,Interrupt 316 priority"
|
|
else
|
|
repeat 8. (increment 0x520 0x04)(increment 72. 1.)
|
|
hgroup.long $1++0x03
|
|
hide.long 0x00 "IPR$2,Interrupt Priority Register"
|
|
repeat.end
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
|
|
group.long 0x540++0x03
|
|
line.long 0x00 "IPR80,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_323 ,Interrupt 323 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_322 ,Interrupt 322 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_321 ,Interrupt 321 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_320 ,Interrupt 320 priority"
|
|
group.long 0x544++0x03
|
|
line.long 0x00 "IPR81,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_327 ,Interrupt 327 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_326 ,Interrupt 326 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_325 ,Interrupt 325 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_324 ,Interrupt 324 priority"
|
|
group.long 0x548++0x03
|
|
line.long 0x00 "IPR82,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_331 ,Interrupt 331 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_330 ,Interrupt 330 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_329 ,Interrupt 329 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_328 ,Interrupt 328 priority"
|
|
group.long 0x54C++0x03
|
|
line.long 0x00 "IPR83,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_335 ,Interrupt 335 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_334 ,Interrupt 334 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_333 ,Interrupt 333 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_332 ,Interrupt 332 priority"
|
|
group.long 0x550++0x03
|
|
line.long 0x00 "IPR84,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_339 ,Interrupt 339 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_338 ,Interrupt 338 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_337 ,Interrupt 337 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_336 ,Interrupt 336 priority"
|
|
group.long 0x554++0x03
|
|
line.long 0x00 "IPR85,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_343 ,Interrupt 343 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_342 ,Interrupt 342 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_341 ,Interrupt 341 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_340 ,Interrupt 340 priority"
|
|
group.long 0x558++0x03
|
|
line.long 0x00 "IPR86,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_347 ,Interrupt 347 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_346 ,Interrupt 346 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_345 ,Interrupt 345 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_344 ,Interrupt 344 priority"
|
|
group.long 0x55C++0x03
|
|
line.long 0x00 "IPR87,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_351 ,Interrupt 351 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_350 ,Interrupt 350 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_349 ,Interrupt 349 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_348 ,Interrupt 348 priority"
|
|
else
|
|
repeat 8. (increment 0x540 0x04)(increment 80. 1.)
|
|
hgroup.long $1++0x03
|
|
hide.long 0x00 "IPR$2,Interrupt Priority Register"
|
|
repeat.end
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
|
|
group.long 0x560++0x03
|
|
line.long 0x00 "IPR88,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_355 ,Interrupt 355 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_354 ,Interrupt 354 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_353 ,Interrupt 353 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_352 ,Interrupt 352 priority"
|
|
group.long 0x564++0x03
|
|
line.long 0x00 "IPR89,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_359 ,Interrupt 359 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_358 ,Interrupt 358 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_357 ,Interrupt 357 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_356 ,Interrupt 356 priority"
|
|
group.long 0x568++0x03
|
|
line.long 0x00 "IPR90,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_363 ,Interrupt 363 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_362 ,Interrupt 362 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_361 ,Interrupt 361 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_360 ,Interrupt 360 priority"
|
|
group.long 0x56C++0x03
|
|
line.long 0x00 "IPR91,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_367 ,Interrupt 367 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_366 ,Interrupt 366 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_365 ,Interrupt 365 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_364 ,Interrupt 364 priority"
|
|
group.long 0x570++0x03
|
|
line.long 0x00 "IPR92,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_371 ,Interrupt 371 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_370 ,Interrupt 370 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_369 ,Interrupt 369 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_368 ,Interrupt 368 priority"
|
|
group.long 0x574++0x03
|
|
line.long 0x00 "IPR93,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_375 ,Interrupt 375 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_374 ,Interrupt 374 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_373 ,Interrupt 373 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_372 ,Interrupt 372 priority"
|
|
group.long 0x578++0x03
|
|
line.long 0x00 "IPR94,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_379 ,Interrupt 379 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_378 ,Interrupt 378 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_377 ,Interrupt 377 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_376 ,Interrupt 376 priority"
|
|
group.long 0x57C++0x03
|
|
line.long 0x00 "IPR95,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_383 ,Interrupt 383 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_382 ,Interrupt 382 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_381 ,Interrupt 381 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_380 ,Interrupt 380 priority"
|
|
else
|
|
repeat 8. (increment 0x560 0x04)(increment 88. 1.)
|
|
hgroup.long $1++0x03
|
|
hide.long 0x00 "IPR$2,Interrupt Priority Register"
|
|
repeat.end
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
|
|
group.long 0x580++0x03
|
|
line.long 0x00 "IPR96,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_387 ,Interrupt 387 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_386 ,Interrupt 386 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_385 ,Interrupt 385 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_384 ,Interrupt 384 priority"
|
|
group.long 0x584++0x03
|
|
line.long 0x00 "IPR97,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_391 ,Interrupt 391 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_390 ,Interrupt 390 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_389 ,Interrupt 389 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_388 ,Interrupt 388 priority"
|
|
group.long 0x588++0x03
|
|
line.long 0x00 "IPR98,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_395 ,Interrupt 395 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_394 ,Interrupt 394 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_393 ,Interrupt 393 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_392 ,Interrupt 392 priority"
|
|
group.long 0x58C++0x03
|
|
line.long 0x00 "IPR99,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_399 ,Interrupt 399 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_398 ,Interrupt 398 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_397 ,Interrupt 397 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_396 ,Interrupt 396 priority"
|
|
group.long 0x590++0x03
|
|
line.long 0x00 "IPR100,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_403 ,Interrupt 403 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_402 ,Interrupt 402 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_401 ,Interrupt 401 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_400 ,Interrupt 400 priority"
|
|
group.long 0x594++0x03
|
|
line.long 0x00 "IPR101,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_407 ,Interrupt 407 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_406 ,Interrupt 406 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_405 ,Interrupt 405 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_404 ,Interrupt 404 priority"
|
|
group.long 0x598++0x03
|
|
line.long 0x00 "IPR102,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_411 ,Interrupt 411 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_410 ,Interrupt 410 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_409 ,Interrupt 409 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_408 ,Interrupt 408 priority"
|
|
group.long 0x59C++0x03
|
|
line.long 0x00 "IPR103,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_415 ,Interrupt 415 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_414 ,Interrupt 414 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_413 ,Interrupt 413 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_412 ,Interrupt 412 priority"
|
|
else
|
|
repeat 8. (increment 0x580 0x04)(increment 96. 1.)
|
|
hgroup.long $1++0x03
|
|
hide.long 0x00 "IPR$2,Interrupt Priority Register"
|
|
repeat.end
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
|
|
group.long 0x5A0++0x03
|
|
line.long 0x00 "IPR104,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_419 ,Interrupt 419 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_418 ,Interrupt 418 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_417 ,Interrupt 417 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_416 ,Interrupt 416 priority"
|
|
group.long 0x5A4++0x03
|
|
line.long 0x00 "IPR105,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_423 ,Interrupt 423 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_422 ,Interrupt 422 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_421 ,Interrupt 421 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_420 ,Interrupt 420 priority"
|
|
group.long 0x5A8++0x03
|
|
line.long 0x00 "IPR106,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_427 ,Interrupt 427 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_426 ,Interrupt 426 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_425 ,Interrupt 425 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_424 ,Interrupt 424 priority"
|
|
group.long 0x5AC++0x03
|
|
line.long 0x00 "IPR107,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_431 ,Interrupt 431 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_430 ,Interrupt 430 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_429 ,Interrupt 429 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_428 ,Interrupt 428 priority"
|
|
group.long 0x5B0++0x03
|
|
line.long 0x00 "IPR108,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_435 ,Interrupt 435 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_434 ,Interrupt 434 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_433 ,Interrupt 433 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_432 ,Interrupt 432 priority"
|
|
group.long 0x5B4++0x03
|
|
line.long 0x00 "IPR109,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_439 ,Interrupt 439 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_438 ,Interrupt 438 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_437 ,Interrupt 437 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_436 ,Interrupt 436 priority"
|
|
group.long 0x5B8++0x03
|
|
line.long 0x00 "IPR110,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_443 ,Interrupt 443 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_442 ,Interrupt 442 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_441 ,Interrupt 441 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_440 ,Interrupt 440 priority"
|
|
group.long 0x5BC++0x03
|
|
line.long 0x00 "IPR111,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_447 ,Interrupt 447 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_446 ,Interrupt 446 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_445 ,Interrupt 445 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_444 ,Interrupt 444 priority"
|
|
else
|
|
repeat 8. (increment 0x5A0 0x04)(increment 104. 1.)
|
|
hgroup.long $1++0x03
|
|
hide.long 0x00 "IPR$2,Interrupt Priority Register"
|
|
repeat.end
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
|
|
group.long 0x5C0++0x03
|
|
line.long 0x00 "IPR112,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_451 ,Interrupt 451 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_450 ,Interrupt 450 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_449 ,Interrupt 449 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_448 ,Interrupt 448 priority"
|
|
group.long 0x5C4++0x03
|
|
line.long 0x00 "IPR113,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_455 ,Interrupt 455 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_454 ,Interrupt 454 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_453 ,Interrupt 453 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_452 ,Interrupt 452 priority"
|
|
group.long 0x5C8++0x03
|
|
line.long 0x00 "IPR114,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_459 ,Interrupt 459 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_458 ,Interrupt 458 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_457 ,Interrupt 457 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_456 ,Interrupt 456 priority"
|
|
group.long 0x5CC++0x03
|
|
line.long 0x00 "IPR115,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_463 ,Interrupt 463 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_462 ,Interrupt 462 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_461 ,Interrupt 461 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_460 ,Interrupt 460 priority"
|
|
group.long 0x5D0++0x03
|
|
line.long 0x00 "IPR116,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_467 ,Interrupt 467 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_466 ,Interrupt 466 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_465 ,Interrupt 465 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_464 ,Interrupt 464 priority"
|
|
group.long 0x5D4++0x03
|
|
line.long 0x00 "IPR117,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_471 ,Interrupt 471 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_470 ,Interrupt 470 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_469 ,Interrupt 469 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_468 ,Interrupt 468 priority"
|
|
group.long 0x5D8++0x03
|
|
line.long 0x00 "IPR118,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_475 ,Interrupt 475 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_474 ,Interrupt 474 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_473 ,Interrupt 473 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_472 ,Interrupt 472 priority"
|
|
group.long 0x5DC++0x03
|
|
line.long 0x00 "IPR119,Interrupt Priority Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRI_479 ,Interrupt 479 priority"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PRI_478 ,Interrupt 478 priority"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRI_477 ,Interrupt 477 priority"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_476 ,Interrupt 476 priority"
|
|
else
|
|
repeat 8. (increment 0x5C0 0x04)(increment 112. 1.)
|
|
hgroup.long $1++0x03
|
|
hide.long 0x00 "IPR$2,Interrupt Priority Register"
|
|
repeat.end
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Floating-Point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " LSPENS ,This bit controls whether the LSPEN bit is writeable from the non-secure state" "Writeable,Write ignored"
|
|
newline
|
|
bitfld.long 0x00 28. " CLRONRET ,Clear floating point caller saved registers on exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " CLRONRETS ,Clear on return secure only" "Both states,Secure only"
|
|
bitfld.long 0x00 26. " TS ,Treat as secure" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " UFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the usage fault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 9. " SPLIMVIOL ,Indicates whether the FP context violates the stack pointer limit that was active when lazy state preservation was activated" "Low,High"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
newline
|
|
bitfld.long 0x00 7. " SFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the SecureFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
newline
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 2. " S ,Indicates the FP context belongs to the specified security state" "Non-secure,Secure"
|
|
newline
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x08 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
newline
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
bitfld.long 0x08 19. " FZ16 ,Flush-to-zero mode control bit on half-precision data-processing instructions" "Disabled,Enabled"
|
|
bitfld.long 0x08 16.--18. " LTPSIZE ,Vector element size used when applying low-overhead-loop tail predication to vector instructions" "8-bit,16-bit,32-bit,64-bit,Not applied,?..."
|
|
rgroup.long 0xF40++0x0B
|
|
line.long 0x00 "MVFR0,Media And FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" "Not supported,All supported,?..."
|
|
bitfld.long 0x00 20.--23. " FPSQRT ,Indicates the hardware support for FP square root operations" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" "Not supported,Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--11. " FPDP ,Indicates the hardware support for FP double precision operations" "Not supported,Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " FPSP ,Indicates the hardware support for FP single-precision operations" "Not supported,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" "Reserved,Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media And FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" "Not supported,Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" "Not supported,Half-single,Half-single/double,?..."
|
|
bitfld.long 0x04 20.--23. " FP16 ,Floating-point half-precision data processing" "Not supported,Supported,?..."
|
|
newline
|
|
bitfld.long 0x04 8.--11. " MVE ,Indicates support for M-profile vector extension" "Not supported,Supported no FP,Supported with FP,?..."
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the default NaN mode" "Not supported,NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the flush-to-zero mode of operation" "Not supported,Fully denormalized,?..."
|
|
line.long 0x08 "MVFR2,Media And FP Feature Register 2"
|
|
bitfld.long 0x08 4.--7. " VFP_MISC ,Indicates the hardware support for FP miscellaneous features" "Not supported,Reserved,Reserved,Reserved,Supported,?..."
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 13.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 5. " PMU ,Indicates whether a PMU counter overflow event has occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a vector catch" "Not triggered,Triggered"
|
|
newline
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates that a halt request debug event or step debug event has occurred" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGSEL ,Specifies the ARM core register special-purpose register or floating-point extension register"
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " MONPRKEY ,Writes to the MON_PEND and MON_REQ fields are ignored" "Not ignored,Ignored"
|
|
bitfld.long 0x04 21. " UMON_EN ,Unprivileged monitor enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x04 20. " SDME ,Indicates whether the DebugMonitor targets the secure or the non-secure state" "Non-secure,Secure"
|
|
bitfld.long 0x04 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x04 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x04 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x04 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Enable halting debug trap on a hard fault exception" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " VC_BUSERR ,Enable halting debug trap on a bus fault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " VC_STATERR ,Enable halting debug trap on a usage fault exception caused by a state information error" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " VC_CHKERR ,Enable halting debug trap on a usage fault exception caused by a checking error" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " VC_NOCPERR ,Enable halting debug trap on a usage fault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Enable reset vector catch" "Disabled,Enabled"
|
|
group.long 0xE04++0x07
|
|
line.long 0x00 "DAUTHCTRL,Debug Authentication Control Register"
|
|
bitfld.long 0x00 10. " UIDEN ,Unprivileged invasive debug enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " UIDAPEN ,Unprivileged invasive DAP access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FSDMA ,Force secure debug monitor allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 3. " INTSPNIDEN ,Internal secure non-invasive debug enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SPNIDENSEL ,Secure non-invasive debug enable select" "Ext. auth. interface,DAUTHCTRL.INTSPNIDEN"
|
|
bitfld.long 0x00 1. " INTSPIDEN ,Internal secure invasive debug enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " SPIDENSEL ,Secure invasive debug enable select" "Ext. auth. interface,DAUTHCTRL.INTSPIDEN"
|
|
line.long 0x04 "DSCSR,Debug Security Control and Status Register"
|
|
bitfld.long 0x04 17. " CDSKEY ,CDS write-enable key" "Not ignored,Ignored"
|
|
bitfld.long 0x04 16. " CDS ,This field indicates the current security state of the processor" "Non-secure,Secure"
|
|
bitfld.long 0x04 1. " SBRSEL ,Secure banked register select" "Non-secure,Secure"
|
|
newline
|
|
bitfld.long 0x04 0. " SBRSELEN ,Secure banked register select enable" "Disabled,Enabled"
|
|
rgroup.long 0xFB8++0x03
|
|
line.long 0x00 "DAUTHSTATUS,Debug Authentication Status Register"
|
|
bitfld.long 0x00 22.--23. " SUNID ,Secure unprivileged non-invasive debug allowed" "Not implemented,Reserved,Prohibited,Allowed"
|
|
bitfld.long 0x00 20.--21. " SUID ,Secure unprivileged invasive debug allowed" "Not implemented,Reserved,Prohibited,Allowed"
|
|
bitfld.long 0x00 18.--19. " NSUNID ,Non-secure unprivileged non-invasive debug allowed" "Not implemented,Reserved,Prohibited,Allowed"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " NSUID ,Non-secure unprivileged invasive debug allowed" "Not implemented,Reserved,Prohibited,Allowed"
|
|
bitfld.long 0x00 6.--7. " SNID ,Secure non-invasive debug" "Not implemented,Reserved,Implemented/Disabled,Implemented/Enabled"
|
|
bitfld.long 0x00 4.--5. " SID ,Secure invasive debug" "Not implemented,Reserved,Implemented/Disabled,Implemented/Enabled"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " NSNID ,Non-secure non-invasive debug" "Reserved,Reserved,Prohibited,Allowed"
|
|
bitfld.long 0x00 0.--1. " NSID ,Non-secure invasive debug" "Reserved,Reserved,Prohibited,Allowed"
|
|
group.long 0x10300++0x07
|
|
line.long 0x00 "CPDLPSTATE,Core Power Domain Low Power State Register"
|
|
bitfld.long 0x00 8.--9. " RLPSTATE ,Power-on state for PDRAMS power domain" "ON,Reserved,Reserved,OFF"
|
|
bitfld.long 0x00 4.--5. " ELPSTATE ,Type of low-power state for PDEPU" "ON,ON clock off,RET,OFF"
|
|
bitfld.long 0x00 0.--1. " CLPSTATE ,Type of low-power state for PDCORE" "ON,ON clock off,RET,OFF"
|
|
line.long 0x04 "DPDLPSTATE,Debug Power Domain Low Power State Register"
|
|
bitfld.long 0x04 0.--1. " DLPSTATE ,Type of low-power state for PDDEBUG" "ON,ON clock off,Reserved,OFF"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "BreakPoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
rbitfld.long 0x00 28.--31. " REV ,Flash patch breakpoint architecture revision" "Reserved,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "Not implemented,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x00 1. " KEY ,FP_CTRL write-enable key" "Ignored,Permitted"
|
|
newline
|
|
bitfld.long 0x00 0. " ENABLE ,Flash patch unit enable" "Disabled,Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "FP_REMAP,Flash Patch Remap"
|
|
repeat 8. (increment 0x08 0x04) (increment 0. 1.)
|
|
group.long $1++0x03
|
|
line.long 0x00 "FP_COMP$2,Flash Patch Comparator Register $2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between remapping and breakpoint functionality" "Disabled,Enabled"
|
|
repeat.end
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Reserved,Present"
|
|
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "FPB v2,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "Reserved,FPB v2,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
|
width 10.
|
|
tree "Peripheral Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "FP_PIDR0,FP Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PART_NUM[7:0] ,Part number bits[7:0]"
|
|
line.long 0x04 "FP_PIDR1,FP Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PART_NUM[11:8] ,Part number bits[11:8]"
|
|
line.long 0x08 "FP_PIDR2,FP Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " REVISION ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "FP_PIDR3,FP Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " REVAND ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "FP_PIDR4,FP Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " COUNT ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "FP_CIDR0,FP Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "FP_CIDR1,FP Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
|
line.long 0x08 "FP_CIDR2,FP Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0C "FP_CIDR3,FP Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DWT_CTRL,DWT Control Register"
|
|
bitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "Not supported,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
bitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
newline
|
|
bitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 23. " CYCDISS ,Controls whether the cycle counter is prevented from incrementing while the PE is in secure state" "No,Yes"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow event counter packets generation" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the sleep counter overflow event" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " PCSAMPLENA ,Enables use of POSTCNT counter as a timer for periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
newline
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x2000000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DWT_CYCCNT,DWT Cycle Count Register"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "DWT_CYCCNT,DWT Cycle Count Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))))&0x1000000)==0x00)
|
|
group.long 0x08++0x13
|
|
line.long 0x00 "DWT_CPICNT,DWT CPI Count Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPICNT ,Base instruction overhead counter"
|
|
line.long 0x04 "DWT_EXCCNT,DWT Exception Overhead Count Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x08 "DWT_SLEEPCNT,DWT Sleep Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " SLEEPCNT ,Sleep counter"
|
|
line.long 0x0C "DWT_LSUCNT,DWT LSU Count Register"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " LSUCNT ,Load-store overhead counter"
|
|
line.long 0x10 "DWT_FOLDCNT,DWT Folded-instruction Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
else
|
|
rgroup.long 0x08++0x13
|
|
line.long 0x00 "DWT_CPICNT,DWT CPI Count Register"
|
|
line.long 0x04 "DWT_EXCCNT,DWT Exception Overhead Count Register"
|
|
line.long 0x08 "DWT_SLEEPCNT,DWT Sleep Count Register"
|
|
line.long 0x0C "DWT_LSUCNT,DWT LSU Count Register"
|
|
line.long 0x10 "DWT_FOLDCNT,DWT Folded-instruction Count Register"
|
|
endif
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,DWT Program Counter Sample Register"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08))&0x0E)==0x02)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " PCVALUE ,PC value"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
endif
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Register 0"
|
|
rbitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr with value,Cycle counter/data addr/data addr with value,Instruction addr/data addr/data addr with value,Cycle counter/instruction addr/data addr/data addr with value,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr limit/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data addr with value,Reserved,Data addr/data addr limit/data value/linked data value/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data value/linked data value/data addr with value,?..."
|
|
newline
|
|
rbitfld.long 0x00 24. " MATCHED ,Comparator matched" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data value size" "1B,2B,4B,?..."
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace data address"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x0E)==0x02)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " PCVALUE ,PC value"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
endif
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Register 1"
|
|
rbitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr with value,Cycle counter/data addr/data addr with value,Instruction addr/data addr/data addr with value,Cycle counter/instruction addr/data addr/data addr with value,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr limit/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data addr with value,Reserved,Data addr/data addr limit/data value/linked data value/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data value/linked data value/data addr with value,?..."
|
|
newline
|
|
rbitfld.long 0x00 24. " MATCHED ,Comparator matched" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data value size" "1B,2B,4B,?..."
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace data address"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0x0C)==0x08)
|
|
group.long (0x30+0x0C)++0x03
|
|
line.long 0x00 "DWT_VMASK1,DWT Comparator Value Mask Register"
|
|
bitfld.long 0x00 31. " VMASK[31] ,Data value mask 31" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " [30] ,Data value mask 30" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " [29] ,Data value mask 29" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,Data value mask 28" "Not masked,Masked"
|
|
bitfld.long 0x00 27. " [27] ,Data value mask 27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " [26] ,Data value mask 26" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Data value mask 25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " [24] ,Data value mask 24" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " [23] ,Data value mask 23" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Data value mask 22" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " [21] ,Data value mask 21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " [20] ,Data value mask 20" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Data value mask 19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " [18] ,Data value mask 18" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " [17] ,Data value mask 17" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Data value mask 16" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " [15] ,Data value mask 15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " [14] ,Data value mask 14" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Data value mask 13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " [12] ,Data value mask 12" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " [11] ,Data value mask 11" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Data value mask 10" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " [9] ,Data value mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " [8] ,Data value mask 8" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Data value mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " [6] ,Data value mask 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " [5] ,Data value mask 5" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Data value mask 4" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " [3] ,Data value mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " [2] ,Data value mask 2" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Data value mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Data value mask 0" "Not masked,Masked"
|
|
else
|
|
rgroup.long (0x30+0x0C)++0x03
|
|
line.long 0x00 "DWT_VMASK1,DWT Comparator Value Mask Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x0E)==0x02)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " PCVALUE ,PC value"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
endif
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Register 2"
|
|
rbitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr with value,Cycle counter/data addr/data addr with value,Instruction addr/data addr/data addr with value,Cycle counter/instruction addr/data addr/data addr with value,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr limit/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data addr with value,Reserved,Data addr/data addr limit/data value/linked data value/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data value/linked data value/data addr with value,?..."
|
|
newline
|
|
rbitfld.long 0x00 24. " MATCHED ,Comparator matched" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data value size" "1B,2B,4B,?..."
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace data address"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x0E)==0x02)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " PCVALUE ,PC value"
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
endif
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Register 3"
|
|
rbitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr with value,Cycle counter/data addr/data addr with value,Instruction addr/data addr/data addr with value,Cycle counter/instruction addr/data addr/data addr with value,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr limit/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data addr with value,Reserved,Data addr/data addr limit/data value/linked data value/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data value/linked data value/data addr with value,?..."
|
|
newline
|
|
rbitfld.long 0x00 24. " MATCHED ,Comparator matched" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data value size" "1B,2B,4B,?..."
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace data address"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0x0C)==0x08)
|
|
group.long (0x50+0x0C)++0x03
|
|
line.long 0x00 "DWT_VMASK3,DWT Comparator Value Mask Register"
|
|
bitfld.long 0x00 31. " VMASK[31] ,Data value mask 31" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " [30] ,Data value mask 30" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " [29] ,Data value mask 29" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,Data value mask 28" "Not masked,Masked"
|
|
bitfld.long 0x00 27. " [27] ,Data value mask 27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " [26] ,Data value mask 26" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Data value mask 25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " [24] ,Data value mask 24" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " [23] ,Data value mask 23" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Data value mask 22" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " [21] ,Data value mask 21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " [20] ,Data value mask 20" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Data value mask 19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " [18] ,Data value mask 18" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " [17] ,Data value mask 17" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Data value mask 16" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " [15] ,Data value mask 15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " [14] ,Data value mask 14" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Data value mask 13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " [12] ,Data value mask 12" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " [11] ,Data value mask 11" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Data value mask 10" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " [9] ,Data value mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " [8] ,Data value mask 8" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Data value mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " [6] ,Data value mask 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " [5] ,Data value mask 5" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Data value mask 4" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " [3] ,Data value mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " [2] ,Data value mask 2" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Data value mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Data value mask 0" "Not masked,Masked"
|
|
else
|
|
rgroup.long (0x50+0x0C)++0x03
|
|
line.long 0x00 "DWT_VMASK3,DWT Comparator Value Mask Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08))&0x0E)==0x02)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " PCVALUE ,PC value"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
endif
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION4,DWT Function Register 4"
|
|
rbitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr with value,Cycle counter/data addr/data addr with value,Instruction addr/data addr/data addr with value,Cycle counter/instruction addr/data addr/data addr with value,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr limit/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data addr with value,Reserved,Data addr/data addr limit/data value/linked data value/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data value/linked data value/data addr with value,?..."
|
|
newline
|
|
rbitfld.long 0x00 24. " MATCHED ,Comparator matched" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data value size" "1B,2B,4B,?..."
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace data address"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08))&0x0E)==0x02)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " PCVALUE ,PC value"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
endif
|
|
group.long (0x70+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION5,DWT Function Register 5"
|
|
rbitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr with value,Cycle counter/data addr/data addr with value,Instruction addr/data addr/data addr with value,Cycle counter/instruction addr/data addr/data addr with value,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr limit/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data addr with value,Reserved,Data addr/data addr limit/data value/linked data value/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data value/linked data value/data addr with value,?..."
|
|
newline
|
|
rbitfld.long 0x00 24. " MATCHED ,Comparator matched" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data value size" "1B,2B,4B,?..."
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace data address"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08))&0x0E)==0x02)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " PCVALUE ,PC value"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
endif
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION6,DWT Function Register 6"
|
|
rbitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr with value,Cycle counter/data addr/data addr with value,Instruction addr/data addr/data addr with value,Cycle counter/instruction addr/data addr/data addr with value,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr limit/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data addr with value,Reserved,Data addr/data addr limit/data value/linked data value/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data value/linked data value/data addr with value,?..."
|
|
newline
|
|
rbitfld.long 0x00 24. " MATCHED ,Comparator matched" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data value size" "1B,2B,4B,?..."
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace data address"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08))&0x0E)==0x02)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " PCVALUE ,PC value"
|
|
else
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
endif
|
|
group.long (0x90+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION7,DWT Function Register 7"
|
|
rbitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr with value,Cycle counter/data addr/data addr with value,Instruction addr/data addr/data addr with value,Cycle counter/instruction addr/data addr/data addr with value,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Data addr/data addr limit/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data addr with value,Reserved,Data addr/data addr limit/data value/linked data value/data addr with value,Reserved,Instruction addr/instruction addr limit/data addr/data addr limit/data value/linked data value/data addr with value,?..."
|
|
newline
|
|
rbitfld.long 0x00 24. " MATCHED ,Comparator matched" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data value size" "1B,2B,4B,?..."
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace data address"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
|
|
hexmask.long.word 0x00 21.--31. 0x20 " ARCHITECT ,Component architect"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Reserved,Present"
|
|
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "DWT v2.0,DWT v2.1,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "Reserved,DWT v2,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
|
rgroup.long 0xFCC++0x03
|
|
line.long 0x00 "DWT_DEVTYPE,DWT Device Type Identifier Register"
|
|
bitfld.long 0x00 4.--7. " SUB ,Sub-type" "Other,?..."
|
|
bitfld.long 0x00 0.--3. " MAJOR ,Major type" "Miscellaneous,?..."
|
|
width 11.
|
|
tree "Peripheral Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "DWT_PIDR0,DWT Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PART_NUM[7:0] ,Part number bits[7:0]"
|
|
line.long 0x04 "DWT_PIDR1,DWT Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PART_NUM[11:8] ,Part number bits[11:8]"
|
|
line.long 0x08 "DWT_PIDR2,DWT Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " REVISION ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "DWT_PIDR3,DWT Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " REVAND ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x0F
|
|
line.long 0x00 "DWT_PIDR4,DWT Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " COUNT ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
line.long 0x04 "DWT_PIDR5,DWT Peripheral Identification Register 5"
|
|
line.long 0x08 "DWT_PIDR6,DWT Peripheral Identification Register 6"
|
|
line.long 0x0C "DWT_PIDR7,DWT Peripheral Identification Register 7"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "DWT_CIDR0,DWT Component Identification Register 0 (Preamble)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "DWT_CIDR1,DWT Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
|
line.long 0x08 "DWT_CIDR2,DWT Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0C "DWT_CIDR3,DWT Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Performance Monitoring Unit Extension (PMU)"
|
|
sif COMPonent.AVAILABLE("BMC")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))
|
|
width 16.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x08)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "PMU_EVCNTR0,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "PMU_EVCNTR1,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "PMU_EVCNTR2,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "PMU_EVCNTR3,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PMU_EVCNTR4,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PMU_EVCNTR5,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PMU_EVCNTR6,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PMU_EVCNTR7,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x07)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "PMU_EVCNTR0,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "PMU_EVCNTR1,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "PMU_EVCNTR2,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "PMU_EVCNTR3,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PMU_EVCNTR4,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PMU_EVCNTR5,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PMU_EVCNTR6,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "PMU_EVCNTR7,Performance Monitoring Unit Event Counter Register"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x06)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "PMU_EVCNTR0,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "PMU_EVCNTR1,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "PMU_EVCNTR2,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "PMU_EVCNTR3,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PMU_EVCNTR4,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PMU_EVCNTR5,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "PMU_EVCNTR6,Performance Monitoring Unit Event Counter Register"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "PMU_EVCNTR7,Performance Monitoring Unit Event Counter Register"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x05)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "PMU_EVCNTR0,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "PMU_EVCNTR1,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "PMU_EVCNTR2,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "PMU_EVCNTR3,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PMU_EVCNTR4,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "PMU_EVCNTR5,Performance Monitoring Unit Event Counter Register"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "PMU_EVCNTR6,Performance Monitoring Unit Event Counter Register"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "PMU_EVCNTR7,Performance Monitoring Unit Event Counter Register"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x04)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "PMU_EVCNTR0,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "PMU_EVCNTR1,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "PMU_EVCNTR2,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "PMU_EVCNTR3,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "PMU_EVCNTR4,Performance Monitoring Unit Event Counter Register"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "PMU_EVCNTR5,Performance Monitoring Unit Event Counter Register"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "PMU_EVCNTR6,Performance Monitoring Unit Event Counter Register"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "PMU_EVCNTR7,Performance Monitoring Unit Event Counter Register"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x03)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "PMU_EVCNTR0,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "PMU_EVCNTR1,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "PMU_EVCNTR2,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
hgroup.long 0xC++0x03
|
|
hide.long 0x00 "PMU_EVCNTR3,Performance Monitoring Unit Event Counter Register"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "PMU_EVCNTR4,Performance Monitoring Unit Event Counter Register"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "PMU_EVCNTR5,Performance Monitoring Unit Event Counter Register"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "PMU_EVCNTR6,Performance Monitoring Unit Event Counter Register"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "PMU_EVCNTR7,Performance Monitoring Unit Event Counter Register"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x02)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "PMU_EVCNTR0,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "PMU_EVCNTR1,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
hgroup.long 0x8++0x03
|
|
hide.long 0x00 "PMU_EVCNTR2,Performance Monitoring Unit Event Counter Register"
|
|
hgroup.long 0xC++0x03
|
|
hide.long 0x00 "PMU_EVCNTR3,Performance Monitoring Unit Event Counter Register"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "PMU_EVCNTR4,Performance Monitoring Unit Event Counter Register"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "PMU_EVCNTR5,Performance Monitoring Unit Event Counter Register"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "PMU_EVCNTR6,Performance Monitoring Unit Event Counter Register"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "PMU_EVCNTR7,Performance Monitoring Unit Event Counter Register"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x01)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "PMU_EVCNTR0,Performance Monitoring Unit Event Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Event counter"
|
|
hgroup.long 0x4++0x03
|
|
hide.long 0x00 "PMU_EVCNTR1,Performance Monitoring Unit Event Counter Register"
|
|
hgroup.long 0x8++0x03
|
|
hide.long 0x00 "PMU_EVCNTR2,Performance Monitoring Unit Event Counter Register"
|
|
hgroup.long 0xC++0x03
|
|
hide.long 0x00 "PMU_EVCNTR3,Performance Monitoring Unit Event Counter Register"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "PMU_EVCNTR4,Performance Monitoring Unit Event Counter Register"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "PMU_EVCNTR5,Performance Monitoring Unit Event Counter Register"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "PMU_EVCNTR6,Performance Monitoring Unit Event Counter Register"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "PMU_EVCNTR7,Performance Monitoring Unit Event Counter Register"
|
|
else
|
|
hgroup.long 0x0++0x03
|
|
hide.long 0x00 "PMU_EVCNTR0,Performance Monitoring Unit Event Counter Register"
|
|
hgroup.long 0x4++0x03
|
|
hide.long 0x00 "PMU_EVCNTR1,Performance Monitoring Unit Event Counter Register"
|
|
hgroup.long 0x8++0x03
|
|
hide.long 0x00 "PMU_EVCNTR2,Performance Monitoring Unit Event Counter Register"
|
|
hgroup.long 0xC++0x03
|
|
hide.long 0x00 "PMU_EVCNTR3,Performance Monitoring Unit Event Counter Register"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "PMU_EVCNTR4,Performance Monitoring Unit Event Counter Register"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "PMU_EVCNTR5,Performance Monitoring Unit Event Counter Register"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "PMU_EVCNTR6,Performance Monitoring Unit Event Counter Register"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "PMU_EVCNTR7,Performance Monitoring Unit Event Counter Register"
|
|
endif
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "PMU_CCNTR,Performance Monitoring Unit Cycle Counter Register"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x08)
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "PMU_EVTYPER0,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "PMU_EVTYPER1,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "PMU_EVTYPER2,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "PMU_EVTYPER3,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "PMU_EVTYPER4,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "PMU_EVTYPER5,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "PMU_EVTYPER6,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
group.long 0x41C++0x03
|
|
line.long 0x00 "PMU_EVTYPER7,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x07)
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "PMU_EVTYPER0,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "PMU_EVTYPER1,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "PMU_EVTYPER2,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "PMU_EVTYPER3,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "PMU_EVTYPER4,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "PMU_EVTYPER5,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "PMU_EVTYPER6,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
hgroup.long 0x41C++0x03
|
|
hide.long 0x00 "PMU_EVTYPER7,Performance Monitoring Unit Event Type and Filter Register"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x06)
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "PMU_EVTYPER0,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "PMU_EVTYPER1,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "PMU_EVTYPER2,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "PMU_EVTYPER3,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "PMU_EVTYPER4,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "PMU_EVTYPER5,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
hgroup.long 0x418++0x03
|
|
hide.long 0x00 "PMU_EVTYPER6,Performance Monitoring Unit Event Type and Filter Register"
|
|
hgroup.long 0x41C++0x03
|
|
hide.long 0x00 "PMU_EVTYPER7,Performance Monitoring Unit Event Type and Filter Register"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x05)
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "PMU_EVTYPER0,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "PMU_EVTYPER1,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "PMU_EVTYPER2,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "PMU_EVTYPER3,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "PMU_EVTYPER4,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
hgroup.long 0x414++0x03
|
|
hide.long 0x00 "PMU_EVTYPER5,Performance Monitoring Unit Event Type and Filter Register"
|
|
hgroup.long 0x418++0x03
|
|
hide.long 0x00 "PMU_EVTYPER6,Performance Monitoring Unit Event Type and Filter Register"
|
|
hgroup.long 0x41C++0x03
|
|
hide.long 0x00 "PMU_EVTYPER7,Performance Monitoring Unit Event Type and Filter Register"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x04)
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "PMU_EVTYPER0,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "PMU_EVTYPER1,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "PMU_EVTYPER2,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "PMU_EVTYPER3,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
hgroup.long 0x410++0x03
|
|
hide.long 0x00 "PMU_EVTYPER4,Performance Monitoring Unit Event Type and Filter Register"
|
|
hgroup.long 0x414++0x03
|
|
hide.long 0x00 "PMU_EVTYPER5,Performance Monitoring Unit Event Type and Filter Register"
|
|
hgroup.long 0x418++0x03
|
|
hide.long 0x00 "PMU_EVTYPER6,Performance Monitoring Unit Event Type and Filter Register"
|
|
hgroup.long 0x41C++0x03
|
|
hide.long 0x00 "PMU_EVTYPER7,Performance Monitoring Unit Event Type and Filter Register"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x03)
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "PMU_EVTYPER0,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "PMU_EVTYPER1,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "PMU_EVTYPER2,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
hgroup.long 0x40C++0x03
|
|
hide.long 0x00 "PMU_EVTYPER3,Performance Monitoring Unit Event Type and Filter Register"
|
|
hgroup.long 0x410++0x03
|
|
hide.long 0x00 "PMU_EVTYPER4,Performance Monitoring Unit Event Type and Filter Register"
|
|
hgroup.long 0x414++0x03
|
|
hide.long 0x00 "PMU_EVTYPER5,Performance Monitoring Unit Event Type and Filter Register"
|
|
hgroup.long 0x418++0x03
|
|
hide.long 0x00 "PMU_EVTYPER6,Performance Monitoring Unit Event Type and Filter Register"
|
|
hgroup.long 0x41C++0x03
|
|
hide.long 0x00 "PMU_EVTYPER7,Performance Monitoring Unit Event Type and Filter Register"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x02)
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "PMU_EVTYPER0,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "PMU_EVTYPER1,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
hgroup.long 0x408++0x03
|
|
hide.long 0x00 "PMU_EVTYPER2,Performance Monitoring Unit Event Type and Filter Register"
|
|
hgroup.long 0x40C++0x03
|
|
hide.long 0x00 "PMU_EVTYPER3,Performance Monitoring Unit Event Type and Filter Register"
|
|
hgroup.long 0x410++0x03
|
|
hide.long 0x00 "PMU_EVTYPER4,Performance Monitoring Unit Event Type and Filter Register"
|
|
hgroup.long 0x414++0x03
|
|
hide.long 0x00 "PMU_EVTYPER5,Performance Monitoring Unit Event Type and Filter Register"
|
|
hgroup.long 0x418++0x03
|
|
hide.long 0x00 "PMU_EVTYPER6,Performance Monitoring Unit Event Type and Filter Register"
|
|
hgroup.long 0x41C++0x03
|
|
hide.long 0x00 "PMU_EVTYPER7,Performance Monitoring Unit Event Type and Filter Register"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BMC",-1))+0xE00))&0x0F)==0x01)
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "PMU_EVTYPER0,Performance Monitoring Unit Event Type and Filter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EVTCOUNT ,Event number"
|
|
hgroup.long 0x404++0x03
|
|
hide.long 0x00 "PMU_EVTYPER1,Performance Monitoring Unit Event Type and Filter Register"
|
|
hgroup.long 0x408++0x03
|
|
hide.long 0x00 "PMU_EVTYPER2,Performance Monitoring Unit Event Type and Filter Register"
|
|
hgroup.long 0x40C++0x03
|
|
hide.long 0x00 "PMU_EVTYPER3,Performance Monitoring Unit Event Type and Filter Register"
|
|
hgroup.long 0x410++0x03
|
|
hide.long 0x00 "PMU_EVTYPER4,Performance Monitoring Unit Event Type and Filter Register"
|
|
hgroup.long 0x414++0x03
|
|
hide.long 0x00 "PMU_EVTYPER5,Performance Monitoring Unit Event Type and Filter Register"
|
|
hgroup.long 0x418++0x03
|
|
hide.long 0x00 "PMU_EVTYPER6,Performance Monitoring Unit Event Type and Filter Register"
|
|
hgroup.long 0x41C++0x03
|
|
hide.long 0x00 "PMU_EVTYPER7,Performance Monitoring Unit Event Type and Filter Register"
|
|
else
|
|
hgroup.long 0x400++0x03
|
|
hide.long 0x00 "PMU_EVTYPER0,Performance Monitoring Unit Event Type and Filter Register"
|
|
hgroup.long 0x404++0x03
|
|
hide.long 0x00 "PMU_EVTYPER1,Performance Monitoring Unit Event Type and Filter Register"
|
|
hgroup.long 0x408++0x03
|
|
hide.long 0x00 "PMU_EVTYPER2,Performance Monitoring Unit Event Type and Filter Register"
|
|
hgroup.long 0x40C++0x03
|
|
hide.long 0x00 "PMU_EVTYPER3,Performance Monitoring Unit Event Type and Filter Register"
|
|
hgroup.long 0x410++0x03
|
|
hide.long 0x00 "PMU_EVTYPER4,Performance Monitoring Unit Event Type and Filter Register"
|
|
hgroup.long 0x414++0x03
|
|
hide.long 0x00 "PMU_EVTYPER5,Performance Monitoring Unit Event Type and Filter Register"
|
|
hgroup.long 0x418++0x03
|
|
hide.long 0x00 "PMU_EVTYPER6,Performance Monitoring Unit Event Type and Filter Register"
|
|
hgroup.long 0x41C++0x03
|
|
hide.long 0x00 "PMU_EVTYPER7,Performance Monitoring Unit Event Type and Filter Register"
|
|
endif
|
|
rgroup.long 0x47C++0x03
|
|
line.long 0x00 "PMU_CCFILTR,Performance Monitoring Unit Cycle Counter Filter Register"
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "PMU_CNTENSET,Performance Monitoring Unit Count Enable Set Register"
|
|
bitfld.long 0x00 31. " C ,Cycle counter enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P7 ,Event counter PMN 7 enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Event counter PMN 6 enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " P5 ,Event counter PMN 5 enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Event counter PMN 4 enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,Event counter PMN 3 enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " P2 ,Event counter PMN 2 enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Event counter PMN 1 enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Event counter PMN 0 enable bit" "Disabled,Enabled"
|
|
group.long 0xC20++0x03
|
|
line.long 0x00 "PMU_CNTENCLR,Performance Monitoring Unit Count Enable Clear Register"
|
|
bitfld.long 0x00 31. " C ,Cycle counter enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P7 ,Event counter PMN 7 enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Event counter PMN 6 enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " P5 ,Event counter PMN 5 enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Event counter PMN 4 enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,Event counter PMN 3 enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " P2 ,Event counter PMN 2 enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Event counter PMN 1 enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Event counter PMN 0 enable bit" "Disabled,Enabled"
|
|
group.long 0xC40++0x03
|
|
line.long 0x00 "PMU_INTENSET,Performance Monitoring Unit Interrupt Enable Set Register"
|
|
bitfld.long 0x00 31. " C ,CCNT overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P7 ,PMCNT7 overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,PMCNT6 overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " P5 ,PMCNT5 overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,PMCNT4 overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " P2 ,PMCNT2 overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,PMCNT1 overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,PMCNT0 overflow interrupt enable" "Disabled,Enabled"
|
|
group.long 0xC60++0x03
|
|
line.long 0x00 "PMU_INTENCLR,Performance Monitoring Unit Interrupt Enable Clear Register"
|
|
bitfld.long 0x00 31. " C ,CCNT overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " P7 ,PMCNT7 overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,PMCNT6 overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " P5 ,PMCNT5 overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,PMCNT4 overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,PMCNT3 overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " P2 ,PMCNT2 overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,PMCNT1 overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,PMCNT0 overflow interrupt enable" "Disabled,Enabled"
|
|
group.long 0xC80++0x03
|
|
line.long 0x00 "PMU_OVSCLR,Performance Monitoring Unit Overflow Flag Status Clear Register"
|
|
bitfld.long 0x00 31. " C ,PMCCNTR overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 7. " P7 ,PMN7 overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 6. " P6 ,PMN6 overflow" "No overflow,Overflow"
|
|
newline
|
|
bitfld.long 0x00 5. " P5 ,PMN5 overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 4. " P4 ,PMN4 overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 3. " P3 ,PMN3 overflow" "No overflow,Overflow"
|
|
newline
|
|
bitfld.long 0x00 2. " P2 ,PMN2 overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 1. " P1 ,PMN1 overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 0. " P0 ,PMN0 overflow" "No overflow,Overflow"
|
|
wgroup.long 0xCA0++0x03
|
|
line.long 0x00 "PMU_SWINC,Performance Monitoring Unit Software Increment Register"
|
|
bitfld.long 0x00 7. " P7 ,PMN7 software increment" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,PMN6 software increment" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,PMN5 software increment" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " P4 ,PMN4 software increment" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,PMN3 software increment" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,PMN2 software increment" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " P1 ,PMN1 software increment" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,PMN0 software increment" "Disabled,Enabled"
|
|
group.long 0xCC0++0x03
|
|
line.long 0x00 "PMU_OVSSET,Performance Monitoring Unit Overflow Flag Status Set Register"
|
|
bitfld.long 0x00 31. " C ,PMCCNTR overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 7. " P7 ,PMN7 overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 6. " P6 ,PMN6 overflow" "No overflow,Overflow"
|
|
newline
|
|
bitfld.long 0x00 5. " P5 ,PMN5 overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 4. " P4 ,PMN4 overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 3. " P3 ,PMN3 Overflow" "No overflow,Overflow"
|
|
newline
|
|
bitfld.long 0x00 2. " P2 ,PMN2 overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 1. " P1 ,PMN1 overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 0. " P0 ,PMN0 overflow" "No overflow,Overflow"
|
|
rgroup.long 0xE00++0x03
|
|
line.long 0x00 "PMU_TYPE,Performance Monitoring Unit Type Register"
|
|
bitfld.long 0x00 23. " TRO ,Trace-on-overflow support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. " FZO ,Freeze-on-overflow support" "Not supported,Supported"
|
|
bitfld.long 0x00 14. " CC ,Dedicated cycle counter" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--13. " SIZE ,Size of counters" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
hexmask.long.byte 0x00 0.--7. 1. " N ,Number of event counters"
|
|
group.long 0xE04++0x03
|
|
line.long 0x00 "PMU_CTRL,Performance Monitors Unit Control Register"
|
|
bitfld.long 0x00 11. " TRO ,Trace-on-overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " FZO ,Freeze-on-overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DP ,Disable cycle counter in prohibited regions" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " C ,Clock counter reset" "No reset,Reset"
|
|
bitfld.long 0x00 1. " P ,Event counter reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " E ,Counters enable" "Disabled,Enabled"
|
|
rgroup.long 0xFB8++0x07
|
|
line.long 0x00 "PMU_AUTHSTATUS,Performance Monitoring Unit Authentication Status Register"
|
|
bitfld.long 0x00 22.--23. " SUNID ,Secure unprivileged non-invasive debug allowed" "Not implemented,Reserved,Prohibited,Allowed"
|
|
bitfld.long 0x00 20.--21. " SUID ,Secure unprivileged invasive debug allowed" "Not implemented,Reserved,Prohibited,Allowed"
|
|
bitfld.long 0x00 18.--19. " NSUNID ,Non-secure unprivileged non-invasive debug allowed" "Not implemented,Reserved,Prohibited,Allowed"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " NSUID ,Non-secure unprivileged invasive debug allowed" "Not implemented,Reserved,Prohibited,Allowed"
|
|
bitfld.long 0x00 6.--7. " SNID ,Secure non-invasive debug" "Not implemented,Reserved,Implemented/Prohibited,Implemented/Allowed"
|
|
bitfld.long 0x00 4.--5. " SID ,Secure invasive debug" "Not implemented,Reserved,Implemented/Prohibited,Implemented/Allowed"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " NSNID ,Non-secure non-invasive debug" "Reserved,Reserved,Prohibited,Allowed"
|
|
bitfld.long 0x00 0.--1. " NSID ,Non-secure invasive debug" "Reserved,Reserved,Prohibited,Allowed"
|
|
line.long 0x04 "PMU_DEVARCH,Performance Monitoring Unit Device Architecture Register"
|
|
hexmask.long.word 0x04 21.--31. 1. " ARCHITECT ,Defines the architect of the component"
|
|
bitfld.long 0x04 20. " PRESENT ,Defines that the DEVARCH register is present" "Reserved,Present"
|
|
bitfld.long 0x04 16.--19. " REVISION ,Defines the architecture revision" "Armv8.1-M,?..."
|
|
newline
|
|
hexmask.long.word 0x04 0.--15. 1. " ARCHID ,Defines this part to be a ARMv8-M debug component"
|
|
rgroup.long 0xFCC++0x03
|
|
line.long 0x00 "PMU_DEVTYPE,Device Type Register"
|
|
bitfld.long 0x00 4.--7. " SUB ,Sub-type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " MAJOR ,Major type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree "Peripheral Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PMU_PIDR0,PMU Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PART_NUM[7:0] ,Part number bits[7:0]"
|
|
line.long 0x04 "PMU_PIDR1,PMU Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PART_NUM[11:8] ,Part number bits[11:8]"
|
|
line.long 0x08 "PMU_PIDR2,PMU Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " REVISION ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PMU_PIDR3,PMU Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " REVAND ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x0F
|
|
line.long 0x00 "PMU_PIDR4,PMU Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " COUNT ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
line.long 0x04 "PMU_PIDR5,PMU Peripheral Identification Register 5"
|
|
line.long 0x08 "PMU_PIDR6,PMU Peripheral Identification Register 6"
|
|
line.long 0x0C "PMU_PIDR7,PMU Peripheral Identification Register 7"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "PMU_CIDR0,PMU Component Identification Register 0 (Preamble)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "PMU_CIDR1,PMU Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class preamble"
|
|
line.long 0x08 "PMU_CIDR2,PMU Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0C "PMU_CIDR3,PMU Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "BMC component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|