28609 lines
1.8 MiB
28609 lines
1.8 MiB
; --------------------------------------------------------------------------------
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; @Title: ATSAMG On-Chip Peripherals
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; @Props: Released
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; @Author: KAO, LSD, ADP
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; @Changelog: 2014-02-26 KAO,
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; 2016-02-16 LSD
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; @Manufacturer: ATMEL - Atmel Corporation
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; @Doc: Atmel-11209-32-bit-Cortex-M4-Microcontroller-SAM-G51_Datasheet.pdf (rev. 2014-11-19)
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; Atmel-11240-32-bit-Cortex-M4-Microcontroller-SAM-G53_Datasheet.pdf (rev. 2015-07-24)
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; Atmel-11266-32-bit Cortex-M4-Microcontroller-SAM-G54_Datasheet.pdf (rev. 2014-12-16)
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; Atmel-11289-32-bit-Cortex-M4-Microcontroller-SAM-G55_Datasheet.pdf (rev. 2015-11-30)
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; @Core: Cortex-M4
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; @Chip: ATSAMG51 ATSAMG53 ATSAMG54 ATSAMG55
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; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: peratsamg.per 17736 2024-04-08 09:26:07Z kwisniewski $
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;Known Problems:
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;-CRCCU: Need to add SRAM mapped registers
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;-CCMC: CMCC_MAINT1 register WAY : The size of INDEX field depends on the cache
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; size, however it is not clearly explained, whether it should expand towards
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; left or right. Refer to page 313 in G55 data sheet
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tree.close "Core Registers (Cortex-M4F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
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bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
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bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
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group.long 0x10++0x0B
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
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bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x07
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line.long 0x00 "HFSR,Hard Fault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
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bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
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group.long 0xD34++0x0B
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line.long 0x00 "MMFAR,MemManage Fault Address Register"
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line.long 0x04 "BFAR,BusFault Address Register"
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line.long 0x08 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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width 10.
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tree "Feature Registers"
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
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|
bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
config 16. 8.
|
|
tree "RSTC (Reset Controller)"
|
|
base ad:0x400E1400
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "RSTC_CR,Controller Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,System Reset Key"
|
|
bitfld.long 0x00 3. " EXTRST ,External Reset" "No effect,Reset"
|
|
bitfld.long 0x00 2. " PERRST ,Peripheral Reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " PROCRST ,Processor Reset" "No effect,Reset"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "RSTC_SR,Reset Controller Status Register"
|
|
bitfld.long 0x00 17. " SRCMP ,Software Reset Command in Progress" "No command,Command"
|
|
bitfld.long 0x00 16. " NRSTL ,NRST Pin Level" "0,1"
|
|
sif (cpu()=="ATSAMG55")
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " RSTTYP ,Reset Type" "GENERAL_RST,BACKUP_RST,WDT_RST,SOFT_RST,USER_RST,,,SLCK_XTAL_RST"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " RSTTYP ,Reset Type" "GENERAL_RST,,WDT_RST,SOFT_RST,USER_RST,?...,,"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " URSTS ,User Reset Status" "No reset,Reset"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RSTC_MR,Reset Controller Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Write Access Password"
|
|
bitfld.long 0x00 8.--11. " ERSTL ,External Reset Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4. " URSTIEN ,User Reset Interrupt Enable" "No effect,Enabled"
|
|
sif (cpu()=="ATSAMG55")
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCKSW ,Slow Clock Switching" "No effect,Reset"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " URSTEN ,User Reset Enable" "Not enabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "RTT (Real-time Timer)"
|
|
base ad:0x400E1430
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "RTT_MR,Mode Register"
|
|
bitfld.long 0x00 24. " RTC1HZ ,Real-Time Clock 1 Hz Clock Selection" "16-bit Prescaler,1 Hz clock"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 22. " EVAEN ,Trigger Event Alarm Enable" "Not source,Source"
|
|
bitfld.long 0x00 21. " INC2AEN ,RTTINC2 Alarm Enable" "Not source,Source"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " RTTDIS ,Real-time Timer Disable" "No,Yes"
|
|
bitfld.long 0x00 18. " RTTRST ,Real-time Timer Restart" "No effect,Restart"
|
|
bitfld.long 0x00 17. " RTTINCIEN ,Real-time Timer Increment Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ALMIEN ,Alarm Interrupt Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--15. 1. " RTPRES ,Real-time Timer Prescaler Value"
|
|
line.long 0x04 "RTT_AR,Alarm Register"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "RTT_VR,Value Register"
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "RTT_SR,Status Register"
|
|
in
|
|
sif (cpu()=="ATSAMG55")
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "RTT_MODR,Modulo Selection Register"
|
|
bitfld.long 0x00 8.--10. " SELTRGEV ,Generate Trigger Event Select" "NO_EVENT,MOD2,MOD4,MOD8,MOD16,MOD32,MOD64,MOD128"
|
|
bitfld.long 0x00 0.--2. " SELINC2 ,Counter Modulo Select" "NO_RTTINC2,MOD64,MOD128,MOD256,MOD512,MOD1024,MOD2048,MOD4096"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "RTC (Real-time Clock)"
|
|
sif cpuis("ATSAMG55")
|
|
base ad:0x400E1460
|
|
width 8.
|
|
if (((per.l(ad:0x400E1460+0xE4))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 16.--17. " CALEVSEL ,Calendar event selection" "Week change,Month change,Year change,?..."
|
|
bitfld.long 0x00 8.--9. " TIMEVSEL ,Time event selection" "Minute change,Hour change,Every midnight,Every noon"
|
|
bitfld.long 0x00 1. " UPDCAL ,Update request calendar register" "No effect,Stopped"
|
|
bitfld.long 0x00 0. " UPDTIM ,Update request time register" "No effect,Stopped"
|
|
else
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 16.--17. " CALEVSEL ,Calendar event selection" "Week change,Month change,Year change,?..."
|
|
bitfld.long 0x00 8.--9. " TIMEVSEL ,Time event selection" "Minute change,Hour change,Every midnight,Every noon"
|
|
bitfld.long 0x00 1. " UPDCAL ,Update request calendar register" "No effect,Stopped"
|
|
bitfld.long 0x00 0. " UPDTIM ,Update request time register" "No effect,Stopped"
|
|
endif
|
|
newline
|
|
if (((per.l(ad:0x400E1460+0xE4))&0x01)==0x00)
|
|
width 8.
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
sif !cpuis("ATSAMG55")
|
|
bitfld.long 0x00 28.--29. " TPERIOD ,Period of the output pulse" "1 s,500 ms,250 ms,125 ms"
|
|
bitfld.long 0x00 24.--26. " THIGH ,High duration of the output pulse" "31.2 ms,15.6 ms,3.91 ms,967 u_s,488 u_s,122 u_s,30.5 u_s,15.2 u_s"
|
|
newline
|
|
endif
|
|
sif cpuis("ATSAMG55")
|
|
bitfld.long 0x00 20.--22. " OUT1 ,RTCOUT1 output source selection" "NO_WAVE,1 Hz wave,32 Hz wave,64 Hz wave,512 Hz wave,ALARM_TOGGLE,ALARM_FLAG,?..."
|
|
bitfld.long 0x00 16.--18. " OUT0 ,RTCOUT0 output source selection" "NO_WAVE,1 Hz wave,32 Hz wave,64 Hz wave,512 Hz wave,ALARM_TOGGLE,ALARM_FLAG,?..."
|
|
else
|
|
bitfld.long 0x00 20.--22. " OUT1 ,RTCOUT1 output source selection" "NO_WAVE,1 Hz wave,32 Hz wave,64 Hz wave,512 Hz wave,ALARM_TOGGLE,ALARM_FLAG,PROG_PULSE"
|
|
bitfld.long 0x00 16.--18. " OUT0 ,RTCOUT0 output source selection" "NO_WAVE,1 Hz wave,32 Hz wave,64 Hz wave,512 Hz wave,ALARM_TOGGLE,ALARM_FLAG,PROG_PULSE"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " HIGHPPM ,HIGH PPM correction" "Lower range,Higher range"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CORRECTION ,Slow clock correction"
|
|
bitfld.long 0x00 4. " NEGPPM ,NEGative PPM correction" "Positive,Negative"
|
|
newline
|
|
bitfld.long 0x00 1. " PERSIAN ,PERSIAN calendar" "Gregorian,Persian"
|
|
bitfld.long 0x00 0. " HRMOD ,12/24 hour mode" "24,12"
|
|
if (((per.l(ad:0x400E1460+0x04)&0x01)==0x01)&&(per.l(ad:0x400E1460+0x08)&0x300000)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIMR,Time Register"
|
|
bitfld.long 0x00 22. " AMPM ,Ante meridiem / post meridiem indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 12.--14. " MIN ,Current minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x400E1460+0x04)&0x01)==0x01)&&(per.l(ad:0x400E1460+0x08)&0x300000)==0x100000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIMR,Time Register"
|
|
bitfld.long 0x00 22. " AMPM ,Ante meridiem / post meridiem indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 12.--14. " MIN ,Current minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x400E1460+0x04)&0x01)==0x01)&&(per.l(ad:0x400E1460+0x08)&0x300000)==(0x200000||0x300000))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIMR,Time Register"
|
|
bitfld.long 0x00 22. " AMPM ,Ante meridiem / post meridiem indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 12.--14. " MIN ,Current minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x400E1460+0x04)&0x01)==0x00)&&(per.l(ad:0x400E1460+0x08)&0x300000)==0x200000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIMR,Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 12.--14. " MIN ,Current minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x400E1460+0x04)&0x01)==0x00)&&(per.l(ad:0x400E1460+0x08)&0x300000)==(0x00||0x100000))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIMR,Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 12.--14. " MIN ,Current minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIMR,Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 12.--14. " MIN ,Current minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
if (((per.l(ad:0x400E1460+0x04)&0x02)==0x00)&&((per.l(ad:0x400E1460+0x0C)&0x30)==0x10))
|
|
if ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==0x20000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,-"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,-,-,-,-,-,-,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x30000000)==0x30000000)
|
|
if ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x010000||0x030000||0x050000||0x070000||0x080000))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,-,-,-,-,-,-,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x40000||0x60000||0x90000))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,-,-,-,-,-,-,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x110000))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,-,-,-,-,-,-,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x100000||0x120000))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,-,-,-,-,-,-,9,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,-,-,-,-,-,-,9,-,-,-,-,-,-"
|
|
endif
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x100000)==0x100000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,-,-,-,-,-,-,9,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,-,-,-,-,-,-,9,-,-,-,-,-,-"
|
|
endif
|
|
elif ((per.l(ad:0x400E1460+0x04)&0x02)==0x00)
|
|
if ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==0x20000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,-"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x30000000)==0x30000000)
|
|
if ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x10000||0x30000||0x50000||0x70000||0x70000))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x40000||0x60000||0x90000))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x110000))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x100000||0x120000))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x100000)==0x100000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x400E1460+0x0C)&0x30000000)==0x30000000)
|
|
if ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x010000||0x020000||0x030000||0x040000||0x050000||0x060000))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Saturday,Sunday,Monday,Tuesday,Wednesday,Thursday,Friday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,-,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,3,4,-,-,-,-,-,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x70000||0x80000||0x90000))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Saturday,Sunday,Monday,Tuesday,Wednesday,Thursday,Friday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,-,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,3,4,-,-,-,-,-,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x100000||0x110000||0x120000))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Saturday,Sunday,Monday,Tuesday,Wednesday,Thursday,Friday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,-,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,3,4,-,-,-,-,-,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Saturday,Sunday,Monday,Tuesday,Wednesday,Thursday,Friday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,-,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,3,4,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x100000)==0x100000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Saturday,Sunday,Monday,Tuesday,Wednesday,Thursday,Friday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,3,4,-,-,-,-,-,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Saturday,Sunday,Monday,Tuesday,Wednesday,Thursday,Friday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,-,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,3,4,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x400E1460+0x04)&0x01)==0x01)&&(per.l(ad:0x400E1460+0x10)&0x300000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour alarm enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " AMPM ,AM/PM indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 15. " MINEN ,Minute alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 7. " SECEN ,Second alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x400E1460+0x04)&0x01)==0x01)&&(per.l(ad:0x400E1460+0x10)&0x300000)==0x100000)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour alarm enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " AMPM ,AM/PM indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 15. " MINEN ,Minute alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 7. " SECEN ,Second alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x400E1460+0x04)&0x01)==0x01)&&(per.l(ad:0x400E1460+0x10)&0x300000)==(0x200000||0x300000))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour alarm enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " AMPM ,AM/PM indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 15. " MINEN ,Minute alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 7. " SECEN ,Second alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x400E1460+0x04)&0x01)==0x00)&&(per.l(ad:0x400E1460+0x10)&0x300000)==0x200000)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour alarm enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 15. " MINEN ,Minute alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 7. " SECEN ,Second alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x400E1460+0x04)&0x01)==0x00)&&(per.l(ad:0x400E1460+0x10)&0x300000)==(0x00||0x100000))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour alarm enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 15. " MINEN ,Minute alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 7. " SECEN ,Second alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour alarm enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 15. " MINEN ,Minute alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 7. " SECEN ,Second alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
if ((per.l(ad:0x400E1460+0x04)&0x08)==0x00)
|
|
if ((per.l(ad:0x400E1460+0x14)&0x1F0000)==0x20000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,-"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x14)&0x30000000)==0x30100000)
|
|
if ((per.l(ad:0x400E1460+0x14)&0x1F0000)==(0x10000||0x30000||0x50000||0x70000||0x70000))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x14)&0x1F0000)==(0x40000||0x60000||0x90000))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x14)&0x1F0000)==(0x110000))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x14)&0x1F0000)==(0x100000||0x120000))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
elif ((per.l(ad:0x400E1460+0x14)&0x100000)==0x100000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x400E1460+0x14)&0x30000000)==0x30100000)
|
|
if ((per.l(ad:0x400E1460+0x14)&0x1F0000)==(0x10000||0x20000||0x30000||0x40000||0x50000||0x60000))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x14)&0x1F0000)==(0x70000||0x80000||0x90000))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x14)&0x1F0000)==(0x100000||0x110000||0x120000))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Current month" "0,1"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
elif ((per.l(ad:0x400E1460+0x14)&0x100000)==0x100000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
else
|
|
width 8.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
sif !cpuis("ATSAMG55")
|
|
bitfld.long 0x00 28.--29. " TPERIOD ,Period of the output pulse" "1 s,500 ms,250 ms,125 ms"
|
|
bitfld.long 0x00 24.--26. " THIGH ,High duration of the output pulse" "31.2 ms,15.6 ms,3.91 ms,967 u_s,488 u_s,122 u_s,30.5 u_s,15.2 u_s"
|
|
newline
|
|
endif
|
|
sif cpuis("ATSAMG55")
|
|
bitfld.long 0x00 20.--22. " OUT1 ,RTCOUT1 output source selection" "NO_WAVE,1 Hz wave,32 Hz wave,64 Hz wave,512 Hz wave,ALARM_TOGGLE,ALARM_FLAG,?..."
|
|
bitfld.long 0x00 16.--18. " OUT0 ,RTCOUT0 output source selection" "NO_WAVE,1 Hz wave,32 Hz wave,64 Hz wave,512 Hz wave,ALARM_TOGGLE,ALARM_FLAG,?..."
|
|
else
|
|
bitfld.long 0x00 20.--22. " OUT1 ,RTCOUT1 output source selection" "NO_WAVE,1 Hz wave,32 Hz wave,64 Hz wave,512 Hz wave,ALARM_TOGGLE,ALARM_FLAG,PROG_PULSE"
|
|
bitfld.long 0x00 16.--18. " OUT0 ,RTCOUT0 output source selection" "NO_WAVE,1 Hz wave,32 Hz wave,64 Hz wave,512 Hz wave,ALARM_TOGGLE,ALARM_FLAG,PROG_PULSE"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " HIGHPPM ,HIGH PPM correction" "Lower range,Higher range"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CORRECTION ,Slow clock correction"
|
|
bitfld.long 0x00 4. " NEGPPM ,NEGative PPM correction" "Positive,Negative"
|
|
newline
|
|
bitfld.long 0x00 1. " PERSIAN ,PERSIAN calendar" "Gregorian,Persian"
|
|
bitfld.long 0x00 0. " HRMOD ,12/24 hour mode" "24,12"
|
|
if (((per.l(ad:0x400E1460+0x04)&0x01)==0x01)&&(per.l(ad:0x400E1460+0x08)&0x300000)==0x00)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TIMR,Time Register"
|
|
bitfld.long 0x00 22. " AMPM ,Ante meridiem / post meridiem indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 12.--14. " MIN ,Current minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x400E1460+0x04)&0x01)==0x01)&&(per.l(ad:0x400E1460+0x08)&0x300000)==0x100000)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TIMR,Time Register"
|
|
bitfld.long 0x00 22. " AMPM ,Ante meridiem / post meridiem indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 12.--14. " MIN ,Current minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x400E1460+0x04)&0x01)==0x01)&&(per.l(ad:0x400E1460+0x08)&0x300000)==(0x200000||0x300000))
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TIMR,Time Register"
|
|
bitfld.long 0x00 22. " AMPM ,Ante meridiem / post meridiem indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 12.--14. " MIN ,Current minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x400E1460+0x04)&0x01)==0x00)&&(per.l(ad:0x400E1460+0x08)&0x300000)==0x200000)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TIMR,Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 12.--14. " MIN ,Current minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x400E1460+0x04)&0x01)==0x00)&&(per.l(ad:0x400E1460+0x08)&0x300000)==(0x00||0x100000))
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TIMR,Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 12.--14. " MIN ,Current minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TIMR,Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 12.--14. " MIN ,Current minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
if (((per.l(ad:0x400E1460+0x04)&0x02)==0x00)&&((per.l(ad:0x400E1460+0x0C)&0x30)==0x10))
|
|
if ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==0x20000)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,-"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,-,-,-,-,-,-,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x30000000)==0x30000000)
|
|
if ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x010000||0x030000||0x050000||0x070000||0x080000))
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,-,-,-,-,-,-,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x40000||0x60000||0x90000))
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,-,-,-,-,-,-,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x110000))
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,-,-,-,-,-,-,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x100000||0x120000))
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,-,-,-,-,-,-,9,-,-,-,-,-,-"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,-,-,-,-,-,-,9,-,-,-,-,-,-"
|
|
endif
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x100000)==0x100000)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,-,-,-,-,-,-,9,-,-,-,-,-,-"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,-,-,-,-,-,-,9,-,-,-,-,-,-"
|
|
endif
|
|
elif ((per.l(ad:0x400E1460+0x04)&0x02)==0x00)
|
|
if ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==0x20000)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,-"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x30000000)==0x30000000)
|
|
if ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x10000||0x30000||0x50000||0x70000||0x70000))
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x40000||0x60000||0x90000))
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x110000))
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x100000||0x120000))
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x100000)==0x100000)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x400E1460+0x0C)&0x30000000)==0x30000000)
|
|
if ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x010000||0x020000||0x030000||0x040000||0x050000||0x060000))
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Saturday,Sunday,Monday,Tuesday,Wednesday,Thursday,Friday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,-,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,3,4,-,-,-,-,-,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x70000||0x80000||0x90000))
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Saturday,Sunday,Monday,Tuesday,Wednesday,Thursday,Friday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,-,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,3,4,-,-,-,-,-,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x100000||0x110000||0x120000))
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Saturday,Sunday,Monday,Tuesday,Wednesday,Thursday,Friday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,-,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,3,4,-,-,-,-,-,-,-,-,-,-,-"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Saturday,Sunday,Monday,Tuesday,Wednesday,Thursday,Friday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,-,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,3,4,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x100000)==0x100000)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Saturday,Sunday,Monday,Tuesday,Wednesday,Thursday,Friday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,3,4,-,-,-,-,-,-,-,-,-,-,-"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Saturday,Sunday,Monday,Tuesday,Wednesday,Thursday,Friday"
|
|
newline
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current year" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CENT ,Current century" "-,1,-,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,3,4,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x400E1460+0x04)&0x01)==0x01)&&(per.l(ad:0x400E1460+0x10)&0x300000)==0x00)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour alarm enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " AMPM ,AM/PM indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 15. " MINEN ,Minute alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 7. " SECEN ,Second alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x400E1460+0x04)&0x01)==0x01)&&(per.l(ad:0x400E1460+0x10)&0x300000)==0x100000)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour alarm enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " AMPM ,AM/PM indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 15. " MINEN ,Minute alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 7. " SECEN ,Second alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x400E1460+0x04)&0x01)==0x01)&&(per.l(ad:0x400E1460+0x10)&0x300000)==(0x200000||0x300000))
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour alarm enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " AMPM ,AM/PM indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 15. " MINEN ,Minute alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 7. " SECEN ,Second alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x400E1460+0x04)&0x01)==0x00)&&(per.l(ad:0x400E1460+0x10)&0x300000)==0x200000)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour alarm enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 15. " MINEN ,Minute alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 7. " SECEN ,Second alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x400E1460+0x04)&0x01)==0x00)&&(per.l(ad:0x400E1460+0x10)&0x300000)==(0x00||0x100000))
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour alarm enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 15. " MINEN ,Minute alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 7. " SECEN ,Second alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour alarm enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 15. " MINEN ,Minute alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 7. " SECEN ,Second alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
if ((per.l(ad:0x400E1460+0x04)&0x08)==0x00)
|
|
if ((per.l(ad:0x400E1460+0x14)&0x1F0000)==0x20000)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,-"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x14)&0x30000000)==0x30100000)
|
|
if ((per.l(ad:0x400E1460+0x14)&0x1F0000)==(0x10000||0x30000||0x50000||0x70000||0x70000))
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x14)&0x1F0000)==(0x40000||0x60000||0x90000))
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x14)&0x1F0000)==(0x110000))
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x14)&0x1F0000)==(0x100000||0x120000))
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
elif ((per.l(ad:0x400E1460+0x14)&0x100000)==0x100000)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x400E1460+0x14)&0x30000000)==0x30100000)
|
|
if ((per.l(ad:0x400E1460+0x14)&0x1F0000)==(0x10000||0x20000||0x30000||0x40000||0x50000||0x60000))
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x14)&0x1F0000)==(0x70000||0x80000||0x90000))
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1460+0x14)&0x1F0000)==(0x100000||0x110000||0x120000))
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Current month" "0,1"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
elif ((per.l(ad:0x400E1460+0x14)&0x100000)==0x100000)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
width 13.
|
|
newline
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
bitfld.long 0x00 5. " TDERR ,Time and/or date free running error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CALEV ,Calendar event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " TIMEV ,Time event" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 2. " SEC ,Second event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " ALARM ,Alarm flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " ACKUPD ,Acknowledge for update" "No,Yes"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "SCCR,Status Clear Command Register"
|
|
bitfld.long 0x00 5. " TDERR ,Time and/or date free running error clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " CALCLR ,Calendar event clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " TIMCLR ,Time event clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 2. " SECCLR ,Second event clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " ALRCLR ,Alarm flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " ACKCLR ,Acknowledge for update clear" "No effect,Clear"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IMR_SET/CLR,Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " TDERR ,Time and/or date event interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CAL ,Calendar event interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " TIM ,Time event interrupt mask" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " SEC ,Second event interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " ALR ,Alarm interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " ACK ,Acknowledge for update interrupt mask" "Disabled,Enabled"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "VER,Valid Entry Register"
|
|
bitfld.long 0x00 3. " NVCALALR ,Non-Valid calendar alarm" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " NVTIMALR ,Non-valid time alarm" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " NVCAL ,Non-valid calendar" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " NVTIM ,Non-valid time" "Not detected,Detected"
|
|
sif cpuis("ATSAMG55")
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "RTC_MSR,Milliseconds Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " MS ,Number of 1/1024 seconds elapsed within 1 second"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protection key"
|
|
bitfld.long 0x00 0. " WPEN ,Write protection enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
else
|
|
base ad:0x400E1460
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 16.--17. " CALEVSEL ,Calendar Event Selection" "Week change,Month change,Year change,?..."
|
|
bitfld.long 0x00 8.--9. " TIMEVSEL ,Time Event Selection" "Minute change,Hour change,Every midnight,Every noon"
|
|
bitfld.long 0x00 1. " UPDCAL ,Update Request Calendar Register" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UPDTIM ,Update Request Time Register" "No effect,Stopped"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
sif (cpuis("ATSAM4S*")||cpuis("ATSAMV7*")||cpuis("ATSAME70*"))
|
|
bitfld.long 0x00 28.--29. " TPERIOD ,Period of the Output Pulse" "1 s,500 ms,250 ms,125 ms"
|
|
bitfld.long 0x00 24.--26. " THIGH ,High Duration of the Output Pulse" "31.2 ms,15.6 ms,3.91 ms,976 us,488 us,122 us,30.5 us,15.2 us"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " OUT1 ,RTCOUT1 Output Source Selection" "NO_WAVE,1 Hz wave,32 Hz wave,64 Hz wave,512 Hz wave,ALARM_TOGGLE,ALARM_FLAG,PROG_PULSE"
|
|
bitfld.long 0x00 16.--18. " OUT0 ,RTCOUT0 Output Source Selection" "NO_WAVE,1 Hz wave,32 Hz wave,64 Hz wave,512 Hz wave,ALARM_TOGGLE,ALARM_FLAG,PROG_PULSE"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " HIGHPPM ,HIGH PPM Correction" "Lower range,Higher range"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CORRECTION ,Slow Clock Correction"
|
|
bitfld.long 0x00 4. " NEGPPM ,NEGative PPM Correction" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PERSIAN ,PERSIAN Calendar" "Gregorian,Persian"
|
|
bitfld.long 0x00 0. " HRMOD ,12/24 Hour Mode" "24,12"
|
|
if (((per.l(ad:0x400E1460+0x04)&0x1)==0x1)&&(per.l(ad:0x400E1460+0x08)&0x300000)==0x0)
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "TIMR,Time Register"
|
|
bitfld.long 0x00 22. " AMPM ,Ante Meridiem Post Meridiem Indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
elif (((per.l(ad:0x400E1460+0x04)&0x1)==0x1)&&(per.l(ad:0x400E1460+0x08)&0x300000)==0x100000)
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "TIMR,Time Register"
|
|
bitfld.long 0x00 22. " AMPM ,Ante Meridiem Post Meridiem Indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
elif (((per.l(ad:0x400E1460+0x04)&0x1)==0x1)&&(per.l(ad:0x400E1460+0x08)&0x300000)==(0x200000||0x300000))
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "TIMR,Time Register"
|
|
bitfld.long 0x00 22. " AMPM ,Ante Meridiem Post Meridiem Indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "-,-,-,-,-,-,-,-,-,- ,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
elif (((per.l(ad:0x400E1460+0x04)&0x1)==0x0)&&(per.l(ad:0x400E1460+0x08)&0x300000)==0x200000)
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "TIMR,Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
elif (((per.l(ad:0x400E1460+0x04)&0x1)==0x0)&&(per.l(ad:0x400E1460+0x08)&0x300000)==(0x0||0x100000))
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "TIMR,Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
else
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "TIMR,Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "-,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
endif
|
|
if ((per.l(ad:0x400E1460+0x04)&0x02)==0x00)
|
|
if ((per.l(ad:0x400E1460+0x0C)&0x30)==0x10)
|
|
if ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==0x20000)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,-"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,CurrentDAY in Current Week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,CurrentYEAR" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,-,-,-,-,-,-,9,?..."
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x30000000)==0x30000000)
|
|
if ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x010000||0x030000||0x050000||0x070000||0x080000))
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,CurrentDAY in Current Week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,CurrentYEAR" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,-,-,-,-,-,-,9,?..."
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x040000||0x060000||0x090000))
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,CurrentDAY in Current Week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,CurrentYEAR" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,-,-,-,-,-,-,9,?..."
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x110000))
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,CurrentDAY in Current Week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,CurrentYEAR" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,-,-,-,-,-,-,9,?..."
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x100000||0x120000))
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,CurrentDAY in Current Week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,CurrentYEAR" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,-,-,-,-,-,-,9,?..."
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,CurrentDAY in Current Week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,CurrentYEAR" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,-,-,-,-,-,-,9,?..."
|
|
endif
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x100000)==0x100000)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,CurrentDAY in Current Week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,CurrentYEAR" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,-,-,-,-,-,-,9,?..."
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,CurrentDAY in Current Week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,CurrentYEAR" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,-,-,-,-,-,-,9,?..."
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==0x20000)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,-"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,CurrentDAY in Current Week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,CurrentYEAR" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,-,-,-,-,-,-,-,-,-,?..."
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x30000000)==0x30000000)
|
|
if ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x10000||0x30000||0x50000||0x70000||0x70000))
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,CurrentDAY in Current Week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,CurrentYEAR" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,-,-,-,-,-,-,-,-,-,?..."
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x40000||0x60000||0x90000))
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,CurrentDAY in Current Week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,CurrentYEAR" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,-,-,-,-,-,-,-,-,-,?..."
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x110000))
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,CurrentDAY in Current Week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,CurrentYEAR" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,-,-,-,-,-,-,-,-,-,?..."
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x100000||0x120000))
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,CurrentDAY in Current Week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,CurrentYEAR" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,-,-,-,-,-,-,-,-,-,?..."
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,CurrentDAY in Current Week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,CurrentYEAR" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,-,-,-,-,-,-,-,-,-,?..."
|
|
endif
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x100000)==0x100000)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,CurrentDAY in Current Week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,CurrentYEAR" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,-,-,-,-,-,-,-,-,-,?..."
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,CurrentDAY in Current Week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,CurrentYEAR" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,2,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,-,-,-,-,-,-,-,-,-,?..."
|
|
endif
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x400E1460+0x0C)&0x30000000)==0x30000000)
|
|
if ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x010000||0x020000||0x030000||0x040000||0x050000||0x060000))
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,CurrentDAY in Current Week" "-,Saturday,Sunday,Monday,Tuesday,Wednesday,Thursday,Friday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,CurrentYEAR" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,-,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,3,4,-,-,-,-,-,?..."
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x070000||0x080000||0x090000))
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,CurrentDAY in Current Week" "-,Saturday,Sunday,Monday,Tuesday,Wednesday,Thursday,Friday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,CurrentYEAR" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,-,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,3,4,-,-,-,-,-,?..."
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x1F0000)==(0x100000||0x110000||0x120000))
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,CurrentDAY in Current Week" "-,Saturday,Sunday,Monday,Tuesday,Wednesday,Thursday,Friday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,CurrentYEAR" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,-,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,3,4,-,-,-,-,-,?..."
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,CurrentDAY in Current Week" "-,Saturday,Sunday,Monday,Tuesday,Wednesday,Thursday,Friday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,CurrentYEAR" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,-,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,3,4,-,-,-,-,-,?..."
|
|
endif
|
|
elif ((per.l(ad:0x400E1460+0x0C)&0x100000)==0x100000)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,CurrentDAY in Current Week" "-,Saturday,Sunday,Monday,Tuesday,Wednesday,Thursday,Friday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,CurrentYEAR" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,-,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,3,4,-,-,-,-,-,?..."
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,CurrentDAY in Current Week" "-,Saturday,Sunday,Monday,Tuesday,Wednesday,Thursday,Friday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,CurrentYEAR" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "-,1,-,-,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "-,-,-,3,4,-,-,-,-,-,?..."
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x400E1460+0x04)&0x1)==0x1)&&(per.l(ad:0x400E1460+0x10)&0x300000)==0x0)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " AMPM ,AM/PM Indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " MINEN ,Minute Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SECEN ,Second Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
elif (((per.l(ad:0x400E1460+0x04)&0x1)==0x1)&&(per.l(ad:0x400E1460+0x10)&0x300000)==0x100000)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " AMPM ,AM/PM Indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " MINEN ,Minute Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SECEN ,Second Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
elif (((per.l(ad:0x400E1460+0x04)&0x1)==0x1)&&(per.l(ad:0x400E1460+0x10)&0x300000)==(0x200000||0x300000))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " AMPM ,AM/PM Indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " MINEN ,Minute Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SECEN ,Second Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
elif (((per.l(ad:0x400E1460+0x04)&0x1)==0x0)&&(per.l(ad:0x400E1460+0x10)&0x300000)==0x200000)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " MINEN ,Minute Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SECEN ,Second Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
elif (((per.l(ad:0x400E1460+0x04)&0x1)==0x0)&&(per.l(ad:0x400E1460+0x10)&0x300000)==(0x0||0x100000))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " MINEN ,Minute Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SECEN ,Second Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "-,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " MINEN ,Minute Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SECEN ,Second Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
endif
|
|
if ((per.l(ad:0x400E1460+0x04)&0x8)==0x00)
|
|
if ((per.l(ad:0x400E1460+0x14)&0x1F0000)==0x20000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN , DATE Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current DATE" "0,1,2,-"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN , MONTH Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current MONTH" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,?..."
|
|
elif ((per.l(ad:0x400E1460+0x14)&0x30000000)==0x30100000)
|
|
if ((per.l(ad:0x400E1460+0x14)&0x1F0000)==(0x10000||0x30000||0x50000||0x70000||0x70000))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN , DATE Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current DATE" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN , MONTH Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current MONTH" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,?..."
|
|
elif ((per.l(ad:0x400E1460+0x14)&0x1F0000)==(0x40000||0x60000||0x90000))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN , DATE Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current DATE" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,- ,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN , MONTH Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current MONTH" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,?..."
|
|
elif ((per.l(ad:0x400E1460+0x14)&0x1F0000)==(0x110000))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN , DATE Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current DATE" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN , MONTH Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current MONTH" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,-,-,-,-,-,-,-,?..."
|
|
elif ((per.l(ad:0x400E1460+0x14)&0x1F0000)==(0x100000||0x120000))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN , DATE Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current DATE" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN , MONTH Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current MONTH" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,-,-,-,-,-,-,-,?..."
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN , DATE Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current DATE" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN , MONTH Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current MONTH" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,?..."
|
|
endif
|
|
elif ((per.l(ad:0x400E1460+0x14)&0x100000)==0x100000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN , DATE Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current DATE" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN , MONTH Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current MONTH" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,?..."
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN , DATE Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current DATE" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN , MONTH Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current MONTH" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,?..."
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x400E1460+0x14)&0x30000000)==0x30100000)
|
|
if ((per.l(ad:0x400E1460+0x14)&0x1F0000)==(0x10000||0x20000||0x30000||0x40000||0x50000||0x60000))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN , DATE Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current DATE" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN , MONTH Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current MONTH" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,?..."
|
|
elif ((per.l(ad:0x400E1460+0x14)&0x1F0000)==(0x70000||0x80000||0x90000))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN , DATE Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current DATE" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN , MONTH Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current MONTH" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,?..."
|
|
elif ((per.l(ad:0x400E1460+0x14)&0x1F0000)==(0x100000||0x110000||0x120000))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN , DATE Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current DATE" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN , MONTH Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current MONTH" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,-,-,-,-,-,-,-,?..."
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN , DATE Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current DATE" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN , MONTH Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current MONTH" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,?..."
|
|
endif
|
|
elif ((per.l(ad:0x400E1460+0x14)&0x100000)==0x100000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN , DATE Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current DATE" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN , MONTH Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current MONTH" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,-,-,-,-,-,-,-,?..."
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN , DATE Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current DATE" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN , MONTH Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Current MONTH" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "-,1,2,3,4,5,6,7,8,9,?..."
|
|
endif
|
|
endif
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
bitfld.long 0x00 5. " TDERR ,Time and/or Date Free Running Error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CALEV ,Calendar Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " TIMEV ,Time Event" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEC ,Second Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " ALARM ,Alarm Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " ACKUPD ,Acknowledge for Update" "No,Yes"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "SCCR,Status Clear Command Register"
|
|
bitfld.long 0x00 5. " TDERR ,Time and/or Date Free Running Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " CALCLR ,Calendar Event Clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " TIMCLR ,Time Event Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SECCLR ,Second Event Clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " ALRCLR ,Alarm Flag Clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " ACKCLR ,Acknowledge for Update Clear" "No effect,Clear"
|
|
textline " "
|
|
sif cpuis("ATSAME70*")
|
|
wgroup.long 0x20++0x07
|
|
line.long 0x00 "IER,RTC Interrupt Enable Register"
|
|
bitfld.long 0x00 5. " TDERREN ,Time and/or Date Error Interrupt Enable" "No effect,Enable"
|
|
line.long 0x04 "IDR,RTC Interrupt Disable Register"
|
|
bitfld.long 0x04 5. " TDERRDIS ,Time and/or Date Error Interrupt Disable" "No effect,Disable"
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
sif (cpuis("ATSAMA5D4*")||cpuis("ATSAM4S*")||cpuis("ATSAMV7")||cpuis("ATSAME70*")||cpuis("ATSAMG55"))
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " TDERR_set/clr ,Time and/or Date Event Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CAL_set/clr ,Calendar Event Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " TIM_set/clr ,Time Event Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " SEC_set/clr ,Second Event Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " ALR_set/clr ,Alarm Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " ACK_set/clr ,Acknowledge for Update Interrupt Mask" "Masked,Not masked"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "VER,Valid Entry Register"
|
|
bitfld.long 0x00 3. " NVCALALR ,Non-Valid Calendar Alarm" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " NVTIMALR ,Non-valid Time Alarm" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NVCAL ,Non-valid Calendar" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " NVTIM ,Non-valid Time" "Not detected,Detected"
|
|
sif cpuis("ATSAMA5D4*")
|
|
textline " "
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "TSTR0,TimeStamp Time Register 0"
|
|
bitfld.long 0x00 31. " BACKUP ,System Mode of the Tamper" "Not backup,Backup"
|
|
bitfld.long 0x00 24.--27. " TEVCNT ,Tamper Events Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22. " AMPM ,AM/PM Indicator of the Tamper" "AM,PM"
|
|
bitfld.long 0x00 16.--21. " HOUR ,Hours of the Tamper" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
hexmask.long.byte 0x00 8.--14. 1. " MIN ,Minutes of the Tamper"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SEC ,Seconds of the Tamper"
|
|
rgroup.long 0xBC++0x03
|
|
line.long 0x00 "TSTR1,TimeStamp Time Register 1"
|
|
bitfld.long 0x00 31. " BACKUP ,System Mode of the Tamper" "Not backup,Backup"
|
|
bitfld.long 0x00 22. " AMPM ,AM/PM Indicator of the Tamper" "AM,PM"
|
|
bitfld.long 0x00 16.--21. " HOUR ,Hours of the Tamper" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
hexmask.long.byte 0x00 8.--14. 1. " MIN ,Minutes of the Tamper"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SEC ,Seconds of the Tamper"
|
|
rgroup.long 0xB4++0x03
|
|
line.long 0x00 "TSDR0,TimeStamp Date Register 0"
|
|
bitfld.long 0x00 24.--29. " DATE ,Date of the Tamper" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Day of the Tamper" ",1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " MONTH ,Month of the Tamper" ",1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " YEAR ,Year of the Tamper"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CENT ,Century of the Tamper"
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "TSDR1,TimeStamp Date Register 1"
|
|
bitfld.long 0x00 24.--29. " DATE ,Date of the Tamper" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Day of the Tamper" ",1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--20. " MONTH ,Month of the Tamper" ",1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " YEAR ,Year of the Tamper"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CENT ,Century of the Tamper"
|
|
hgroup.long 0xB8++0x03
|
|
hide.long 0x00 "TSSR0,TimeStamp Source Register 0"
|
|
in
|
|
hgroup.long 0xC4++0x03
|
|
hide.long 0x00 "TSSR1,TimeStamp Source Register 1"
|
|
in
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0x400E1450
|
|
width 8.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "WDT_CR,Watchdog Timer Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password"
|
|
bitfld.long 0x00 0. " WDRSTT ,Watchdog Restart" "No effect,Restart"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "WDT_MR,Watchdog Timer Mode Register"
|
|
bitfld.long 0x00 29. " WDIDLEHLT ,Watchdog Idle Halt" "Run,Stopped"
|
|
bitfld.long 0x00 28. " WDDBGHLT ,Watchdog Debug Halt" "Run,Stopped"
|
|
hexmask.long.word 0x00 16.--27. 1. " WDD ,Watchdog Delta Value"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WDDIS ,Watchdog Disable" "No,Yes"
|
|
bitfld.long 0x00 14. " WDRPROC ,Watchdog Reset Processor" "All reset,Processor reset"
|
|
bitfld.long 0x00 13. " WDRSTEN ,Watchdog Reset Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " WDFIEN ,Watchdog Fault Interrupt Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--11. 1. " WDV ,Watchdog Counter Value"
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "WDT_SR,Watchdog Timer Status Register"
|
|
in
|
|
width 0xB
|
|
tree.end
|
|
tree "SUPC (Supply Controller)"
|
|
base ad:0x400E1410
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SUPC_CR,Supply Controller Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password"
|
|
bitfld.long 0x00 3. " XTALSEL ,Crystal Oscillator Select" "No effect,Select"
|
|
sif (cpu()=="ATSAMG55")
|
|
textline " "
|
|
bitfld.long 0x00 2. " VROFF ,Voltage Regulator Off" "No effect,Stop"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 2. " ZERO ,Zero" "0,"
|
|
endif
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "SUPC_SMMR,Supply Controller Supply Monitor Mode Register"
|
|
bitfld.long 0x00 13. " SMIEN ,Monitor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SMRSTEN ,Supply Monitor Reset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " SMSMPL ,Supply Monitor Sampling Period" "Disabled,Continuous,32 SLCK,256 SLCK,2048 SLCK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " SMTH ,Supply Monitor Threshold" "0,1,2,3,4,5,6,7,?..."
|
|
line.long 0x04 "SUPC_MR,Supply Controller Mode Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " KEY ,Password Key"
|
|
textline " "
|
|
sif (cpu()=="ATSAMG53"||cpu()=="ATSAMG54")
|
|
bitfld.long 0x04 23. " PSWITCH2 ,SRAM2 Power Switch" "Not powered,Powered"
|
|
bitfld.long 0x04 22. " PSWITCH1 ,SRAM1 Power Switch" "Not powered,Powered"
|
|
textline " "
|
|
elif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x04 23. " ONE ,One" ",1"
|
|
bitfld.long 0x04 22. " CTPSWITCH ,Cache Tag SRAM Power Switch" "Not powered,Powered"
|
|
bitfld.long 0x04 21. " CDPSWITCH ,Cache Data SRAM Power Switch" "Not powered,Powered"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 20. " OSCBYPASS ,Oscillator Bypass" "Not effect,Enabled"
|
|
bitfld.long 0x04 13. " BODDIS ,POR Core Disable" "No,Yes"
|
|
bitfld.long 0x04 12. " BODRSTEN ,POR Core Reset Enable" "Disabled,Enabled"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55")
|
|
textline " "
|
|
bitfld.long 0x04 9.--11. " VRVDD ,Voltage Regulator Output Voltage Selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 8. " VDDSEL ,VRVDD Field Selection" "FACTORY,USER_VRVDD"
|
|
endif
|
|
sif (cpu()=="ATSAMG55")
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "SUPC_WUMR,Supply Controller Wake-up Mode Register"
|
|
bitfld.long 0x00 16.--18. " LPDBC ,Low-power Debouncer Period" "Disabled,2_RTCOUT0,3_RTCOUT0,4_RTCOUT0,5_RTCOUT0,6_RTCOUT0,7_RTCOUT0,8_RTCOUT0"
|
|
bitfld.long 0x00 12.--14. " WKUPDBC ,Wake-up Inputs Debouncer Period" "Immediate,3_SCLK,32_SCLK,512_SCLK,4096_SCLK,32768_SCLK,?..."
|
|
bitfld.long 0x00 7. " LPDBCCLR ,Low-power Debouncer Clear" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LPDBCEN1 ,Low-power Debouncer Enable WKUP1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " LPDBCEN0 ,Low-power Debouncer Enable WKUP0" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RTCEN ,Real-time Clock Wake-up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RTTEN ,Real-time Timer Wake-up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SMEN ,Supply Monitor Wake-up Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SUPC_WUIR,System Controller Wake-up Inputs Register"
|
|
bitfld.long 0x04 31. " WKUPT15 ,Wake-up Input Type 15" "Low,High"
|
|
bitfld.long 0x04 30. " WKUPT14 ,Wake-up Input Type 14" "Low,High"
|
|
bitfld.long 0x04 29. " WKUPT13 ,Wake-up Input Type 13" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 28. " WKUPT12 ,Wake-up Input Type 12" "Low,High"
|
|
bitfld.long 0x04 27. " WKUPT11 ,Wake-up Input Type 11" "Low,High"
|
|
bitfld.long 0x04 26. " WKUPT10 ,Wake-up Input Type 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 25. " WKUPT9 ,Wake-up Input Type 9" "Low,High"
|
|
bitfld.long 0x04 24. " WKUPT8 ,Wake-up Input Type 8" "Low,High"
|
|
bitfld.long 0x04 23. " WKUPT7 ,Wake-up Input Type 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 22. " WKUPT6 ,Wake-up Input Type 6" "Low,High"
|
|
bitfld.long 0x04 21. " WKUPT5 ,Wake-up Input Type 5" "Low,High"
|
|
bitfld.long 0x04 20. " WKUPT4 ,Wake-up Input Type 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 19. " WKUPT3 ,Wake-up Input Type 3" "Low,High"
|
|
bitfld.long 0x04 18. " WKUPT2 ,Wake-up Input Type 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 17. " WKUPT1 ,Wake-up Input Type 1" "Low,High"
|
|
bitfld.long 0x04 16. " WKUPT0 ,Wake-up Input Type 0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 15. " WKUPEN15 ,Wake-up Input Enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " WKUPEN14 ,Wake-up Input Enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " WKUPEN13 ,Wake-up Input Enable 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " WKUPEN12 ,Wake-up Input Enable 12" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " WKUPEN11 ,Wake-up Input Enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " WKUPEN10 ,Wake-up Input Enable 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " WKUPEN9 ,Wake-up Input Enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " WKUPEN8 ,Wake-up Input Enable 8" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " WKUPEN7 ,Wake-up Input Enable 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " WKUPEN6 ,Wake-up Input Enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " WKUPEN5 ,Wake-up Input Enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " WKUPEN4 ,Wake-up Input Enable 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " WKUPEN3 ,Wake-up Input Enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " WKUPEN2 ,Wake-up Input Enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " WKUPEN1 ,Wake-up Input Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " WKUPEN0 ,Wake-up Input Enable 0" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "SUPC_SR,Supply Controller Status Register"
|
|
in
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "SYSC_WPMR,System Controller Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protection Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
sif (cpu()=="ATSAMG55")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SUPC_PWMR,Supply Controller Power Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password Key"
|
|
bitfld.long 0x00 23. " DPRAMON ,Dual-port RAM Power Control" "Off,On"
|
|
bitfld.long 0x00 22. " SRAM6ON ,SRAM Power Control" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SRAM5ON ,SRAM Power Control" "Off,On"
|
|
bitfld.long 0x00 20. " SRAM4ON ,SRAM Power Control" "Off,On"
|
|
bitfld.long 0x00 19. " SRAM3ON ,SRAM Power Control" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SRAM2ON ,SRAM Power Control" "Off,On"
|
|
bitfld.long 0x00 17. " SRAM1ON ,SRAM Power Control" "Off,On"
|
|
bitfld.long 0x00 16. " SRAM0ON ,SRAM Power Control" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ECPWR3 ,Enhanced Custom Power Value" "0,1"
|
|
bitfld.long 0x00 11. " ECPWR2 ,Enhanced Custom Power Value" "0,1"
|
|
bitfld.long 0x00 10. " ECPWR1 ,Enhanced Custom Power Value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ECPWR0 ,Enhanced Custom Power Value" "0,1"
|
|
bitfld.long 0x00 8. " ECPWRS ,Enhanced Custom Power Value Selection" "Factory,User"
|
|
bitfld.long 0x00 7. " STUPTIME ,Start-up Time when Resuming from Wait Mode" "Fast,Slow"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LPOWER3 ,Low Power Value" "0,1"
|
|
bitfld.long 0x00 3. " LPOWER2 ,Low Power Value" "0,1"
|
|
bitfld.long 0x00 2. " LPOWER1 ,Low Power Value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LPOWER0 ,Low Power Value" "0,1"
|
|
bitfld.long 0x00 0. " LPOWERS ,Low Power Value Selection" "Factory,User"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "GPBR (General-Purpose Backup Registers)"
|
|
base ad:0x400E1490
|
|
width 8.
|
|
sif (cpuis("AT91SAM3S8*")||cpuis("AT91SAM3N*")||cpuis("ATSAM4N*")||cpuis("ATSAM4S*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMG5*"))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "GPBR0,General Purpose Backup Register 0"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "GPBR1,General Purpose Backup Register 1"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "GPBR2,General Purpose Backup Register 2"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "GPBR3,General Purpose Backup Register 3"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GPBR4,General Purpose Backup Register 4"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPBR5,General Purpose Backup Register 5"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "GPBR6,General Purpose Backup Register 6"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPBR7,General Purpose Backup Register 7"
|
|
elif (cpuis("ATSAM4E*"))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "GPBR0,General Purpose Backup Register 0"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "GPBR1,General Purpose Backup Register 1"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "GPBR2,General Purpose Backup Register 2"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "GPBR3,General Purpose Backup Register 3"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GPBR4,General Purpose Backup Register 4"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPBR5,General Purpose Backup Register 5"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "GPBR6,General Purpose Backup Register 6"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPBR7,General Purpose Backup Register 7"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPBR8,General Purpose Backup Register 8"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GPBR9,General Purpose Backup Register 9"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "GPBR10,General Purpose Backup Register 10"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "GPBR11,General Purpose Backup Register 11"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "GPBR12,General Purpose Backup Register 12"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "GPBR13,General Purpose Backup Register 13"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "GPBR14,General Purpose Backup Register 14"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "GPBR15,General Purpose Backup Register 15"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPBR16,General Purpose Backup Register 16"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "GPBR17,General Purpose Backup Register 17"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "GPBR18,General Purpose Backup Register 18"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "GPBR19,General Purpose Backup Register 19"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "GPBR0,General Purpose Backup Register 0"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "GPBR1,General Purpose Backup Register 1"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "GPBR2,General Purpose Backup Register 2"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "GPBR3,General Purpose Backup Register 3"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "MEM2MEM (Memory to Memory)"
|
|
base ad:0x40028000
|
|
width 13.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "MEM2MEM_THR,Memory to Memory Transfer Holding Register"
|
|
hexmask.long 0x00 0.--31. 1. " THDATA ,Transfer Holding Data"
|
|
line.long 0x04 "MEM2MEM_MR,Memory to Memory Mode Register"
|
|
bitfld.long 0x04 0.--1. " TSIZE ,Transfer Size" "T_8BIT,T_16BIT,T_32BIT,?..."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MEM2MEM_IMR,Memory to Memory Interrupt Mask Register"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXEND_set/clr ,End of Transfer Interrupt Mask" "Masked,Not masked"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "MEM2MEM_ISR,Memory to Memory Interrupt Status Register"
|
|
bitfld.long 0x00 1. " RXBUFF_set/clr ,Buffer Full Interrupt Enable" "Inactive,Active"
|
|
bitfld.long 0x00 0. " RXEND_set/clr ,End of Transfer Interrupt Enable" "Inactive,Active"
|
|
width 0xB
|
|
tree "MEM2MEM PDC (Peripheral DMA Controller)"
|
|
width 14.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "MEM2MEM_RPR,Receive Pointer Register"
|
|
line.long 0x04 "MEM2MEM_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "MEM2MEM_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "MEM2MEM_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "MEM2MEM_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "MEM2MEM_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "MEM2MEM_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "MEM2MEM_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "MEM2MEM_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "MEM2MEM_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "EEFC (Enhanced Embedded Flash Controller)"
|
|
base ad:0x400E0A00
|
|
width 10.
|
|
sif (cpu()=="ATSAMG55")
|
|
if (((d.l(ad:0x400E0A00+0xE4))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EEFC_FMR,EEFC Flash Mode Register"
|
|
bitfld.long 0x00 26. " CLOE ,Code Loop Optimization Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " FAM ,Flash Access Mode" "128-bit,64-bit"
|
|
bitfld.long 0x00 16. " SCOD ,Sequential Code Optimization Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " FWS ,Flash Wait State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " FRDY ,Ready Interrupt Enable" "No interrupt,Interrupt"
|
|
else
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "EEFC_FMR,EEFC Flash Mode Register"
|
|
bitfld.long 0x00 26. " CLOE ,Code Loop Optimization Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " FAM ,Flash Access Mode" "128-bit,64-bit"
|
|
bitfld.long 0x00 16. " SCOD ,Sequential Code Optimization Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " FWS ,Flash Wait State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " FRDY ,Ready Interrupt Enable" "No interrupt,Interrupt"
|
|
endif
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EEFC_FMR,EEFC Flash Mode Register"
|
|
bitfld.long 0x00 26. " CLOE ,Code Loop Optimization Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " FAM ,Flash Access Mode" "128-bit,64-bit"
|
|
bitfld.long 0x00 16. " SCOD ,Sequential Code Optimization Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " FWS ,Flash Wait State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " FRDY ,Ready Interrupt Enable" "No interrupt,Interrupt"
|
|
endif
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "EEFC_FCR,EEFC Flash Command Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " FKEY ,Flash Writing Protection Key"
|
|
hexmask.long.word 0x00 8.--23. 1. " FARG ,Flash Command Argument"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FCMD ,Flash Command"
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "EEFC_FSR,EEFC Flash Status Register"
|
|
in
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "EEFC_FRR,EEFC Flash Result Register"
|
|
hexmask.long 0x00 0.--31. 1. " FVALUE ,Flash Result Value"
|
|
sif (cpu()=="ATSAMG55")
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "EEFC_WPMR,EEFC Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protection Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "MATRIX (Bus Matrix)"
|
|
base ad:0x400E0200
|
|
width 14.
|
|
if (((d.l(ad:0x400E0200+0x1E4))&0x01)==0x00)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "MATRIX_MCFG0,Bus Matrix Master Configuration Register 0"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "INFINITE,SINGLE,4_BEAT,8_BEAT,16_BEAT,?..."
|
|
else
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "MATRIX_MCFG0,Bus Matrix Master Configuration Register 0"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "INFINITE,SINGLE,4_BEAT,8_BEAT,16_BEAT,?..."
|
|
endif
|
|
if (((d.l(ad:0x400E0200+0x1E4))&0x01)==0x00)
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "MATRIX_MCFG1,Bus Matrix Master Configuration Register 1"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "INFINITE,SINGLE,4_BEAT,8_BEAT,16_BEAT,?..."
|
|
else
|
|
rgroup.long 0x4++0x03
|
|
line.long 0x00 "MATRIX_MCFG1,Bus Matrix Master Configuration Register 1"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "INFINITE,SINGLE,4_BEAT,8_BEAT,16_BEAT,?..."
|
|
endif
|
|
if (((d.l(ad:0x400E0200+0x1E4))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "MATRIX_MCFG2,Bus Matrix Master Configuration Register 2"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "INFINITE,SINGLE,4_BEAT,8_BEAT,16_BEAT,?..."
|
|
else
|
|
rgroup.long 0x8++0x03
|
|
line.long 0x00 "MATRIX_MCFG2,Bus Matrix Master Configuration Register 2"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "INFINITE,SINGLE,4_BEAT,8_BEAT,16_BEAT,?..."
|
|
endif
|
|
if (((d.l(ad:0x400E0200+0x1E4))&0x01)==0x00)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MATRIX_SCFG0,Bus Matrix Slave Configuration Register 0"
|
|
bitfld.long 0x00 18.--20. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "NO DEFAULT,LAST,FIXED,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
else
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "MATRIX_SCFG0,Bus Matrix Slave Configuration Register 0"
|
|
bitfld.long 0x00 18.--20. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "NO DEFAULT,LAST,FIXED,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
endif
|
|
if (((d.l(ad:0x400E0200+0x1E4))&0x01)==0x00)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "MATRIX_SCFG1,Bus Matrix Slave Configuration Register 1"
|
|
bitfld.long 0x00 18.--20. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "NO DEFAULT,LAST,FIXED,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
else
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "MATRIX_SCFG1,Bus Matrix Slave Configuration Register 1"
|
|
bitfld.long 0x00 18.--20. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "NO DEFAULT,LAST,FIXED,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
endif
|
|
if (((d.l(ad:0x400E0200+0x1E4))&0x01)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "MATRIX_SCFG2,Bus Matrix Slave Configuration Register 2"
|
|
bitfld.long 0x00 18.--20. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "NO DEFAULT,LAST,FIXED,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "MATRIX_SCFG2,Bus Matrix Slave Configuration Register 2"
|
|
bitfld.long 0x00 18.--20. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "NO DEFAULT,LAST,FIXED,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
endif
|
|
if (((d.l(ad:0x400E0200+0x1E4))&0x01)==0x00)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "MATRIX_SCFG3,Bus Matrix Slave Configuration Register 3"
|
|
bitfld.long 0x00 18.--20. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "NO DEFAULT,LAST,FIXED,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
else
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "MATRIX_SCFG3,Bus Matrix Slave Configuration Register 3"
|
|
bitfld.long 0x00 18.--20. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "NO DEFAULT,LAST,FIXED,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst"
|
|
endif
|
|
if (((d.l(ad:0x400E0200+0x1E4))&0x01)==0x00)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "MATRIX_PRAS0,Bus Matrix Priority Registers For Slaves - Register 0"
|
|
bitfld.long 0x00 12.--13. " M3PR ,M3PR: Master 3 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " M2PR ,M2PR: Master 2 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,M3PR: Master 1 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " M0PR ,M0PR: Master 0 Priority" "Lowest,1,2,Highest"
|
|
else
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "MATRIX_PRAS0,Bus Matrix Priority Registers For Slaves - Register 0"
|
|
bitfld.long 0x00 12.--13. " M3PR ,M3PR: Master 3 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " M2PR ,M2PR: Master 2 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,M3PR: Master 1 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " M0PR ,M0PR: Master 0 Priority" "Lowest,1,2,Highest"
|
|
endif
|
|
if (((d.l(ad:0x400E0200+0x1E4))&0x01)==0x00)
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "MATRIX_PRAS1,Bus Matrix Priority Registers For Slaves - Register 1"
|
|
bitfld.long 0x00 12.--13. " M3PR ,M3PR: Master 3 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " M2PR ,M2PR: Master 2 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,M3PR: Master 1 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " M0PR ,M0PR: Master 0 Priority" "Lowest,1,2,Highest"
|
|
else
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "MATRIX_PRAS1,Bus Matrix Priority Registers For Slaves - Register 1"
|
|
bitfld.long 0x00 12.--13. " M3PR ,M3PR: Master 3 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " M2PR ,M2PR: Master 2 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,M3PR: Master 1 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " M0PR ,M0PR: Master 0 Priority" "Lowest,1,2,Highest"
|
|
endif
|
|
if (((d.l(ad:0x400E0200+0x1E4))&0x01)==0x00)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "MATRIX_PRAS2,Bus Matrix Priority Registers For Slaves - Register 2"
|
|
bitfld.long 0x00 12.--13. " M3PR ,M3PR: Master 3 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " M2PR ,M2PR: Master 2 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,M3PR: Master 1 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " M0PR ,M0PR: Master 0 Priority" "Lowest,1,2,Highest"
|
|
else
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "MATRIX_PRAS2,Bus Matrix Priority Registers For Slaves - Register 2"
|
|
bitfld.long 0x00 12.--13. " M3PR ,M3PR: Master 3 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " M2PR ,M2PR: Master 2 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,M3PR: Master 1 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " M0PR ,M0PR: Master 0 Priority" "Lowest,1,2,Highest"
|
|
endif
|
|
if (((d.l(ad:0x400E0200+0x1E4))&0x01)==0x00)
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "MATRIX_PRAS3,Bus Matrix Priority Registers For Slaves - Register 3"
|
|
bitfld.long 0x00 12.--13. " M3PR ,M3PR: Master 3 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " M2PR ,M2PR: Master 2 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,M3PR: Master 1 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " M0PR ,M0PR: Master 0 Priority" "Lowest,1,2,Highest"
|
|
else
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "MATRIX_PRAS3,Bus Matrix Priority Registers For Slaves - Register 3"
|
|
bitfld.long 0x00 12.--13. " M3PR ,M3PR: Master 3 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " M2PR ,M2PR: Master 2 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,M3PR: Master 1 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " M0PR ,M0PR: Master 0 Priority" "Lowest,1,2,Highest"
|
|
endif
|
|
if (((d.l(ad:0x400E0200+0x1E4))&0x01)==0x00)
|
|
group.long 0x0114++0x03
|
|
line.long 0x00 "CCFG_SYSIO,System I/O Configuration Register"
|
|
bitfld.long 0x00 12. " SYSIO12 ,PB12 or ERASE Assignment" "ERASE,PB12"
|
|
sif (cpu()=="ATSAMG55")
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYSIO11 ,PA22 or DP Assignment" "DP,PA22"
|
|
bitfld.long 0x00 10. " SYSIO10 ,PA21 or DM Assignment" "DM,PA21"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " SYSIO7 ,PB7 or TCK/SWCLK Assignment" "TCK/SWCLK,PB7"
|
|
bitfld.long 0x00 6. " SYSIO6 ,PB6 or TMS/SWDIO Assignment" "TMS/SWDIO,PB6"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SYSIO5 ,PB5 or TDO/TRACESWO Assignment" "TDO/TRACESWO,PB5"
|
|
bitfld.long 0x00 4. " SYSIO4 ,PB4 or TDI Assignment" "TDI,PB4"
|
|
else
|
|
rgroup.long 0x0114++0x03
|
|
line.long 0x00 "CCFG_SYSIO,System I/O Configuration Register"
|
|
bitfld.long 0x00 12. " SYSIO12 ,PB12 or ERASE Assignment" "ERASE,PB12"
|
|
sif (cpu()=="ATSAMG55")
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYSIO11 ,PA22 or DP Assignment" "DP,PA22"
|
|
bitfld.long 0x00 10. " SYSIO10 ,PA21 or DM Assignment" "DM,PA21"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " SYSIO7 ,PB7 or TCK/SWCLK Assignment" "TCK/SWCLK,PB7"
|
|
bitfld.long 0x00 6. " SYSIO6 ,PB6 or TMS/SWDIO Assignment" "TMS/SWDIO,PB6"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SYSIO5 ,PB5 or TDO/TRACESWO Assignment" "TDO/TRACESWO,PB5"
|
|
bitfld.long 0x00 4. " SYSIO4 ,PB4 or TDI Assignment" "TDI,PB4"
|
|
endif
|
|
sif (cpu()=="ATSAMG55")
|
|
group.long 0x0118++0x0B
|
|
line.long 0x00 "CCFG_DYNCKG,Dynamic Clock Gating Register"
|
|
bitfld.long 0x00 2. " EFCCKG ,EFC Dynamic Clock Gating Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 1. " BRIDCKG ,Bridge Dynamic Clock Gating Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " MATCKG ,MATRIX Dynamic Clock Gating" "Enabled,Disabled"
|
|
line.long 0x04 "CCFG_I2SCLKSEL,I2S Clock Source Selection Register"
|
|
bitfld.long 0x04 1. " CLKSEL1 ,I2S1 Clock Source" "Peripheral CLK,PMC PCK4"
|
|
bitfld.long 0x04 0. " CLKSEL0 ,I2S0 Clock Source" "Peripheral CLK,PMC PCK4"
|
|
line.long 0x08 "CCFG_USBMR,USB Management Register"
|
|
bitfld.long 0x08 2. " USBHTSC ,USB Host Transceiver Suspend Control" "OHCI,USBHTSSC"
|
|
bitfld.long 0x08 1. " USBHTSSC ,USB Transceiver Suspend Software Control" "Active,Suspend"
|
|
bitfld.long 0x08 0. " USBMODE ,USB Mode Selection" "Host,Device"
|
|
endif
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "MATRIX_WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protection Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0x1E8++0x03
|
|
hide.long 0x00 "MATRIX_WPSR,Write Protection Status Register"
|
|
in
|
|
width 0xB
|
|
tree.end
|
|
tree "PMC (Power Management Controller)"
|
|
base ad:0x400E0400
|
|
width 15.
|
|
if (((d.l(ad:0x400E0400+0xE4))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PMC_SCSR,PMC System Clock Status Register"
|
|
sif (cpu()=="ATSAMG55")
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " PCK7_set/clr ,Programmable Clock x Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " PCK6_set/clr ,Programmable Clock x Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " PCK5_set/clr ,Programmable Clock x Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " PCK4_set/clr ,Programmable Clock x Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " PCK3_set/clr ,Programmable Clock x Output Status" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " PCK2_set/clr ,Programmable Clock x Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " PCK1_set/clr ,Programmable Clock x Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " PCK0_set/clr ,Programmable Clock x Output Status" "Disabled,Enabled"
|
|
sif (cpu()=="ATSAMG55")
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " UDP_set/clr ,USB Device Port Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " UHP_set/clr ,USB Host Port Clock Status" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "PMC_SCSR,PMC System Clock Status Register"
|
|
sif (cpu()=="ATSAMG55")
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " PCK7_set/clr ,Programmable Clock x Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " PCK6_set/clr ,Programmable Clock x Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " PCK5_set/clr ,Programmable Clock x Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " PCK4_set/clr ,Programmable Clock x Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " PCK3_set/clr ,Programmable Clock x Output Status" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " PCK2_set/clr ,Programmable Clock x Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " PCK1_set/clr ,Programmable Clock x Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " PCK0_set/clr ,Programmable Clock x Output Status" "Disabled,Enabled"
|
|
sif (cpu()=="ATSAMG55")
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " UDP_set/clr ,USB Device Port Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " UHP_set/clr ,USB Host Port Clock Status" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpuis("ATSAMG51"))
|
|
if (((d.l(ad:0x400E0400+0xE4))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PMC_PCER0,PMC Peripheral Clock Status Register"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " ADC ,Analog-to-Digital Converter (Peripheral ID 29) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " TC2 ,Timer/Counter 2 (Peripheral ID 25) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " TC1 ,Timer/Counter 1 (Peripheral ID 24) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " TC0 ,Timer/Counter 0 (Peripheral ID 23) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " TWI2 ,Two Wire Interface 2 (Peripheral ID 22) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " SPI ,Serial Peripheral Interface (Peripheral ID 21) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " TWI1 ,Two-Wire Interface 1 (Peripheral ID 20) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " TWI0 ,Two-Wire Interface 0 HS (Peripheral ID 19) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " MEM2MEM ,MEM2MEM (Peripheral ID 15) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " UASRT ,USART (Peripheral ID 14) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " PIOB ,Parallel I/O Controller B (Peripheral ID 12) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " PIOA ,Parallel I/O Controller A (Peripheral ID 11) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " UART1 ,UART 1 (Peripheral ID 9) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " UART0 ,UART 0 (Peripheral ID 8) Clock Status" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "PMC_PCER0,PMC Peripheral Clock Status Register"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " ADC ,Analog-to-Digital Converter (Peripheral ID 29) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " TC2 ,Timer/Counter 2 (Peripheral ID 25) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " TC1 ,Timer/Counter 1 (Peripheral ID 24) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " TC0 ,Timer/Counter 0 (Peripheral ID 23) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " TWI2 ,Two Wire Interface 2 (Peripheral ID 22) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " SPI ,Serial Peripheral Interface (Peripheral ID 21) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " TWI1 ,Two-Wire Interface 1 (Peripheral ID 20) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " TWI0 ,Two-Wire Interface 0 HS (Peripheral ID 19) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " MEM2MEM ,MEM2MEM (Peripheral ID 15) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " UASRT ,USART (Peripheral ID 14) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " PIOB ,Parallel I/O Controller B (Peripheral ID 12) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " PIOA ,Parallel I/O Controller A (Peripheral ID 11) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " UART1 ,UART 1 (Peripheral ID 9) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " UART0 ,UART 0 (Peripheral ID 8) Clock Status" "Disabled,Enabled"
|
|
endif
|
|
elif cpuis("ATSAMG53")||cpuis("ATSAMG54")
|
|
if (((d.l(ad:0x400E0400+0xE4))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PMC_PCER0,PMC Peripheral Clock Status Register"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " ADC ,Analog-to-Digital Converter (Peripheral ID 29) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " TC5 ,Timer/Counter 5 (Peripheral ID 28) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " TC4 ,Timer/Counter 4 (Peripheral ID 27) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " TC3 ,Timer/Counter 3 (Peripheral ID 26) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " TC2 ,Timer/Counter 2 (Peripheral ID 25) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " TC1 ,Timer/Counter 1 (Peripheral ID 24) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " TC0 ,Timer/Counter 0 (Peripheral ID 23) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " TWI2 ,Two Wire Interface 2 (Peripheral ID 22) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " SPI ,Serial Peripheral Interface (Peripheral ID 21) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " TWI1 ,Two-Wire Interface 1 (Peripheral ID 20) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " TWI0 ,Two-Wire Interface 0 HS (Peripheral ID 19) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " PDMIC1 ,PDM 1 (Peripheral ID 18) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " I2SC1 ,I2SC 1 (Peripheral ID 17) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " I2SC0 ,I2SC 0 (Peripheral ID 16) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " MEM2MEM ,MEM2MEM (Peripheral ID 15) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " UASRT ,USART (Peripheral ID 14) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " PDMIC0 ,PDM 0 (Peripheral ID 13) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " PIOB ,Parallel I/O Controller B (Peripheral ID 12) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " PIOA ,Parallel I/O Controller A (Peripheral ID 11) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " UART1 ,UART 1 (Peripheral ID 9) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " UART0 ,UART 0 (Peripheral ID 8) Clock Status" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "PMC_PCER0,PMC Peripheral Clock Status Register"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " ADC ,Analog-to-Digital Converter (Peripheral ID 29) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " TC5 ,Timer/Counter 5 (Peripheral ID 28) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " TC4 ,Timer/Counter 4 (Peripheral ID 27) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " TC3 ,Timer/Counter 3 (Peripheral ID 26) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " TC2 ,Timer/Counter 2 (Peripheral ID 25) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " TC1 ,Timer/Counter 1 (Peripheral ID 24) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " TC0 ,Timer/Counter 0 (Peripheral ID 23) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " TWI2 ,Two Wire Interface 2 (Peripheral ID 22) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " SPI ,Serial Peripheral Interface (Peripheral ID 21) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " TWI1 ,Two-Wire Interface 1 (Peripheral ID 20) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " TWI0 ,Two-Wire Interface 0 HS (Peripheral ID 19) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " PDMIC1 ,PDM 1 (Peripheral ID 18) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " I2SC1 ,I2SC 1 (Peripheral ID 17) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " I2SC0 ,I2SC 0 (Peripheral ID 16) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " MEM2MEM ,MEM2MEM (Peripheral ID 15) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " UASRT ,USART (Peripheral ID 14) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " PDMIC0 ,PDM 0 (Peripheral ID 13) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " PIOB ,Parallel I/O Controller B (Peripheral ID 12) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " PIOA ,Parallel I/O Controller A (Peripheral ID 11) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " UART1 ,UART 1 (Peripheral ID 9) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " UART0 ,UART 0 (Peripheral ID 8) Clock Status" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((d.l(ad:0x400E0400+0xE4))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PMC_PCER0,PMC Peripheral Clock Status Register"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " ADC ,Analog-to-Digital Converter (Peripheral ID 29) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " TC5 ,Timer/Counter 5 (Peripheral ID 28) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " TC4 ,Timer/Counter 4 (Peripheral ID 27) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " TC3 ,Timer/Counter 3 (Peripheral ID 26) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " TC2 ,Timer/Counter 2 (Peripheral ID 25) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " TC1 ,Timer/Counter 1 (Peripheral ID 24) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " TC0 ,Timer/Counter 0 (Peripheral ID 23) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " USART6/SPI6/TWI6 ,USART/SPI/TWI 6 (Peripheral ID 22) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " USART5/SPI5/TWI5 ,SART/SPI/TWI 5 (Peripheral ID 21) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " USART4/SPI4/TWI4 ,USART/SPI/TWI 4 (Peripheral ID 20) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " USART3/SPI3/TWI3 ,USART/SPI/TWI 3 (Peripheral ID 19) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " PDMIC1 ,PDM 1 (Peripheral ID 18) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " I2SC1 ,I2SC 1 (Peripheral ID 17) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " I2SC0 ,I2SC 0 (Peripheral ID 16) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " MEM2MEM ,MEM2MEM (Peripheral ID 15) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " USART2/SPI2/TWI2 ,USART/SPI/TWI 2 (Peripheral ID 14) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " PDMIC0 ,PDM 0 (Peripheral ID 13) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " PIOB ,Parallel I/O Controller B (Peripheral ID 12) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " PIOA ,Parallel I/O Controller A (Peripheral ID 11) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " USART1/SPI1/TWI1 ,USART/SPI/TWI 1 (Peripheral ID 9) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " USART0/SPI0/TWI0 ,USART/SPI/TWI 0 (Peripheral ID 8) Clock Status" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "PMC_PCER0,PMC Peripheral Clock Status Register"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " ADC ,Analog-to-Digital Converter (Peripheral ID 29) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " TC5 ,Timer/Counter 5 (Peripheral ID 28) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " TC4 ,Timer/Counter 4 (Peripheral ID 27) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " TC3 ,Timer/Counter 3 (Peripheral ID 26) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " TC2 ,Timer/Counter 2 (Peripheral ID 25) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " TC1 ,Timer/Counter 1 (Peripheral ID 24) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " TC0 ,Timer/Counter 0 (Peripheral ID 23) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " USART6/SPI6/TWI6 ,USART/SPI/TWI 6 (Peripheral ID 22) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " USART5/SPI5/TWI5 ,SART/SPI/TWI 5 (Peripheral ID 21) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " USART4/SPI4/TWI4 ,USART/SPI/TWI 4 (Peripheral ID 20) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " USART3/SPI3/TWI3 ,USART/SPI/TWI 3 (Peripheral ID 19) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " PDMIC1 ,PDM 1 (Peripheral ID 18) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " I2SC1 ,I2SC 1 (Peripheral ID 17) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " I2SC0 ,I2SC 0 (Peripheral ID 16) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " MEM2MEM ,MEM2MEM (Peripheral ID 15) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " USART2/SPI2/TWI2 ,USART/SPI/TWI 2 (Peripheral ID 14) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " PDMIC0 ,PDM 0 (Peripheral ID 13) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " PIOB ,Parallel I/O Controller B (Peripheral ID 12) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " PIOA ,Parallel I/O Controller A (Peripheral ID 11) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " USART1/SPI1/TWI1 ,USART/SPI/TWI 1 (Peripheral ID 9) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " USART0/SPI0/TWI0 ,USART/SPI/TWI 0 (Peripheral ID 8) Clock Status" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((d.l(ad:0x400E0400+0xE4))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CKGR_MOR,PMC Clock Generator Main Oscillator Register"
|
|
bitfld.long 0x00 25. " CFDEN ,Clock Failure Detector Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " MOSCSEL ,Main Oscillator Selection" "On-chip RC,Crystal"
|
|
hexmask.long.byte 0x00 16.--23. 1. " KEY ,Write Access Password"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " MOSCXTST ,Main Crystal Oscillator Start-up Time"
|
|
bitfld.long 0x00 4.--6. " MOSCRCF ,Main On-Chip RC Oscillator Frequency Selection" "8 MHz,16 MHz,24 MHz,?..."
|
|
bitfld.long 0x00 3. " MOSCRCEN ,Main On-Chip RC Oscillator Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WAITMODE ,Wait Mode Command (write-only)" "No effect,Wait"
|
|
bitfld.long 0x00 1. " MOSCXTBY ,Main Crystal Oscillator Bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 0. " MOSCXTEN ,Main Crystal Oscillator Enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "CKGR_MOR,PMC Clock Generator Main Oscillator Register"
|
|
bitfld.long 0x00 25. " CFDEN ,Clock Failure Detector Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " MOSCSEL ,Main Oscillator Selection" "On-chip RC,Crystal"
|
|
hexmask.long.byte 0x00 16.--23. 1. " KEY ,Write Access Password"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " MOSCXTST ,Main Crystal Oscillator Start-up Time"
|
|
bitfld.long 0x00 4.--6. " MOSCRCF ,Main On-Chip RC Oscillator Frequency Selection" "8 MHz,16 MHz,24 MHz,?..."
|
|
bitfld.long 0x00 3. " MOSCRCEN ,Main On-Chip RC Oscillator Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WAITMODE ,Wait Mode Command (write-only)" "No effect,Wait"
|
|
bitfld.long 0x00 1. " MOSCXTBY ,Main Crystal Oscillator Bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 0. " MOSCXTEN ,Main Crystal Oscillator Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x400E0400+0xE4))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CKGR_MCFR,PMC Clock Generator Main Clock Frequency Register"
|
|
bitfld.long 0x00 20. " RCMEAS ,RC Oscillator Frequency Measure (write-only)" "No effect,Restart"
|
|
bitfld.long 0x00 16. " MAINFRDY ,Main Clock Ready" "Not ready,Ready"
|
|
hexmask.long.word 0x00 0.--15. 1. " MAINF ,Main Clock Frequency"
|
|
else
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "CKGR_MCFR,PMC Clock Generator Main Clock Frequency Register"
|
|
bitfld.long 0x00 20. " RCMEAS ,RC Oscillator Frequency Measure (write-only)" "No effect,Restart"
|
|
bitfld.long 0x00 16. " MAINFRDY ,Main Clock Ready" "Not ready,Ready"
|
|
hexmask.long.word 0x00 0.--15. 1. " MAINF ,Main Clock Frequency"
|
|
endif
|
|
textline ""
|
|
if (((d.l(ad:0x400E0400+0xE4))&0x01)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CKGR_PLLAR,PMC Clock Generator PLLA Register"
|
|
bitfld.long 0x00 29. " ZERO ,Must Be Written to 0" "0,?.."
|
|
sif (cpu()=="ATSAMG55")
|
|
hexmask.long.word 0x00 16.--28. 1. " MULA ,PLLA Multiplier"
|
|
else
|
|
hexmask.long.word 0x00 16.--27. 1. " MULA ,PLLA Multiplier"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " PLLACOUNT ,PLLA Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PLLAEN ,PLLA Control"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "CKGR_PLLAR,PMC Clock Generator PLLA Register"
|
|
bitfld.long 0x00 29. " ZERO ,Must Be Written to 0" "0,?.."
|
|
sif (cpu()=="ATSAMG55")
|
|
textline " "
|
|
hexmask.long.word 0x00 16.--28. 1. " MULA ,PLLA Multiplier"
|
|
else
|
|
textline " "
|
|
hexmask.long.word 0x00 16.--27. 1. " MULA ,PLLA Multiplier"
|
|
endif
|
|
bitfld.long 0x00 8.--13. " PLLACOUNT ,PLLA Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PLLAEN ,PLLA Control"
|
|
endif
|
|
sif (cpu()=="ATSAMG55")
|
|
if (((d.l(ad:0x400E0400+0xE4))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CKGR_PLLBR,PMC Clock Generator PLLB Register"
|
|
bitfld.long 0x00 29. " ZERO ,Must Be Written to 0" "0,?.."
|
|
hexmask.long.word 0x00 16.--26. 1. " MULB ,PLLB Multiplier"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " PLLBCOUNT ,PLLB Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PLLBEN ,PLLB Control"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "CKGR_PLLBR,PMC Clock Generator PLLB Register"
|
|
bitfld.long 0x00 29. " ZERO ,Must Be Written to 0" "0,?.."
|
|
hexmask.long.word 0x00 16.--26. 1. " MULB ,PLLB Multiplier"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " PLLBCOUNT ,PLLB Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PLLBEN ,PLLB Control"
|
|
endif
|
|
endif
|
|
if (((d.l(ad:0x400E0400+0xE4))&0x01)==0x00)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PMC_MCKR,10PMC Master Clock Register"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 13. " PLLBDIV2 ,PLLB Divisor by 2" "/1,/2"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12. " PLLADIV2 ,PLLA Divisor by 2" "/1,/2"
|
|
bitfld.long 0x00 4.--6. " PRES ,Processor Clock Prescaler" "CLK_1,CLK_2,CLK_4,CLK_8,CLK_16,CLK_32,CLK_64,CLK_3"
|
|
sif (cpu()=="ATSAMG55")
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CSS ,Master Clock Source Selection" "SLOW_CLK,MAIN_CLK,PLLA_CLK,PLLB_CLK"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CSS ,Master Clock Source Selection" "SLOW_CLK,MAIN_CLK,PLLA_CLK,?..."
|
|
endif
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "PMC_MCKR,10PMC Master Clock Register"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 13. " PLLBDIV2 ,PLLB Divisor by 2" "/1,/2"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12. " PLLADIV2 ,PLLA Divisor by 2" "/1,/2"
|
|
bitfld.long 0x00 4.--6. " PRES ,Processor Clock Prescaler" "CLK_1,CLK_2,CLK_4,CLK_8,CLK_16,CLK_32,CLK_64,CLK_3"
|
|
sif (cpu()=="ATSAMG55")
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CSS ,Master Clock Source Selection" "SLOW_CLK,MAIN_CLK,PLLA_CLK,PLLB_CLK"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CSS ,Master Clock Source Selection" "SLOW_CLK,MAIN_CLK,PLLA_CLK,?..."
|
|
endif
|
|
endif
|
|
sif (cpu()=="ATSAMG55")
|
|
if (((d.l(ad:0x400E0400+0xE4))&0x01)==0x00)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PMC_USB,PMC USB Clock Register"
|
|
bitfld.long 0x00 8.--11. " USBDIV ,Divider for USB Clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " USBS ,USB Input Clock Selection" "PLLA,PLLB"
|
|
else
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "PMC_USB,PMC USB Clock Register"
|
|
bitfld.long 0x00 8.--11. " USBDIV ,Divider for USB Clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " USBS ,USB Input Clock Selection" "PLLA,PLLB"
|
|
endif
|
|
endif
|
|
sif cpuis("ATSAMG55")
|
|
if (((d.l(ad:0x400E0400+0xE4))&0x01)==0x00)
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "PMC_PCK0,PMC Programmable Clock Register"
|
|
hexmask.long.byte 0x00 4.--11. 1. " PRES ,Programmable Clock Prescaler"
|
|
bitfld.long 0x00 0.--3. " CSS ,Master Clock Source Selection" "SLOW_CLK,MAIN_CLK,PLLA_CLK,PLLB_CLK,MCK,?..."
|
|
else
|
|
rgroup.long 0x40++0x0B
|
|
line.long 0x00 "PMC_PCK0,PMC Programmable Clock Register"
|
|
hexmask.long.byte 0x00 4.--11. 1. " PRES ,Programmable Clock Prescaler"
|
|
bitfld.long 0x00 0.--3. " CSS ,Master Clock Source Selection" "SLOW_CLK,MAIN_CLK,PLLA_CLK,PLLB_CLK,MCK,?..."
|
|
endif
|
|
if (((d.l(ad:0x400E0400+0xE4))&0x01)==0x00)
|
|
group.long 0x44++0x0B
|
|
line.long 0x00 "PMC_PCK1,PMC Programmable Clock Register"
|
|
hexmask.long.byte 0x00 4.--11. 1. " PRES ,Programmable Clock Prescaler"
|
|
bitfld.long 0x00 0.--3. " CSS ,Master Clock Source Selection" "SLOW_CLK,MAIN_CLK,PLLA_CLK,PLLB_CLK,MCK,?..."
|
|
else
|
|
rgroup.long 0x44++0x0B
|
|
line.long 0x00 "PMC_PCK1,PMC Programmable Clock Register"
|
|
hexmask.long.byte 0x00 4.--11. 1. " PRES ,Programmable Clock Prescaler"
|
|
bitfld.long 0x00 0.--3. " CSS ,Master Clock Source Selection" "SLOW_CLK,MAIN_CLK,PLLA_CLK,PLLB_CLK,MCK,?..."
|
|
endif
|
|
if (((d.l(ad:0x400E0400+0xE4))&0x01)==0x00)
|
|
group.long 0x48++0x0B
|
|
line.long 0x00 "PMC_PCK2,PMC Programmable Clock Register"
|
|
hexmask.long.byte 0x00 4.--11. 1. " PRES ,Programmable Clock Prescaler"
|
|
bitfld.long 0x00 0.--3. " CSS ,Master Clock Source Selection" "SLOW_CLK,MAIN_CLK,PLLA_CLK,PLLB_CLK,MCK,?..."
|
|
else
|
|
rgroup.long 0x48++0x0B
|
|
line.long 0x00 "PMC_PCK2,PMC Programmable Clock Register"
|
|
hexmask.long.byte 0x00 4.--11. 1. " PRES ,Programmable Clock Prescaler"
|
|
bitfld.long 0x00 0.--3. " CSS ,Master Clock Source Selection" "SLOW_CLK,MAIN_CLK,PLLA_CLK,PLLB_CLK,MCK,?..."
|
|
endif
|
|
if (((d.l(ad:0x400E0400+0xE4))&0x01)==0x00)
|
|
group.long 0x4C++0x0B
|
|
line.long 0x00 "PMC_PCK3,PMC Programmable Clock Register"
|
|
hexmask.long.byte 0x00 4.--11. 1. " PRES ,Programmable Clock Prescaler"
|
|
bitfld.long 0x00 0.--3. " CSS ,Master Clock Source Selection" "SLOW_CLK,MAIN_CLK,PLLA_CLK,PLLB_CLK,MCK,?..."
|
|
else
|
|
rgroup.long 0x4C++0x0B
|
|
line.long 0x00 "PMC_PCK3,PMC Programmable Clock Register"
|
|
hexmask.long.byte 0x00 4.--11. 1. " PRES ,Programmable Clock Prescaler"
|
|
bitfld.long 0x00 0.--3. " CSS ,Master Clock Source Selection" "SLOW_CLK,MAIN_CLK,PLLA_CLK,PLLB_CLK,MCK,?..."
|
|
endif
|
|
if (((d.l(ad:0x400E0400+0xE4))&0x01)==0x00)
|
|
group.long 0x50++0x0B
|
|
line.long 0x00 "PMC_PCK4,PMC Programmable Clock Register"
|
|
hexmask.long.byte 0x00 4.--11. 1. " PRES ,Programmable Clock Prescaler"
|
|
bitfld.long 0x00 0.--3. " CSS ,Master Clock Source Selection" "SLOW_CLK,MAIN_CLK,PLLA_CLK,PLLB_CLK,MCK,?..."
|
|
else
|
|
rgroup.long 0x50++0x0B
|
|
line.long 0x00 "PMC_PCK4,PMC Programmable Clock Register"
|
|
hexmask.long.byte 0x00 4.--11. 1. " PRES ,Programmable Clock Prescaler"
|
|
bitfld.long 0x00 0.--3. " CSS ,Master Clock Source Selection" "SLOW_CLK,MAIN_CLK,PLLA_CLK,PLLB_CLK,MCK,?..."
|
|
endif
|
|
if (((d.l(ad:0x400E0400+0xE4))&0x01)==0x00)
|
|
group.long 0x54++0x0B
|
|
line.long 0x00 "PMC_PCK5,PMC Programmable Clock Register"
|
|
hexmask.long.byte 0x00 4.--11. 1. " PRES ,Programmable Clock Prescaler"
|
|
bitfld.long 0x00 0.--3. " CSS ,Master Clock Source Selection" "SLOW_CLK,MAIN_CLK,PLLA_CLK,PLLB_CLK,MCK,?..."
|
|
else
|
|
rgroup.long 0x54++0x0B
|
|
line.long 0x00 "PMC_PCK5,PMC Programmable Clock Register"
|
|
hexmask.long.byte 0x00 4.--11. 1. " PRES ,Programmable Clock Prescaler"
|
|
bitfld.long 0x00 0.--3. " CSS ,Master Clock Source Selection" "SLOW_CLK,MAIN_CLK,PLLA_CLK,PLLB_CLK,MCK,?..."
|
|
endif
|
|
if (((d.l(ad:0x400E0400+0xE4))&0x01)==0x00)
|
|
group.long 0x58++0x0B
|
|
line.long 0x00 "PMC_PCK6,PMC Programmable Clock Register"
|
|
hexmask.long.byte 0x00 4.--11. 1. " PRES ,Programmable Clock Prescaler"
|
|
bitfld.long 0x00 0.--3. " CSS ,Master Clock Source Selection" "SLOW_CLK,MAIN_CLK,PLLA_CLK,PLLB_CLK,MCK,?..."
|
|
else
|
|
rgroup.long 0x58++0x0B
|
|
line.long 0x00 "PMC_PCK6,PMC Programmable Clock Register"
|
|
hexmask.long.byte 0x00 4.--11. 1. " PRES ,Programmable Clock Prescaler"
|
|
bitfld.long 0x00 0.--3. " CSS ,Master Clock Source Selection" "SLOW_CLK,MAIN_CLK,PLLA_CLK,PLLB_CLK,MCK,?..."
|
|
endif
|
|
if (((d.l(ad:0x400E0400+0xE4))&0x01)==0x00)
|
|
group.long 0x5C++0x0B
|
|
line.long 0x00 "PMC_PCK7,PMC Programmable Clock Register"
|
|
hexmask.long.byte 0x00 4.--11. 1. " PRES ,Programmable Clock Prescaler"
|
|
bitfld.long 0x00 0.--3. " CSS ,Master Clock Source Selection" "SLOW_CLK,MAIN_CLK,PLLA_CLK,PLLB_CLK,MCK,?..."
|
|
else
|
|
rgroup.long 0x5C++0x0B
|
|
line.long 0x00 "PMC_PCK7,PMC Programmable Clock Register"
|
|
hexmask.long.byte 0x00 4.--11. 1. " PRES ,Programmable Clock Prescaler"
|
|
bitfld.long 0x00 0.--3. " CSS ,Master Clock Source Selection" "SLOW_CLK,MAIN_CLK,PLLA_CLK,PLLB_CLK,MCK,?..."
|
|
endif
|
|
else
|
|
if (((d.l(ad:0x400E0400+0xE4))&0x01)==0x00)
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "PMC_PCK0,PMC Programmable Clock Register"
|
|
bitfld.long 0x00 4.--6. " PRES ,Programmable Clock Prescaler" "CLK_1,CLK_2,CLK_4,CLK_8,CLK_16,CLK_32,CLK_64,?..."
|
|
bitfld.long 0x00 0.--2. " CSS ,Master Clock Source Selection" "SLOW_CLK,MAIN_CLK,PLLA_CLK,MCK,?..."
|
|
else
|
|
rgroup.long 0x40++0x0B
|
|
line.long 0x00 "PMC_PCK0,PMC Programmable Clock Register"
|
|
bitfld.long 0x00 4.--6. " PRES ,Programmable Clock Prescaler" "CLK_1,CLK_2,CLK_4,CLK_8,CLK_16,CLK_32,CLK_64,?..."
|
|
bitfld.long 0x00 0.--2. " CSS ,Master Clock Source Selection" "SLOW_CLK,MAIN_CLK,PLLA_CLK,MCK,?..."
|
|
endif
|
|
if (((d.l(ad:0x400E0400+0xE4))&0x01)==0x00)
|
|
group.long 0x44++0x0B
|
|
line.long 0x00 "PMC_PCK1,PMC Programmable Clock Register"
|
|
bitfld.long 0x00 4.--6. " PRES ,Programmable Clock Prescaler" "CLK_1,CLK_2,CLK_4,CLK_8,CLK_16,CLK_32,CLK_64,?..."
|
|
bitfld.long 0x00 0.--2. " CSS ,Master Clock Source Selection" "SLOW_CLK,MAIN_CLK,PLLA_CLK,MCK,?..."
|
|
else
|
|
rgroup.long 0x44++0x0B
|
|
line.long 0x00 "PMC_PCK1,PMC Programmable Clock Register"
|
|
bitfld.long 0x00 4.--6. " PRES ,Programmable Clock Prescaler" "CLK_1,CLK_2,CLK_4,CLK_8,CLK_16,CLK_32,CLK_64,?..."
|
|
bitfld.long 0x00 0.--2. " CSS ,Master Clock Source Selection" "SLOW_CLK,MAIN_CLK,PLLA_CLK,MCK,?..."
|
|
endif
|
|
if (((d.l(ad:0x400E0400+0xE4))&0x01)==0x00)
|
|
group.long 0x48++0x0B
|
|
line.long 0x00 "PMC_PCK2,PMC Programmable Clock Register"
|
|
bitfld.long 0x00 4.--6. " PRES ,Programmable Clock Prescaler" "CLK_1,CLK_2,CLK_4,CLK_8,CLK_16,CLK_32,CLK_64,?..."
|
|
bitfld.long 0x00 0.--2. " CSS ,Master Clock Source Selection" "SLOW_CLK,MAIN_CLK,PLLA_CLK,MCK,?..."
|
|
else
|
|
rgroup.long 0x48++0x0B
|
|
line.long 0x00 "PMC_PCK2,PMC Programmable Clock Register"
|
|
bitfld.long 0x00 4.--6. " PRES ,Programmable Clock Prescaler" "CLK_1,CLK_2,CLK_4,CLK_8,CLK_16,CLK_32,CLK_64,?..."
|
|
bitfld.long 0x00 0.--2. " CSS ,Master Clock Source Selection" "SLOW_CLK,MAIN_CLK,PLLA_CLK,MCK,?..."
|
|
endif
|
|
endif
|
|
hgroup.long 0x68++0x03
|
|
hide.long 0x00 "PMC_SR,PMC Status Register"
|
|
in
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PMC_IMR,PMC Interrupt Mask Register"
|
|
setclrfld.long 0x00 18. -0x0C 18. -0x08 18. " CFDEV ,Clock Failure Detector Event Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 17. -0x0C 17. -0x08 17. " MOSCRCS ,Main On-Chip RC Status Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 16. -0x0C 16. -0x08 16. " MOSCSELS ,Main Oscillator Selection Status Interrupt Mask" "Masked,Not masked"
|
|
sif (cpu()=="ATSAMG55")
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x0C 15. -0x08 15. " PCKRDY7 ,Programmable Clock Ready x Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 14. -0x0C 14. -0x08 14. " PCKRDY6 ,Programmable Clock Ready x Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 13. -0x0C 13. -0x08 13. " PCKRDY5 ,Programmable Clock Ready x Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x0C 12. -0x08 12. " PCKRDY4 ,Programmable Clock Ready x Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 11. -0x0C 11. -0x08 11. " PCKRDY3 ,Programmable Clock Ready x Interrupt Mask" "Masked,Not masked"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x0C 10. -0x08 10. " PCKRDY2 ,Programmable Clock Ready x Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x0C 9. -0x08 9. " PCKRDY1 ,Programmable Clock Ready x Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x0C 8. -0x08 8. " PCKRDY0 ,Programmable Clock Ready x Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x0C 3. -0x08 3. " MCKRDY ,Master Clock Ready Interrupt Mask" "Masked,Not masked"
|
|
sif (cpu()=="ATSAMG55")
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x0C 2. -0x08 2. " LOCKB ,PLLB Lock Interrupt Mask" "Masked,Not masked"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x0C 2. -0x08 2. " LOCKA ,PLLA Lock Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x0C 0. -0x08 0. " MOSCXTS ,Main Crystal Oscillator Status Interrupt Mask" "Masked,Not masked"
|
|
if (((d.l(ad:0x400E0400+0xE4))&0x01)==0x00)
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "PMC_FSMR,PMC Fast Startup Mode Register"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 23. " FFLPM ,Force Flash Low-power Mode" "Automatic,User defined"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 21.--22. " FLPM ,Flash Low-power Mode" "FLASH_STANDBY,FLASH_DEEP_POWERDOWN,FLASH_IDLE,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20. " LPM ,Low-power Mode" "Sleep Mode,Wait Mode"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 18. " USBAL ,USB Alarm Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17. " RTCAL ,RTC Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RTTAL ,RTT Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " FSTT5 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FSTT4 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FSTT13 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " FSTT12 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " FSTT11 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSTT10 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " FSTT9 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FSTT8 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FSTT7 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FSTT6 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FSTT5 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FSTT4 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FSTT3 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FSTT2 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FSTT1 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FSTT0 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
line.long 0x04 "PMC_FSPR,PMC Fast Startup Polarity Register"
|
|
bitfld.long 0x04 15. " FSTP15 ,Fast Startup Input Polarityx" "0,1"
|
|
bitfld.long 0x04 14. " FSTP14 ,Fast Startup Input Polarityx" "0,1"
|
|
bitfld.long 0x04 13. " FSTP13 ,Fast Startup Input Polarityx" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 12. " FSTP12 ,Fast Startup Input Polarityx" "0,1"
|
|
bitfld.long 0x04 11. " FSTP11 ,Fast Startup Input Polarityx" "0,1"
|
|
bitfld.long 0x04 10. " FSTP10 ,Fast Startup Input Polarityx" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FSTP9 ,Fast Startup Input Polarityx" "0,1"
|
|
bitfld.long 0x04 8. " FSTP8 ,Fast Startup Input Polarityx" "0,1"
|
|
bitfld.long 0x04 7. " FSTP7 ,Fast Startup Input Polarityx" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 6. " FSTP6 ,Fast Startup Input Polarityx" "0,1"
|
|
bitfld.long 0x04 5. " FSTP5 ,Fast Startup Input Polarityx" "0,1"
|
|
bitfld.long 0x04 4. " FSTP4 ,Fast Startup Input Polarityx" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FSTP3 ,Fast Startup Input Polarityx" "0,1"
|
|
bitfld.long 0x04 2. " FSTP2 ,Fast Startup Input Polarityx" "0,1"
|
|
bitfld.long 0x04 1. " FSTP1 ,Fast Startup Input Polarityx" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 0. " FSTP0 ,Fast Startup Input Polarityx" "0,1"
|
|
else
|
|
rgroup.long 0x70++0x07
|
|
line.long 0x00 "PMC_FSMR,PMC Fast Startup Mode Register"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 23. " FFLPM ,Force Flash Low-power Mode" "Automatic,User defined"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 21.--22. " FLPM ,Flash Low-power Mode" "FLASH_STANDBY,FLASH_DEEP_POWERDOWN,FLASH_IDLE,?..."
|
|
bitfld.long 0x00 20. " LPM ,Low-power Mode" "Sleep Mode,Wait Mode"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 18. " USBAL ,USB Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " RTCAL ,RTC Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RTTAL ,RTT Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " FSTT5 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FSTT4 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FSTT13 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " FSTT12 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " FSTT11 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSTT10 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " FSTT9 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FSTT8 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FSTT7 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FSTT6 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FSTT5 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FSTT4 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FSTT3 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FSTT2 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FSTT1 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FSTT0 ,Fast Startup Input Enable" "Disabled,Enabled"
|
|
line.long 0x04 "PMC_FSPR,PMC Fast Startup Polarity Register"
|
|
bitfld.long 0x04 15. " FSTP15 ,Fast Startup Input Polarityx" "0,1"
|
|
bitfld.long 0x04 14. " FSTP14 ,Fast Startup Input Polarityx" "0,1"
|
|
bitfld.long 0x04 13. " FSTP13 ,Fast Startup Input Polarityx" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 12. " FSTP12 ,Fast Startup Input Polarityx" "0,1"
|
|
bitfld.long 0x04 11. " FSTP11 ,Fast Startup Input Polarityx" "0,1"
|
|
bitfld.long 0x04 10. " FSTP10 ,Fast Startup Input Polarityx" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FSTP9 ,Fast Startup Input Polarityx" "0,1"
|
|
bitfld.long 0x04 8. " FSTP8 ,Fast Startup Input Polarityx" "0,1"
|
|
bitfld.long 0x04 7. " FSTP7 ,Fast Startup Input Polarityx" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 6. " FSTP6 ,Fast Startup Input Polarityx" "0,1"
|
|
bitfld.long 0x04 5. " FSTP5 ,Fast Startup Input Polarityx" "0,1"
|
|
bitfld.long 0x04 4. " FSTP4 ,Fast Startup Input Polarityx" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FSTP3 ,Fast Startup Input Polarityx" "0,1"
|
|
bitfld.long 0x04 2. " FSTP2 ,Fast Startup Input Polarityx" "0,1"
|
|
bitfld.long 0x04 1. " FSTP1 ,Fast Startup Input Polarityx" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 0. " FSTP0 ,Fast Startup Input Polarityx" "0,1"
|
|
endif
|
|
wgroup.long 0x78++0x03
|
|
line.long 0x00 "PMC_FOCR,PMC Fault Output Clear Register"
|
|
bitfld.long 0x00 0. " FOCLR ,Fault Output Clear" "No effect,Clear"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "PMC_WPMR,PMC Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protection Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "PMC_WPSR,PMC Write Protection Status Register"
|
|
in
|
|
sif (cpu()=="ATSAMG55")
|
|
if (((d.l(ad:0x400E0400+0xE4))&0x01)==0x00)
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "PMC_PCSR1,PMC Peripheral Clock Status Register 1"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " CRCCU ,CRCCU (Peripheral ID 49) Clock Status" "No effect,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " UDP ,USB Device FS (Peripheral ID 48) Clock Status" "No effect,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " UHP ,USB OHCI (Peripheral ID 47)" "No effect,Enabled"
|
|
else
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "PMC_PCSR1,PMC Peripheral Clock Status Register 1"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " CRCCU ,CRCCU (Peripheral ID 49) Clock Status" "No effect,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " UDP ,USB Device FS (Peripheral ID 48) Clock Status" "No effect,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " UHP ,USB OHCI (Peripheral ID 47)" "No effect,Enabled"
|
|
endif
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "PMC_PCR,PMC Peripheral Control Register"
|
|
bitfld.long 0x00 28. " EN ,Enable Selected Peripheral clock" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " DIV ,Divisor Value" "PERIPH_DIV_MCK,PERIPH_DIV2_MCK,PERIPH_DIV4_MCK,PERIPH_DIV8_MCK"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMD ,Command" "Read,Write"
|
|
bitfld.long 0x00 0.--5. " PID ,Peripheral ID" ",,,,,,,USART7/SPI7/TWI7,USART0/SPI0/TWI0,USART1/SPI1/TWI1,,PIOA,PIOB,PDMIC0,USART2/SPI2/TWI2,MEM2MEM,I2SC0,I2SC1,PDMIC1,USART3/SPI3/TWI3,USART4/SPI4/TWI4,USART5/SPI5/TWI5,USART6/SPI6/TWI6,TC0,TC1,TC2,TC3,TC4,TC5,ADC,?..."
|
|
endif
|
|
if (((d.l(ad:0x400E0400+0xE4))&0x01)==0x00)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "PMC_OCR,PMC Oscillator Calibration Register"
|
|
bitfld.long 0x00 23. " SEL24 ,Selection of RC Oscillator Calibration bits for 24 MHz" "Factory determined,CAL24"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CAL24 ,RC Oscillator Calibration bits for 24 MHz"
|
|
bitfld.long 0x00 15. " SEL16 ,Selection of RC Oscillator Calibration bits for 16 MHz" "Factory Determined,CAL16"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " CAL16 ,RC Oscillator Calibration bits for 16 MHz"
|
|
bitfld.long 0x00 7. " SEL8 ,Selection of RC Oscillator Calibration bits for 8 MHz" "Default value,CAL8"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CAL8 ,RC Oscillator Calibration bits for 8 MHz"
|
|
else
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "PMC_OCR,PMC Oscillator Calibration Register"
|
|
bitfld.long 0x00 23. " SEL24 ,Selection of RC Oscillator Calibration bits for 24 MHz" "Factory determined,CAL24"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CAL24 ,RC Oscillator Calibration bits for 24 MHz"
|
|
bitfld.long 0x00 15. " SEL16 ,Selection of RC Oscillator Calibration bits for 16 MHz" "Factory Determined,CAL16"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " CAL16 ,RC Oscillator Calibration bits for 16 MHz"
|
|
bitfld.long 0x00 7. " SEL8 ,Selection of RC Oscillator Calibration bits for 8 MHz" "Default value,CAL8"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CAL8 ,RC Oscillator Calibration bits for 8 MHz"
|
|
endif
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
if (((d.l(ad:0x400E0400+0xE4))&0x01)==0x00)
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "PMC_SLPWK_SR0,PMC SleepWalking Status Register 0r"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " PID29_set/clr ,Peripheral ADC SleepWalking Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " PID28_set/clr ,Peripheral TC5 SleepWalking Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " PID27_set/clr ,Peripheral TC4 SleepWalking Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " PID26_set/clr ,Peripheral TC3 SleepWalking Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " PID25_set/clr ,Peripheral TC2 SleepWalking Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " PID24_set/clr ,Peripheral TC1 SleepWalking Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " PID23_set/clr ,Peripheral TC0 SleepWalking Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " PID22_set/clr ,Peripheral USART6/SPI6/TWI6 SleepWalking Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " PID21_set/clr ,Peripheral USART5/SPI5/TWI5 SleepWalking Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " PID20_set/clr ,Peripheral USART4/SPI4/TWI4 SleepWalking Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " PID19_set/clr ,Peripheral USART3/SPI3/TWI3 SleepWalking Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " PID18_set/clr ,Peripheral PDMIC1 SleepWalking Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " PID17_set/clr ,Peripheral I2SC1 SleepWalking Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " PID16_set/clr ,Peripheral I2SC0 SleepWalking Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " PID15_set/clr ,Peripheral MEM2MEM SleepWalking Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " PID14_set/clr ,Peripheral USART2/SPI2/TWI2 SleepWalking Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " PID13_set/clr ,Peripheral PDMIC0 SleepWalking Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " PID12_set/clr ,Peripheral PIOB SleepWalking Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " PID11_set/clr ,Peripheral PIOA SleepWalking Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " PID9_set/clr ,Peripheral USART1/SPI1/TWI1 SleepWalking Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " PID8_set/clr ,Peripheral USART0/SPI0/TWI0 SleepWalking Status" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x11C++0x03
|
|
line.long 0x00 "PMC_SLPWK_SR0,PMC SleepWalking Status Register 0r"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " PID29_set/clr ,Peripheral ADC SleepWalking Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " PID28_set/clr ,Peripheral TC5 SleepWalking Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " PID27_set/clr ,Peripheral TC4 SleepWalking Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " PID26_set/clr ,Peripheral TC3 SleepWalking Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " PID25_set/clr ,Peripheral TC2 SleepWalking Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " PID24_set/clr ,Peripheral TC1 SleepWalking Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " PID23_set/clr ,Peripheral TC0 SleepWalking Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " PID22_set/clr ,Peripheral USART6/SPI6/TWI6 SleepWalking Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " PID21_set/clr ,Peripheral USART5/SPI5/TWI5 SleepWalking Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " PID20_set/clr ,Peripheral USART4/SPI4/TWI4 SleepWalking Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " PID19_set/clr ,Peripheral USART3/SPI3/TWI3 SleepWalking Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " PID18_set/clr ,Peripheral PDMIC1 SleepWalking Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " PID17_set/clr ,Peripheral I2SC1 SleepWalking Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " PID16_set/clr ,Peripheral I2SC0 SleepWalking Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " PID15_set/clr ,Peripheral MEM2MEM SleepWalking Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " PID14_set/clr ,Peripheral USART2/SPI2/TWI2 SleepWalking Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " PID13_set/clr ,Peripheral PDMIC0 SleepWalking Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " PID12_set/clr ,Peripheral PIOB SleepWalking Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " PID11_set/clr ,Peripheral PIOA SleepWalking Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " PID9_set/clr ,Peripheral USART1/SPI1/TWI1 SleepWalking Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " PID8_set/clr ,Peripheral USART0/SPI0/TWI0 SleepWalking Status" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "PMC_SLPWK_ASR0,PMC SleepWalking Activity Status Register 0"
|
|
bitfld.long 0x00 29. " PID29 ,Peripheral ADC Activity Status" "Not active,Active"
|
|
bitfld.long 0x00 28. " PID28 ,Peripheral TC5 Activity Status" "Not active,Active"
|
|
bitfld.long 0x00 27. " PID27 ,Peripheral TC4 Activity Status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PID26 ,Peripheral TC3 Activity Status" "Not active,Active"
|
|
bitfld.long 0x00 25. " PID25 ,Peripheral TC2 Activity Status" "Not active,Active"
|
|
bitfld.long 0x00 24. " PID24 ,Peripheral TC1 Activity Status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PID23 ,Peripheral TC0 Activity Status" "Not active,Active"
|
|
bitfld.long 0x00 22. " PID22 ,Peripheral USART6/SPI6/TWI6 Activity Status" "Not active,Active"
|
|
bitfld.long 0x00 21. " PID21 ,Peripheral USART5/SPI5/TWI5 Activity Status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PID20 ,Peripheral USART4/SPI4/TWI4 Activity Status" "Not active,Active"
|
|
bitfld.long 0x00 19. " PID19 ,Peripheral USART3/SPI3/TWI3 Activity Status" "Not active,Active"
|
|
bitfld.long 0x00 18. " PID18 ,Peripheral PDMIC1 Activity Status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PID17 ,Peripheral I2SC1 Activity Status" "Not active,Active"
|
|
bitfld.long 0x00 16. " PID16 ,Peripheral I2SC0 Activity Status" "Not active,Active"
|
|
bitfld.long 0x00 15. " PID15 ,Peripheral MEM2MEM Activity Status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PID14 ,Peripheral USART2/SPI2/TWI2 Activity Status" "Not active,Active"
|
|
bitfld.long 0x00 13. " PID13 ,Peripheral PDMIC0 Activity Status" "Not active,Active"
|
|
bitfld.long 0x00 12. " PID12 ,Peripheral PIOB Activity Status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PID11 ,Peripheral PIOA Activity Status" "Not active,Active"
|
|
bitfld.long 0x00 9. " PID9 ,Peripheral USART1/SPI1/TWI1 Activity Status" "Not active,Active"
|
|
bitfld.long 0x00 8. " PID8 ,Peripheral USART0/SPI0/TWI0 Activity Status" "Not active,Active"
|
|
endif
|
|
if (((d.l(ad:0x400E0400+0xE4))&0x01)==0x00)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "PMC_PMMR,PLL Maximum Multiplier Value Register"
|
|
sif (cpu()=="ATSAMG55")
|
|
hexmask.long.word 0x00 16.--26. 1. " PLLB_MMAX ,PLLB Maximum Allowed Multiplier Value"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x00 0.--10. 1. " PLLA_MMAX ,PLLA Maximum Allowed Multiplier Value"
|
|
else
|
|
rgroup.long 0x130++0x03
|
|
line.long 0x00 "PMC_PMMR,PLL Maximum Multiplier Value Register"
|
|
sif (cpu()=="ATSAMG55")
|
|
hexmask.long.word 0x00 16.--26. 1. " PLLB_MMAX ,PLLB Maximum Allowed Multiplier Value"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x00 0.--10. 1. " PLLA_MMAX ,PLLA Maximum Allowed Multiplier Value"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "CHIPID (Chip Identifier)"
|
|
base ad:0x400E0740
|
|
width 13.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "CHIPID_CIDR,Chip ID Register"
|
|
bitfld.long 0x00 31. " EXT ,Extension Flag" "No extension,Extension"
|
|
bitfld.long 0x00 28.--30. " NVPTYP ," "ROM,ROMLESS,FLASH,ROM_FLASH,SRAM,?..."
|
|
hexmask.long.byte 0x00 20.--27. 1. " ARCH ,Architecture Identifier"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " SRAMSIZ ,Internal SRAM Size" "48K,192K,384K,6K,24K,4K,80K,160K,8K,16K,32K,64K,128K,256K,96K,512K"
|
|
bitfld.long 0x00 12.--15. " NVPSIZ2 ,Second Nonvolatile Program Memory Size" "NONE,8K,16K,32K,,64K,,128K,,256K,512K,,1024K,,2048K,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " NVPSIZ ,Nonvolatile Program Memory Size" "NONE,8K,16K,32K,,64K,,128K,160K,256K,512K,,1024K,,2048K,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " EPROC ,Embedded Processor" "Cortex-M7,ARM946ES,ARM7TDMI,Cortex-M3,ARM920T,ARM926EJS,Cortex-A5,Cortex-M4"
|
|
bitfld.long 0x00 0.--4. " VERSION ,Version of the Device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "CHIPID_EXID,Chip ID Extension Register"
|
|
hexmask.long 0x04 0.--31. 1. " EXID ,Chip ID Extension"
|
|
width 0xB
|
|
tree.end
|
|
tree.open "PIO (Parallel Input/Output Controller)"
|
|
tree "PI0A"
|
|
base ad:0x400E0E00
|
|
if ((d.l(ad:0x400E0E00+0xE4)&0x01)==0x00)
|
|
width 13.
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PIO_PSR,PIO Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,PIO Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,PIO Status 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,PIO Status 29" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,PIO Status 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,PIO Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,PIO Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,PIO Status 25" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,PIO Status 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,PIO Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,PIO Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,PIO Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO Status 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO Status 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO Status 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO Status 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO Status 13" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO Status 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO Status 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO Status 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO Status 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO Status 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO Status 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO Status 0" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PIO_OSR,PIO Output Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Status pin 31" "Input only,Input/Output"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Status pin 30" "Input only,Input/Output"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Status pin 29" "Input only,Input/Output"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Status pin 28" "Input only,Input/Output"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Status pin 27" "Input only,Input/Output"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Status pin 26" "Input only,Input/Output"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Status pin 25" "Input only,Input/Output"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Status pin 24" "Input only,Input/Output"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Status pin 23" "Input only,Input/Output"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Status pin 22" "Input only,Input/Output"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Status pin 21" "Input only,Input/Output"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Status pin 20" "Input only,Input/Output"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Status pin 19" "Input only,Input/Output"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Status pin 18" "Input only,Input/Output"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Status pin 17" "Input only,Input/Output"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Status pin 16" "Input only,Input/Output"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Status pin 15" "Input only,Input/Output"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Status pin 14" "Input only,Input/Output"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Status pin 13" "Input only,Input/Output"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Status pin 12" "Input only,Input/Output"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Status pin 11" "Input only,Input/Output"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Status pin 10" "Input only,Input/Output"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Status pin 9" "Input only,Input/Output"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Status pin 8" "Input only,Input/Output"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Status pin 7" "Input only,Input/Output"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Status pin 6" "Input only,Input/Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Status pin 5" "Input only,Input/Output"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Status pin 4" "Input only,Input/Output"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Status pin 3" "Input only,Input/Output"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Status pin 2" "Input only,Input/Output"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Status pin 1" "Input only,Input/Output"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Status pin 0" "Input only,Input/Output"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PIO_IFSR,PIO Input Filter Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Input Filer Status pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Input Filer Status pin 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Input Filer Status pin 29" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Input Filer Status pin 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Input Filer Status pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Input Filer Status pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Input Filer Status pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Input Filer Status pin 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Input Filer Status pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Input Filer Status pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Input Filer Status pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Input Filer Status pin 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Input Filer Status pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Input Filer Status pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Input Filer Status pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Input Filer Status pin 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Input Filer Status pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Filer Status pin 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Filer Status pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Filer Status pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Filer Status pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Filer Status pin 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Filer Status pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Filer Status pin 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Filer Status pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Filer Status pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Filer Status pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Filer Status pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Filer Status pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Filer Status pin 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Filer Status pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Filer Status pin 0" "Disabled,Enabled"
|
|
textline ""
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PIO_ODSR,PIO Output Data Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Data Status pin 31" "0,1"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Data Status pin 30" "0,1"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Data Status pin 29" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Data Status pin 28" "0,1"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Data Status pin 27" "0,1"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Data Status pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Data Status pin 25" "0,1"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Data Status pin 24" "0,1"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Data Status pin 23" "0,1"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Data Status pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Data Status pin 21" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Data Status pin 20" "0,1"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Data Status pin 19" "0,1"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Data Status pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Data Status pin 17" "0,1"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Data Status pin 16" "0,1"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Data Status pin 15" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Data Status pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Data Status pin 13" "0,1"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Data Status pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Data Status pin 11" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Data Status pin 10" "0,1"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Data Status pin 9" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Data Status pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Data Status pin 7" "0,1"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Data Status pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Data Status pin 5" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Data Status pin 4" "0,1"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Data Status pin 3" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Data Status pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Data Status pin 1" "0,1"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Data Status pin 0" "0,1"
|
|
textline ""
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "PIO_PDSR,PIO Pin Data Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
bitfld.long 0x00 31. " P31 ,Output Data Status pin 31" "Level 0,Level 1"
|
|
bitfld.long 0x00 30. " P30 ,Output Data Status pin 30" "Level 0,Level 1"
|
|
bitfld.long 0x00 29. " P29 ,Output Data Status pin 29" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " P28 ,Output Data Status pin 28" "Level 0,Level 1"
|
|
bitfld.long 0x00 27. " P27 ,Output Data Status pin 27" "Level 0,Level 1"
|
|
bitfld.long 0x00 26. " P26 ,Output Data Status pin 26" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Data Status pin 25" "Level 0,Level 1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24. " P24 ,Output Data Status pin 24" "Level 0,Level 1"
|
|
bitfld.long 0x00 23. " P23 ,Output Data Status pin 23" "Level 0,Level 1"
|
|
bitfld.long 0x00 22. " P22 ,Output Data Status pin 22" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Data Status pin 21" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Output Data Status pin 20" "Level 0,Level 1"
|
|
bitfld.long 0x00 19. " P19 ,Output Data Status pin 19" "Level 0,Level 1"
|
|
bitfld.long 0x00 18. " P18 ,Output Data Status pin 18" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Data Status pin 17" "Level 0,Level 1"
|
|
bitfld.long 0x00 16. " P16 ,Output Data Status pin 16" "Level 0,Level 1"
|
|
bitfld.long 0x00 15. " P15 ,Output Data Status pin 15" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Output Data Status pin 14" "Level 0,Level 1"
|
|
bitfld.long 0x00 13. " P13 ,Output Data Status pin 13" "Level 0,Level 1"
|
|
bitfld.long 0x00 12. " P12 ,Output Data Status pin 12" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Data Status pin 11" "Level 0,Level 1"
|
|
bitfld.long 0x00 10. " P10 ,Output Data Status pin 10" "Level 0,Level 1"
|
|
bitfld.long 0x00 9. " P9 ,Output Data Status pin 9" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Output Data Status pin 8" "Level 0,Level 1"
|
|
bitfld.long 0x00 7. " P7 ,Output Data Status pin 7" "Level 0,Level 1"
|
|
bitfld.long 0x00 6. " P6 ,Output Data Status pin 6" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Data Status pin 5" "Level 0,Level 1"
|
|
bitfld.long 0x00 4. " P4 ,Output Data Status pin 4" "Level 0,Level 1"
|
|
bitfld.long 0x00 3. " P3 ,Output Data Status pin 3" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Output Data Status pin 2" "Level 0,Level 1"
|
|
bitfld.long 0x00 1. " P1 ,Output Data Status pin 1" "Level 0,Level 1"
|
|
bitfld.long 0x00 0. " P0 ,Output Data Status pin 0" "Level 0,Level 1"
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "PIO_ISR,PIO Interrupt Status Register"
|
|
in
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PIO_IMR,PIO Interrupt Mask Register"
|
|
sif cpu()=="ATSAMG55"
|
|
bitfld.long 0x00 31. " P31 ,Input Change Interrupt Mask pin 31" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " P30 ,Input Change Interrupt Mask pin 30" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " P29 ,Input Change Interrupt Mask pin 29" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " P28 ,Input Change Interrupt Mask pin 28" "Masked,Not masked"
|
|
bitfld.long 0x00 27. " P27 ,Input Change Interrupt Mask pin 27" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " P26 ,Input Change Interrupt Mask pin 26" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Input Change Interrupt Mask pin 25" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24. " P24 ,Input Change Interrupt Mask pin 24" "Masked,Not masked"
|
|
bitfld.long 0x00 23. " P23 ,Input Change Interrupt Mask pin 23" "Masked,Not masked"
|
|
bitfld.long 0x00 22. " P22 ,Input Change Interrupt Mask pin 22" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Input Change Interrupt Mask pin 21" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Input Change Interrupt Mask pin 20" "Masked,Not masked"
|
|
bitfld.long 0x00 19. " P19 ,Input Change Interrupt Mask pin 19" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " P18 ,Input Change Interrupt Mask pin 18" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Input Change Interrupt Mask pin 17" "Masked,Not masked"
|
|
bitfld.long 0x00 16. " P16 ,Input Change Interrupt Mask pin 16" "Masked,Not masked"
|
|
bitfld.long 0x00 15. " P15 ,Input Change Interrupt Mask pin 15" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Input Change Interrupt Mask pin 14" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " P13 ,Input Change Interrupt Mask pin 13" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " P12 ,Input Change Interrupt Mask pin 12" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Input Change Interrupt Mask pin 11" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " P10 ,Input Change Interrupt Mask pin 10" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " P9 ,Input Change Interrupt Mask pin 9" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Input Change Interrupt Mask pin 8" "Masked,Not masked"
|
|
bitfld.long 0x00 7. " P7 ,Input Change Interrupt Mask pin 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " P6 ,Input Change Interrupt Mask pin 6" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Input Change Interrupt Mask pin 5" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " P4 ,Input Change Interrupt Mask pin 4" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " P3 ,Input Change Interrupt Mask pin 3" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Input Change Interrupt Mask pin 2" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " P1 ,Input Change Interrupt Mask pin 1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " P0 ,Input Change Interrupt Mask pin 0" "Masked,Not masked"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PIO_MDSR,PIO Multi-driver Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Multi Drive Status/Drive pin 31" "Low,High"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Multi Drive Status/Drive pin 30" "Low,High"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Multi Drive Status/Drive pin 29" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Multi Drive Status/Drive pin 28" "Low,High"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Multi Drive Status/Drive pin 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Multi Drive Status/Drive pin 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Multi Drive Status/Drive pin 25" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Multi Drive Status/Drive pin 24" "Low,High"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Multi Drive Status/Drive pin 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Multi Drive Status/Drive pin 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Multi Drive Status/Drive pin 21" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Multi Drive Status/Drive pin 20" "Low,High"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Multi Drive Status/Drive pin 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Multi Drive Status/Drive pin 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Multi Drive Status/Drive pin 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Multi Drive Status/Drive pin 16" "Low,High"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Multi Drive Status/Drive pin 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Multi Drive Status/Drive pin 14" "Low,High"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Multi Drive Status/Drive pin 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Multi Drive Status/Drive pin 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Multi Drive Status/Drive pin 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Multi Drive Status/Drive pin 10" "Low,High"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Multi Drive Status/Drive pin 9" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Multi Drive Status/Drive pin 8" "Low,High"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Multi Drive Status/Drive pin 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Multi Drive Status/Drive pin 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Multi Drive Status/Drive pin 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Multi Drive Status/Drive pin 4" "Low,High"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Multi Drive Status/Drive pin 3" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Multi Drive Status/Drive pin 2" "Low,High"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Multi Drive Status/Drive pin 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Multi Drive Status/Drive pin 0" "Low,High"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PIO_PUSR,PIO Pull Up Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Pull Up Status pin 31" "Enabled,Disabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Pull Up Status pin 30" "Enabled,Disabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Pull Up Status pin 29" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Pull Up Status pin 28" "Enabled,Disabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Pull Up Status pin 27" "Enabled,Disabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Pull Up Status pin 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Pull Up Status pin 25" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Pull Up Status pin 24" "Enabled,Disabled"
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_set/clr ,Pull Up Status pin 23" "Enabled,Disabled"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_set/clr ,Pull Up Status pin 22" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_set/clr ,Pull Up Status pin 21" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Pull Up Status pin 20" "Enabled,Disabled"
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_set/clr ,Pull Up Status pin 19" "Enabled,Disabled"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_set/clr ,Pull Up Status pin 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_set/clr ,Pull Up Status pin 17" "Enabled,Disabled"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_set/clr ,Pull Up Status pin 16" "Enabled,Disabled"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Pull Up Status pin 15" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Pull Up Status pin 14" "Enabled,Disabled"
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Pull Up Status pin 13" "Enabled,Disabled"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Pull Up Status pin 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Pull Up Status pin 11" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Pull Up Status pin 10" "Enabled,Disabled"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Pull Up Status pin 9" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Pull Up Status pin 8" "Enabled,Disabled"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Pull Up Status pin 7" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Pull Up Status pin 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Pull Up Status pin 5" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Pull Up Status pin 4" "Enabled,Disabled"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Pull Up Status pin 3" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Pull Up Status pin 2" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr ,Pull Up Status pin 1" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Pull Up Status pin 0" "Enabled,Disabled"
|
|
textline ""
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "PIO_ABCDSR1,Peripheral Select Register 1"
|
|
sif cpu()=="ATSAMG55"
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Select pin 31 - A/C B/D" "PCK2/C,SPI7_NPCS1/RTS7/D"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Select pin 30 - A/C B/D" "PCK1/C,SPI7_NPCS0/CTS7/D"
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Select pin 29 - A/C B/D" "SPI1_NPCS1/RTS1/C,SCK7/SPI7_SPCK/D"
|
|
textline " "
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Select pin 28 - A/C B/D" "SPI1_NPCS0/CTS1/C,TXD7/SPI7_MOSI/TWD7/D"
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Select pin 27 - A/C B/D" "SCK1/SPI1_SPCK/C,RXD7/SPI7_MISO/TWCK7/D"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Select pin 26 - A/C B/D" "SPI0_NPCS1/RTS0/C,I2SMCK1/D"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Select pin 25 - A/C B/D" "SPI0_NPCS0/CTS0/C,I2SDO1/D"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Select pin 24 - A/C B/D" "I2SMCK1/C,SCK2/SPI2_SPCK/D"
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Select pin 23 - A/C B/D" "I2SDO1/C,TIOA1/D"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Select pin 22 - A/C B/D" "TIOB2/C,I2SDI1/D"
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Select pin 21 - A/C B/D" "TIOA2/C,PCK1/D"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Select pin 20 - A/C B/D" "TCLK2/C,I2SWS1/D"
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Select pin 19 - A/C B/D" "TCLK1/C,I2SCK1/D"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Select pin 18 - A/C B/D" "I2SMCK0/C,PCK2/D"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Select pin 17 - A/C B/D" "I2SDO0/C,PCK1/D"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Select pin 16 - A/C B/D" "SPI2_NPCS0/CTS2/C,TIOB1/D"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select pin 15 - A/C B/D" "SPI2_NPCS1/RTS2/C,SCK2/SPI2_SPCK/D"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select pin 14 - A/C B/D" "SCK5/SPI5_SPCK/C,B/D"
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select pin 13 - A/C B/D" "TXD5/SPI5_MOSI/TWD5/C,B/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select pin 12 - A/C B/D" "RXD5/SPI5_MISO/TWCK5/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select pin 11 - A/C B/D" "SPI5_NPCS0/CTS5/C,B/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select pin 10 - A/C B/D" "TXD0/SPI0_MOSI/TWD0/C,PDMIC_CLK/D"
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select pin 9 - A/C B/D" "RXD0/SPI0_MISO/TWCK0/C,PDMIC_DAT/D"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select pin 8 - A/C B/D" "A/C,ADTRG/D"
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select pin 7 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select pin 6 - A/C B/D" "TXD2/SPI2_MOSI/TWD2/C,PCK0/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select pin 5 - A/C B/D" "RXD2/SPI2_MISO/TWCK2/C,SPI5_NPCS1/RTS5/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select pin 4 - A/C B/D" "RXD3/SPI3_MISO/TWCK3/C,I2SMCK0/D"
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select pin 3 - A/C B/D" "TXD3/SPI3_MOSI/TWD3/C,I2SDO0/D"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select pin 2 - A/C B/D" "TCLK0/C,I2SDI0/D"
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select pin 1 - A/C B/D" "I2SWS0/C,TIOB0/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select pin 0 - A/C B/D" "I2SCK0/C,TIOA0/D"
|
|
elif cpuis("ATSAMG54")||cpuis("ATSAMG53")
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Select pin 24 - A/C B/D" "I2SMCK1/C,B/D"
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Select pin 23 - A/C B/D" "I2SDO1/C,TIOA1/D"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Select pin 22 - A/C B/D" "TIOB2/C,I2SDI1/D"
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Select pin 21 - A/C B/D" "TIOA2/C,PCK1/D"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Select pin 20 - A/C B/D" "TCLK2/C,I2SWS1/D"
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Select pin 19 - A/C B/D" "TCLK1/C,I2SCK1/D"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Select pin 18 - A/C B/D" "I2SMCK0/C,PCK2/D"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Select pin 17 - A/C B/D" "I2SDO0/C,PCK1/D"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Select pin 16 - A/C B/D" "CTS/C,TIOB1/D"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select pin 15 - A/C B/D" "RTS/C,SCK/D"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select pin 14 - A/C B/D" "SPCK/C,B/D"
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select pin 13 - A/C B/D" "MOSI/C,B/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select pin 12 - A/C B/D" "MISO/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select pin 11 - A/C B/D" "NPCS0/C,B/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select pin 10 - A/C B/D" "UTXD0/C,PDMCLK0/D"
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select pin 9 - A/C B/D" "URXD0/C,PDMDAT0/D"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select pin 8 - A/C B/D" "A/C,ADTRG/D"
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select pin 7 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select pin 6 - A/C B/D" "TXD/C,PCK0/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select pin 5 - A/C B/D" "RXD/C,NPCS1/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select pin 4 - A/C B/D" "TWCK0/C,I2SMCK0/D"
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select pin 3 - A/C B/D" "TWD0/C,I2SDO0/D"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select pin 2 - A/C B/D" "TCLK0/C,I2SDI0/D"
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select pin 1 - A/C B/D" "I2SWS0/C,TIOB0/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select pin 0 - A/C B/D" "I2SCK0/C,TIOA0/D"
|
|
else
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Select pin 24 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Select pin 23 - A/C B/D" "A/C,TIOA1/D"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Select pin 22 - A/C B/D" "TIOB2/C,B/D"
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Select pin 21 - A/C B/D" "TIOA2/C,PCK1/D"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Select pin 20 - A/C B/D" "TCLK2/C,B/D"
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Select pin 19 - A/C B/D" "TCLK1/C,B/D"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Select pin 18 - A/C B/D" "A/C,PCK2/D"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Select pin 17 - A/C B/D" "A/C,PCK1/D"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Select pin 16 - A/C B/D" "CTS/C,TIOB1/D"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select pin 15 - A/C B/D" "RTS/C,SCK/D"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select pin 14 - A/C B/D" "SPCK/C,B/D"
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select pin 13 - A/C B/D" "MOSI/C,B/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select pin 12 - A/C B/D" "MISO/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select pin 11 - A/C B/D" "NPCS0/C,B/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select pin 10 - A/C B/D" "UTXD0/C,B/D"
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select pin 9 - A/C B/D" "URXD0/C,NPCS1/D"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select pin 8 - A/C B/D" "A/C,ADTRG/D"
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select pin 7 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select pin 6 - A/C B/D" "TXD/C,PCK0/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select pin 5 - A/C B/D" "RXD/C,B/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select pin 4 - A/C B/D" "TWCK0/C,B/D"
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select pin 3 - A/C B/D" "TWD0/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select pin 2 - A/C B/D" "TCLK0/C,B/D"
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select pin 1 - A/C B/D" "A/C,TIOB0/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select pin 0 - A/C B/D" "A/C,TIOA0/D"
|
|
endif
|
|
line.long 0x04 "PIO_ABCDSR2,Peripheral Select Register 2"
|
|
sif cpu()=="ATSAMG55"
|
|
bitfld.long 0x04 31. " P31 ,Peripheral Select pin 31 - A/C B/D" "PCK2/SPI7_NPCS1/RTS7,C/D"
|
|
bitfld.long 0x04 30. " P30 ,Peripheral Select pin 30 - A/C B/D" "PCK1/SPI7_NPCS0/CTS7,C/D"
|
|
bitfld.long 0x04 29. " P29 ,Peripheral Select pin 29 - A/C B/D" "SPI1_NPCS1/RTS1/SCK7/SPI7_SPCK,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 28. " P28 ,Peripheral Select pin 28 - A/C B/D" "SPI1_NPCS0/CTS1/TXD7/SPI7_MOSI/TWD7,C/D"
|
|
bitfld.long 0x04 27. " P27 ,Peripheral Select pin 27 - A/C B/D" "SCK1/SPI1_SPCK/RXD7/SPI7_MISO/TWCK7,C/D"
|
|
bitfld.long 0x04 26. " P26 ,Peripheral Select pin 26 - A/C B/D" "SPI0_NPCS1/RTS0/I2SMCK1,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 25. " P25 ,Peripheral Select pin 25 - A/C B/D" "SPI0_NPCS0/CTS0/I2SDO1,C/D"
|
|
bitfld.long 0x04 24. " P24 ,Peripheral Select pin 24 - A/C B/D" "I2SMCK1/SCK2/SPI2_SPCK,C/D"
|
|
bitfld.long 0x04 23. " P23 ,Peripheral Select pin 23 - A/C B/D" "I2SDO1/TIOA1,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 22. " P22 ,Peripheral Select pin 22 - A/C B/D" "TIOB2/I2SDI1,C/D"
|
|
bitfld.long 0x04 21. " P21 ,Peripheral Select pin 21 - A/C B/D" "TIOA2/PCK1,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 20. " P20 ,Peripheral Select pin 20 - A/C B/D" "TCLK2/I2SWS1,C/D"
|
|
bitfld.long 0x04 19. " P19 ,Peripheral Select pin 19 - A/C B/D" "TCLK1/I2SCK1,C/D"
|
|
bitfld.long 0x04 18. " P18 ,Peripheral Select pin 18 - A/C B/D" "I2SMCK0/PCK2,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 17. " P17 ,Peripheral Select pin 17 - A/C B/D" "I2SDO0/PCK1,C/D"
|
|
bitfld.long 0x04 16. " P16 ,Peripheral Select pin 16 - A/C B/D" "SPI2_NPCS0/CTS2/TIOB1,C/D"
|
|
bitfld.long 0x04 15. " P15 ,Peripheral Select pin 15 - A/C B/D" "SPI2_NPCS1/RTS2/SCK2/SPI2_SPCK,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 14. " P14 ,Peripheral Select pin 14 - A/C B/D" "SCK5/SPI5_SPCK/B,C/D"
|
|
bitfld.long 0x04 13. " P13 ,Peripheral Select pin 13 - A/C B/D" "TXD5/SPI5_MOSI/TWD5/B,C/D"
|
|
bitfld.long 0x04 12. " P12 ,Peripheral Select pin 12 - A/C B/D" "RXD5/SPI5_MISO/TWCK5/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 11. " P11 ,Peripheral Select pin 11 - A/C B/D" "SPI5_NPCS0/CTS5/B,C/D"
|
|
bitfld.long 0x04 10. " P10 ,Peripheral Select pin 10 - A/C B/D" "TXD0/SPI0_MOSI/TWD0/PDMIC_CLK,C/D"
|
|
bitfld.long 0x04 9. " P9 ,Peripheral Select pin 9 - A/C B/D" "RXD0/SPI0_MISO/TWCK0/PDMIC_DAT,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 8. " P8 ,Peripheral Select pin 8 - A/C B/D" "A/ADTRG,C/D"
|
|
bitfld.long 0x04 7. " P7 ,Peripheral Select pin 7 - A/C B/D" "A/B,C/D"
|
|
bitfld.long 0x04 6. " P6 ,Peripheral Select pin 6 - A/C B/D" "TXD2/SPI2_MOSI/TWD2/PCK0,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 5. " P5 ,Peripheral Select pin 5 - A/C B/D" "RXD2/SPI2_MISO/TWCK2/SPI5_NPCS1/RTS5,C/D"
|
|
bitfld.long 0x04 4. " P4 ,Peripheral Select pin 4 - A/C B/D" "RXD3/SPI3_MISO/TWCK3/I2SMCK0,C/D"
|
|
bitfld.long 0x04 3. " P3 ,Peripheral Select pin 3 - A/C B/D" "TXD3/SPI3_MOSI/TWD3/I2SDO0,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 2. " P2 ,Peripheral Select pin 2 - A/C B/D" "TCLK0/I2SDI0,C/D"
|
|
bitfld.long 0x04 1. " P1 ,Peripheral Select pin 1 - A/C B/D" "I2SWS0/TIOB0,C/D"
|
|
bitfld.long 0x04 0. " P0 ,Peripheral Select pin 0 - A/C B/D" "I2SCK0/TIOA0,C/D"
|
|
elif cpuis("ATSAMG54")||cpuis("ATSAMG53")
|
|
bitfld.long 0x04 24. " P24 ,Peripheral Select pin 24 - A/C B/D" "I2SMCK1/B,C/D"
|
|
bitfld.long 0x04 23. " P23 ,Peripheral Select pin 23 - A/B C/D" "I2SDO1/C,TIOA1/D"
|
|
textline " "
|
|
bitfld.long 0x04 22. " P22 ,Peripheral Select pin 22 - A/C B/D" "TIOB2/I2SDI1,C/D"
|
|
bitfld.long 0x04 21. " P21 ,Peripheral Select pin 21 - A/C B/D" "TIOA2/PCK1,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 20. " P20 ,Peripheral Select pin 20 - A/C B/D" "TCLK2/I2SWS1,C/D"
|
|
bitfld.long 0x04 19. " P19 ,Peripheral Select pin 19 - A/C B/D" "TCLK1/I2SCK1,C/D"
|
|
bitfld.long 0x04 18. " P18 ,Peripheral Select pin 18 - A/C B/D" "I2SMCK0/PCK2,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 17. " P17 ,Peripheral Select pin 17 - A/C B/D" "I2SDO0/PCK1,C/D"
|
|
bitfld.long 0x04 16. " P16 ,Peripheral Select pin 16 - A/C B/D" "CTS/TIOB1,C/D"
|
|
bitfld.long 0x04 15. " P15 ,Peripheral Select pin 15 - A/C B/D" "RTS/SCK,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 14. " P14 ,Peripheral Select pin 14 - A/C B/D" "SPCK/B,C/D"
|
|
bitfld.long 0x04 13. " P13 ,Peripheral Select pin 13 - A/C B/D" "MOSI/B,C/D"
|
|
bitfld.long 0x04 12. " P12 ,Peripheral Select pin 12 - A/C B/D" "MISO/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 11. " P11 ,Peripheral Select pin 11 - A/C B/D" "NPCS0/B,C/D"
|
|
bitfld.long 0x04 10. " P10 ,Peripheral Select pin 10 - A/C B/D" "UTXD0/PDMCLK0,C/D"
|
|
bitfld.long 0x04 9. " P9 ,Peripheral Select pin 9 - A/C B/D" "URXD0/PDMDAT0,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 8. " P8 ,Peripheral Select pin 8 - A/C B/D" "A/ADTRG,C/D"
|
|
bitfld.long 0x04 7. " P7 ,Peripheral Select pin 7 - A/C B/D" "A/B,C/D"
|
|
bitfld.long 0x04 6. " P6 ,Peripheral Select pin 6 - A/C B/D" "TXD/PCK0,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 5. " P5 ,Peripheral Select pin 5 - A/C B/D" "RXD/NPCS1,C/D"
|
|
bitfld.long 0x04 4. " P4 ,Peripheral Select pin 4 - A/C B/D" "TWCK0/I2SMCK0,C/D"
|
|
bitfld.long 0x04 3. " P3 ,Peripheral Select pin 3 - A/C B/D" "TWD0/I2SDO0,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 2. " P2 ,Peripheral Select pin 2 - A/C B/D" "TCLK0/I2SDI0,C/D"
|
|
bitfld.long 0x04 1. " P1 ,Peripheral Select pin 1 - A/C B/D" "I2SWS0/TIOB0,C/D"
|
|
bitfld.long 0x04 0. " P0 ,Peripheral Select pin 0 - A/C B/D" "I2SCK0/TIOA0,C/D"
|
|
else
|
|
bitfld.long 0x04 23. " P23 ,Peripheral Select pin 23 - A/B C/D" "A/TIOA1,C/D"
|
|
bitfld.long 0x04 22. " P22 ,Peripheral Select pin 22 - A/B C/D" "TIOB2/B,C/D"
|
|
bitfld.long 0x04 21. " P21 ,Peripheral Select pin 21 - A/B C/D" "TIOA2/PCK1,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 20. " P20 ,Peripheral Select pin 20 - A/B C/D" "TCLK2/B,C/D"
|
|
bitfld.long 0x04 19. " P19 ,Peripheral Select pin 19 - A/B C/D" "TCLK1/B,C/D"
|
|
bitfld.long 0x04 18. " P18 ,Peripheral Select pin 18 - A/B C/D" "A/PCK2,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 17. " P17 ,Peripheral Select pin 17 - A/B C/D" "A/PCK1,C/D"
|
|
bitfld.long 0x04 16. " P16 ,Peripheral Select pin 16 - A/B C/D" "CTS/TIOB1,C/D"
|
|
bitfld.long 0x04 15. " P15 ,Peripheral Select pin 15 - A/B C/D" "RTS/SCK,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 14. " P14 ,Peripheral Select pin 14 - A/B C/D" "SPCK/B,C/D"
|
|
bitfld.long 0x04 13. " P13 ,Peripheral Select pin 13 - A/B C/D" "MOSI/B,C/D"
|
|
bitfld.long 0x04 12. " P12 ,Peripheral Select pin 12 - A/B C/D" "MISO/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 11. " P11 ,Peripheral Select pin 11 - A/B C/D" "NPCS0/B,C/D"
|
|
bitfld.long 0x04 10. " P10 ,Peripheral Select pin 10 - A/B C/D" "UTXD0/B,C/D"
|
|
bitfld.long 0x04 9. " P9 ,Peripheral Select pin 9 - A/B C/D" "URXD0/NPCS1,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 8. " P8 ,Peripheral Select pin 8 - A/B C/D" "A/ADTRG,C/D"
|
|
bitfld.long 0x04 7. " P7 ,Peripheral Select pin 7 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 6. " P6 ,Peripheral Select pin 6 - A/B C/D" "TXD/PCK0,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 5. " P5 ,Peripheral Select pin 5 - A/B C/D" "RXD/B,C/D"
|
|
bitfld.long 0x04 4. " P4 ,Peripheral Select pin 4 - A/B C/D" "TWCK0/B,C/D"
|
|
bitfld.long 0x04 3. " P3 ,Peripheral Select pin 3 - A/B C/D" "TWD0/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 2. " P2 ,Peripheral Select pin 2 - A/B C/D" "TCLK0/B,C/D"
|
|
bitfld.long 0x04 1. " P1 ,Peripheral Select pin 1 - A/B C/D" "A/TIOB0,C/D"
|
|
bitfld.long 0x04 0. " P0 ,Peripheral Select pin 0 - A/B C/D" "A/TIOA0,C/D"
|
|
endif
|
|
textline ""
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PIO_IFSCSR,PIO Input Filter Slow Clock Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Glitch or Debouncing Filter Selection Status pin 31" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Glitch or Debouncing Filter Selection Status pin 30" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Glitch or Debouncing Filter Selection Status pin 29" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Glitch or Debouncing Filter Selection Status pin 28" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Glitch or Debouncing Filter Selection Status pin 27" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Glitch or Debouncing Filter Selection Status pin 26" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Glitch or Debouncing Filter Selection Status pin 25" "Glitch,Debouncing"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Glitch or Debouncing Filter Selection Status pin 24" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_set/clr ,Glitch or Debouncing Filter Selection Status pin 23" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_set/clr ,Glitch or Debouncing Filter Selection Status pin 22" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_set/clr ,Glitch or Debouncing Filter Selection Status pin 21" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Glitch or Debouncing Filter Selection Status pin 20" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_set/clr ,Glitch or Debouncing Filter Selection Status pin 19" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_set/clr ,Glitch or Debouncing Filter Selection Status pin 18" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_set/clr ,Glitch or Debouncing Filter Selection Status pin 17" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_set/clr ,Glitch or Debouncing Filter Selection Status pin 16" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Glitch or Debouncing Filter Selection Status pin 15" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status pin 14" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status pin 13" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status pin 12" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status pin 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status pin 10" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status pin 9" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status pin 8" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status pin 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status pin 6" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status pin 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status pin 4" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status pin 3" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status pin 2" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr ,Glitch or Debouncing Filter Selection Status pin 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status pin 0" "Glitch,Debouncing"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PIO_SCDR,PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow Clock Divider Selection for Debouncing"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PIO_PPDSR,PIO Pad Pull Down Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Pull Down Status pin 31" "Enabled,Disabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Pull Down Status pin 30" "Enabled,Disabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Pull Down Status pin 29" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Pull Down Status pin 28" "Enabled,Disabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Pull Down Status pin 27" "Enabled,Disabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Pull Down Status pin 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Pull Down Status pin 25" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Pull Down Status pin 24" "Enabled,Disabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Pull Down Status pin 23" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Pull Down Status pin 22" "Enabled,Disabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Pull Down Status pin 21" "Enabled,Disabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Pull Down Status pin 20" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Pull Down Status pin 19" "Enabled,Disabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Pull Down Status pin 18" "Enabled,Disabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Pull Down Status pin 17" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Pull Down Status pin 16" "Enabled,Disabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Pull Down Status pin 15" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Pull Down Status pin 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Pull Down Status pin 13" "Enabled,Disabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Pull Down Status pin 12" "Enabled,Disabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Pull Down Status pin 11" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Pull Down Status pin 10" "Enabled,Disabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Pull Down Status pin 9" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Pull Down Status pin 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Pull Down Status pin 7" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Pull Down Status pin 6" "Enabled,Disabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Pull Down Status pin 5" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Pull Down Status pin 4" "Enabled,Disabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Pull Down Status pin 3" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Pull Down Status pin 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Pull Down Status pin 1" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Pull Down Status pin 0" "Enabled,Disabled"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PIO_OWSR,PIO Output Write Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Write Status pin 31" "Enabled,Disabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Write Status pin 30" "Enabled,Disabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Write Status pin 29" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Write Status pin 28" "Enabled,Disabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Write Status pin 27" "Enabled,Disabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Write Status pin 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Write Status pin 25" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Write Status pin 24" "Enabled,Disabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Write Status pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Write Status pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Write Status pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Write Status pin 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Write Status pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Write Status pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Write Status pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Write Status pin 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Write Status pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Write Status pin 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Write Status pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Write Status pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Write Status pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Write Status pin 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Write Status pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Write Status pin 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Write Status pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Write Status pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Write Status pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Write Status pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Write Status pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Write Status pin 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Write Status pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Write Status pin 0" "Disabled,Enabled"
|
|
width 0x0b
|
|
else
|
|
width 13.
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PIO_PSR,PIO Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,PIO Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,PIO Status 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,PIO Status 29" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,PIO Status 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,PIO Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,PIO Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,PIO Status 25" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,PIO Status 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,PIO Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,PIO Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,PIO Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO Status 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO Status 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO Status 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO Status 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO Status 13" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO Status 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO Status 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO Status 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO Status 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO Status 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO Status 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO Status 0" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PIO_OSR,PIO Output Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Status pin 31" "Input only,Input/Output"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Status pin 30" "Input only,Input/Output"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Status pin 29" "Input only,Input/Output"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Status pin 28" "Input only,Input/Output"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Status pin 27" "Input only,Input/Output"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Status pin 26" "Input only,Input/Output"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Status pin 25" "Input only,Input/Output"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Status pin 24" "Input only,Input/Output"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Status pin 23" "Input only,Input/Output"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Status pin 22" "Input only,Input/Output"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Status pin 21" "Input only,Input/Output"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Status pin 20" "Input only,Input/Output"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Status pin 19" "Input only,Input/Output"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Status pin 18" "Input only,Input/Output"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Status pin 17" "Input only,Input/Output"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Status pin 16" "Input only,Input/Output"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Status pin 15" "Input only,Input/Output"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Status pin 14" "Input only,Input/Output"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Status pin 13" "Input only,Input/Output"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Status pin 12" "Input only,Input/Output"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Status pin 11" "Input only,Input/Output"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Status pin 10" "Input only,Input/Output"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Status pin 9" "Input only,Input/Output"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Status pin 8" "Input only,Input/Output"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Status pin 7" "Input only,Input/Output"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Status pin 6" "Input only,Input/Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Status pin 5" "Input only,Input/Output"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Status pin 4" "Input only,Input/Output"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Status pin 3" "Input only,Input/Output"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Status pin 2" "Input only,Input/Output"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Status pin 1" "Input only,Input/Output"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Status pin 0" "Input only,Input/Output"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PIO_IFSR,PIO Input Filter Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Input Filer Status pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Input Filer Status pin 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Input Filer Status pin 29" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Input Filer Status pin 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Input Filer Status pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Input Filer Status pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Input Filer Status pin 25" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Input Filer Status pin 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Input Filer Status pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Input Filer Status pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Input Filer Status pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Input Filer Status pin 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Input Filer Status pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Input Filer Status pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Input Filer Status pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Input Filer Status pin 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Input Filer Status pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Filer Status pin 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Filer Status pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Filer Status pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Filer Status pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Filer Status pin 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Filer Status pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Filer Status pin 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Filer Status pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Filer Status pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Filer Status pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Filer Status pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Filer Status pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Filer Status pin 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Filer Status pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Filer Status pin 0" "Disabled,Enabled"
|
|
textline ""
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PIO_ODSR,PIO Output Data Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Data Status pin 31" "0,1"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Data Status pin 30" "0,1"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Data Status pin 29" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Data Status pin 28" "0,1"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Data Status pin 27" "0,1"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Data Status pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Data Status pin 25" "0,1"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Data Status pin 24" "0,1"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Data Status pin 23" "0,1"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Data Status pin 22" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Data Status pin 21" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Data Status pin 20" "0,1"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Data Status pin 19" "0,1"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Data Status pin 18" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Data Status pin 17" "0,1"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Data Status pin 16" "0,1"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Data Status pin 15" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Data Status pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Data Status pin 13" "0,1"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Data Status pin 12" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Data Status pin 11" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Data Status pin 10" "0,1"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Data Status pin 9" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Data Status pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Data Status pin 7" "0,1"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Data Status pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Data Status pin 5" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Data Status pin 4" "0,1"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Data Status pin 3" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Data Status pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Data Status pin 1" "0,1"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Data Status pin 0" "0,1"
|
|
textline ""
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "PIO_PDSR,PIO Pin Data Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
bitfld.long 0x00 31. " P31 ,Output Data Status pin 31" "Level 0,Level 1"
|
|
bitfld.long 0x00 30. " P30 ,Output Data Status pin 30" "Level 0,Level 1"
|
|
bitfld.long 0x00 29. " P29 ,Output Data Status pin 29" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " P28 ,Output Data Status pin 28" "Level 0,Level 1"
|
|
bitfld.long 0x00 27. " P27 ,Output Data Status pin 27" "Level 0,Level 1"
|
|
bitfld.long 0x00 26. " P26 ,Output Data Status pin 26" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Data Status pin 25" "Level 0,Level 1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24. " P24 ,Output Data Status pin 24" "Level 0,Level 1"
|
|
bitfld.long 0x00 23. " P23 ,Output Data Status pin 23" "Level 0,Level 1"
|
|
bitfld.long 0x00 22. " P22 ,Output Data Status pin 22" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Data Status pin 21" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Output Data Status pin 20" "Level 0,Level 1"
|
|
bitfld.long 0x00 19. " P19 ,Output Data Status pin 19" "Level 0,Level 1"
|
|
bitfld.long 0x00 18. " P18 ,Output Data Status pin 18" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Data Status pin 17" "Level 0,Level 1"
|
|
bitfld.long 0x00 16. " P16 ,Output Data Status pin 16" "Level 0,Level 1"
|
|
bitfld.long 0x00 15. " P15 ,Output Data Status pin 15" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Output Data Status pin 14" "Level 0,Level 1"
|
|
bitfld.long 0x00 13. " P13 ,Output Data Status pin 13" "Level 0,Level 1"
|
|
bitfld.long 0x00 12. " P12 ,Output Data Status pin 12" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Data Status pin 11" "Level 0,Level 1"
|
|
bitfld.long 0x00 10. " P10 ,Output Data Status pin 10" "Level 0,Level 1"
|
|
bitfld.long 0x00 9. " P9 ,Output Data Status pin 9" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Output Data Status pin 8" "Level 0,Level 1"
|
|
bitfld.long 0x00 7. " P7 ,Output Data Status pin 7" "Level 0,Level 1"
|
|
bitfld.long 0x00 6. " P6 ,Output Data Status pin 6" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Data Status pin 5" "Level 0,Level 1"
|
|
bitfld.long 0x00 4. " P4 ,Output Data Status pin 4" "Level 0,Level 1"
|
|
bitfld.long 0x00 3. " P3 ,Output Data Status pin 3" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Output Data Status pin 2" "Level 0,Level 1"
|
|
bitfld.long 0x00 1. " P1 ,Output Data Status pin 1" "Level 0,Level 1"
|
|
bitfld.long 0x00 0. " P0 ,Output Data Status pin 0" "Level 0,Level 1"
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "PIO_ISR,PIO Interrupt Status Register"
|
|
in
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PIO_IMR,PIO Interrupt Mask Register"
|
|
sif cpu()=="ATSAMG55"
|
|
bitfld.long 0x00 31. " P31 ,Input Change Interrupt Mask pin 31" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " P30 ,Input Change Interrupt Mask pin 30" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " P29 ,Input Change Interrupt Mask pin 29" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " P28 ,Input Change Interrupt Mask pin 28" "Masked,Not masked"
|
|
bitfld.long 0x00 27. " P27 ,Input Change Interrupt Mask pin 27" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " P26 ,Input Change Interrupt Mask pin 26" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Input Change Interrupt Mask pin 25" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24. " P24 ,Input Change Interrupt Mask pin 24" "Masked,Not masked"
|
|
bitfld.long 0x00 23. " P23 ,Input Change Interrupt Mask pin 23" "Masked,Not masked"
|
|
bitfld.long 0x00 22. " P22 ,Input Change Interrupt Mask pin 22" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Input Change Interrupt Mask pin 21" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Input Change Interrupt Mask pin 20" "Masked,Not masked"
|
|
bitfld.long 0x00 19. " P19 ,Input Change Interrupt Mask pin 19" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " P18 ,Input Change Interrupt Mask pin 18" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Input Change Interrupt Mask pin 17" "Masked,Not masked"
|
|
bitfld.long 0x00 16. " P16 ,Input Change Interrupt Mask pin 16" "Masked,Not masked"
|
|
bitfld.long 0x00 15. " P15 ,Input Change Interrupt Mask pin 15" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Input Change Interrupt Mask pin 14" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " P13 ,Input Change Interrupt Mask pin 13" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " P12 ,Input Change Interrupt Mask pin 12" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Input Change Interrupt Mask pin 11" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " P10 ,Input Change Interrupt Mask pin 10" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " P9 ,Input Change Interrupt Mask pin 9" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Input Change Interrupt Mask pin 8" "Masked,Not masked"
|
|
bitfld.long 0x00 7. " P7 ,Input Change Interrupt Mask pin 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " P6 ,Input Change Interrupt Mask pin 6" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Input Change Interrupt Mask pin 5" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " P4 ,Input Change Interrupt Mask pin 4" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " P3 ,Input Change Interrupt Mask pin 3" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Input Change Interrupt Mask pin 2" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " P1 ,Input Change Interrupt Mask pin 1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " P0 ,Input Change Interrupt Mask pin 0" "Masked,Not masked"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PIO_MDSR,PIO Multi-driver Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Multi Drive Status/Drive pin 31" "Low,High"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Multi Drive Status/Drive pin 30" "Low,High"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Multi Drive Status/Drive pin 29" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Multi Drive Status/Drive pin 28" "Low,High"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Multi Drive Status/Drive pin 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Multi Drive Status/Drive pin 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Multi Drive Status/Drive pin 25" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Multi Drive Status/Drive pin 24" "Low,High"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Multi Drive Status/Drive pin 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Multi Drive Status/Drive pin 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Multi Drive Status/Drive pin 21" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Multi Drive Status/Drive pin 20" "Low,High"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Multi Drive Status/Drive pin 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Multi Drive Status/Drive pin 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Multi Drive Status/Drive pin 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Multi Drive Status/Drive pin 16" "Low,High"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Multi Drive Status/Drive pin 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Multi Drive Status/Drive pin 14" "Low,High"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Multi Drive Status/Drive pin 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Multi Drive Status/Drive pin 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Multi Drive Status/Drive pin 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Multi Drive Status/Drive pin 10" "Low,High"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Multi Drive Status/Drive pin 9" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Multi Drive Status/Drive pin 8" "Low,High"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Multi Drive Status/Drive pin 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Multi Drive Status/Drive pin 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Multi Drive Status/Drive pin 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Multi Drive Status/Drive pin 4" "Low,High"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Multi Drive Status/Drive pin 3" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Multi Drive Status/Drive pin 2" "Low,High"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Multi Drive Status/Drive pin 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Multi Drive Status/Drive pin 0" "Low,High"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PIO_PUSR,PIO Pull Up Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Pull Up Status pin 31" "Enabled,Disabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Pull Up Status pin 30" "Enabled,Disabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Pull Up Status pin 29" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Pull Up Status pin 28" "Enabled,Disabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Pull Up Status pin 27" "Enabled,Disabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Pull Up Status pin 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Pull Up Status pin 25" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Pull Up Status pin 24" "Enabled,Disabled"
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_set/clr ,Pull Up Status pin 23" "Enabled,Disabled"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_set/clr ,Pull Up Status pin 22" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_set/clr ,Pull Up Status pin 21" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Pull Up Status pin 20" "Enabled,Disabled"
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_set/clr ,Pull Up Status pin 19" "Enabled,Disabled"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_set/clr ,Pull Up Status pin 18" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_set/clr ,Pull Up Status pin 17" "Enabled,Disabled"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_set/clr ,Pull Up Status pin 16" "Enabled,Disabled"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Pull Up Status pin 15" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Pull Up Status pin 14" "Enabled,Disabled"
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Pull Up Status pin 13" "Enabled,Disabled"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Pull Up Status pin 12" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Pull Up Status pin 11" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Pull Up Status pin 10" "Enabled,Disabled"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Pull Up Status pin 9" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Pull Up Status pin 8" "Enabled,Disabled"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Pull Up Status pin 7" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Pull Up Status pin 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Pull Up Status pin 5" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Pull Up Status pin 4" "Enabled,Disabled"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Pull Up Status pin 3" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Pull Up Status pin 2" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr ,Pull Up Status pin 1" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Pull Up Status pin 0" "Enabled,Disabled"
|
|
textline ""
|
|
rgroup.long 0x70++0x07
|
|
line.long 0x00 "PIO_ABCDSR1,Peripheral Select Register 1"
|
|
sif cpu()=="ATSAMG55"
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Select pin 31 - A/C B/D" "PCK2/C,SPI7_NPCS1/RTS7/D"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Select pin 30 - A/C B/D" "PCK1/C,SPI7_NPCS0/CTS7/D"
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Select pin 29 - A/C B/D" "SPI1_NPCS1/RTS1/C,SCK7/SPI7_SPCK/D"
|
|
textline " "
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Select pin 28 - A/C B/D" "SPI1_NPCS0/CTS1/C,TXD7/SPI7_MOSI/TWD7/D"
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Select pin 27 - A/C B/D" "SCK1/SPI1_SPCK/C,RXD7/SPI7_MISO/TWCK7/D"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Select pin 26 - A/C B/D" "SPI0_NPCS1/RTS0/C,I2SMCK1/D"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Select pin 25 - A/C B/D" "SPI0_NPCS0/CTS0/C,I2SDO1/D"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Select pin 24 - A/C B/D" "I2SMCK1/C,SCK2/SPI2_SPCK/D"
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Select pin 23 - A/C B/D" "I2SDO1/C,TIOA1/D"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Select pin 22 - A/C B/D" "TIOB2/C,I2SDI1/D"
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Select pin 21 - A/C B/D" "TIOA2/C,PCK1/D"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Select pin 20 - A/C B/D" "TCLK2/C,I2SWS1/D"
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Select pin 19 - A/C B/D" "TCLK1/C,I2SCK1/D"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Select pin 18 - A/C B/D" "I2SMCK0/C,PCK2/D"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Select pin 17 - A/C B/D" "I2SDO0/C,PCK1/D"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Select pin 16 - A/C B/D" "SPI2_NPCS0/CTS2/C,TIOB1/D"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select pin 15 - A/C B/D" "SPI2_NPCS1/RTS2/C,SCK2/SPI2_SPCK/D"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select pin 14 - A/C B/D" "SCK5/SPI5_SPCK/C,B/D"
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select pin 13 - A/C B/D" "TXD5/SPI5_MOSI/TWD5/C,B/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select pin 12 - A/C B/D" "RXD5/SPI5_MISO/TWCK5/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select pin 11 - A/C B/D" "SPI5_NPCS0/CTS5/C,B/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select pin 10 - A/C B/D" "TXD0/SPI0_MOSI/TWD0/C,PDMIC_CLK/D"
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select pin 9 - A/C B/D" "RXD0/SPI0_MISO/TWCK0/C,PDMIC_DAT/D"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select pin 8 - A/C B/D" "A/C,ADTRG/D"
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select pin 7 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select pin 6 - A/C B/D" "TXD2/SPI2_MOSI/TWD2/C,PCK0/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select pin 5 - A/C B/D" "RXD2/SPI2_MISO/TWCK2/C,SPI5_NPCS1/RTS5/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select pin 4 - A/C B/D" "RXD3/SPI3_MISO/TWCK3/C,I2SMCK0/D"
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select pin 3 - A/C B/D" "TXD3/SPI3_MOSI/TWD3/C,I2SDO0/D"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select pin 2 - A/C B/D" "TCLK0/C,I2SDI0/D"
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select pin 1 - A/C B/D" "I2SWS0/C,TIOB0/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select pin 0 - A/C B/D" "I2SCK0/C,TIOA0/D"
|
|
elif cpuis("ATSAMG54")||cpuis("ATSAMG53")
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Select pin 24 - A/C B/D" "I2SMCK1/C,B/D"
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Select pin 23 - A/C B/D" "I2SDO1/C,TIOA1/D"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Select pin 22 - A/C B/D" "TIOB2/C,I2SDI1/D"
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Select pin 21 - A/C B/D" "TIOA2/C,PCK1/D"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Select pin 20 - A/C B/D" "TCLK2/C,I2SWS1/D"
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Select pin 19 - A/C B/D" "TCLK1/C,I2SCK1/D"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Select pin 18 - A/C B/D" "I2SMCK0/C,PCK2/D"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Select pin 17 - A/C B/D" "I2SDO0/C,PCK1/D"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Select pin 16 - A/C B/D" "CTS/C,TIOB1/D"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select pin 15 - A/C B/D" "RTS/C,SCK/D"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select pin 14 - A/C B/D" "SPCK/C,B/D"
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select pin 13 - A/C B/D" "MOSI/C,B/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select pin 12 - A/C B/D" "MISO/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select pin 11 - A/C B/D" "NPCS0/C,B/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select pin 10 - A/C B/D" "UTXD0/C,PDMCLK0/D"
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select pin 9 - A/C B/D" "URXD0/C,PDMDAT0/D"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select pin 8 - A/C B/D" "A/C,ADTRG/D"
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select pin 7 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select pin 6 - A/C B/D" "TXD/C,PCK0/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select pin 5 - A/C B/D" "RXD/C,NPCS1/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select pin 4 - A/C B/D" "TWCK0/C,I2SMCK0/D"
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select pin 3 - A/C B/D" "TWD0/C,I2SDO0/D"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select pin 2 - A/C B/D" "TCLK0/C,I2SDI0/D"
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select pin 1 - A/C B/D" "I2SWS0/C,TIOB0/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select pin 0 - A/C B/D" "I2SCK0/C,TIOA0/D"
|
|
else
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Select pin 24 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Select pin 23 - A/C B/D" "A/C,TIOA1/D"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Select pin 22 - A/C B/D" "TIOB2/C,B/D"
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Select pin 21 - A/C B/D" "TIOA2/C,PCK1/D"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Select pin 20 - A/C B/D" "TCLK2/C,B/D"
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Select pin 19 - A/C B/D" "TCLK1/C,B/D"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Select pin 18 - A/C B/D" "A/C,PCK2/D"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Select pin 17 - A/C B/D" "A/C,PCK1/D"
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Select pin 16 - A/C B/D" "CTS/C,TIOB1/D"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select pin 15 - A/C B/D" "RTS/C,SCK/D"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select pin 14 - A/C B/D" "SPCK/C,B/D"
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select pin 13 - A/C B/D" "MOSI/C,B/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select pin 12 - A/C B/D" "MISO/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select pin 11 - A/C B/D" "NPCS0/C,B/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select pin 10 - A/C B/D" "UTXD0/C,B/D"
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select pin 9 - A/C B/D" "URXD0/C,NPCS1/D"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select pin 8 - A/C B/D" "A/C,ADTRG/D"
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select pin 7 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select pin 6 - A/C B/D" "TXD/C,PCK0/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select pin 5 - A/C B/D" "RXD/C,B/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select pin 4 - A/C B/D" "TWCK0/C,B/D"
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select pin 3 - A/C B/D" "TWD0/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select pin 2 - A/C B/D" "TCLK0/C,B/D"
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select pin 1 - A/C B/D" "A/C,TIOB0/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select pin 0 - A/C B/D" "A/C,TIOA0/D"
|
|
endif
|
|
line.long 0x04 "PIO_ABCDSR2,Peripheral Select Register 2"
|
|
sif cpu()=="ATSAMG55"
|
|
bitfld.long 0x04 31. " P31 ,Peripheral Select pin 31 - A/C B/D" "PCK2/SPI7_NPCS1/RTS7,C/D"
|
|
bitfld.long 0x04 30. " P30 ,Peripheral Select pin 30 - A/C B/D" "PCK1/SPI7_NPCS0/CTS7,C/D"
|
|
bitfld.long 0x04 29. " P29 ,Peripheral Select pin 29 - A/C B/D" "SPI1_NPCS1/RTS1/SCK7/SPI7_SPCK,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 28. " P28 ,Peripheral Select pin 28 - A/C B/D" "SPI1_NPCS0/CTS1/TXD7/SPI7_MOSI/TWD7,C/D"
|
|
bitfld.long 0x04 27. " P27 ,Peripheral Select pin 27 - A/C B/D" "SCK1/SPI1_SPCK/RXD7/SPI7_MISO/TWCK7,C/D"
|
|
bitfld.long 0x04 26. " P26 ,Peripheral Select pin 26 - A/C B/D" "SPI0_NPCS1/RTS0/I2SMCK1,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 25. " P25 ,Peripheral Select pin 25 - A/C B/D" "SPI0_NPCS0/CTS0/I2SDO1,C/D"
|
|
bitfld.long 0x04 24. " P24 ,Peripheral Select pin 24 - A/C B/D" "I2SMCK1/SCK2/SPI2_SPCK,C/D"
|
|
bitfld.long 0x04 23. " P23 ,Peripheral Select pin 23 - A/C B/D" "I2SDO1/TIOA1,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 22. " P22 ,Peripheral Select pin 22 - A/C B/D" "TIOB2/I2SDI1,C/D"
|
|
bitfld.long 0x04 21. " P21 ,Peripheral Select pin 21 - A/C B/D" "TIOA2/PCK1,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 20. " P20 ,Peripheral Select pin 20 - A/C B/D" "TCLK2/I2SWS1,C/D"
|
|
bitfld.long 0x04 19. " P19 ,Peripheral Select pin 19 - A/C B/D" "TCLK1/I2SCK1,C/D"
|
|
bitfld.long 0x04 18. " P18 ,Peripheral Select pin 18 - A/C B/D" "I2SMCK0/PCK2,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 17. " P17 ,Peripheral Select pin 17 - A/C B/D" "I2SDO0/PCK1,C/D"
|
|
bitfld.long 0x04 16. " P16 ,Peripheral Select pin 16 - A/C B/D" "SPI2_NPCS0/CTS2/TIOB1,C/D"
|
|
bitfld.long 0x04 15. " P15 ,Peripheral Select pin 15 - A/C B/D" "SPI2_NPCS1/RTS2/SCK2/SPI2_SPCK,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 14. " P14 ,Peripheral Select pin 14 - A/C B/D" "SCK5/SPI5_SPCK/B,C/D"
|
|
bitfld.long 0x04 13. " P13 ,Peripheral Select pin 13 - A/C B/D" "TXD5/SPI5_MOSI/TWD5/B,C/D"
|
|
bitfld.long 0x04 12. " P12 ,Peripheral Select pin 12 - A/C B/D" "RXD5/SPI5_MISO/TWCK5/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 11. " P11 ,Peripheral Select pin 11 - A/C B/D" "SPI5_NPCS0/CTS5/B,C/D"
|
|
bitfld.long 0x04 10. " P10 ,Peripheral Select pin 10 - A/C B/D" "TXD0/SPI0_MOSI/TWD0/PDMIC_CLK,C/D"
|
|
bitfld.long 0x04 9. " P9 ,Peripheral Select pin 9 - A/C B/D" "RXD0/SPI0_MISO/TWCK0/PDMIC_DAT,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 8. " P8 ,Peripheral Select pin 8 - A/C B/D" "A/ADTRG,C/D"
|
|
bitfld.long 0x04 7. " P7 ,Peripheral Select pin 7 - A/C B/D" "A/B,C/D"
|
|
bitfld.long 0x04 6. " P6 ,Peripheral Select pin 6 - A/C B/D" "TXD2/SPI2_MOSI/TWD2/PCK0,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 5. " P5 ,Peripheral Select pin 5 - A/C B/D" "RXD2/SPI2_MISO/TWCK2/SPI5_NPCS1/RTS5,C/D"
|
|
bitfld.long 0x04 4. " P4 ,Peripheral Select pin 4 - A/C B/D" "RXD3/SPI3_MISO/TWCK3/I2SMCK0,C/D"
|
|
bitfld.long 0x04 3. " P3 ,Peripheral Select pin 3 - A/C B/D" "TXD3/SPI3_MOSI/TWD3/I2SDO0,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 2. " P2 ,Peripheral Select pin 2 - A/C B/D" "TCLK0/I2SDI0,C/D"
|
|
bitfld.long 0x04 1. " P1 ,Peripheral Select pin 1 - A/C B/D" "I2SWS0/TIOB0,C/D"
|
|
bitfld.long 0x04 0. " P0 ,Peripheral Select pin 0 - A/C B/D" "I2SCK0/TIOA0,C/D"
|
|
elif cpuis("ATSAMG54")||cpuis("ATSAMG53")
|
|
bitfld.long 0x04 24. " P24 ,Peripheral Select pin 24 - A/C B/D" "I2SMCK1/B,C/D"
|
|
bitfld.long 0x04 23. " P23 ,Peripheral Select pin 23 - A/B C/D" "I2SDO1/C,TIOA1/D"
|
|
textline " "
|
|
bitfld.long 0x04 22. " P22 ,Peripheral Select pin 22 - A/C B/D" "TIOB2/I2SDI1,C/D"
|
|
bitfld.long 0x04 21. " P21 ,Peripheral Select pin 21 - A/C B/D" "TIOA2/PCK1,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 20. " P20 ,Peripheral Select pin 20 - A/C B/D" "TCLK2/I2SWS1,C/D"
|
|
bitfld.long 0x04 19. " P19 ,Peripheral Select pin 19 - A/C B/D" "TCLK1/I2SCK1,C/D"
|
|
bitfld.long 0x04 18. " P18 ,Peripheral Select pin 18 - A/C B/D" "I2SMCK0/PCK2,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 17. " P17 ,Peripheral Select pin 17 - A/C B/D" "I2SDO0/PCK1,C/D"
|
|
bitfld.long 0x04 16. " P16 ,Peripheral Select pin 16 - A/C B/D" "CTS/TIOB1,C/D"
|
|
bitfld.long 0x04 15. " P15 ,Peripheral Select pin 15 - A/C B/D" "RTS/SCK,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 14. " P14 ,Peripheral Select pin 14 - A/C B/D" "SPCK/B,C/D"
|
|
bitfld.long 0x04 13. " P13 ,Peripheral Select pin 13 - A/C B/D" "MOSI/B,C/D"
|
|
bitfld.long 0x04 12. " P12 ,Peripheral Select pin 12 - A/C B/D" "MISO/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 11. " P11 ,Peripheral Select pin 11 - A/C B/D" "NPCS0/B,C/D"
|
|
bitfld.long 0x04 10. " P10 ,Peripheral Select pin 10 - A/C B/D" "UTXD0/PDMCLK0,C/D"
|
|
bitfld.long 0x04 9. " P9 ,Peripheral Select pin 9 - A/C B/D" "URXD0/PDMDAT0,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 8. " P8 ,Peripheral Select pin 8 - A/C B/D" "A/ADTRG,C/D"
|
|
bitfld.long 0x04 7. " P7 ,Peripheral Select pin 7 - A/C B/D" "A/B,C/D"
|
|
bitfld.long 0x04 6. " P6 ,Peripheral Select pin 6 - A/C B/D" "TXD/PCK0,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 5. " P5 ,Peripheral Select pin 5 - A/C B/D" "RXD/NPCS1,C/D"
|
|
bitfld.long 0x04 4. " P4 ,Peripheral Select pin 4 - A/C B/D" "TWCK0/I2SMCK0,C/D"
|
|
bitfld.long 0x04 3. " P3 ,Peripheral Select pin 3 - A/C B/D" "TWD0/I2SDO0,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 2. " P2 ,Peripheral Select pin 2 - A/C B/D" "TCLK0/I2SDI0,C/D"
|
|
bitfld.long 0x04 1. " P1 ,Peripheral Select pin 1 - A/C B/D" "I2SWS0/TIOB0,C/D"
|
|
bitfld.long 0x04 0. " P0 ,Peripheral Select pin 0 - A/C B/D" "I2SCK0/TIOA0,C/D"
|
|
else
|
|
bitfld.long 0x04 23. " P23 ,Peripheral Select pin 23 - A/B C/D" "A/TIOA1,C/D"
|
|
bitfld.long 0x04 22. " P22 ,Peripheral Select pin 22 - A/B C/D" "TIOB2/B,C/D"
|
|
bitfld.long 0x04 21. " P21 ,Peripheral Select pin 21 - A/B C/D" "TIOA2/PCK1,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 20. " P20 ,Peripheral Select pin 20 - A/B C/D" "TCLK2/B,C/D"
|
|
bitfld.long 0x04 19. " P19 ,Peripheral Select pin 19 - A/B C/D" "TCLK1/B,C/D"
|
|
bitfld.long 0x04 18. " P18 ,Peripheral Select pin 18 - A/B C/D" "A/PCK2,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 17. " P17 ,Peripheral Select pin 17 - A/B C/D" "A/PCK1,C/D"
|
|
bitfld.long 0x04 16. " P16 ,Peripheral Select pin 16 - A/B C/D" "CTS/TIOB1,C/D"
|
|
bitfld.long 0x04 15. " P15 ,Peripheral Select pin 15 - A/B C/D" "RTS/SCK,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 14. " P14 ,Peripheral Select pin 14 - A/B C/D" "SPCK/B,C/D"
|
|
bitfld.long 0x04 13. " P13 ,Peripheral Select pin 13 - A/B C/D" "MOSI/B,C/D"
|
|
bitfld.long 0x04 12. " P12 ,Peripheral Select pin 12 - A/B C/D" "MISO/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 11. " P11 ,Peripheral Select pin 11 - A/B C/D" "NPCS0/B,C/D"
|
|
bitfld.long 0x04 10. " P10 ,Peripheral Select pin 10 - A/B C/D" "UTXD0/B,C/D"
|
|
bitfld.long 0x04 9. " P9 ,Peripheral Select pin 9 - A/B C/D" "URXD0/NPCS1,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 8. " P8 ,Peripheral Select pin 8 - A/B C/D" "A/ADTRG,C/D"
|
|
bitfld.long 0x04 7. " P7 ,Peripheral Select pin 7 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 6. " P6 ,Peripheral Select pin 6 - A/B C/D" "TXD/PCK0,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 5. " P5 ,Peripheral Select pin 5 - A/B C/D" "RXD/B,C/D"
|
|
bitfld.long 0x04 4. " P4 ,Peripheral Select pin 4 - A/B C/D" "TWCK0/B,C/D"
|
|
bitfld.long 0x04 3. " P3 ,Peripheral Select pin 3 - A/B C/D" "TWD0/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 2. " P2 ,Peripheral Select pin 2 - A/B C/D" "TCLK0/B,C/D"
|
|
bitfld.long 0x04 1. " P1 ,Peripheral Select pin 1 - A/B C/D" "A/TIOB0,C/D"
|
|
bitfld.long 0x04 0. " P0 ,Peripheral Select pin 0 - A/B C/D" "A/TIOA0,C/D"
|
|
endif
|
|
textline ""
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PIO_IFSCSR,PIO Input Filter Slow Clock Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Glitch or Debouncing Filter Selection Status pin 31" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Glitch or Debouncing Filter Selection Status pin 30" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Glitch or Debouncing Filter Selection Status pin 29" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Glitch or Debouncing Filter Selection Status pin 28" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Glitch or Debouncing Filter Selection Status pin 27" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Glitch or Debouncing Filter Selection Status pin 26" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Glitch or Debouncing Filter Selection Status pin 25" "Glitch,Debouncing"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Glitch or Debouncing Filter Selection Status pin 24" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_set/clr ,Glitch or Debouncing Filter Selection Status pin 23" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_set/clr ,Glitch or Debouncing Filter Selection Status pin 22" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_set/clr ,Glitch or Debouncing Filter Selection Status pin 21" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Glitch or Debouncing Filter Selection Status pin 20" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_set/clr ,Glitch or Debouncing Filter Selection Status pin 19" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_set/clr ,Glitch or Debouncing Filter Selection Status pin 18" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_set/clr ,Glitch or Debouncing Filter Selection Status pin 17" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_set/clr ,Glitch or Debouncing Filter Selection Status pin 16" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Glitch or Debouncing Filter Selection Status pin 15" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status pin 14" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status pin 13" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status pin 12" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status pin 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status pin 10" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status pin 9" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status pin 8" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status pin 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status pin 6" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status pin 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status pin 4" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status pin 3" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status pin 2" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr ,Glitch or Debouncing Filter Selection Status pin 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status pin 0" "Glitch,Debouncing"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PIO_SCDR,PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow Clock Divider Selection for Debouncing"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PIO_PPDSR,PIO Pad Pull Down Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Pull Down Status pin 31" "Enabled,Disabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Pull Down Status pin 30" "Enabled,Disabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Pull Down Status pin 29" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Pull Down Status pin 28" "Enabled,Disabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Pull Down Status pin 27" "Enabled,Disabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Pull Down Status pin 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Pull Down Status pin 25" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Pull Down Status pin 24" "Enabled,Disabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Pull Down Status pin 23" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Pull Down Status pin 22" "Enabled,Disabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Pull Down Status pin 21" "Enabled,Disabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Pull Down Status pin 20" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Pull Down Status pin 19" "Enabled,Disabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Pull Down Status pin 18" "Enabled,Disabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Pull Down Status pin 17" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Pull Down Status pin 16" "Enabled,Disabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Pull Down Status pin 15" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Pull Down Status pin 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Pull Down Status pin 13" "Enabled,Disabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Pull Down Status pin 12" "Enabled,Disabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Pull Down Status pin 11" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Pull Down Status pin 10" "Enabled,Disabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Pull Down Status pin 9" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Pull Down Status pin 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Pull Down Status pin 7" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Pull Down Status pin 6" "Enabled,Disabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Pull Down Status pin 5" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Pull Down Status pin 4" "Enabled,Disabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Pull Down Status pin 3" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Pull Down Status pin 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Pull Down Status pin 1" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Pull Down Status pin 0" "Enabled,Disabled"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PIO_OWSR,PIO Output Write Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Write Status pin 31" "Enabled,Disabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Write Status pin 30" "Enabled,Disabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Write Status pin 29" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Write Status pin 28" "Enabled,Disabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Write Status pin 27" "Enabled,Disabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Write Status pin 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Write Status pin 25" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Write Status pin 24" "Enabled,Disabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Write Status pin 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Write Status pin 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Write Status pin 21" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Write Status pin 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Write Status pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Write Status pin 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Write Status pin 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Write Status pin 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Write Status pin 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Write Status pin 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Write Status pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Write Status pin 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Write Status pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Write Status pin 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Write Status pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Write Status pin 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Write Status pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Write Status pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Write Status pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Write Status pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Write Status pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Write Status pin 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Write Status pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Write Status pin 0" "Disabled,Enabled"
|
|
width 0x0b
|
|
endif
|
|
width 13.
|
|
textline ""
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "PIO_AIMMR,PIO Additional Interrupt Modes Mask Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Peripheral CD Status pin 31" "Masked,Not masked"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Peripheral CD Status pin 30" "Masked,Not masked"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Peripheral CD Status pin 29" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Peripheral CD Status pin 28" "Masked,Not masked"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Peripheral CD Status pin 27" "Masked,Not masked"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Peripheral CD Status pin 26" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Peripheral CD Status pin 25" "Masked,Not masked"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Peripheral CD Status pin 24" "Masked,Not masked"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Peripheral CD Status pin 23" "Masked,Not masked"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Peripheral CD Status pin 22" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Peripheral CD Status pin 21" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Peripheral CD Status pin 20" "Masked,Not masked"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Peripheral CD Status pin 19" "Masked,Not masked"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Peripheral CD Status pin 18" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Peripheral CD Status pin 17" "Masked,Not masked"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Peripheral CD Status pin 16" "Masked,Not masked"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Peripheral CD Status pin 15" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Peripheral CD Status pin 14" "Masked,Not masked"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Peripheral CD Status pin 13" "Masked,Not masked"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Peripheral CD Status pin 12" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Peripheral CD Status pin 11" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Peripheral CD Status pin 10" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Peripheral CD Status pin 9" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Peripheral CD Status pin 8" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Peripheral CD Status pin 7" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Peripheral CD Status pin 6" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Peripheral CD Status pin 5" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Peripheral CD Status pin 4" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Peripheral CD Status pin 3" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Peripheral CD Status pin 2" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Peripheral CD Status pin 1" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Peripheral CD Status pin 0" "Masked,Not masked"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "PIO_ELSR,PIO Edge/Level Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Edge/Level Interrupt source selection pin 31" "Edge,Level"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Edge/Level Interrupt source selection pin 30" "Edge,Level"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Edge/Level Interrupt source selection pin 29" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Edge/Level Interrupt source selection pin 28" "Edge,Level"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Edge/Level Interrupt source selection pin 27" "Edge,Level"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Edge/Level Interrupt source selection pin 26" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Edge/Level Interrupt source selection pin 25" "Edge,Level"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Edge/Level Interrupt source selection pin 24" "Edge,Level"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Edge/Level Interrupt source selection pin 23" "Edge,Level"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Edge/Level Interrupt source selection pin 22" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Edge/Level Interrupt source selection pin 21" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Edge/Level Interrupt source selection pin 20" "Edge,Level"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Edge/Level Interrupt source selection pin 19" "Edge,Level"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Edge/Level Interrupt source selection pin 18" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Edge/Level Interrupt source selection pin 17" "Edge,Level"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Edge/Level Interrupt source selection pin 16" "Edge,Level"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Edge/Level Interrupt source selection pin 15" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection pin 14" "Edge,Level"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection pin 13" "Edge,Level"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection pin 12" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection pin 11" "Edge,Level"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection pin 10" "Edge,Level"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection pin 9" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection pin 8" "Edge,Level"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection pin 7" "Edge,Level"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection pin 6" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection pin 5" "Edge,Level"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection pin 4" "Edge,Level"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection pin 3" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection pin 2" "Edge,Level"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Edge/Level Interrupt source selection pin 1" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection pin 0" "Edge,Level"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "PIO_FRLHSR,PIO Fall/Rise - Low/High Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Edge /Level Interrupt Source Selection pin 31" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Edge /Level Interrupt Source Selection pin 30" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Edge /Level Interrupt Source Selection pin 29" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Edge /Level Interrupt Source Selection pin 28" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Edge /Level Interrupt Source Selection pin 27" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Edge /Level Interrupt Source Selection pin 26" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Edge /Level Interrupt Source Selection pin 25" "Falling/Low,Rising/High"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Edge /Level Interrupt Source Selection pin 24" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_set/clr ,Edge /Level Interrupt Source Selection pin 23" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_set/clr ,Edge /Level Interrupt Source Selection pin 22" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_set/clr ,Edge /Level Interrupt Source Selection pin 21" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Edge /Level Interrupt Source Selection pin 20" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_set/clr ,Edge /Level Interrupt Source Selection pin 19" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_set/clr ,Edge /Level Interrupt Source Selection pin 18" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_set/clr ,Edge /Level Interrupt Source Selection pin 17" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_set/clr ,Edge /Level Interrupt Source Selection pin 16" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Edge /Level Interrupt Source Selection pin 15" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Edge /Level Interrupt Source Selection pin 14" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Edge /Level Interrupt Source Selection pin 13" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Edge /Level Interrupt Source Selection pin 12" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Edge /Level Interrupt Source Selection pin 11" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Edge /Level Interrupt Source Selection pin 10" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Edge /Level Interrupt Source Selection pin 9" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Edge /Level Interrupt Source Selection pin 8" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Edge /Level Interrupt Source Selection pin 7" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Edge /Level Interrupt Source Selection pin 6" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Edge /Level Interrupt Source Selection pin 5" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Edge /Level Interrupt Source Selection pin 4" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Edge /Level Interrupt Source Selection pin 3" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Edge /Level Interrupt Source Selection pin 2" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr ,Edge /Level Interrupt Source Selection pin 1" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Edge /Level Interrupt Source Selection pin 0" "Falling/Low,Rising/High"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in.
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PIO_SCHMITT,PIO Schmitt Trigger Register"
|
|
sif cpu()=="ATSAMG55"
|
|
bitfld.long 0x00 31. " SCHMITT31 ,Schmitt Trigger 31 Disabled" "No,Yes"
|
|
bitfld.long 0x00 30. " SCHMITT30 ,Schmitt Trigger 30 Disabled" "No,Yes"
|
|
bitfld.long 0x00 29. " SCHMITT29 ,Schmitt Trigger 29 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SCHMITT28 ,Schmitt Trigger 28 Disabled" "No,Yes"
|
|
bitfld.long 0x00 27. " SCHMITT27 ,Schmitt Trigger 27 Disabled" "No,Yes"
|
|
bitfld.long 0x00 26. " SCHMITT26 ,Schmitt Trigger 26 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SCHMITT25 ,Schmitt Trigger 25 Disabled" "No,Yes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 24. " SCHMITT24 ,Schmitt Trigger 24 Disabled" "No,Yes"
|
|
bitfld.long 0x00 23. " SCHMITT23 ,Schmitt Trigger 23 Disabled" "No,Yes"
|
|
bitfld.long 0x00 22. " SCHMITT22 ,Schmitt Trigger 22 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SCHMITT21 ,Schmitt Trigger 21 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCHMITT20 ,Schmitt Trigger 20 Disabled" "No,Yes"
|
|
bitfld.long 0x00 19. " SCHMITT19 ,Schmitt Trigger 19 Disabled" "No,Yes"
|
|
bitfld.long 0x00 18. " SCHMITT18 ,Schmitt Trigger 18 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SCHMITT17 ,Schmitt Trigger 17 Disabled" "No,Yes"
|
|
bitfld.long 0x00 16. " SCHMITT16 ,Schmitt Trigger 16 Disabled" "No,Yes"
|
|
bitfld.long 0x00 15. " SCHMITT15 ,Schmitt Trigger 15 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SCHMITT14 ,Schmitt Trigger 14 Disabled" "No,Yes"
|
|
bitfld.long 0x00 13. " SCHMITT13 ,Schmitt Trigger 13 Disabled" "No,Yes"
|
|
bitfld.long 0x00 12. " SCHMITT12 ,Schmitt Trigger 12 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SCHMITT11 ,Schmitt Trigger 11 Disabled" "No,Yes"
|
|
bitfld.long 0x00 10. " SCHMITT10 ,Schmitt Trigger 10 Disabled" "No,Yes"
|
|
bitfld.long 0x00 9. " SCHMITT9 ,Schmitt Trigger 9 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SCHMITT8 ,Schmitt Trigger 8 Disabled" "No,Yes"
|
|
bitfld.long 0x00 7. " SCHMITT7 ,Schmitt Trigger 7 Disabled" "No,Yes"
|
|
bitfld.long 0x00 6. " SCHMITT6 ,Schmitt Trigger 6 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCHMITT5 ,Schmitt Trigger 5 Disabled" "No,Yes"
|
|
bitfld.long 0x00 4. " SCHMITT4 ,Schmitt Trigger 4 Disabled" "No,Yes"
|
|
bitfld.long 0x00 3. " SCHMITT3 ,Schmitt Trigger 3 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SCHMITT2 ,Schmitt Trigger 2 Disabled" "No,Yes"
|
|
bitfld.long 0x00 1. " SCHMITT1 ,Schmitt Trigger 1 Disabled" "No,Yes"
|
|
bitfld.long 0x00 0. " SCHMITT0 ,Schmitt Trigger 0 Disabled" "No,Yes"
|
|
sif (cpu()=="ATSAMG55")
|
|
group.long 0x110++0x03
|
|
line.long 0x00 " PIO_DRIVER ,PIO I/O Drive Register"
|
|
bitfld.long 0x00 31. " LINE31 ,Drive of PIO Line 31" "Low drive,High drive"
|
|
bitfld.long 0x00 30. " LINE30 ,Drive of PIO Line 30" "Low drive,High drive"
|
|
bitfld.long 0x00 29. " LINE29 ,Drive of PIO Line 29" "Low drive,High drive"
|
|
textline " "
|
|
bitfld.long 0x00 28. " LINE28 ,Drive of PIO Line 28" "Low drive,High drive"
|
|
bitfld.long 0x00 27. " LINE27 ,Drive of PIO Line 27" "Low drive,High drive"
|
|
bitfld.long 0x00 26. " LINE26 ,Drive of PIO Line 26" "Low drive,High drive"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LINE25 ,Drive of PIO Line 25" "Low drive,High drive"
|
|
bitfld.long 0x00 24. " LINE24 ,Drive of PIO Line 24" "Low drive,High drive"
|
|
bitfld.long 0x00 23. " LINE23 ,Drive of PIO Line 23" "Low drive,High drive"
|
|
textline " "
|
|
bitfld.long 0x00 22. " LINE22 ,Drive of PIO Line 22" "Low drive,High drive"
|
|
bitfld.long 0x00 21. " LINE21 ,Drive of PIO Line 21" "Low drive,High drive"
|
|
textline " "
|
|
bitfld.long 0x00 20. " LINE20 ,Drive of PIO Line 20" "Low drive,High drive"
|
|
bitfld.long 0x00 19. " LINE19 ,Drive of PIO Line 19" "Low drive,High drive"
|
|
bitfld.long 0x00 18. " LINE18 ,Drive of PIO Line 18" "Low drive,High drive"
|
|
textline " "
|
|
bitfld.long 0x00 17. " LINE17 ,Drive of PIO Line 17" "Low drive,High drive"
|
|
bitfld.long 0x00 16. " LINE16 ,Drive of PIO Line 16" "Low drive,High drive"
|
|
bitfld.long 0x00 15. " LINE15 ,Drive of PIO Line 15" "Low drive,High drive"
|
|
textline " "
|
|
bitfld.long 0x00 14. " LINE14 ,Drive of PIO Line 14" "Low drive,High drive"
|
|
bitfld.long 0x00 13. " LINE13 ,Drive of PIO Line 13" "Low drive,High drive"
|
|
bitfld.long 0x00 12. " LINE12 ,Drive of PIO Line 12" "Low drive,High drive"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LINE11 ,Drive of PIO Line 11" "Low drive,High drive"
|
|
bitfld.long 0x00 10. " LINE10 ,Drive of PIO Line 10" "Low drive,High drive"
|
|
bitfld.long 0x00 9. " LINE9 ,Drive of PIO Line 9" "Low drive,High drive"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LINE8 ,Drive of PIO Line 8" "Low drive,High drive"
|
|
bitfld.long 0x00 7. " LINE7 ,Drive of PIO Line 7" "Low drive,High drive"
|
|
bitfld.long 0x00 6. " LINE6 ,Drive of PIO Line 6" "Low drive,High drive"
|
|
textline " "
|
|
bitfld.long 0x00 5. " LINE5 ,Drive of PIO Line 5" "Low drive,High drive"
|
|
bitfld.long 0x00 4. " LINE4 ,Drive of PIO Line 4" "Low drive,High drive"
|
|
bitfld.long 0x00 3. " LINE3 ,Drive of PIO Line 3" "Low drive,High drive"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LINE2 ,Drive of PIO Line 2" "Low drive,High drive"
|
|
bitfld.long 0x00 1. " LINE1 ,Drive of PIO Line 1" "Low drive,High drive"
|
|
bitfld.long 0x00 0. " LINE0 ,Drive of PIO Line 0" "Low drive,High drive"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "PIOB"
|
|
base ad:0x400E1000
|
|
if ((d.l(ad:0x400E1000+0xE4)&0x01)==0x00)
|
|
width 13.
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PIO_PSR,PIO Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO Status 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO Status 13" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO Status 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO Status 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO Status 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO Status 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO Status 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO Status 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO Status 0" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PIO_OSR,PIO Output Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Status pin 15" "Input only,Input/Output"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Status pin 14" "Input only,Input/Output"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Status pin 13" "Input only,Input/Output"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Status pin 12" "Input only,Input/Output"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Status pin 11" "Input only,Input/Output"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Status pin 10" "Input only,Input/Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Status pin 9" "Input only,Input/Output"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Status pin 8" "Input only,Input/Output"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Status pin 7" "Input only,Input/Output"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Status pin 6" "Input only,Input/Output"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Status pin 5" "Input only,Input/Output"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Status pin 4" "Input only,Input/Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Status pin 3" "Input only,Input/Output"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Status pin 2" "Input only,Input/Output"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Status pin 1" "Input only,Input/Output"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Status pin 0" "Input only,Input/Output"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PIO_IFSR,PIO Input Filter Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Input Filer Status pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Filer Status pin 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Filer Status pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Filer Status pin 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Filer Status pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Filer Status pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Filer Status pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Filer Status pin 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Filer Status pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Filer Status pin 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Filer Status pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Filer Status pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Filer Status pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Filer Status pin 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Filer Status pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Filer Status pin 0" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PIO_ODSR,PIO Output Data Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Data Status pin 15" "0,1"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Data Status pin 14" "0,1"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Data Status pin 13" "0,1"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Data Status pin 12" "0,1"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Data Status pin 11" "0,1"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Data Status pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Data Status pin 9" "0,1"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Data Status pin 8" "0,1"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Data Status pin 7" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Data Status pin 6" "0,1"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Data Status pin 5" "0,1"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Data Status pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Data Status pin 3" "0,1"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Data Status pin 2" "0,1"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Data Status pin 1" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Data Status pin 0" "0,1"
|
|
textline " "
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "PIO_PDSR,PIO Pin Data Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
bitfld.long 0x00 15. " P15 ,Output Data Status pin 15" "Level 0,Level 1"
|
|
bitfld.long 0x00 14. " P14 ,Output Data Status pin 14" "Level 0,Level 1"
|
|
bitfld.long 0x00 13. " P13 ,Output Data Status pin 13" "Level 0,Level 1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12. " P12 ,Output Data Status pin 12" "Level 0,Level 1"
|
|
bitfld.long 0x00 11. " P11 ,Output Data Status pin 11" "Level 0,Level 1"
|
|
bitfld.long 0x00 10. " P10 ,Output Data Status pin 10" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Data Status pin 9" "Level 0,Level 1"
|
|
bitfld.long 0x00 8. " P8 ,Output Data Status pin 8" "Level 0,Level 1"
|
|
bitfld.long 0x00 7. " P7 ,Output Data Status pin 7" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Output Data Status pin 6" "Level 0,Level 1"
|
|
bitfld.long 0x00 5. " P5 ,Output Data Status pin 5" "Level 0,Level 1"
|
|
bitfld.long 0x00 4. " P4 ,Output Data Status pin 4" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Data Status pin 3" "Level 0,Level 1"
|
|
bitfld.long 0x00 2. " P2 ,Output Data Status pin 2" "Level 0,Level 1"
|
|
bitfld.long 0x00 1. " P1 ,Output Data Status pin 1" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Output Data Status pin 0" "Level 0,Level 1"
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "PIO_ISR,PIO Interrupt Status Register"
|
|
in
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PIO_ISR,PIO Interrupt Mask Register"
|
|
sif cpu()=="ATSAMG55"
|
|
bitfld.long 0x00 15. " P15 ,Input Change Interrupt Mask pin 15" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " P14 ,Input Change Interrupt Mask pin 14" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " P13 ,Input Change Interrupt Mask pin 13" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12. " P12 ,Input Change Interrupt Mask pin 12" "Masked,Not masked"
|
|
bitfld.long 0x00 11. " P11 ,Input Change Interrupt Mask pin 11" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " P10 ,Input Change Interrupt Mask pin 10" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Input Change Interrupt Mask pin 9" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " P8 ,Input Change Interrupt Mask pin 8" "Masked,Not masked"
|
|
bitfld.long 0x00 7. " P7 ,Input Change Interrupt Mask pin 7" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Input Change Interrupt Mask pin 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " P5 ,Input Change Interrupt Mask pin 5" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " P4 ,Input Change Interrupt Mask pin 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Input Change Interrupt Mask pin 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " P2 ,Input Change Interrupt Mask pin 2" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " P1 ,Input Change Interrupt Mask pin 1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Input Change Interrupt Mask pin 0" "Masked,Not masked"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PIO_MDSR,PIO Multi-driver Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Multi Drive Status/Drive pin 15" "Low,High"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Multi Drive Status/Drive pin 14" "Low,High"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Multi Drive Status/Drive pin 13" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Multi Drive Status/Drive pin 12" "Low,High"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Multi Drive Status/Drive pin 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Multi Drive Status/Drive pin 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Multi Drive Status/Drive pin 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Multi Drive Status/Drive pin 8" "Low,High"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Multi Drive Status/Drive pin 7" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Multi Drive Status/Drive pin 6" "Low,High"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Multi Drive Status/Drive pin 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Multi Drive Status/Drive pin 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Multi Drive Status/Drive pin 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Multi Drive Status/Drive pin 2" "Low,High"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Multi Drive Status/Drive pin 1" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Multi Drive Status/Drive pin 0" "Low,High"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PIO_PUSR,PIO Pull Up Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Pull Up Status pin 15" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Pull Up Status pin 14" "Enabled,Disabled"
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Pull Up Status pin 13" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Pull Up Status pin 12" "Enabled,Disabled"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Pull Up Status pin 11" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Pull Up Status pin 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Pull Up Status pin 9" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Pull Up Status pin 8" "Enabled,Disabled"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Pull Up Status pin 7" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Pull Up Status pin 6" "Enabled,Disabled"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Pull Up Status pin 5" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Pull Up Status pin 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Pull Up Status pin 3" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Pull Up Status pin 2" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr ,Pull Up Status pin 1" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Pull Up Status pin 0" "Enabled,Disabled"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "PIO_ABCDSR1,Peripheral Select Register 1"
|
|
sif cpu()=="ATSAMG55"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select pin 15 - A/C B/D" "SPI3_NPCS1/RTS3/C,SPI6_NPCS1/RTS6/D"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select pin 14 - A/C B/D" "SPI3_NPCS0/CTS3/C,SPI6_NPCS0/CTS6/D"
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select pin 13 - A/C B/D" "SCK3/SPI3_SPCK/C,SCK6/SPI6_SPCK/D"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select pin 12 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select pin 11 - A/C B/D" "RXD4/SPI4_MISO/TWCK4/C,RXD6/SPI6_MISO/TWCK6/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select pin 10 - A/C B/D" "TXD4/SPI4_MOSI/TWD4/C,TXD6/SPI6_MOSI/TWD6/D"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select pin 9 - A/C B/D" "RXD4/SPI4_MISO/TWCK4/C,SPI4_NPCS1/RTS4/D"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select pin 8 - A/C B/D" "TXD4/SPI4_MOSI/TWD4/C,SPI4_NPCS0/CTS4/D"
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select pin 7 - A/C B/D" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select pin 6 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select pin 5 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select pin 4 - A/C B/D" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select pin 3 - A/C B/D" "TXD1/SPI1_MOSI/TWD1/C,PCK2/D"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select pin 2 - A/C B/D" "RXD1/SPI1_MISO/TWCK1/C,RXD6/SPI6_MISO/TWCK6/D"
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select pin 1 - A/C B/D" "SCK4/SPI4_SPCK/C,TWCK2/D"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select pin 0 - A/C B/D" "SCK0/SPI0_SPCK/C,TXD6/SPI6_MOSI/TWD6/D"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select pin 12 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select pin 11 - A/C B/D" "TWCK1/C,TWCK2/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select pin 10 - A/C B/D" "TWD1/C,TWD2/D"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select pin 9 - A/C B/D" "TWCK1/C,B/D"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select pin 8 - A/C B/D" "TWD1/C,B/D"
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select pin 7 - A/C B/D" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select pin 6 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select pin 5 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select pin 4 - A/C B/D" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select pin 3 - A/C B/D" "UTXD1/C,PCK2/D"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select pin 2 - A/C B/D" "URXD1/C,NPCS1/D"
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select pin 1 - A/C B/D" "A/C,TWCK2/D"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select pin 0 - A/C B/D" "A/C,TWD2/D"
|
|
endif
|
|
line.long 0x04 "PIO_ABCDSR2,Peripheral Select Register 2"
|
|
sif cpu()=="ATSAMG55"
|
|
bitfld.long 0x04 15. " P15 ,Peripheral Select pin 15 - A/B C/D" "SPI3_NPCS1/RTS3/SPI6_NPCS1/RTS6,C/D"
|
|
bitfld.long 0x04 14. " P14 ,Peripheral Select pin 14 - A/B C/D" "SPI3_NPCS0/CTS3/SPI6_NPCS0/CTS6,C/D"
|
|
bitfld.long 0x04 13. " P13 ,Peripheral Select pin 13 - A/B C/D" "SCK3/SPI3_SPCK/SCK6/SPI6_SPCK,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 12. " P12 ,Peripheral Select pin 12 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 11. " P11 ,Peripheral Select pin 11 - A/B C/D" "RXD4/SPI4_MISO/TWCK4/RXD6/SPI6_MISO/TWCK6,C/D"
|
|
bitfld.long 0x04 10. " P10 ,Peripheral Select pin 10 - A/B C/D" "TXD4/SPI4_MOSI/TWD4/TXD6/SPI6_MOSI/TWD6,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 9. " P9 ,Peripheral Select pin 9 - A/B C/D" "RXD4/SPI4_MISO/TWCK4/SPI4_NPCS1/RTS4,C/D"
|
|
bitfld.long 0x04 8. " P8 ,Peripheral Select pin 8 - A/B C/D" "TXD4/SPI4_MOSI/TWD4/SPI4_NPCS0/CTS4,C/D"
|
|
bitfld.long 0x04 7. " P7 ,Peripheral Select pin 7 - A/B C/D" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 6. " P6 ,Peripheral Select pin 6 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 5. " P5 ,Peripheral Select pin 5 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 4. " P4 ,Peripheral Select pin 4 - A/B C/D" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P3 ,Peripheral Select pin 3 - A/B C/D" "TXD1/SPI1_MOSI/TWD1/PCK2,C/D"
|
|
bitfld.long 0x04 2. " P2 ,Peripheral Select pin 2 - A/B C/D" "RXD1/SPI1_MISO/TWCK1/RXD6/SPI6_MISO/TWCK6,C/D"
|
|
bitfld.long 0x04 1. " P1 ,Peripheral Select pin 1 - A/B C/D" "SCK4/SPI4_SPCK/TWCK2,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 0. " P0 ,Peripheral Select pin 0 - A/B C/D" "SCK0/SPI0_SPCK/TXD6/SPI6_MOSI/TWD6,C/D"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 12. " P12 ,Peripheral Select pin 12 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 11. " P11 ,Peripheral Select pin 11 - A/B C/D" "TWCK1/TWCK2,C/D"
|
|
bitfld.long 0x04 10. " P10 ,Peripheral Select pin 10 - A/B C/D" "TWD1/TWD2,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 9. " P9 ,Peripheral Select pin 9 - A/B C/D" "TWCK1/B,C/D"
|
|
bitfld.long 0x04 8. " P8 ,Peripheral Select pin 8 - A/B C/D" "TWD1/B,C/D"
|
|
bitfld.long 0x04 7. " P7 ,Peripheral Select pin 7 - A/B C/D" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 6. " P6 ,Peripheral Select pin 6 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 5. " P5 ,Peripheral Select pin 5 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 4. " P4 ,Peripheral Select pin 4 - A/B C/D" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P3 ,Peripheral Select pin 3 - A/B C/D" "UTXD1/PCK2,C/D"
|
|
bitfld.long 0x04 2. " P2 ,Peripheral Select pin 2 - A/B C/D" "URXD1/NPCS1,C/D"
|
|
bitfld.long 0x04 1. " P1 ,Peripheral Select pin 1 - A/B C/D" "A/TWCK2,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 0. " P0 ,Peripheral Select pin 0 - A/B C/D" "A/TWD2,C/D"
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PIO_IFSCSR,PIO Input Filter Slow Clock Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Glitch or Debouncing Filter Selection Status pin 15" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status pin 14" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status pin 13" "Glitch,Debouncing"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status pin 12" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status pin 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status pin 10" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status pin 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status pin 8" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status pin 7" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status pin 6" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status pin 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status pin 4" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status pin 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status pin 2" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr ,Glitch or Debouncing Filter Selection Status pin 1" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status pin 0" "Glitch,Debouncing"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PIO_SCDR,PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow Clock Divider Selection for Debouncing"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PIO_PPDSR,PIO Pad Pull Down Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Pull Down Status pin 15" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Pull Down Status pin 14" "Enabled,Disabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Pull Down Status pin 13" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12 ,Pull Down Status pin 12" "Enabled,Disabled"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11 ,Pull Down Status pin 11" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10 ,Pull Down Status pin 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9 ,Pull Down Status pin 9" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8 ,Pull Down Status pin 8" "Enabled,Disabled"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7 ,Pull Down Status pin 7" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6 ,Pull Down Status pin 6" "Enabled,Disabled"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5 ,Pull Down Status pin 5" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4 ,Pull Down Status pin 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3 ,Pull Down Status pin 3" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2 ,Pull Down Status pin 2" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1 ,Pull Down Status pin 1" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0 ,Pull Down Status pin 0" "Enabled,Disabled"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PIO_OWSR,PIO Output Write Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Write Status pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Write Status pin 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Write Status pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Write Status pin 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Write Status pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Write Status pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Write Status pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Write Status pin 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Write Status pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Write Status pin 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Write Status pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Write Status pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Write Status pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Write Status pin 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Write Status pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Write Status pin 0" "Disabled,Enabled"
|
|
width 0x0b
|
|
else
|
|
width 13.
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PIO_PSR,PIO Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO Status 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO Status 13" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO Status 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO Status 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO Status 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO Status 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO Status 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO Status 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO Status 0" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PIO_OSR,PIO Output Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Status pin 15" "Input only,Input/Output"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Status pin 14" "Input only,Input/Output"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Status pin 13" "Input only,Input/Output"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Status pin 12" "Input only,Input/Output"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Status pin 11" "Input only,Input/Output"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Status pin 10" "Input only,Input/Output"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Status pin 9" "Input only,Input/Output"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Status pin 8" "Input only,Input/Output"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Status pin 7" "Input only,Input/Output"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Status pin 6" "Input only,Input/Output"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Status pin 5" "Input only,Input/Output"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Status pin 4" "Input only,Input/Output"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Status pin 3" "Input only,Input/Output"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Status pin 2" "Input only,Input/Output"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Status pin 1" "Input only,Input/Output"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Status pin 0" "Input only,Input/Output"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PIO_IFSR,PIO Input Filter Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Input Filer Status pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Filer Status pin 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Filer Status pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Filer Status pin 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Filer Status pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Filer Status pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Filer Status pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Filer Status pin 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Filer Status pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Filer Status pin 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Filer Status pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Filer Status pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Filer Status pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Filer Status pin 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Filer Status pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Filer Status pin 0" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PIO_ODSR,PIO Output Data Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Data Status pin 15" "0,1"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Data Status pin 14" "0,1"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Data Status pin 13" "0,1"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Data Status pin 12" "0,1"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Data Status pin 11" "0,1"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Data Status pin 10" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Data Status pin 9" "0,1"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Data Status pin 8" "0,1"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Data Status pin 7" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Data Status pin 6" "0,1"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Data Status pin 5" "0,1"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Data Status pin 4" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Data Status pin 3" "0,1"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Data Status pin 2" "0,1"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Data Status pin 1" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Data Status pin 0" "0,1"
|
|
textline " "
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "PIO_PDSR,PIO Pin Data Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
bitfld.long 0x00 15. " P15 ,Output Data Status pin 15" "Level 0,Level 1"
|
|
bitfld.long 0x00 14. " P14 ,Output Data Status pin 14" "Level 0,Level 1"
|
|
bitfld.long 0x00 13. " P13 ,Output Data Status pin 13" "Level 0,Level 1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12. " P12 ,Output Data Status pin 12" "Level 0,Level 1"
|
|
bitfld.long 0x00 11. " P11 ,Output Data Status pin 11" "Level 0,Level 1"
|
|
bitfld.long 0x00 10. " P10 ,Output Data Status pin 10" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Data Status pin 9" "Level 0,Level 1"
|
|
bitfld.long 0x00 8. " P8 ,Output Data Status pin 8" "Level 0,Level 1"
|
|
bitfld.long 0x00 7. " P7 ,Output Data Status pin 7" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Output Data Status pin 6" "Level 0,Level 1"
|
|
bitfld.long 0x00 5. " P5 ,Output Data Status pin 5" "Level 0,Level 1"
|
|
bitfld.long 0x00 4. " P4 ,Output Data Status pin 4" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Data Status pin 3" "Level 0,Level 1"
|
|
bitfld.long 0x00 2. " P2 ,Output Data Status pin 2" "Level 0,Level 1"
|
|
bitfld.long 0x00 1. " P1 ,Output Data Status pin 1" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Output Data Status pin 0" "Level 0,Level 1"
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "PIO_ISR,PIO Interrupt Status Register"
|
|
in
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PIO_ISR,PIO Interrupt Mask Register"
|
|
sif cpu()=="ATSAMG55"
|
|
bitfld.long 0x00 15. " P15 ,Input Change Interrupt Mask pin 15" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " P14 ,Input Change Interrupt Mask pin 14" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " P13 ,Input Change Interrupt Mask pin 13" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12. " P12 ,Input Change Interrupt Mask pin 12" "Masked,Not masked"
|
|
bitfld.long 0x00 11. " P11 ,Input Change Interrupt Mask pin 11" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " P10 ,Input Change Interrupt Mask pin 10" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Input Change Interrupt Mask pin 9" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " P8 ,Input Change Interrupt Mask pin 8" "Masked,Not masked"
|
|
bitfld.long 0x00 7. " P7 ,Input Change Interrupt Mask pin 7" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Input Change Interrupt Mask pin 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " P5 ,Input Change Interrupt Mask pin 5" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " P4 ,Input Change Interrupt Mask pin 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Input Change Interrupt Mask pin 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " P2 ,Input Change Interrupt Mask pin 2" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " P1 ,Input Change Interrupt Mask pin 1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Input Change Interrupt Mask pin 0" "Masked,Not masked"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PIO_MDSR,PIO Multi-driver Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Multi Drive Status/Drive pin 15" "Low,High"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Multi Drive Status/Drive pin 14" "Low,High"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Multi Drive Status/Drive pin 13" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Multi Drive Status/Drive pin 12" "Low,High"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Multi Drive Status/Drive pin 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Multi Drive Status/Drive pin 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Multi Drive Status/Drive pin 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Multi Drive Status/Drive pin 8" "Low,High"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Multi Drive Status/Drive pin 7" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Multi Drive Status/Drive pin 6" "Low,High"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Multi Drive Status/Drive pin 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Multi Drive Status/Drive pin 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Multi Drive Status/Drive pin 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Multi Drive Status/Drive pin 2" "Low,High"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Multi Drive Status/Drive pin 1" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Multi Drive Status/Drive pin 0" "Low,High"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PIO_PUSR,PIO Pull Up Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Pull Up Status pin 15" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Pull Up Status pin 14" "Enabled,Disabled"
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Pull Up Status pin 13" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Pull Up Status pin 12" "Enabled,Disabled"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Pull Up Status pin 11" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Pull Up Status pin 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Pull Up Status pin 9" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Pull Up Status pin 8" "Enabled,Disabled"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Pull Up Status pin 7" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Pull Up Status pin 6" "Enabled,Disabled"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Pull Up Status pin 5" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Pull Up Status pin 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Pull Up Status pin 3" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Pull Up Status pin 2" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr ,Pull Up Status pin 1" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Pull Up Status pin 0" "Enabled,Disabled"
|
|
rgroup.long 0x70++0x07
|
|
line.long 0x00 "PIO_ABCDSR1,Peripheral Select Register 1"
|
|
sif cpu()=="ATSAMG55"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select pin 15 - A/C B/D" "SPI3_NPCS1/RTS3/C,SPI6_NPCS1/RTS6/D"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select pin 14 - A/C B/D" "SPI3_NPCS0/CTS3/C,SPI6_NPCS0/CTS6/D"
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select pin 13 - A/C B/D" "SCK3/SPI3_SPCK/C,SCK6/SPI6_SPCK/D"
|
|
textline " "
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select pin 12 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select pin 11 - A/C B/D" "RXD4/SPI4_MISO/TWCK4/C,RXD6/SPI6_MISO/TWCK6/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select pin 10 - A/C B/D" "TXD4/SPI4_MOSI/TWD4/C,TXD6/SPI6_MOSI/TWD6/D"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select pin 9 - A/C B/D" "RXD4/SPI4_MISO/TWCK4/C,SPI4_NPCS1/RTS4/D"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select pin 8 - A/C B/D" "TXD4/SPI4_MOSI/TWD4/C,SPI4_NPCS0/CTS4/D"
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select pin 7 - A/C B/D" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select pin 6 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select pin 5 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select pin 4 - A/C B/D" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select pin 3 - A/C B/D" "TXD1/SPI1_MOSI/TWD1/C,PCK2/D"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select pin 2 - A/C B/D" "RXD1/SPI1_MISO/TWCK1/C,RXD6/SPI6_MISO/TWCK6/D"
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select pin 1 - A/C B/D" "SCK4/SPI4_SPCK/C,TWCK2/D"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select pin 0 - A/C B/D" "SCK0/SPI0_SPCK/C,TXD6/SPI6_MOSI/TWD6/D"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select pin 12 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select pin 11 - A/C B/D" "TWCK1/C,TWCK2/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select pin 10 - A/C B/D" "TWD1/C,TWD2/D"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select pin 9 - A/C B/D" "TWCK1/C,B/D"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select pin 8 - A/C B/D" "TWD1/C,B/D"
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select pin 7 - A/C B/D" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select pin 6 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select pin 5 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select pin 4 - A/C B/D" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select pin 3 - A/C B/D" "UTXD1/C,PCK2/D"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select pin 2 - A/C B/D" "URXD1/C,NPCS1/D"
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select pin 1 - A/C B/D" "A/C,TWCK2/D"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select pin 0 - A/C B/D" "A/C,TWD2/D"
|
|
endif
|
|
line.long 0x04 "PIO_ABCDSR2,Peripheral Select Register 2"
|
|
sif cpu()=="ATSAMG55"
|
|
bitfld.long 0x04 15. " P15 ,Peripheral Select pin 15 - A/B C/D" "SPI3_NPCS1/RTS3/SPI6_NPCS1/RTS6,C/D"
|
|
bitfld.long 0x04 14. " P14 ,Peripheral Select pin 14 - A/B C/D" "SPI3_NPCS0/CTS3/SPI6_NPCS0/CTS6,C/D"
|
|
bitfld.long 0x04 13. " P13 ,Peripheral Select pin 13 - A/B C/D" "SCK3/SPI3_SPCK/SCK6/SPI6_SPCK,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 12. " P12 ,Peripheral Select pin 12 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 11. " P11 ,Peripheral Select pin 11 - A/B C/D" "RXD4/SPI4_MISO/TWCK4/RXD6/SPI6_MISO/TWCK6,C/D"
|
|
bitfld.long 0x04 10. " P10 ,Peripheral Select pin 10 - A/B C/D" "TXD4/SPI4_MOSI/TWD4/TXD6/SPI6_MOSI/TWD6,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 9. " P9 ,Peripheral Select pin 9 - A/B C/D" "RXD4/SPI4_MISO/TWCK4/SPI4_NPCS1/RTS4,C/D"
|
|
bitfld.long 0x04 8. " P8 ,Peripheral Select pin 8 - A/B C/D" "TXD4/SPI4_MOSI/TWD4/SPI4_NPCS0/CTS4,C/D"
|
|
bitfld.long 0x04 7. " P7 ,Peripheral Select pin 7 - A/B C/D" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 6. " P6 ,Peripheral Select pin 6 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 5. " P5 ,Peripheral Select pin 5 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 4. " P4 ,Peripheral Select pin 4 - A/B C/D" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P3 ,Peripheral Select pin 3 - A/B C/D" "TXD1/SPI1_MOSI/TWD1/PCK2,C/D"
|
|
bitfld.long 0x04 2. " P2 ,Peripheral Select pin 2 - A/B C/D" "RXD1/SPI1_MISO/TWCK1/RXD6/SPI6_MISO/TWCK6,C/D"
|
|
bitfld.long 0x04 1. " P1 ,Peripheral Select pin 1 - A/B C/D" "SCK4/SPI4_SPCK/TWCK2,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 0. " P0 ,Peripheral Select pin 0 - A/B C/D" "SCK0/SPI0_SPCK/TXD6/SPI6_MOSI/TWD6,C/D"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 12. " P12 ,Peripheral Select pin 12 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 11. " P11 ,Peripheral Select pin 11 - A/B C/D" "TWCK1/TWCK2,C/D"
|
|
bitfld.long 0x04 10. " P10 ,Peripheral Select pin 10 - A/B C/D" "TWD1/TWD2,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 9. " P9 ,Peripheral Select pin 9 - A/B C/D" "TWCK1/B,C/D"
|
|
bitfld.long 0x04 8. " P8 ,Peripheral Select pin 8 - A/B C/D" "TWD1/B,C/D"
|
|
bitfld.long 0x04 7. " P7 ,Peripheral Select pin 7 - A/B C/D" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 6. " P6 ,Peripheral Select pin 6 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 5. " P5 ,Peripheral Select pin 5 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 4. " P4 ,Peripheral Select pin 4 - A/B C/D" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P3 ,Peripheral Select pin 3 - A/B C/D" "UTXD1/PCK2,C/D"
|
|
bitfld.long 0x04 2. " P2 ,Peripheral Select pin 2 - A/B C/D" "URXD1/NPCS1,C/D"
|
|
bitfld.long 0x04 1. " P1 ,Peripheral Select pin 1 - A/B C/D" "A/TWCK2,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 0. " P0 ,Peripheral Select pin 0 - A/B C/D" "A/TWD2,C/D"
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PIO_IFSCSR,PIO Input Filter Slow Clock Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Glitch or Debouncing Filter Selection Status pin 15" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status pin 14" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status pin 13" "Glitch,Debouncing"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status pin 12" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status pin 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status pin 10" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status pin 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status pin 8" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status pin 7" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status pin 6" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status pin 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status pin 4" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status pin 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status pin 2" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr ,Glitch or Debouncing Filter Selection Status pin 1" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status pin 0" "Glitch,Debouncing"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PIO_SCDR,PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow Clock Divider Selection for Debouncing"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PIO_PPDSR,PIO Pad Pull Down Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Pull Down Status pin 15" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Pull Down Status pin 14" "Enabled,Disabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Pull Down Status pin 13" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12 ,Pull Down Status pin 12" "Enabled,Disabled"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11 ,Pull Down Status pin 11" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10 ,Pull Down Status pin 10" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9 ,Pull Down Status pin 9" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8 ,Pull Down Status pin 8" "Enabled,Disabled"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7 ,Pull Down Status pin 7" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6 ,Pull Down Status pin 6" "Enabled,Disabled"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5 ,Pull Down Status pin 5" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4 ,Pull Down Status pin 4" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3 ,Pull Down Status pin 3" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2 ,Pull Down Status pin 2" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1 ,Pull Down Status pin 1" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0 ,Pull Down Status pin 0" "Enabled,Disabled"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PIO_OWSR,PIO Output Write Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Write Status pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Write Status pin 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Write Status pin 13" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Write Status pin 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Write Status pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Write Status pin 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Write Status pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Write Status pin 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Write Status pin 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Write Status pin 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Write Status pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Write Status pin 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Write Status pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Write Status pin 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Write Status pin 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Write Status pin 0" "Disabled,Enabled"
|
|
width 0x0b
|
|
endif
|
|
width 13.
|
|
textline ""
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "PIO_AIMMR,PIO Additional Interrupt Modes Mask Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Peripheral CD Status pin 15" "Masked,Not masked"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Peripheral CD Status pin 14" "Masked,Not masked"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Peripheral CD Status pin 13" "Masked,Not masked"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Peripheral CD Status pin 12" "Masked,Not masked"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Peripheral CD Status pin 11" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Peripheral CD Status pin 10" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Peripheral CD Status pin 9" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Peripheral CD Status pin 8" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Peripheral CD Status pin 7" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Peripheral CD Status pin 6" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Peripheral CD Status pin 5" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Peripheral CD Status pin 4" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Peripheral CD Status pin 3" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Peripheral CD Status pin 2" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Peripheral CD Status pin 1" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Peripheral CD Status pin 0" "Masked,Not masked"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "PIO_ELSR,PIO Edge/Level Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Edge/Level Interrupt source selection pin 15" "Edge,Level"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection pin 14" "Edge,Level"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection pin 13" "Edge,Level"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection pin 12" "Edge,Level"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection pin 11" "Edge,Level"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection pin 10" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection pin 9" "Edge,Level"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection pin 8" "Edge,Level"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection pin 7" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection pin 6" "Edge,Level"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection pin 5" "Edge,Level"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection pin 4" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection pin 3" "Edge,Level"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection pin 2" "Edge,Level"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Edge/Level Interrupt source selection pin 1" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection pin 0" "Edge,Level"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "PIO_FRLHSR,PIO Fall/Rise - Low/High Status Register"
|
|
sif cpu()=="ATSAMG55"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Edge /Level Interrupt Source Selection pin 15" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Edge /Level Interrupt Source Selection pin 14" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Edge /Level Interrupt Source Selection pin 13" "Falling/Low,Rising/High"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Edge /Level Interrupt Source Selection pin 12" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Edge /Level Interrupt Source Selection pin 11" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Edge /Level Interrupt Source Selection pin 10" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Edge /Level Interrupt Source Selection pin 9" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Edge /Level Interrupt Source Selection pin 8" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Edge /Level Interrupt Source Selection pin 7" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Edge /Level Interrupt Source Selection pin 6" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Edge /Level Interrupt Source Selection pin 5" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Edge /Level Interrupt Source Selection pin 4" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Edge /Level Interrupt Source Selection pin 3" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Edge /Level Interrupt Source Selection pin 2" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr ,Edge /Level Interrupt Source Selection pin 1" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Edge /Level Interrupt Source Selection pin 0" "Falling/Low,Rising/High"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in.
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PIO_SCHMITT,PIO Schmitt Trigger Register"
|
|
sif cpu()=="ATSAMG55"
|
|
bitfld.long 0x00 15. " SCHMITT15 ,Schmitt Trigger 15 Disabled" "No,Yes"
|
|
bitfld.long 0x00 14. " SCHMITT14 ,Schmitt Trigger 14 Disabled" "No,Yes"
|
|
bitfld.long 0x00 13. " SCHMITT13 ,Schmitt Trigger 13 Disabled" "No,Yes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12. " SCHMITT12 ,Schmitt Trigger pin 12 Disabled" "No,Yes"
|
|
bitfld.long 0x00 11. " SCHMITT11 ,Schmitt Trigger pin 11 Disabled" "No,Yes"
|
|
bitfld.long 0x00 10. " SCHMITT10 ,Schmitt Trigger pin 10 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SCHMITT9 ,Schmitt Trigger pin 9 Disabled" "No,Yes"
|
|
bitfld.long 0x00 8. " SCHMITT8 ,Schmitt Trigger pin 8 Disabled" "No,Yes"
|
|
bitfld.long 0x00 7. " SCHMITT7 ,Schmitt Trigger pin 7 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCHMITT6 ,Schmitt Trigger pin 6 Disabled" "No,Yes"
|
|
bitfld.long 0x00 5. " SCHMITT5 ,Schmitt Trigger pin 5 Disabled" "No,Yes"
|
|
bitfld.long 0x00 4. " SCHMITT4 ,Schmitt Trigger pin 4 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCHMITT3 ,Schmitt Trigger pin 3 Disabled" "No,Yes"
|
|
bitfld.long 0x00 2. " SCHMITT2 ,Schmitt Trigger pin 2 Disabled" "No,Yes"
|
|
bitfld.long 0x00 1. " SCHMITT1 ,Schmitt Trigger pin 1 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCHMITT0 ,Schmitt Trigger pin 0 Disabled" "No,Yes"
|
|
sif (cpu()=="ATSAMG55")
|
|
group.long 0x110++0x03
|
|
line.long 0x00 " PIO_DRIVER ,PIO I/O Drive Register"
|
|
bitfld.long 0x00 15. " LINE15 ,Drive of PIO Line 15" "Low drive,High drive"
|
|
textline " "
|
|
bitfld.long 0x00 14. " LINE14 ,Drive of PIO Line 14" "Low drive,High drive"
|
|
bitfld.long 0x00 13. " LINE13 ,Drive of PIO Line 13" "Low drive,High drive"
|
|
bitfld.long 0x00 12. " LINE12 ,Drive of PIO Line 12" "Low drive,High drive"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LINE11 ,Drive of PIO Line 11" "Low drive,High drive"
|
|
bitfld.long 0x00 10. " LINE10 ,Drive of PIO Line 10" "Low drive,High drive"
|
|
bitfld.long 0x00 9. " LINE9 ,Drive of PIO Line 9" "Low drive,High drive"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LINE8 ,Drive of PIO Line 8" "Low drive,High drive"
|
|
bitfld.long 0x00 7. " LINE7 ,Drive of PIO Line 7" "Low drive,High drive"
|
|
bitfld.long 0x00 6. " LINE6 ,Drive of PIO Line 6" "Low drive,High drive"
|
|
textline " "
|
|
bitfld.long 0x00 5. " LINE5 ,Drive of PIO Line 5" "Low drive,High drive"
|
|
bitfld.long 0x00 4. " LINE4 ,Drive of PIO Line 4" "Low drive,High drive"
|
|
bitfld.long 0x00 3. " LINE3 ,Drive of PIO Line 3" "Low drive,High drive"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LINE2 ,Drive of PIO Line 2" "Low drive,High drive"
|
|
bitfld.long 0x00 1. " LINE1 ,Drive of PIO Line 1" "Low drive,High drive"
|
|
bitfld.long 0x00 0. " LINE0 ,Drive of PIO Line 0" "Low drive,High drive"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
sif (cpu()=="ATSAMG55")
|
|
tree "SPI0"
|
|
base ad:0x4000C400
|
|
width 10.
|
|
sif (cpu()=="ATSAMG55")
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI_CR,SPI Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 12. " REQCLR ,Request to Clear the Comparison Trigger" "No effect,Cleared"
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI_CR,SPI Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
endif
|
|
if ((d.l(ad:0x4000C400+0xE4)&0x01)==0x00)
|
|
if (((d.l((ad:0x4000C400+0x04)))&0x07)==0x01)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x4000C400+0x04)))&0x07)==0x05)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x4000C400+0x04)))&0x07)==(0x03||0x07))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x4000C400+0x04)))&0x07)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x4000C400+0x04)))&0x07)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0x4000C400+0x04)))&0x07)==0x01)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x4000C400+0x04)))&0x07)==0x05)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x4000C400+0x04)))&0x07)==(0x03||0x07))
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x4000C400+0x04)))&0x07)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x4000C400+0x04)))&0x07)==0x04)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
endif
|
|
endif
|
|
if (((d.l((ad:0x4000C400+0x04)))&0x01)==0x01)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x00 16.--17. 1. " PCS ,Peripheral Chip Select"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
endif
|
|
if (((d.l((ad:0x4000C400+0x04)))&0x06)==0x02)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
elif (((d.l((ad:0x4000C400+0x04)))&0x06)==0x06)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SPI_SR,SPI Status Register"
|
|
in
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SPI_IMR,SPI Interrupt Mask Register"
|
|
sif (cpu()=="ATSAMG55")
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " CMP_set/clr ,Comparison Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNDES_set/clr ,Underrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,Transmission Registers Empty Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NSSR_set/clr ,NSS Rising Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " OVRES_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MODF_set/clr ,Mode Fault Error Inrerrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TDRE_set/clr ,SPI Transmit Data Register Empty Inrerrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RDRF_set/clr ,Receive Data Register Full Inrerrupt Mask" "Masked,Not masked"
|
|
if ((d.l(ad:0x4000C400+0xE4)&0x01)==0x00)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
if ((d.l(ad:0x4000C400+0xE4)&0x01)==0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
sif (cpu()=="ATSAMG55")
|
|
if ((d.l(ad:0x4000C400+0xE4)&0x01)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
endif
|
|
endif
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " SPIWPKEY ,SPI Write Protection Key Password"
|
|
bitfld.long 0x00 0. " SPIWPEN ,SPI Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "SPI_WPSR,SPI Write Protection Status Register"
|
|
in
|
|
width 0x0B
|
|
tree "SPI0 PDC (Peripheral DMA Controller)"
|
|
width 12.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "SPI0_RPR,Receive Pointer Register"
|
|
line.long 0x04 "SPI0_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "SPI0_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "SPI0_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "SPI0_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "SPI0_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "SPI0_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "SPI0_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "SPI0_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "SPI0_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "SPI1"
|
|
base ad:0x40020400
|
|
width 10.
|
|
sif (cpu()=="ATSAMG55")
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI_CR,SPI Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 12. " REQCLR ,Request to Clear the Comparison Trigger" "No effect,Cleared"
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI_CR,SPI Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
endif
|
|
if ((d.l(ad:0x40020400+0xE4)&0x01)==0x00)
|
|
if (((d.l((ad:0x40020400+0x04)))&0x07)==0x01)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40020400+0x04)))&0x07)==0x05)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40020400+0x04)))&0x07)==(0x03||0x07))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40020400+0x04)))&0x07)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40020400+0x04)))&0x07)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0x40020400+0x04)))&0x07)==0x01)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40020400+0x04)))&0x07)==0x05)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40020400+0x04)))&0x07)==(0x03||0x07))
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40020400+0x04)))&0x07)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40020400+0x04)))&0x07)==0x04)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
endif
|
|
endif
|
|
if (((d.l((ad:0x40020400+0x04)))&0x01)==0x01)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x00 16.--17. 1. " PCS ,Peripheral Chip Select"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
endif
|
|
if (((d.l((ad:0x40020400+0x04)))&0x06)==0x02)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
elif (((d.l((ad:0x40020400+0x04)))&0x06)==0x06)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SPI_SR,SPI Status Register"
|
|
in
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SPI_IMR,SPI Interrupt Mask Register"
|
|
sif (cpu()=="ATSAMG55")
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " CMP_set/clr ,Comparison Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNDES_set/clr ,Underrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,Transmission Registers Empty Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NSSR_set/clr ,NSS Rising Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " OVRES_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MODF_set/clr ,Mode Fault Error Inrerrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TDRE_set/clr ,SPI Transmit Data Register Empty Inrerrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RDRF_set/clr ,Receive Data Register Full Inrerrupt Mask" "Masked,Not masked"
|
|
if ((d.l(ad:0x40020400+0xE4)&0x01)==0x00)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
if ((d.l(ad:0x40020400+0xE4)&0x01)==0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
sif (cpu()=="ATSAMG55")
|
|
if ((d.l(ad:0x40020400+0xE4)&0x01)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
endif
|
|
endif
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " SPIWPKEY ,SPI Write Protection Key Password"
|
|
bitfld.long 0x00 0. " SPIWPEN ,SPI Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "SPI_WPSR,SPI Write Protection Status Register"
|
|
in
|
|
width 0x0B
|
|
tree "SPI1 PDC (Peripheral DMA Controller)"
|
|
width 12.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "SPI1_RPR,Receive Pointer Register"
|
|
line.long 0x04 "SPI1_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "SPI1_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "SPI1_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "SPI1_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "SPI1_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "SPI1_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "SPI1_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "SPI1_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "SPI1_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "SPI2"
|
|
base ad:0x40024400
|
|
width 10.
|
|
sif (cpu()=="ATSAMG55")
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI_CR,SPI Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 12. " REQCLR ,Request to Clear the Comparison Trigger" "No effect,Cleared"
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI_CR,SPI Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
endif
|
|
if ((d.l(ad:0x40024400+0xE4)&0x01)==0x00)
|
|
if (((d.l((ad:0x40024400+0x04)))&0x07)==0x01)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40024400+0x04)))&0x07)==0x05)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40024400+0x04)))&0x07)==(0x03||0x07))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40024400+0x04)))&0x07)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40024400+0x04)))&0x07)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0x40024400+0x04)))&0x07)==0x01)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40024400+0x04)))&0x07)==0x05)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40024400+0x04)))&0x07)==(0x03||0x07))
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40024400+0x04)))&0x07)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40024400+0x04)))&0x07)==0x04)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
endif
|
|
endif
|
|
if (((d.l((ad:0x40024400+0x04)))&0x01)==0x01)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x00 16.--17. 1. " PCS ,Peripheral Chip Select"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
endif
|
|
if (((d.l((ad:0x40024400+0x04)))&0x06)==0x02)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
elif (((d.l((ad:0x40024400+0x04)))&0x06)==0x06)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SPI_SR,SPI Status Register"
|
|
in
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SPI_IMR,SPI Interrupt Mask Register"
|
|
sif (cpu()=="ATSAMG55")
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " CMP_set/clr ,Comparison Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNDES_set/clr ,Underrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,Transmission Registers Empty Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NSSR_set/clr ,NSS Rising Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " OVRES_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MODF_set/clr ,Mode Fault Error Inrerrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TDRE_set/clr ,SPI Transmit Data Register Empty Inrerrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RDRF_set/clr ,Receive Data Register Full Inrerrupt Mask" "Masked,Not masked"
|
|
if ((d.l(ad:0x40024400+0xE4)&0x01)==0x00)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
if ((d.l(ad:0x40024400+0xE4)&0x01)==0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
sif (cpu()=="ATSAMG55")
|
|
if ((d.l(ad:0x40024400+0xE4)&0x01)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
endif
|
|
endif
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " SPIWPKEY ,SPI Write Protection Key Password"
|
|
bitfld.long 0x00 0. " SPIWPEN ,SPI Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "SPI_WPSR,SPI Write Protection Status Register"
|
|
in
|
|
width 0x0B
|
|
tree "SPI2 PDC (Peripheral DMA Controller)"
|
|
width 12.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "SPI2_RPR,Receive Pointer Register"
|
|
line.long 0x04 "SPI2_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "SPI2_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "SPI2_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "SPI2_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "SPI2_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "SPI2_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "SPI2_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "SPI2_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "SPI2_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "SPI3"
|
|
base ad:0x40018400
|
|
width 10.
|
|
sif (cpu()=="ATSAMG55")
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI_CR,SPI Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 12. " REQCLR ,Request to Clear the Comparison Trigger" "No effect,Cleared"
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI_CR,SPI Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
endif
|
|
if ((d.l(ad:0x40018400+0xE4)&0x01)==0x00)
|
|
if (((d.l((ad:0x40018400+0x04)))&0x07)==0x01)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40018400+0x04)))&0x07)==0x05)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40018400+0x04)))&0x07)==(0x03||0x07))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40018400+0x04)))&0x07)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40018400+0x04)))&0x07)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0x40018400+0x04)))&0x07)==0x01)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40018400+0x04)))&0x07)==0x05)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40018400+0x04)))&0x07)==(0x03||0x07))
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40018400+0x04)))&0x07)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40018400+0x04)))&0x07)==0x04)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
endif
|
|
endif
|
|
if (((d.l((ad:0x40018400+0x04)))&0x01)==0x01)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x00 16.--17. 1. " PCS ,Peripheral Chip Select"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
endif
|
|
if (((d.l((ad:0x40018400+0x04)))&0x06)==0x02)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
elif (((d.l((ad:0x40018400+0x04)))&0x06)==0x06)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SPI_SR,SPI Status Register"
|
|
in
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SPI_IMR,SPI Interrupt Mask Register"
|
|
sif (cpu()=="ATSAMG55")
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " CMP_set/clr ,Comparison Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNDES_set/clr ,Underrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,Transmission Registers Empty Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NSSR_set/clr ,NSS Rising Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " OVRES_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MODF_set/clr ,Mode Fault Error Inrerrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TDRE_set/clr ,SPI Transmit Data Register Empty Inrerrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RDRF_set/clr ,Receive Data Register Full Inrerrupt Mask" "Masked,Not masked"
|
|
if ((d.l(ad:0x40018400+0xE4)&0x01)==0x00)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
if ((d.l(ad:0x40018400+0xE4)&0x01)==0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
sif (cpu()=="ATSAMG55")
|
|
if ((d.l(ad:0x40018400+0xE4)&0x01)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
endif
|
|
endif
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " SPIWPKEY ,SPI Write Protection Key Password"
|
|
bitfld.long 0x00 0. " SPIWPEN ,SPI Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "SPI_WPSR,SPI Write Protection Status Register"
|
|
in
|
|
width 0x0B
|
|
tree "SPI3 PDC (Peripheral DMA Controller)"
|
|
width 12.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "SPI3_RPR,Receive Pointer Register"
|
|
line.long 0x04 "SPI3_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "SPI3_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "SPI3_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "SPI3_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "SPI3_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "SPI3_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "SPI3_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "SPI3_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "SPI3_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "SPI4"
|
|
base ad:0x4001C400
|
|
width 10.
|
|
sif (cpu()=="ATSAMG55")
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI_CR,SPI Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 12. " REQCLR ,Request to Clear the Comparison Trigger" "No effect,Cleared"
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI_CR,SPI Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
endif
|
|
if ((d.l(ad:0x4001C400+0xE4)&0x01)==0x00)
|
|
if (((d.l((ad:0x4001C400+0x04)))&0x07)==0x01)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x4001C400+0x04)))&0x07)==0x05)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x4001C400+0x04)))&0x07)==(0x03||0x07))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x4001C400+0x04)))&0x07)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x4001C400+0x04)))&0x07)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0x4001C400+0x04)))&0x07)==0x01)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x4001C400+0x04)))&0x07)==0x05)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x4001C400+0x04)))&0x07)==(0x03||0x07))
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x4001C400+0x04)))&0x07)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x4001C400+0x04)))&0x07)==0x04)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
endif
|
|
endif
|
|
if (((d.l((ad:0x4001C400+0x04)))&0x01)==0x01)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x00 16.--17. 1. " PCS ,Peripheral Chip Select"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
endif
|
|
if (((d.l((ad:0x4001C400+0x04)))&0x06)==0x02)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
elif (((d.l((ad:0x4001C400+0x04)))&0x06)==0x06)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SPI_SR,SPI Status Register"
|
|
in
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SPI_IMR,SPI Interrupt Mask Register"
|
|
sif (cpu()=="ATSAMG55")
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " CMP_set/clr ,Comparison Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNDES_set/clr ,Underrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,Transmission Registers Empty Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NSSR_set/clr ,NSS Rising Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " OVRES_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MODF_set/clr ,Mode Fault Error Inrerrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TDRE_set/clr ,SPI Transmit Data Register Empty Inrerrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RDRF_set/clr ,Receive Data Register Full Inrerrupt Mask" "Masked,Not masked"
|
|
if ((d.l(ad:0x4001C400+0xE4)&0x01)==0x00)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
if ((d.l(ad:0x4001C400+0xE4)&0x01)==0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
sif (cpu()=="ATSAMG55")
|
|
if ((d.l(ad:0x4001C400+0xE4)&0x01)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
endif
|
|
endif
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " SPIWPKEY ,SPI Write Protection Key Password"
|
|
bitfld.long 0x00 0. " SPIWPEN ,SPI Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "SPI_WPSR,SPI Write Protection Status Register"
|
|
in
|
|
width 0x0B
|
|
tree "SPI4 PDC (Peripheral DMA Controller)"
|
|
width 12.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "SPI4_RPR,Receive Pointer Register"
|
|
line.long 0x04 "SPI4_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "SPI4_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "SPI4_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "SPI4_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "SPI4_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "SPI4_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "SPI4_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "SPI4_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "SPI4_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "SPI5"
|
|
base ad:0x40008400
|
|
width 10.
|
|
sif (cpu()=="ATSAMG55")
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI_CR,SPI Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 12. " REQCLR ,Request to Clear the Comparison Trigger" "No effect,Cleared"
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI_CR,SPI Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
endif
|
|
if ((d.l(ad:0x40008400+0xE4)&0x01)==0x00)
|
|
if (((d.l((ad:0x40008400+0x04)))&0x07)==0x01)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40008400+0x04)))&0x07)==0x05)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40008400+0x04)))&0x07)==(0x03||0x07))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40008400+0x04)))&0x07)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40008400+0x04)))&0x07)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0x40008400+0x04)))&0x07)==0x01)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40008400+0x04)))&0x07)==0x05)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40008400+0x04)))&0x07)==(0x03||0x07))
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40008400+0x04)))&0x07)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40008400+0x04)))&0x07)==0x04)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
endif
|
|
endif
|
|
if (((d.l((ad:0x40008400+0x04)))&0x01)==0x01)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x00 16.--17. 1. " PCS ,Peripheral Chip Select"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
endif
|
|
if (((d.l((ad:0x40008400+0x04)))&0x06)==0x02)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
elif (((d.l((ad:0x40008400+0x04)))&0x06)==0x06)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SPI_SR,SPI Status Register"
|
|
in
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SPI_IMR,SPI Interrupt Mask Register"
|
|
sif (cpu()=="ATSAMG55")
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " CMP_set/clr ,Comparison Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNDES_set/clr ,Underrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,Transmission Registers Empty Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NSSR_set/clr ,NSS Rising Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " OVRES_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MODF_set/clr ,Mode Fault Error Inrerrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TDRE_set/clr ,SPI Transmit Data Register Empty Inrerrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RDRF_set/clr ,Receive Data Register Full Inrerrupt Mask" "Masked,Not masked"
|
|
if ((d.l(ad:0x40008400+0xE4)&0x01)==0x00)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
if ((d.l(ad:0x40008400+0xE4)&0x01)==0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
sif (cpu()=="ATSAMG55")
|
|
if ((d.l(ad:0x40008400+0xE4)&0x01)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
endif
|
|
endif
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " SPIWPKEY ,SPI Write Protection Key Password"
|
|
bitfld.long 0x00 0. " SPIWPEN ,SPI Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "SPI_WPSR,SPI Write Protection Status Register"
|
|
in
|
|
width 0x0B
|
|
tree "SPI5 PDC (Peripheral DMA Controller)"
|
|
width 12.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "SPI5_RPR,Receive Pointer Register"
|
|
line.long 0x04 "SPI5_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "SPI5_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "SPI5_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "SPI5_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "SPI5_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "SPI5_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "SPI5_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "SPI5_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "SPI5_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "SPI6"
|
|
base ad:0x40040400
|
|
width 10.
|
|
sif (cpu()=="ATSAMG55")
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI_CR,SPI Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 12. " REQCLR ,Request to Clear the Comparison Trigger" "No effect,Cleared"
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI_CR,SPI Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
endif
|
|
if ((d.l(ad:0x40040400+0xE4)&0x01)==0x00)
|
|
if (((d.l((ad:0x40040400+0x04)))&0x07)==0x01)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40040400+0x04)))&0x07)==0x05)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40040400+0x04)))&0x07)==(0x03||0x07))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40040400+0x04)))&0x07)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40040400+0x04)))&0x07)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0x40040400+0x04)))&0x07)==0x01)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40040400+0x04)))&0x07)==0x05)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40040400+0x04)))&0x07)==(0x03||0x07))
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40040400+0x04)))&0x07)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40040400+0x04)))&0x07)==0x04)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
endif
|
|
endif
|
|
if (((d.l((ad:0x40040400+0x04)))&0x01)==0x01)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x00 16.--17. 1. " PCS ,Peripheral Chip Select"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
endif
|
|
if (((d.l((ad:0x40040400+0x04)))&0x06)==0x02)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
elif (((d.l((ad:0x40040400+0x04)))&0x06)==0x06)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SPI_SR,SPI Status Register"
|
|
in
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SPI_IMR,SPI Interrupt Mask Register"
|
|
sif (cpu()=="ATSAMG55")
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " CMP_set/clr ,Comparison Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNDES_set/clr ,Underrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,Transmission Registers Empty Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NSSR_set/clr ,NSS Rising Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " OVRES_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MODF_set/clr ,Mode Fault Error Inrerrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TDRE_set/clr ,SPI Transmit Data Register Empty Inrerrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RDRF_set/clr ,Receive Data Register Full Inrerrupt Mask" "Masked,Not masked"
|
|
if ((d.l(ad:0x40040400+0xE4)&0x01)==0x00)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
if ((d.l(ad:0x40040400+0xE4)&0x01)==0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
sif (cpu()=="ATSAMG55")
|
|
if ((d.l(ad:0x40040400+0xE4)&0x01)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
endif
|
|
endif
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " SPIWPKEY ,SPI Write Protection Key Password"
|
|
bitfld.long 0x00 0. " SPIWPEN ,SPI Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "SPI_WPSR,SPI Write Protection Status Register"
|
|
in
|
|
width 0x0B
|
|
tree "SPI6 PDC (Peripheral DMA Controller)"
|
|
width 12.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "SPI6_RPR,Receive Pointer Register"
|
|
line.long 0x04 "SPI6_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "SPI6_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "SPI6_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "SPI6_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "SPI6_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "SPI6_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "SPI6_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "SPI6_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "SPI6_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "SPI7"
|
|
base ad:0x40034400
|
|
width 10.
|
|
sif (cpu()=="ATSAMG55")
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI_CR,SPI Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 12. " REQCLR ,Request to Clear the Comparison Trigger" "No effect,Cleared"
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI_CR,SPI Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
endif
|
|
if ((d.l(ad:0x40034400+0xE4)&0x01)==0x00)
|
|
if (((d.l((ad:0x40034400+0x04)))&0x07)==0x01)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40034400+0x04)))&0x07)==0x05)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40034400+0x04)))&0x07)==(0x03||0x07))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40034400+0x04)))&0x07)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40034400+0x04)))&0x07)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0x40034400+0x04)))&0x07)==0x01)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40034400+0x04)))&0x07)==0x05)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40034400+0x04)))&0x07)==(0x03||0x07))
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40034400+0x04)))&0x07)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40034400+0x04)))&0x07)==0x04)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
endif
|
|
endif
|
|
if (((d.l((ad:0x40034400+0x04)))&0x01)==0x01)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x00 16.--17. 1. " PCS ,Peripheral Chip Select"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
endif
|
|
if (((d.l((ad:0x40034400+0x04)))&0x06)==0x02)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
elif (((d.l((ad:0x40034400+0x04)))&0x06)==0x06)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SPI_SR,SPI Status Register"
|
|
in
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SPI_IMR,SPI Interrupt Mask Register"
|
|
sif (cpu()=="ATSAMG55")
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " CMP_set/clr ,Comparison Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNDES_set/clr ,Underrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,Transmission Registers Empty Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NSSR_set/clr ,NSS Rising Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " OVRES_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MODF_set/clr ,Mode Fault Error Inrerrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TDRE_set/clr ,SPI Transmit Data Register Empty Inrerrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RDRF_set/clr ,Receive Data Register Full Inrerrupt Mask" "Masked,Not masked"
|
|
if ((d.l(ad:0x40034400+0xE4)&0x01)==0x00)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
if ((d.l(ad:0x40034400+0xE4)&0x01)==0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
sif (cpu()=="ATSAMG55")
|
|
if ((d.l(ad:0x40034400+0xE4)&0x01)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
endif
|
|
endif
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " SPIWPKEY ,SPI Write Protection Key Password"
|
|
bitfld.long 0x00 0. " SPIWPEN ,SPI Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "SPI_WPSR,SPI Write Protection Status Register"
|
|
in
|
|
width 0x0B
|
|
tree "SPI7 PDC (Peripheral DMA Controller)"
|
|
width 12.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "SPI7_RPR,Receive Pointer Register"
|
|
line.long 0x04 "SPI7_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "SPI7_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "SPI7_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "SPI7_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "SPI7_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "SPI7_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "SPI7_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "SPI7_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "SPI7_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
else
|
|
tree "SPI"
|
|
base ad:0x40008000
|
|
width 10.
|
|
sif (cpu()=="ATSAMG55")
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI_CR,SPI Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 12. " REQCLR ,Request to Clear the Comparison Trigger" "No effect,Cleared"
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SPI_CR,SPI Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enable"
|
|
endif
|
|
if ((d.l(ad:0x40008000+0xE4)&0x01)==0x00)
|
|
if (((d.l((ad:0x40008000+0x04)))&0x07)==0x01)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40008000+0x04)))&0x07)==0x05)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40008000+0x04)))&0x07)==(0x03||0x07))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40008000+0x04)))&0x07)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40008000+0x04)))&0x07)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0x40008000+0x04)))&0x07)==0x01)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40008000+0x04)))&0x07)==0x05)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40008000+0x04)))&0x07)==(0x03||0x07))
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40008000+0x04)))&0x07)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,"
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
elif (((d.l((ad:0x40008000+0x04)))&0x07)==0x04)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "FLAG_ONLY,START_CONDITION"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WDRBT ,Wait Data Read Before Transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "No,Yes"
|
|
bitfld.long 0x00 3. " BRSRCCLK ,Bit Rate Source Clock" "PERIPH_CLK,PMC_PCK"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master"
|
|
endif
|
|
endif
|
|
if (((d.l((ad:0x40008000+0x04)))&0x01)==0x01)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x00 16.--17. 1. " PCS ,Peripheral Chip Select"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RD ,Receive Data"
|
|
endif
|
|
if (((d.l((ad:0x40008000+0x04)))&0x06)==0x02)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 10,NPCS = 01,NPCS = 10,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
elif (((d.l((ad:0x40008000+0x04)))&0x06)==0x06)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 00,NPCS = 01,NPCS = 10,NPCS = 11,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SPI_TDR,SPI Transmit Data Register"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SPI_SR,SPI Status Register"
|
|
in
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SPI_IMR,SPI Interrupt Mask Register"
|
|
sif (cpu()=="ATSAMG55")
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " CMP_set/clr ,Comparison Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNDES_set/clr ,Underrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,Transmission Registers Empty Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NSSR_set/clr ,NSS Rising Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " OVRES_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MODF_set/clr ,Mode Fault Error Inrerrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TDRE_set/clr ,SPI Transmit Data Register Empty Inrerrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RDRF_set/clr ,Receive Data Register Full Inrerrupt Mask" "Masked,Not masked"
|
|
if ((d.l(ad:0x40008000+0xE4)&0x01)==0x00)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SPI_CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
if ((d.l(ad:0x40008000+0xE4)&0x01)==0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "SPI_CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay Before SPCK"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial Clock Baud Rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip Select Not Active After Transfer" "Not risen,Risen"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock Polarity" "Low,High"
|
|
endif
|
|
sif (cpu()=="ATSAMG55")
|
|
if ((d.l(ad:0x40008000+0xE4)&0x01)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
endif
|
|
endif
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " SPIWPKEY ,SPI Write Protection Key Password"
|
|
bitfld.long 0x00 0. " SPIWPEN ,SPI Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "SPI_WPSR,SPI Write Protection Status Register"
|
|
in
|
|
width 0x0B
|
|
tree "SPI PDC (Peripheral DMA Controller)"
|
|
width 10.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "spi_RPR,Receive Pointer Register"
|
|
line.long 0x04 "spi_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "spi_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "spi_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "spi_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "spi_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "spi_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "spi_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "spi_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "spi_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif !cpuis("ATSAMG55")
|
|
tree "TWIHS (Two-wire Interface High Speed)"
|
|
base ad:0x40018000
|
|
width 13.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "TWI,TWI Control Register"
|
|
sif (cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 29. " FIFODIS ,FIFO Disable" "No effect,Disable"
|
|
bitfld.long 0x00 28. " FIFOEN ,FIFO Enable" "No effect,Enable"
|
|
bitfld.long 0x00 26. " LOCKCLR ,Lock Clear" "No effect,Clear"
|
|
bitfld.long 0x00 24. " THRCLR ,Transmit Holding Register Clear" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " CLEAR ,Bus CLEAR Command" "No effect,Enable"
|
|
sif (cpu()!="ATSAMG53")
|
|
bitfld.long 0x00 14. " PECRQ ,PEC Request" "No effect,Request"
|
|
bitfld.long 0x00 13. " PECDIS ,Packet Error Checking Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PECEN ,Packet Error Checking Enable" "No effect,Enable"
|
|
bitfld.long 0x00 11. " SMBDIS ,SMBus Mode Disabled" "No effect,Disabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 10. " SMBEN ,SMBus Mode Enabled" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " HSDIS ,TWI High-Speed Mode Disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " HSEN ,TWI High-Speed Mode Enabled" "No effect,Enabled"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS Quick Command(for master)" "No effect,Sent"
|
|
bitfld.long 0x00 5. " SVDIS ,TWI Slave Mode Disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " SVEN ,TWI Slave Mode Enabled" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSDIS ,TWI Master Mode Disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 2. " MSEN ,TWI Master Mode Enabled" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP Condition" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 0. " START ,Send a START Condition" "No effect,Send"
|
|
line.long 0x04 "TWIHS_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x04 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x04 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
bitfld.long 0x04 8.--9. " IADRSZ ,Internal Device Address Size" "NONE,1-byte,2-byte,3-byte"
|
|
if (((d.l(ad:0x40018000+0xE4))&0x01)==0x00)
|
|
sif (cpu()=="ATSAMG54")||(cpu()=="ATSAMG53")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TWIHS_SMR,TWI Slave Mode Register"
|
|
bitfld.long 0x00 31. " DATAMEN ,Data Matching Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SADR3EN ,Slave Address 3 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SADR2EN ,Slave Address 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SADR1EN ,Slave Address 1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR ,Slave Address"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MASK ,Slave Address Mask"
|
|
bitfld.long 0x00 6. " SCLWSDIS ,Clock Wait State Disable" "No effect,Disabled"
|
|
textline " "
|
|
sif cpu()!="ATSAMG53"
|
|
bitfld.long 0x00 3. " SMHH ,SMBus Host Header" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SMDA ,SMBus Default Address" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NACKEN ,Slave Receiver Data Phase NACK enable" "Normal,NACK"
|
|
endif
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TWIHS_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR ,Slave Address"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MASK ,Slave Address Mask"
|
|
bitfld.long 0x00 6. " SCLWSDIS ,Clock Wait State Disable" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SMHH ,SMBus Host Header" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SMDA ,SMBus Default Address" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NACKEN ,Slave Receiver Data Phase NACK enable" "Normal,NACK"
|
|
endif
|
|
else
|
|
sif (cpu()=="ATSAMG54")||(cpu()=="ATSAMG53")
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TWIHS_SMR,TWI Slave Mode Register"
|
|
bitfld.long 0x00 31. " DATAMEN ,Data Matching Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SADR3EN ,Slave Address 3 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SADR2EN ,Slave Address 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SADR1EN ,Slave Address 1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR ,Slave Address"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MASK ,Slave Address Mask"
|
|
bitfld.long 0x00 6. " SCLWSDIS ,Clock Wait State Disable" "No effect,Disabled"
|
|
textline " "
|
|
sif cpu()!="ATSAMG53"
|
|
bitfld.long 0x00 3. " SMHH ,SMBus Host Header" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SMDA ,SMBus Default Address" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NACKEN ,Slave Receiver Data Phase NACK enable" "Normal,NACK"
|
|
endif
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TWIHS_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR ,Slave Address"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MASK ,Slave Address Mask"
|
|
bitfld.long 0x00 6. " SCLWSDIS ,Clock Wait State Disable" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SMHH ,SMBus Host Header" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SMDA ,SMBus Default Address" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NACKEN ,Slave Receiver Data Phase NACK enable" "Normal,NACK"
|
|
endif
|
|
endif
|
|
if (((d.l((ad:0x40018000+0x4)))&0x300)==0x100)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWIHS_IADR,TWI Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x40018000+0x4)))&0x300)==0x200)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWIHS_IADR,TWI Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x40018000+0x4)))&0x300)==0x300)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWIHS_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IADR ,Internal Address"
|
|
else
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "TWIHS_IADR,TWI Internal Address Register"
|
|
endif
|
|
if (((d.l(ad:0x40018000+0xE4))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TWIHS_CWGR,TWI Clock Waveform Generator Register"
|
|
bitfld.long 0x00 24.--28. " HOLD ,TWD Hold Time Versus TWCK Falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " CKDIV ,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TWIHS_CWGR,TWI Clock Waveform Generator Register"
|
|
bitfld.long 0x00 24.--28. " HOLD ,TWD Hold Time Versus TWCK Falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " CKDIV ,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
endif
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TWIHS_SR,TWI Status Register(master mode)"
|
|
in
|
|
sif cpu()!="ATSAMG53"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TWIHS_SMBTR,TWI SMBus Timing Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " THMAX ,Clock High Maximum Cycles"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TLOWM ,Master Clock Stretch Maximum Cycles"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TLOWS ,Slave Clock Stretch Maximum Cycles"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PRESC ,SMBus Clock Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TWIHS_FILTR,TWI Filter Register"
|
|
bitfld.long 0x00 8.--10. " THRES ,Digital Filter Threshold" "Inactive,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PADFCFG ,PAD Filter Config" "0,1"
|
|
bitfld.long 0x00 1. " PADFEN ,PAD Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FILT ,RX Digital Filter" "Inactive,Active"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TWIHS_IMR,TWI Interrupt Mask Register"
|
|
sif cpu()!="ATSAMG53"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " SMBHHM ,SMBus Host Header Address Match Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " SMBDAM ,SMBus Default Address Match Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " PECERR ,PEC Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " TOUT ,Timeout Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " MCACK ,Master Code Acknowledge Interrupt Mask" "Masked,Not masked"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " TXBUFE ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " RXBUFF ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " ENDTX ,End of Transmit Buffer Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " ENDRX ,End of Receive Buffer Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " EOSACC ,End Of Slave Access Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. -0x08 11. -0x04 11. " SCL_WS ,Clock Wait State Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " ARBLST ,Arbitration Lost Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NACK ,Not Acknowledge Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " UNRE ,Underrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " OVRE ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " GACC ,General Call Access Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " SVACC ,Slave Access Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " TXRDY ,Transmit Holding Register Ready Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " RXRDY ,Receive Holding Register Ready Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " TXCOMP ,Transmission Completed Interrupt Mask" "Masked,Not masked"
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x04 "TWIHS_RHR,TWI Receive Holding Register"
|
|
in
|
|
sif (cpu()=="ATSAMG54")||(cpu()=="ATSAMG53")
|
|
if (((d.l(ad:0x40018000+0xE4))&0x01)==0x00)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TWIHS_SWMR,TWIHS SleepWalking Matching Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATAM ,Data Match"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR3 ,Slave Address 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " SADR2 ,Slave Address 2"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SADR1 ,Slave Address 1"
|
|
else
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "TWIHS_SWMR,TWIHS SleepWalking Matching Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATAM ,Data Match"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR3 ,Slave Address 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " SADR2 ,Slave Address 2"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SADR1 ,Slave Address 1"
|
|
endif
|
|
endif
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "TWIHS_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TWIHS_WPMR,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protection Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "TWIHS_WPSR,TWI Write Protection Status Register"
|
|
in
|
|
width 0xB
|
|
tree "TWIHS PDC (Peripheral DMA Controller)"
|
|
width 12.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "TWIHS_RPR,Receive Pointer Register"
|
|
line.long 0x04 "TWIHS_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "TWIHS_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "TWIHS_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "TWIHS_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "TWIHS_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "TWIHS_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "TWIHS_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "TWIHS_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "TWIHS_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="ATSAMG55")
|
|
tree.open "FLEXCOM (Flexible Serial Communication Controller)"
|
|
tree "FLEXCOM0"
|
|
base ad:0x4000C000
|
|
width 13.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FLEXCOM_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x00 0.--1. " OPMODE ,FLEXCOM Operating Mode" "NO_COM,USART,SPI,TWI"
|
|
textline " "
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FLEXCOM_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit Data"
|
|
textline " "
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FLEXCOM_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA ,Receive Data"
|
|
textline " "
|
|
width 0x0B
|
|
tree "FLEXCOM0 PDC (Peripheral DMA Controller)"
|
|
width 13.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "FLEXCOM_RPR,Receive Pointer Register"
|
|
line.long 0x04 "FLEXCOM_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "FLEXCOM_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "FLEXCOM_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "FLEXCOM_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "FLEXCOM_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "FLEXCOM_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "FLEXCOM_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "FLEXCOM_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "FLEXCOM_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "FLEXCOM1"
|
|
base ad:0x40020000
|
|
width 13.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FLEXCOM_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x00 0.--1. " OPMODE ,FLEXCOM Operating Mode" "NO_COM,USART,SPI,TWI"
|
|
textline " "
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FLEXCOM_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit Data"
|
|
textline " "
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FLEXCOM_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA ,Receive Data"
|
|
textline " "
|
|
width 0x0B
|
|
tree "FLEXCOM1 PDC (Peripheral DMA Controller)"
|
|
width 13.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "FLEXCOM_RPR,Receive Pointer Register"
|
|
line.long 0x04 "FLEXCOM_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "FLEXCOM_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "FLEXCOM_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "FLEXCOM_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "FLEXCOM_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "FLEXCOM_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "FLEXCOM_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "FLEXCOM_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "FLEXCOM_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "FLEXCOM2"
|
|
base ad:0x40024000
|
|
width 13.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FLEXCOM_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x00 0.--1. " OPMODE ,FLEXCOM Operating Mode" "NO_COM,USART,SPI,TWI"
|
|
textline " "
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FLEXCOM_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit Data"
|
|
textline " "
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FLEXCOM_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA ,Receive Data"
|
|
textline " "
|
|
width 0x0B
|
|
tree "FLEXCOM2 PDC (Peripheral DMA Controller)"
|
|
width 13.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "FLEXCOM_RPR,Receive Pointer Register"
|
|
line.long 0x04 "FLEXCOM_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "FLEXCOM_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "FLEXCOM_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "FLEXCOM_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "FLEXCOM_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "FLEXCOM_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "FLEXCOM_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "FLEXCOM_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "FLEXCOM_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "FLEXCOM3"
|
|
base ad:0x40018000
|
|
width 13.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FLEXCOM_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x00 0.--1. " OPMODE ,FLEXCOM Operating Mode" "NO_COM,USART,SPI,TWI"
|
|
textline " "
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FLEXCOM_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit Data"
|
|
textline " "
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FLEXCOM_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA ,Receive Data"
|
|
textline " "
|
|
width 0x0B
|
|
tree "FLEXCOM3 PDC (Peripheral DMA Controller)"
|
|
width 13.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "FLEXCOM_RPR,Receive Pointer Register"
|
|
line.long 0x04 "FLEXCOM_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "FLEXCOM_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "FLEXCOM_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "FLEXCOM_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "FLEXCOM_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "FLEXCOM_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "FLEXCOM_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "FLEXCOM_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "FLEXCOM_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "FLEXCOM4"
|
|
base ad:0x4001C000
|
|
width 13.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FLEXCOM_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x00 0.--1. " OPMODE ,FLEXCOM Operating Mode" "NO_COM,USART,SPI,TWI"
|
|
textline " "
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FLEXCOM_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit Data"
|
|
textline " "
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FLEXCOM_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA ,Receive Data"
|
|
textline " "
|
|
width 0x0B
|
|
tree "FLEXCOM4 PDC (Peripheral DMA Controller)"
|
|
width 13.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "FLEXCOM_RPR,Receive Pointer Register"
|
|
line.long 0x04 "FLEXCOM_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "FLEXCOM_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "FLEXCOM_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "FLEXCOM_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "FLEXCOM_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "FLEXCOM_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "FLEXCOM_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "FLEXCOM_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "FLEXCOM_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "FLEXCOM5"
|
|
base ad:0x40008000
|
|
width 13.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FLEXCOM_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x00 0.--1. " OPMODE ,FLEXCOM Operating Mode" "NO_COM,USART,SPI,TWI"
|
|
textline " "
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FLEXCOM_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit Data"
|
|
textline " "
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FLEXCOM_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA ,Receive Data"
|
|
textline " "
|
|
width 0x0B
|
|
tree "FLEXCOM5 PDC (Peripheral DMA Controller)"
|
|
width 13.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "FLEXCOM_RPR,Receive Pointer Register"
|
|
line.long 0x04 "FLEXCOM_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "FLEXCOM_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "FLEXCOM_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "FLEXCOM_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "FLEXCOM_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "FLEXCOM_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "FLEXCOM_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "FLEXCOM_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "FLEXCOM_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "FLEXCOM6"
|
|
base ad:0x40040000
|
|
width 13.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FLEXCOM_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x00 0.--1. " OPMODE ,FLEXCOM Operating Mode" "NO_COM,USART,SPI,TWI"
|
|
textline " "
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FLEXCOM_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit Data"
|
|
textline " "
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FLEXCOM_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA ,Receive Data"
|
|
textline " "
|
|
width 0x0B
|
|
tree "FLEXCOM6 PDC (Peripheral DMA Controller)"
|
|
width 13.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "FLEXCOM_RPR,Receive Pointer Register"
|
|
line.long 0x04 "FLEXCOM_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "FLEXCOM_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "FLEXCOM_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "FLEXCOM_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "FLEXCOM_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "FLEXCOM_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "FLEXCOM_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "FLEXCOM_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "FLEXCOM_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "FLEXCOM7"
|
|
base ad:0x40034000
|
|
width 13.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FLEXCOM_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x00 0.--1. " OPMODE ,FLEXCOM Operating Mode" "NO_COM,USART,SPI,TWI"
|
|
textline " "
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FLEXCOM_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit Data"
|
|
textline " "
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "FLEXCOM_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA ,Receive Data"
|
|
textline " "
|
|
width 0x0B
|
|
tree "FLEXCOM7 PDC (Peripheral DMA Controller)"
|
|
width 13.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "FLEXCOM_RPR,Receive Pointer Register"
|
|
line.long 0x04 "FLEXCOM_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "FLEXCOM_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "FLEXCOM_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "FLEXCOM_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "FLEXCOM_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "FLEXCOM_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "FLEXCOM_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "FLEXCOM_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "FLEXCOM_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree.open "TWI (Two-wire Interface)"
|
|
sif (cpu()=="ATSAMG55")
|
|
tree "TWI0"
|
|
base ad:0x4000C600
|
|
width 16.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TWI_CR,TWI Control Register"
|
|
sif cpuis("ATSAMG55")
|
|
bitfld.long 0x00 26. " LOCKCLR ,Lock Clear" "No effect,Clear"
|
|
bitfld.long 0x00 24. " THRCLR ,Transmit Holding Register Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ACMDIS ,Alternative Command Mode Disable" "No effect,Disable"
|
|
bitfld.long 0x00 16. " ACMEN ,Alternative Command Mode Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CLEAR ,Bus CLEAR Command" "No effect,Clear"
|
|
bitfld.long 0x00 14. " PECRQ ,PEC Request" "No effect,Request"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PECDIS ,Packet Error Checking Disable" "No effect,Disable"
|
|
bitfld.long 0x00 12. " PECEN ,Packet Error Checking Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SMBDIS ,SMBus Mode Disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 10. " SMBEN ,SMBus Mode Enabled" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " HSDIS ,TWI High-Speed Mode Disabled" "No effect,H-S Disabled"
|
|
bitfld.long 0x00 8. " HSEN ,TWI High-Speed Mode Enabled" "No effect,H-S Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
sif !cpuis("ATSAMG53")
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS Quick Command" "No effect,Sent"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " SVDIS ,TWI Slave Mode Disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " SVEN ,TWI Slave Mode Enabled" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSDIS ,TWI Master Transfer Disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 2. " MSEN ,TWI Master Transfer Enabled" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP Condition" "No effect,Sent"
|
|
bitfld.long 0x00 0. " START ,Send a START Condition" "No effect,Sent"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "None,1_Byte,2_Byte,3_Byte"
|
|
sif !cpuis("ATSAMG55")
|
|
if (((d.l((ad:0x4000C600+0xE4)))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave Address"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave Address"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0x4000C600+0xE4)))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
bitfld.long 0x00 31. " DATAMEN ,Data Matching Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SADR3EN ,Slave Address 3 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SADR2EN ,Slave Address 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SADR1EN ,Slave Address 1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave Address"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MASK ,Slave Address Mask"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCLWSDIS ,Clock Wait State Disable" "No,Yes"
|
|
bitfld.long 0x00 3. " SMHH ,SMBus Host Header" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SMDA ,SMBus Default Address" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NACKEN ,Slave Receiver Data Phase NACK Enable" "Normal,NACK"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
bitfld.long 0x00 31. " DATAMEN ,Data Matching Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SADR3EN ,Slave Address 3 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SADR2EN ,Slave Address 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SADR1EN ,Slave Address 1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 0x10000 " SADR ,Slave Address"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MASK ,Slave Address Mask"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCLWSDIS ,Clock Wait State Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 3. " SMHH ,SMBus Host Header" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SMDA ,SMBus Default Address" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NACKEN ,Slave Receiver Data Phase NACK Enable" "Normal,NACK"
|
|
endif
|
|
endif
|
|
if (((d.l((ad:0x4000C600+0x4)))&0x300)==0x300)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x4000C600+0x4)))&0x300)==0x200)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x4000C600+0x4)))&0x300)==0x100)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IADR ,Internal Address"
|
|
else
|
|
hgroup.long 0x0c++0x3
|
|
hide.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
endif
|
|
if (((d.l((ad:0x4000C600+0xE4)))&0x01)==0x00)
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
bitfld.long 0x0 24.--28. " HOLD ,TWD Hold Time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("ATSAMG55")
|
|
bitfld.long 0x0 20. " BRSRCCLK ,Bit Rate Source Clock" "Periph_clk,Pmc_pck"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " CKDIV ,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
else
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
bitfld.long 0x0 24.--28. " HOLD ,TWD Hold Time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("ATSAMG55")
|
|
bitfld.long 0x0 20. " BRSRCCLK ,Bit Rate Source Clock" "Periph_clk,Pmc_pck"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " CKDIV ,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
endif
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TWI_SR,TWI Status Register"
|
|
in
|
|
group.long 0x2c++0x03
|
|
line.long 0x0 "TWI_IMR,TWI Interrupt Mask Register"
|
|
sif cpuis("ATSAMG55")
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " SMBHHM_set/clr ,SMBus Host Header Address Match Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " SMBDAM_set/clr ,SMBus Default Address Match Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " PECERR_set/clr ,PEC Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " TOUT_set/clr ,Timeout Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " MCACK_set/clr ,Master Code Acknowledge Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " EOSACC_set/clr ,End Of Slave Access Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " SCL_WS_set/clr ,Clock Wait State Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " ABRLST_set/clr ,Arbitration Lost Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " NACK_set/clr ,Not Acknowledge" "Masked,Not masked"
|
|
textline " "
|
|
sif cpuis("ATSAMG55")
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " UNRE_set/clr ,Underrun Error" "Masked,Not masked"
|
|
endif
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " OVRE_set/clr ,Overrun Error" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " GACC_set/clr ,General Call Access Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " SVACC_set/clr ,Slave Access Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " TXRDY_set/clr ,Transmit Holding Register Ready" "Masked,Not masked"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " RXRDY_set/clr ,Receive Holding Register Ready" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " TXCOMP_set/clr ,Transmission Completed" "Masked,Not masked"
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x00 "TWI_RHR,TWI Receive Holding Register"
|
|
in
|
|
wgroup.long 0x34++0x3
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
sif cpuis("ATSAMG55")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TWI_SMBTR,TWI SMBus Timing Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " THMAX ,Clock High Maximum Cycles"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TLOWM ,Master Clock Stretch Maximum Cycles"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " TLOWS ,Slave Clock Stretch Maximum Cycles"
|
|
bitfld.long 0x00 0.--3. " PRESC ,SMBus Clock Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TWI_ACR,TWI Alternative Command Register"
|
|
bitfld.long 0x00 25. " NPEC ,NextPEC Request" "Not used,Used"
|
|
bitfld.long 0x00 24. " NDIR ,Next Transfer Direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " NDATAL ,Next Data Length"
|
|
bitfld.long 0x00 9. " PEC ,PEC Request" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIR ,Transfer Direction" "Write,Read"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATAL ,Data Length"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TWI_FILTR,TWI Filter Register"
|
|
bitfld.long 0x00 8.--10. " THRES ,Digital Filter Threshold" "No filtering,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PADFCFG ,PAD Filter Config" "No filtering,Filtering"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PADFEN ,PAD Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FILT ,RX Digital Filter" "No filtering,Filtering"
|
|
group.long 0x4C++0x3
|
|
line.long 0x00 "TWI_SWMR,TWI SleepWalking Matching Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATAM ,Data Match"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR3 ,Slave Address 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " SADR2 ,Slave Address 2"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SADR1 ,Slave Address 1"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TWI_WPROT_MODE,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protection Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "TWI_WPSR,TWI Write Protection Status Register"
|
|
in
|
|
width 0xB
|
|
tree "TWI0 PDC (Peripheral DMA Controller)"
|
|
width 11.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "TWI0_RPR,Receive Pointer Register"
|
|
line.long 0x04 "TWI0_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "TWI0_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "TWI0_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "TWI0_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "TWI0_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "TWI0_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "TWI0_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "TWI0_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "TWI0_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "TWI1"
|
|
base ad:0x40020600
|
|
width 16.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TWI_CR,TWI Control Register"
|
|
sif cpuis("ATSAMG55")
|
|
bitfld.long 0x00 26. " LOCKCLR ,Lock Clear" "No effect,Clear"
|
|
bitfld.long 0x00 24. " THRCLR ,Transmit Holding Register Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ACMDIS ,Alternative Command Mode Disable" "No effect,Disable"
|
|
bitfld.long 0x00 16. " ACMEN ,Alternative Command Mode Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CLEAR ,Bus CLEAR Command" "No effect,Clear"
|
|
bitfld.long 0x00 14. " PECRQ ,PEC Request" "No effect,Request"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PECDIS ,Packet Error Checking Disable" "No effect,Disable"
|
|
bitfld.long 0x00 12. " PECEN ,Packet Error Checking Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SMBDIS ,SMBus Mode Disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 10. " SMBEN ,SMBus Mode Enabled" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " HSDIS ,TWI High-Speed Mode Disabled" "No effect,H-S Disabled"
|
|
bitfld.long 0x00 8. " HSEN ,TWI High-Speed Mode Enabled" "No effect,H-S Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
sif !cpuis("ATSAMG53")
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS Quick Command" "No effect,Sent"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " SVDIS ,TWI Slave Mode Disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " SVEN ,TWI Slave Mode Enabled" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSDIS ,TWI Master Transfer Disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 2. " MSEN ,TWI Master Transfer Enabled" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP Condition" "No effect,Sent"
|
|
bitfld.long 0x00 0. " START ,Send a START Condition" "No effect,Sent"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "None,1_Byte,2_Byte,3_Byte"
|
|
sif !cpuis("ATSAMG55")
|
|
if (((d.l((ad:0x40020600+0xE4)))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave Address"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave Address"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0x40020600+0xE4)))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
bitfld.long 0x00 31. " DATAMEN ,Data Matching Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SADR3EN ,Slave Address 3 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SADR2EN ,Slave Address 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SADR1EN ,Slave Address 1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave Address"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MASK ,Slave Address Mask"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCLWSDIS ,Clock Wait State Disable" "No,Yes"
|
|
bitfld.long 0x00 3. " SMHH ,SMBus Host Header" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SMDA ,SMBus Default Address" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NACKEN ,Slave Receiver Data Phase NACK Enable" "Normal,NACK"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
bitfld.long 0x00 31. " DATAMEN ,Data Matching Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SADR3EN ,Slave Address 3 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SADR2EN ,Slave Address 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SADR1EN ,Slave Address 1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 0x10000 " SADR ,Slave Address"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MASK ,Slave Address Mask"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCLWSDIS ,Clock Wait State Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 3. " SMHH ,SMBus Host Header" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SMDA ,SMBus Default Address" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NACKEN ,Slave Receiver Data Phase NACK Enable" "Normal,NACK"
|
|
endif
|
|
endif
|
|
if (((d.l((ad:0x40020600+0x4)))&0x300)==0x300)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x40020600+0x4)))&0x300)==0x200)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x40020600+0x4)))&0x300)==0x100)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IADR ,Internal Address"
|
|
else
|
|
hgroup.long 0x0c++0x3
|
|
hide.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
endif
|
|
if (((d.l((ad:0x40020600+0xE4)))&0x01)==0x00)
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
bitfld.long 0x0 24.--28. " HOLD ,TWD Hold Time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("ATSAMG55")
|
|
bitfld.long 0x0 20. " BRSRCCLK ,Bit Rate Source Clock" "Periph_clk,Pmc_pck"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " CKDIV ,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
else
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
bitfld.long 0x0 24.--28. " HOLD ,TWD Hold Time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("ATSAMG55")
|
|
bitfld.long 0x0 20. " BRSRCCLK ,Bit Rate Source Clock" "Periph_clk,Pmc_pck"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " CKDIV ,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
endif
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TWI_SR,TWI Status Register"
|
|
in
|
|
group.long 0x2c++0x03
|
|
line.long 0x0 "TWI_IMR,TWI Interrupt Mask Register"
|
|
sif cpuis("ATSAMG55")
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " SMBHHM_set/clr ,SMBus Host Header Address Match Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " SMBDAM_set/clr ,SMBus Default Address Match Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " PECERR_set/clr ,PEC Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " TOUT_set/clr ,Timeout Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " MCACK_set/clr ,Master Code Acknowledge Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " EOSACC_set/clr ,End Of Slave Access Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " SCL_WS_set/clr ,Clock Wait State Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " ABRLST_set/clr ,Arbitration Lost Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " NACK_set/clr ,Not Acknowledge" "Masked,Not masked"
|
|
textline " "
|
|
sif cpuis("ATSAMG55")
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " UNRE_set/clr ,Underrun Error" "Masked,Not masked"
|
|
endif
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " OVRE_set/clr ,Overrun Error" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " GACC_set/clr ,General Call Access Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " SVACC_set/clr ,Slave Access Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " TXRDY_set/clr ,Transmit Holding Register Ready" "Masked,Not masked"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " RXRDY_set/clr ,Receive Holding Register Ready" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " TXCOMP_set/clr ,Transmission Completed" "Masked,Not masked"
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x00 "TWI_RHR,TWI Receive Holding Register"
|
|
in
|
|
wgroup.long 0x34++0x3
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
sif cpuis("ATSAMG55")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TWI_SMBTR,TWI SMBus Timing Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " THMAX ,Clock High Maximum Cycles"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TLOWM ,Master Clock Stretch Maximum Cycles"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " TLOWS ,Slave Clock Stretch Maximum Cycles"
|
|
bitfld.long 0x00 0.--3. " PRESC ,SMBus Clock Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TWI_ACR,TWI Alternative Command Register"
|
|
bitfld.long 0x00 25. " NPEC ,NextPEC Request" "Not used,Used"
|
|
bitfld.long 0x00 24. " NDIR ,Next Transfer Direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " NDATAL ,Next Data Length"
|
|
bitfld.long 0x00 9. " PEC ,PEC Request" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIR ,Transfer Direction" "Write,Read"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATAL ,Data Length"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TWI_FILTR,TWI Filter Register"
|
|
bitfld.long 0x00 8.--10. " THRES ,Digital Filter Threshold" "No filtering,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PADFCFG ,PAD Filter Config" "No filtering,Filtering"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PADFEN ,PAD Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FILT ,RX Digital Filter" "No filtering,Filtering"
|
|
group.long 0x4C++0x3
|
|
line.long 0x00 "TWI_SWMR,TWI SleepWalking Matching Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATAM ,Data Match"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR3 ,Slave Address 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " SADR2 ,Slave Address 2"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SADR1 ,Slave Address 1"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TWI_WPROT_MODE,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protection Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "TWI_WPSR,TWI Write Protection Status Register"
|
|
in
|
|
width 0xB
|
|
tree "TWI1 PDC (Peripheral DMA Controller)"
|
|
width 11.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "TWI1_RPR,Receive Pointer Register"
|
|
line.long 0x04 "TWI1_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "TWI1_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "TWI1_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "TWI1_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "TWI1_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "TWI1_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "TWI1_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "TWI1_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "TWI1_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "TWI2"
|
|
base ad:0x40024600
|
|
width 16.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TWI_CR,TWI Control Register"
|
|
sif cpuis("ATSAMG55")
|
|
bitfld.long 0x00 26. " LOCKCLR ,Lock Clear" "No effect,Clear"
|
|
bitfld.long 0x00 24. " THRCLR ,Transmit Holding Register Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ACMDIS ,Alternative Command Mode Disable" "No effect,Disable"
|
|
bitfld.long 0x00 16. " ACMEN ,Alternative Command Mode Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CLEAR ,Bus CLEAR Command" "No effect,Clear"
|
|
bitfld.long 0x00 14. " PECRQ ,PEC Request" "No effect,Request"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PECDIS ,Packet Error Checking Disable" "No effect,Disable"
|
|
bitfld.long 0x00 12. " PECEN ,Packet Error Checking Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SMBDIS ,SMBus Mode Disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 10. " SMBEN ,SMBus Mode Enabled" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " HSDIS ,TWI High-Speed Mode Disabled" "No effect,H-S Disabled"
|
|
bitfld.long 0x00 8. " HSEN ,TWI High-Speed Mode Enabled" "No effect,H-S Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
sif !cpuis("ATSAMG53")
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS Quick Command" "No effect,Sent"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " SVDIS ,TWI Slave Mode Disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " SVEN ,TWI Slave Mode Enabled" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSDIS ,TWI Master Transfer Disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 2. " MSEN ,TWI Master Transfer Enabled" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP Condition" "No effect,Sent"
|
|
bitfld.long 0x00 0. " START ,Send a START Condition" "No effect,Sent"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "None,1_Byte,2_Byte,3_Byte"
|
|
sif !cpuis("ATSAMG55")
|
|
if (((d.l((ad:0x40024600+0xE4)))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave Address"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave Address"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0x40024600+0xE4)))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
bitfld.long 0x00 31. " DATAMEN ,Data Matching Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SADR3EN ,Slave Address 3 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SADR2EN ,Slave Address 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SADR1EN ,Slave Address 1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave Address"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MASK ,Slave Address Mask"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCLWSDIS ,Clock Wait State Disable" "No,Yes"
|
|
bitfld.long 0x00 3. " SMHH ,SMBus Host Header" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SMDA ,SMBus Default Address" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NACKEN ,Slave Receiver Data Phase NACK Enable" "Normal,NACK"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
bitfld.long 0x00 31. " DATAMEN ,Data Matching Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SADR3EN ,Slave Address 3 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SADR2EN ,Slave Address 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SADR1EN ,Slave Address 1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 0x10000 " SADR ,Slave Address"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MASK ,Slave Address Mask"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCLWSDIS ,Clock Wait State Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 3. " SMHH ,SMBus Host Header" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SMDA ,SMBus Default Address" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NACKEN ,Slave Receiver Data Phase NACK Enable" "Normal,NACK"
|
|
endif
|
|
endif
|
|
if (((d.l((ad:0x40024600+0x4)))&0x300)==0x300)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x40024600+0x4)))&0x300)==0x200)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x40024600+0x4)))&0x300)==0x100)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IADR ,Internal Address"
|
|
else
|
|
hgroup.long 0x0c++0x3
|
|
hide.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
endif
|
|
if (((d.l((ad:0x40024600+0xE4)))&0x01)==0x00)
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
bitfld.long 0x0 24.--28. " HOLD ,TWD Hold Time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("ATSAMG55")
|
|
bitfld.long 0x0 20. " BRSRCCLK ,Bit Rate Source Clock" "Periph_clk,Pmc_pck"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " CKDIV ,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
else
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
bitfld.long 0x0 24.--28. " HOLD ,TWD Hold Time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("ATSAMG55")
|
|
bitfld.long 0x0 20. " BRSRCCLK ,Bit Rate Source Clock" "Periph_clk,Pmc_pck"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " CKDIV ,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
endif
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TWI_SR,TWI Status Register"
|
|
in
|
|
group.long 0x2c++0x03
|
|
line.long 0x0 "TWI_IMR,TWI Interrupt Mask Register"
|
|
sif cpuis("ATSAMG55")
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " SMBHHM_set/clr ,SMBus Host Header Address Match Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " SMBDAM_set/clr ,SMBus Default Address Match Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " PECERR_set/clr ,PEC Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " TOUT_set/clr ,Timeout Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " MCACK_set/clr ,Master Code Acknowledge Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " EOSACC_set/clr ,End Of Slave Access Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " SCL_WS_set/clr ,Clock Wait State Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " ABRLST_set/clr ,Arbitration Lost Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " NACK_set/clr ,Not Acknowledge" "Masked,Not masked"
|
|
textline " "
|
|
sif cpuis("ATSAMG55")
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " UNRE_set/clr ,Underrun Error" "Masked,Not masked"
|
|
endif
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " OVRE_set/clr ,Overrun Error" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " GACC_set/clr ,General Call Access Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " SVACC_set/clr ,Slave Access Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " TXRDY_set/clr ,Transmit Holding Register Ready" "Masked,Not masked"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " RXRDY_set/clr ,Receive Holding Register Ready" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " TXCOMP_set/clr ,Transmission Completed" "Masked,Not masked"
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x00 "TWI_RHR,TWI Receive Holding Register"
|
|
in
|
|
wgroup.long 0x34++0x3
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
sif cpuis("ATSAMG55")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TWI_SMBTR,TWI SMBus Timing Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " THMAX ,Clock High Maximum Cycles"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TLOWM ,Master Clock Stretch Maximum Cycles"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " TLOWS ,Slave Clock Stretch Maximum Cycles"
|
|
bitfld.long 0x00 0.--3. " PRESC ,SMBus Clock Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TWI_ACR,TWI Alternative Command Register"
|
|
bitfld.long 0x00 25. " NPEC ,NextPEC Request" "Not used,Used"
|
|
bitfld.long 0x00 24. " NDIR ,Next Transfer Direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " NDATAL ,Next Data Length"
|
|
bitfld.long 0x00 9. " PEC ,PEC Request" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIR ,Transfer Direction" "Write,Read"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATAL ,Data Length"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TWI_FILTR,TWI Filter Register"
|
|
bitfld.long 0x00 8.--10. " THRES ,Digital Filter Threshold" "No filtering,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PADFCFG ,PAD Filter Config" "No filtering,Filtering"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PADFEN ,PAD Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FILT ,RX Digital Filter" "No filtering,Filtering"
|
|
group.long 0x4C++0x3
|
|
line.long 0x00 "TWI_SWMR,TWI SleepWalking Matching Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATAM ,Data Match"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR3 ,Slave Address 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " SADR2 ,Slave Address 2"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SADR1 ,Slave Address 1"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TWI_WPROT_MODE,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protection Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "TWI_WPSR,TWI Write Protection Status Register"
|
|
in
|
|
width 0xB
|
|
tree "TWI2 PDC (Peripheral DMA Controller)"
|
|
width 11.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "TWI2_RPR,Receive Pointer Register"
|
|
line.long 0x04 "TWI2_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "TWI2_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "TWI2_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "TWI2_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "TWI2_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "TWI2_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "TWI2_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "TWI2_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "TWI2_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "TWI3"
|
|
base ad:0x40018600
|
|
width 16.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TWI_CR,TWI Control Register"
|
|
sif cpuis("ATSAMG55")
|
|
bitfld.long 0x00 26. " LOCKCLR ,Lock Clear" "No effect,Clear"
|
|
bitfld.long 0x00 24. " THRCLR ,Transmit Holding Register Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ACMDIS ,Alternative Command Mode Disable" "No effect,Disable"
|
|
bitfld.long 0x00 16. " ACMEN ,Alternative Command Mode Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CLEAR ,Bus CLEAR Command" "No effect,Clear"
|
|
bitfld.long 0x00 14. " PECRQ ,PEC Request" "No effect,Request"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PECDIS ,Packet Error Checking Disable" "No effect,Disable"
|
|
bitfld.long 0x00 12. " PECEN ,Packet Error Checking Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SMBDIS ,SMBus Mode Disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 10. " SMBEN ,SMBus Mode Enabled" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " HSDIS ,TWI High-Speed Mode Disabled" "No effect,H-S Disabled"
|
|
bitfld.long 0x00 8. " HSEN ,TWI High-Speed Mode Enabled" "No effect,H-S Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
sif !cpuis("ATSAMG53")
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS Quick Command" "No effect,Sent"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " SVDIS ,TWI Slave Mode Disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " SVEN ,TWI Slave Mode Enabled" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSDIS ,TWI Master Transfer Disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 2. " MSEN ,TWI Master Transfer Enabled" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP Condition" "No effect,Sent"
|
|
bitfld.long 0x00 0. " START ,Send a START Condition" "No effect,Sent"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "None,1_Byte,2_Byte,3_Byte"
|
|
sif !cpuis("ATSAMG55")
|
|
if (((d.l((ad:0x40018600+0xE4)))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave Address"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave Address"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0x40018600+0xE4)))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
bitfld.long 0x00 31. " DATAMEN ,Data Matching Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SADR3EN ,Slave Address 3 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SADR2EN ,Slave Address 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SADR1EN ,Slave Address 1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave Address"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MASK ,Slave Address Mask"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCLWSDIS ,Clock Wait State Disable" "No,Yes"
|
|
bitfld.long 0x00 3. " SMHH ,SMBus Host Header" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SMDA ,SMBus Default Address" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NACKEN ,Slave Receiver Data Phase NACK Enable" "Normal,NACK"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
bitfld.long 0x00 31. " DATAMEN ,Data Matching Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SADR3EN ,Slave Address 3 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SADR2EN ,Slave Address 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SADR1EN ,Slave Address 1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 0x10000 " SADR ,Slave Address"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MASK ,Slave Address Mask"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCLWSDIS ,Clock Wait State Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 3. " SMHH ,SMBus Host Header" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SMDA ,SMBus Default Address" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NACKEN ,Slave Receiver Data Phase NACK Enable" "Normal,NACK"
|
|
endif
|
|
endif
|
|
if (((d.l((ad:0x40018600+0x4)))&0x300)==0x300)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x40018600+0x4)))&0x300)==0x200)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x40018600+0x4)))&0x300)==0x100)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IADR ,Internal Address"
|
|
else
|
|
hgroup.long 0x0c++0x3
|
|
hide.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
endif
|
|
if (((d.l((ad:0x40018600+0xE4)))&0x01)==0x00)
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
bitfld.long 0x0 24.--28. " HOLD ,TWD Hold Time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("ATSAMG55")
|
|
bitfld.long 0x0 20. " BRSRCCLK ,Bit Rate Source Clock" "Periph_clk,Pmc_pck"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " CKDIV ,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
else
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
bitfld.long 0x0 24.--28. " HOLD ,TWD Hold Time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("ATSAMG55")
|
|
bitfld.long 0x0 20. " BRSRCCLK ,Bit Rate Source Clock" "Periph_clk,Pmc_pck"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " CKDIV ,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
endif
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TWI_SR,TWI Status Register"
|
|
in
|
|
group.long 0x2c++0x03
|
|
line.long 0x0 "TWI_IMR,TWI Interrupt Mask Register"
|
|
sif cpuis("ATSAMG55")
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " SMBHHM_set/clr ,SMBus Host Header Address Match Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " SMBDAM_set/clr ,SMBus Default Address Match Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " PECERR_set/clr ,PEC Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " TOUT_set/clr ,Timeout Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " MCACK_set/clr ,Master Code Acknowledge Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " EOSACC_set/clr ,End Of Slave Access Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " SCL_WS_set/clr ,Clock Wait State Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " ABRLST_set/clr ,Arbitration Lost Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " NACK_set/clr ,Not Acknowledge" "Masked,Not masked"
|
|
textline " "
|
|
sif cpuis("ATSAMG55")
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " UNRE_set/clr ,Underrun Error" "Masked,Not masked"
|
|
endif
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " OVRE_set/clr ,Overrun Error" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " GACC_set/clr ,General Call Access Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " SVACC_set/clr ,Slave Access Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " TXRDY_set/clr ,Transmit Holding Register Ready" "Masked,Not masked"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " RXRDY_set/clr ,Receive Holding Register Ready" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " TXCOMP_set/clr ,Transmission Completed" "Masked,Not masked"
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x00 "TWI_RHR,TWI Receive Holding Register"
|
|
in
|
|
wgroup.long 0x34++0x3
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
sif cpuis("ATSAMG55")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TWI_SMBTR,TWI SMBus Timing Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " THMAX ,Clock High Maximum Cycles"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TLOWM ,Master Clock Stretch Maximum Cycles"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " TLOWS ,Slave Clock Stretch Maximum Cycles"
|
|
bitfld.long 0x00 0.--3. " PRESC ,SMBus Clock Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TWI_ACR,TWI Alternative Command Register"
|
|
bitfld.long 0x00 25. " NPEC ,NextPEC Request" "Not used,Used"
|
|
bitfld.long 0x00 24. " NDIR ,Next Transfer Direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " NDATAL ,Next Data Length"
|
|
bitfld.long 0x00 9. " PEC ,PEC Request" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIR ,Transfer Direction" "Write,Read"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATAL ,Data Length"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TWI_FILTR,TWI Filter Register"
|
|
bitfld.long 0x00 8.--10. " THRES ,Digital Filter Threshold" "No filtering,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PADFCFG ,PAD Filter Config" "No filtering,Filtering"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PADFEN ,PAD Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FILT ,RX Digital Filter" "No filtering,Filtering"
|
|
group.long 0x4C++0x3
|
|
line.long 0x00 "TWI_SWMR,TWI SleepWalking Matching Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATAM ,Data Match"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR3 ,Slave Address 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " SADR2 ,Slave Address 2"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SADR1 ,Slave Address 1"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TWI_WPROT_MODE,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protection Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "TWI_WPSR,TWI Write Protection Status Register"
|
|
in
|
|
width 0xB
|
|
tree "TWI3 PDC (Peripheral DMA Controller)"
|
|
width 11.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "TWI3_RPR,Receive Pointer Register"
|
|
line.long 0x04 "TWI3_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "TWI3_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "TWI3_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "TWI3_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "TWI3_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "TWI3_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "TWI3_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "TWI3_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "TWI3_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "TWI4"
|
|
base ad:0x4001C600
|
|
width 16.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TWI_CR,TWI Control Register"
|
|
sif cpuis("ATSAMG55")
|
|
bitfld.long 0x00 26. " LOCKCLR ,Lock Clear" "No effect,Clear"
|
|
bitfld.long 0x00 24. " THRCLR ,Transmit Holding Register Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ACMDIS ,Alternative Command Mode Disable" "No effect,Disable"
|
|
bitfld.long 0x00 16. " ACMEN ,Alternative Command Mode Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CLEAR ,Bus CLEAR Command" "No effect,Clear"
|
|
bitfld.long 0x00 14. " PECRQ ,PEC Request" "No effect,Request"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PECDIS ,Packet Error Checking Disable" "No effect,Disable"
|
|
bitfld.long 0x00 12. " PECEN ,Packet Error Checking Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SMBDIS ,SMBus Mode Disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 10. " SMBEN ,SMBus Mode Enabled" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " HSDIS ,TWI High-Speed Mode Disabled" "No effect,H-S Disabled"
|
|
bitfld.long 0x00 8. " HSEN ,TWI High-Speed Mode Enabled" "No effect,H-S Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
sif !cpuis("ATSAMG53")
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS Quick Command" "No effect,Sent"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " SVDIS ,TWI Slave Mode Disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " SVEN ,TWI Slave Mode Enabled" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSDIS ,TWI Master Transfer Disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 2. " MSEN ,TWI Master Transfer Enabled" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP Condition" "No effect,Sent"
|
|
bitfld.long 0x00 0. " START ,Send a START Condition" "No effect,Sent"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "None,1_Byte,2_Byte,3_Byte"
|
|
sif !cpuis("ATSAMG55")
|
|
if (((d.l((ad:0x4001C600+0xE4)))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave Address"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave Address"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0x4001C600+0xE4)))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
bitfld.long 0x00 31. " DATAMEN ,Data Matching Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SADR3EN ,Slave Address 3 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SADR2EN ,Slave Address 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SADR1EN ,Slave Address 1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave Address"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MASK ,Slave Address Mask"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCLWSDIS ,Clock Wait State Disable" "No,Yes"
|
|
bitfld.long 0x00 3. " SMHH ,SMBus Host Header" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SMDA ,SMBus Default Address" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NACKEN ,Slave Receiver Data Phase NACK Enable" "Normal,NACK"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
bitfld.long 0x00 31. " DATAMEN ,Data Matching Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SADR3EN ,Slave Address 3 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SADR2EN ,Slave Address 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SADR1EN ,Slave Address 1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 0x10000 " SADR ,Slave Address"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MASK ,Slave Address Mask"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCLWSDIS ,Clock Wait State Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 3. " SMHH ,SMBus Host Header" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SMDA ,SMBus Default Address" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NACKEN ,Slave Receiver Data Phase NACK Enable" "Normal,NACK"
|
|
endif
|
|
endif
|
|
if (((d.l((ad:0x4001C600+0x4)))&0x300)==0x300)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x4001C600+0x4)))&0x300)==0x200)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x4001C600+0x4)))&0x300)==0x100)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IADR ,Internal Address"
|
|
else
|
|
hgroup.long 0x0c++0x3
|
|
hide.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
endif
|
|
if (((d.l((ad:0x4001C600+0xE4)))&0x01)==0x00)
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
bitfld.long 0x0 24.--28. " HOLD ,TWD Hold Time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("ATSAMG55")
|
|
bitfld.long 0x0 20. " BRSRCCLK ,Bit Rate Source Clock" "Periph_clk,Pmc_pck"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " CKDIV ,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
else
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
bitfld.long 0x0 24.--28. " HOLD ,TWD Hold Time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("ATSAMG55")
|
|
bitfld.long 0x0 20. " BRSRCCLK ,Bit Rate Source Clock" "Periph_clk,Pmc_pck"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " CKDIV ,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
endif
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TWI_SR,TWI Status Register"
|
|
in
|
|
group.long 0x2c++0x03
|
|
line.long 0x0 "TWI_IMR,TWI Interrupt Mask Register"
|
|
sif cpuis("ATSAMG55")
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " SMBHHM_set/clr ,SMBus Host Header Address Match Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " SMBDAM_set/clr ,SMBus Default Address Match Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " PECERR_set/clr ,PEC Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " TOUT_set/clr ,Timeout Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " MCACK_set/clr ,Master Code Acknowledge Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " EOSACC_set/clr ,End Of Slave Access Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " SCL_WS_set/clr ,Clock Wait State Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " ABRLST_set/clr ,Arbitration Lost Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " NACK_set/clr ,Not Acknowledge" "Masked,Not masked"
|
|
textline " "
|
|
sif cpuis("ATSAMG55")
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " UNRE_set/clr ,Underrun Error" "Masked,Not masked"
|
|
endif
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " OVRE_set/clr ,Overrun Error" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " GACC_set/clr ,General Call Access Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " SVACC_set/clr ,Slave Access Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " TXRDY_set/clr ,Transmit Holding Register Ready" "Masked,Not masked"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " RXRDY_set/clr ,Receive Holding Register Ready" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " TXCOMP_set/clr ,Transmission Completed" "Masked,Not masked"
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x00 "TWI_RHR,TWI Receive Holding Register"
|
|
in
|
|
wgroup.long 0x34++0x3
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
sif cpuis("ATSAMG55")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TWI_SMBTR,TWI SMBus Timing Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " THMAX ,Clock High Maximum Cycles"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TLOWM ,Master Clock Stretch Maximum Cycles"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " TLOWS ,Slave Clock Stretch Maximum Cycles"
|
|
bitfld.long 0x00 0.--3. " PRESC ,SMBus Clock Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TWI_ACR,TWI Alternative Command Register"
|
|
bitfld.long 0x00 25. " NPEC ,NextPEC Request" "Not used,Used"
|
|
bitfld.long 0x00 24. " NDIR ,Next Transfer Direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " NDATAL ,Next Data Length"
|
|
bitfld.long 0x00 9. " PEC ,PEC Request" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIR ,Transfer Direction" "Write,Read"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATAL ,Data Length"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TWI_FILTR,TWI Filter Register"
|
|
bitfld.long 0x00 8.--10. " THRES ,Digital Filter Threshold" "No filtering,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PADFCFG ,PAD Filter Config" "No filtering,Filtering"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PADFEN ,PAD Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FILT ,RX Digital Filter" "No filtering,Filtering"
|
|
group.long 0x4C++0x3
|
|
line.long 0x00 "TWI_SWMR,TWI SleepWalking Matching Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATAM ,Data Match"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR3 ,Slave Address 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " SADR2 ,Slave Address 2"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SADR1 ,Slave Address 1"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TWI_WPROT_MODE,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protection Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "TWI_WPSR,TWI Write Protection Status Register"
|
|
in
|
|
width 0xB
|
|
tree "TWI4 PDC (Peripheral DMA Controller)"
|
|
width 11.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "TWI4_RPR,Receive Pointer Register"
|
|
line.long 0x04 "TWI4_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "TWI4_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "TWI4_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "TWI4_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "TWI4_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "TWI4_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "TWI4_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "TWI4_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "TWI4_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "TWI5"
|
|
base ad:0x40008600
|
|
width 16.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TWI_CR,TWI Control Register"
|
|
sif cpuis("ATSAMG55")
|
|
bitfld.long 0x00 26. " LOCKCLR ,Lock Clear" "No effect,Clear"
|
|
bitfld.long 0x00 24. " THRCLR ,Transmit Holding Register Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ACMDIS ,Alternative Command Mode Disable" "No effect,Disable"
|
|
bitfld.long 0x00 16. " ACMEN ,Alternative Command Mode Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CLEAR ,Bus CLEAR Command" "No effect,Clear"
|
|
bitfld.long 0x00 14. " PECRQ ,PEC Request" "No effect,Request"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PECDIS ,Packet Error Checking Disable" "No effect,Disable"
|
|
bitfld.long 0x00 12. " PECEN ,Packet Error Checking Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SMBDIS ,SMBus Mode Disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 10. " SMBEN ,SMBus Mode Enabled" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " HSDIS ,TWI High-Speed Mode Disabled" "No effect,H-S Disabled"
|
|
bitfld.long 0x00 8. " HSEN ,TWI High-Speed Mode Enabled" "No effect,H-S Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
sif !cpuis("ATSAMG53")
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS Quick Command" "No effect,Sent"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " SVDIS ,TWI Slave Mode Disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " SVEN ,TWI Slave Mode Enabled" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSDIS ,TWI Master Transfer Disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 2. " MSEN ,TWI Master Transfer Enabled" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP Condition" "No effect,Sent"
|
|
bitfld.long 0x00 0. " START ,Send a START Condition" "No effect,Sent"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "None,1_Byte,2_Byte,3_Byte"
|
|
sif !cpuis("ATSAMG55")
|
|
if (((d.l((ad:0x40008600+0xE4)))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave Address"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave Address"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0x40008600+0xE4)))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
bitfld.long 0x00 31. " DATAMEN ,Data Matching Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SADR3EN ,Slave Address 3 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SADR2EN ,Slave Address 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SADR1EN ,Slave Address 1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave Address"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MASK ,Slave Address Mask"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCLWSDIS ,Clock Wait State Disable" "No,Yes"
|
|
bitfld.long 0x00 3. " SMHH ,SMBus Host Header" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SMDA ,SMBus Default Address" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NACKEN ,Slave Receiver Data Phase NACK Enable" "Normal,NACK"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
bitfld.long 0x00 31. " DATAMEN ,Data Matching Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SADR3EN ,Slave Address 3 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SADR2EN ,Slave Address 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SADR1EN ,Slave Address 1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 0x10000 " SADR ,Slave Address"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MASK ,Slave Address Mask"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCLWSDIS ,Clock Wait State Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 3. " SMHH ,SMBus Host Header" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SMDA ,SMBus Default Address" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NACKEN ,Slave Receiver Data Phase NACK Enable" "Normal,NACK"
|
|
endif
|
|
endif
|
|
if (((d.l((ad:0x40008600+0x4)))&0x300)==0x300)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x40008600+0x4)))&0x300)==0x200)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x40008600+0x4)))&0x300)==0x100)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IADR ,Internal Address"
|
|
else
|
|
hgroup.long 0x0c++0x3
|
|
hide.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
endif
|
|
if (((d.l((ad:0x40008600+0xE4)))&0x01)==0x00)
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
bitfld.long 0x0 24.--28. " HOLD ,TWD Hold Time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("ATSAMG55")
|
|
bitfld.long 0x0 20. " BRSRCCLK ,Bit Rate Source Clock" "Periph_clk,Pmc_pck"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " CKDIV ,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
else
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
bitfld.long 0x0 24.--28. " HOLD ,TWD Hold Time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("ATSAMG55")
|
|
bitfld.long 0x0 20. " BRSRCCLK ,Bit Rate Source Clock" "Periph_clk,Pmc_pck"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " CKDIV ,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
endif
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TWI_SR,TWI Status Register"
|
|
in
|
|
group.long 0x2c++0x03
|
|
line.long 0x0 "TWI_IMR,TWI Interrupt Mask Register"
|
|
sif cpuis("ATSAMG55")
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " SMBHHM_set/clr ,SMBus Host Header Address Match Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " SMBDAM_set/clr ,SMBus Default Address Match Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " PECERR_set/clr ,PEC Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " TOUT_set/clr ,Timeout Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " MCACK_set/clr ,Master Code Acknowledge Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " EOSACC_set/clr ,End Of Slave Access Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " SCL_WS_set/clr ,Clock Wait State Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " ABRLST_set/clr ,Arbitration Lost Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " NACK_set/clr ,Not Acknowledge" "Masked,Not masked"
|
|
textline " "
|
|
sif cpuis("ATSAMG55")
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " UNRE_set/clr ,Underrun Error" "Masked,Not masked"
|
|
endif
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " OVRE_set/clr ,Overrun Error" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " GACC_set/clr ,General Call Access Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " SVACC_set/clr ,Slave Access Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " TXRDY_set/clr ,Transmit Holding Register Ready" "Masked,Not masked"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " RXRDY_set/clr ,Receive Holding Register Ready" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " TXCOMP_set/clr ,Transmission Completed" "Masked,Not masked"
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x00 "TWI_RHR,TWI Receive Holding Register"
|
|
in
|
|
wgroup.long 0x34++0x3
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
sif cpuis("ATSAMG55")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TWI_SMBTR,TWI SMBus Timing Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " THMAX ,Clock High Maximum Cycles"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TLOWM ,Master Clock Stretch Maximum Cycles"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " TLOWS ,Slave Clock Stretch Maximum Cycles"
|
|
bitfld.long 0x00 0.--3. " PRESC ,SMBus Clock Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TWI_ACR,TWI Alternative Command Register"
|
|
bitfld.long 0x00 25. " NPEC ,NextPEC Request" "Not used,Used"
|
|
bitfld.long 0x00 24. " NDIR ,Next Transfer Direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " NDATAL ,Next Data Length"
|
|
bitfld.long 0x00 9. " PEC ,PEC Request" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIR ,Transfer Direction" "Write,Read"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATAL ,Data Length"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TWI_FILTR,TWI Filter Register"
|
|
bitfld.long 0x00 8.--10. " THRES ,Digital Filter Threshold" "No filtering,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PADFCFG ,PAD Filter Config" "No filtering,Filtering"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PADFEN ,PAD Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FILT ,RX Digital Filter" "No filtering,Filtering"
|
|
group.long 0x4C++0x3
|
|
line.long 0x00 "TWI_SWMR,TWI SleepWalking Matching Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATAM ,Data Match"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR3 ,Slave Address 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " SADR2 ,Slave Address 2"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SADR1 ,Slave Address 1"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TWI_WPROT_MODE,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protection Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "TWI_WPSR,TWI Write Protection Status Register"
|
|
in
|
|
width 0xB
|
|
tree "TWI5 PDC (Peripheral DMA Controller)"
|
|
width 11.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "TWI5_RPR,Receive Pointer Register"
|
|
line.long 0x04 "TWI5_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "TWI5_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "TWI5_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "TWI5_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "TWI5_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "TWI5_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "TWI5_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "TWI5_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "TWI5_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "TWI6"
|
|
base ad:0x40040600
|
|
width 16.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TWI_CR,TWI Control Register"
|
|
sif cpuis("ATSAMG55")
|
|
bitfld.long 0x00 26. " LOCKCLR ,Lock Clear" "No effect,Clear"
|
|
bitfld.long 0x00 24. " THRCLR ,Transmit Holding Register Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ACMDIS ,Alternative Command Mode Disable" "No effect,Disable"
|
|
bitfld.long 0x00 16. " ACMEN ,Alternative Command Mode Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CLEAR ,Bus CLEAR Command" "No effect,Clear"
|
|
bitfld.long 0x00 14. " PECRQ ,PEC Request" "No effect,Request"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PECDIS ,Packet Error Checking Disable" "No effect,Disable"
|
|
bitfld.long 0x00 12. " PECEN ,Packet Error Checking Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SMBDIS ,SMBus Mode Disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 10. " SMBEN ,SMBus Mode Enabled" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " HSDIS ,TWI High-Speed Mode Disabled" "No effect,H-S Disabled"
|
|
bitfld.long 0x00 8. " HSEN ,TWI High-Speed Mode Enabled" "No effect,H-S Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
sif !cpuis("ATSAMG53")
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS Quick Command" "No effect,Sent"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " SVDIS ,TWI Slave Mode Disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " SVEN ,TWI Slave Mode Enabled" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSDIS ,TWI Master Transfer Disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 2. " MSEN ,TWI Master Transfer Enabled" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP Condition" "No effect,Sent"
|
|
bitfld.long 0x00 0. " START ,Send a START Condition" "No effect,Sent"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "None,1_Byte,2_Byte,3_Byte"
|
|
sif !cpuis("ATSAMG55")
|
|
if (((d.l((ad:0x40040600+0xE4)))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave Address"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave Address"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0x40040600+0xE4)))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
bitfld.long 0x00 31. " DATAMEN ,Data Matching Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SADR3EN ,Slave Address 3 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SADR2EN ,Slave Address 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SADR1EN ,Slave Address 1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave Address"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MASK ,Slave Address Mask"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCLWSDIS ,Clock Wait State Disable" "No,Yes"
|
|
bitfld.long 0x00 3. " SMHH ,SMBus Host Header" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SMDA ,SMBus Default Address" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NACKEN ,Slave Receiver Data Phase NACK Enable" "Normal,NACK"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
bitfld.long 0x00 31. " DATAMEN ,Data Matching Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SADR3EN ,Slave Address 3 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SADR2EN ,Slave Address 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SADR1EN ,Slave Address 1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 0x10000 " SADR ,Slave Address"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MASK ,Slave Address Mask"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCLWSDIS ,Clock Wait State Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 3. " SMHH ,SMBus Host Header" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SMDA ,SMBus Default Address" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NACKEN ,Slave Receiver Data Phase NACK Enable" "Normal,NACK"
|
|
endif
|
|
endif
|
|
if (((d.l((ad:0x40040600+0x4)))&0x300)==0x300)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x40040600+0x4)))&0x300)==0x200)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x40040600+0x4)))&0x300)==0x100)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IADR ,Internal Address"
|
|
else
|
|
hgroup.long 0x0c++0x3
|
|
hide.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
endif
|
|
if (((d.l((ad:0x40040600+0xE4)))&0x01)==0x00)
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
bitfld.long 0x0 24.--28. " HOLD ,TWD Hold Time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("ATSAMG55")
|
|
bitfld.long 0x0 20. " BRSRCCLK ,Bit Rate Source Clock" "Periph_clk,Pmc_pck"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " CKDIV ,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
else
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
bitfld.long 0x0 24.--28. " HOLD ,TWD Hold Time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("ATSAMG55")
|
|
bitfld.long 0x0 20. " BRSRCCLK ,Bit Rate Source Clock" "Periph_clk,Pmc_pck"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " CKDIV ,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
endif
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TWI_SR,TWI Status Register"
|
|
in
|
|
group.long 0x2c++0x03
|
|
line.long 0x0 "TWI_IMR,TWI Interrupt Mask Register"
|
|
sif cpuis("ATSAMG55")
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " SMBHHM_set/clr ,SMBus Host Header Address Match Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " SMBDAM_set/clr ,SMBus Default Address Match Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " PECERR_set/clr ,PEC Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " TOUT_set/clr ,Timeout Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " MCACK_set/clr ,Master Code Acknowledge Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " EOSACC_set/clr ,End Of Slave Access Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " SCL_WS_set/clr ,Clock Wait State Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " ABRLST_set/clr ,Arbitration Lost Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " NACK_set/clr ,Not Acknowledge" "Masked,Not masked"
|
|
textline " "
|
|
sif cpuis("ATSAMG55")
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " UNRE_set/clr ,Underrun Error" "Masked,Not masked"
|
|
endif
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " OVRE_set/clr ,Overrun Error" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " GACC_set/clr ,General Call Access Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " SVACC_set/clr ,Slave Access Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " TXRDY_set/clr ,Transmit Holding Register Ready" "Masked,Not masked"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " RXRDY_set/clr ,Receive Holding Register Ready" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " TXCOMP_set/clr ,Transmission Completed" "Masked,Not masked"
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x00 "TWI_RHR,TWI Receive Holding Register"
|
|
in
|
|
wgroup.long 0x34++0x3
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
sif cpuis("ATSAMG55")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TWI_SMBTR,TWI SMBus Timing Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " THMAX ,Clock High Maximum Cycles"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TLOWM ,Master Clock Stretch Maximum Cycles"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " TLOWS ,Slave Clock Stretch Maximum Cycles"
|
|
bitfld.long 0x00 0.--3. " PRESC ,SMBus Clock Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TWI_ACR,TWI Alternative Command Register"
|
|
bitfld.long 0x00 25. " NPEC ,NextPEC Request" "Not used,Used"
|
|
bitfld.long 0x00 24. " NDIR ,Next Transfer Direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " NDATAL ,Next Data Length"
|
|
bitfld.long 0x00 9. " PEC ,PEC Request" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIR ,Transfer Direction" "Write,Read"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATAL ,Data Length"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TWI_FILTR,TWI Filter Register"
|
|
bitfld.long 0x00 8.--10. " THRES ,Digital Filter Threshold" "No filtering,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PADFCFG ,PAD Filter Config" "No filtering,Filtering"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PADFEN ,PAD Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FILT ,RX Digital Filter" "No filtering,Filtering"
|
|
group.long 0x4C++0x3
|
|
line.long 0x00 "TWI_SWMR,TWI SleepWalking Matching Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATAM ,Data Match"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR3 ,Slave Address 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " SADR2 ,Slave Address 2"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SADR1 ,Slave Address 1"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TWI_WPROT_MODE,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protection Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "TWI_WPSR,TWI Write Protection Status Register"
|
|
in
|
|
width 0xB
|
|
tree "TWI6 PDC (Peripheral DMA Controller)"
|
|
width 11.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "TWI6_RPR,Receive Pointer Register"
|
|
line.long 0x04 "TWI6_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "TWI6_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "TWI6_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "TWI6_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "TWI6_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "TWI6_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "TWI6_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "TWI6_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "TWI6_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "TWI7"
|
|
base ad:0x40034600
|
|
width 16.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TWI_CR,TWI Control Register"
|
|
sif cpuis("ATSAMG55")
|
|
bitfld.long 0x00 26. " LOCKCLR ,Lock Clear" "No effect,Clear"
|
|
bitfld.long 0x00 24. " THRCLR ,Transmit Holding Register Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ACMDIS ,Alternative Command Mode Disable" "No effect,Disable"
|
|
bitfld.long 0x00 16. " ACMEN ,Alternative Command Mode Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CLEAR ,Bus CLEAR Command" "No effect,Clear"
|
|
bitfld.long 0x00 14. " PECRQ ,PEC Request" "No effect,Request"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PECDIS ,Packet Error Checking Disable" "No effect,Disable"
|
|
bitfld.long 0x00 12. " PECEN ,Packet Error Checking Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SMBDIS ,SMBus Mode Disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 10. " SMBEN ,SMBus Mode Enabled" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " HSDIS ,TWI High-Speed Mode Disabled" "No effect,H-S Disabled"
|
|
bitfld.long 0x00 8. " HSEN ,TWI High-Speed Mode Enabled" "No effect,H-S Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
sif !cpuis("ATSAMG53")
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS Quick Command" "No effect,Sent"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " SVDIS ,TWI Slave Mode Disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " SVEN ,TWI Slave Mode Enabled" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSDIS ,TWI Master Transfer Disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 2. " MSEN ,TWI Master Transfer Enabled" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP Condition" "No effect,Sent"
|
|
bitfld.long 0x00 0. " START ,Send a START Condition" "No effect,Sent"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "None,1_Byte,2_Byte,3_Byte"
|
|
sif !cpuis("ATSAMG55")
|
|
if (((d.l((ad:0x40034600+0xE4)))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave Address"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave Address"
|
|
endif
|
|
else
|
|
if (((d.l((ad:0x40034600+0xE4)))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
bitfld.long 0x00 31. " DATAMEN ,Data Matching Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SADR3EN ,Slave Address 3 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SADR2EN ,Slave Address 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SADR1EN ,Slave Address 1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave Address"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MASK ,Slave Address Mask"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCLWSDIS ,Clock Wait State Disable" "No,Yes"
|
|
bitfld.long 0x00 3. " SMHH ,SMBus Host Header" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SMDA ,SMBus Default Address" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NACKEN ,Slave Receiver Data Phase NACK Enable" "Normal,NACK"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
bitfld.long 0x00 31. " DATAMEN ,Data Matching Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SADR3EN ,Slave Address 3 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SADR2EN ,Slave Address 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SADR1EN ,Slave Address 1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 0x10000 " SADR ,Slave Address"
|
|
hexmask.long.byte 0x00 8.--14. 1. " MASK ,Slave Address Mask"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SCLWSDIS ,Clock Wait State Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 3. " SMHH ,SMBus Host Header" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SMDA ,SMBus Default Address" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NACKEN ,Slave Receiver Data Phase NACK Enable" "Normal,NACK"
|
|
endif
|
|
endif
|
|
if (((d.l((ad:0x40034600+0x4)))&0x300)==0x300)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x40034600+0x4)))&0x300)==0x200)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x40034600+0x4)))&0x300)==0x100)
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IADR ,Internal Address"
|
|
else
|
|
hgroup.long 0x0c++0x3
|
|
hide.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
endif
|
|
if (((d.l((ad:0x40034600+0xE4)))&0x01)==0x00)
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
bitfld.long 0x0 24.--28. " HOLD ,TWD Hold Time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("ATSAMG55")
|
|
bitfld.long 0x0 20. " BRSRCCLK ,Bit Rate Source Clock" "Periph_clk,Pmc_pck"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " CKDIV ,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
else
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
bitfld.long 0x0 24.--28. " HOLD ,TWD Hold Time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("ATSAMG55")
|
|
bitfld.long 0x0 20. " BRSRCCLK ,Bit Rate Source Clock" "Periph_clk,Pmc_pck"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " CKDIV ,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
endif
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TWI_SR,TWI Status Register"
|
|
in
|
|
group.long 0x2c++0x03
|
|
line.long 0x0 "TWI_IMR,TWI Interrupt Mask Register"
|
|
sif cpuis("ATSAMG55")
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " SMBHHM_set/clr ,SMBus Host Header Address Match Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " SMBDAM_set/clr ,SMBus Default Address Match Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " PECERR_set/clr ,PEC Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " TOUT_set/clr ,Timeout Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " MCACK_set/clr ,Master Code Acknowledge Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " EOSACC_set/clr ,End Of Slave Access Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " SCL_WS_set/clr ,Clock Wait State Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " ABRLST_set/clr ,Arbitration Lost Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " NACK_set/clr ,Not Acknowledge" "Masked,Not masked"
|
|
textline " "
|
|
sif cpuis("ATSAMG55")
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " UNRE_set/clr ,Underrun Error" "Masked,Not masked"
|
|
endif
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " OVRE_set/clr ,Overrun Error" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " GACC_set/clr ,General Call Access Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " SVACC_set/clr ,Slave Access Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " TXRDY_set/clr ,Transmit Holding Register Ready" "Masked,Not masked"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " RXRDY_set/clr ,Receive Holding Register Ready" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " TXCOMP_set/clr ,Transmission Completed" "Masked,Not masked"
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x00 "TWI_RHR,TWI Receive Holding Register"
|
|
in
|
|
wgroup.long 0x34++0x3
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
sif cpuis("ATSAMG55")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TWI_SMBTR,TWI SMBus Timing Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " THMAX ,Clock High Maximum Cycles"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TLOWM ,Master Clock Stretch Maximum Cycles"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " TLOWS ,Slave Clock Stretch Maximum Cycles"
|
|
bitfld.long 0x00 0.--3. " PRESC ,SMBus Clock Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TWI_ACR,TWI Alternative Command Register"
|
|
bitfld.long 0x00 25. " NPEC ,NextPEC Request" "Not used,Used"
|
|
bitfld.long 0x00 24. " NDIR ,Next Transfer Direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " NDATAL ,Next Data Length"
|
|
bitfld.long 0x00 9. " PEC ,PEC Request" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIR ,Transfer Direction" "Write,Read"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATAL ,Data Length"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TWI_FILTR,TWI Filter Register"
|
|
bitfld.long 0x00 8.--10. " THRES ,Digital Filter Threshold" "No filtering,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PADFCFG ,PAD Filter Config" "No filtering,Filtering"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PADFEN ,PAD Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FILT ,RX Digital Filter" "No filtering,Filtering"
|
|
group.long 0x4C++0x3
|
|
line.long 0x00 "TWI_SWMR,TWI SleepWalking Matching Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATAM ,Data Match"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR3 ,Slave Address 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " SADR2 ,Slave Address 2"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SADR1 ,Slave Address 1"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TWI_WPROT_MODE,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protection Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "TWI_WPSR,TWI Write Protection Status Register"
|
|
in
|
|
width 0xB
|
|
tree "TWI7 PDC (Peripheral DMA Controller)"
|
|
width 11.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "TWI7_RPR,Receive Pointer Register"
|
|
line.long 0x04 "TWI7_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "TWI7_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "TWI7_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "TWI7_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "TWI7_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "TWI7_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "TWI7_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "TWI7_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "TWI7_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
else
|
|
tree "TWI1"
|
|
base ad:0x4001C000
|
|
width 16.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TWI_CR,TWI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS Quick Command" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SVDIS ,TWI Slave Mode Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 4. " SVEN ,TWI Slave Mode Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSDIS ,TWI Master Transfer Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 2. " MSEN ,TWI Master Transfer Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP Condition" "No effect,Stop"
|
|
bitfld.long 0x00 0. " START ,Send a START Condition" "No effect,Start"
|
|
sif ((cpu()!="ATSAMG5*")||cpuis("ATSAM4S*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
endif
|
|
sif (cpuis("ATSAM4S*"))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR ,Slave Address"
|
|
endif
|
|
if (((d.l((ad:0x4001C000+0x04)))&0x300)==0x300)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x4001C000+0x04)))&0x300)==0x200)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x4001C000+0x04)))&0x300)==0x100)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IADR ,Internal Address"
|
|
else
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
endif
|
|
sif cpuis("ATSAM4S*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
sif cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 24.--28. " HOLD ,TWD Hold Time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16.--18. " CKDIV ,Clock Divider" "1,2,4,8,16,32,64,128"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TWI_SR,TWI Status Register"
|
|
in
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TWI_IMR,TWI Interrupt Mask Register"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " EOSACC_set/clr ,End Of Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " SCL_WS_set/clr ,Clock Wait State Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " ARBLST_set/clr ,Arbitration Lost Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NACK_set/clr ,Not Acknowledge" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " OVRE_set/clr ,Overrun Error" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " GACC_set/clr ,General Call Access Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " SVACC_set/clr ,Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " TXRDY_set/clr ,Transmit Holding Register Ready" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " RXRDY_set/clr ,Receive Holding Register Ready" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " TXCOMP_set/clr ,Transmission Completed" "Disabled,Enabled"
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "TWI_RHR,TWI Receive Holding Register"
|
|
in
|
|
sif cpuis("ATSAM4S*")
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
endif
|
|
sif cpuis("ATSAM4E*")
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TWI_WPROT_MODE,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " SECURITY_CODE ,Write protection mode security code"
|
|
bitfld.long 0x00 0. " WPROT ,Write protection bit" "Disabled,Enabled"
|
|
sif (cpu()=="ATSAMG5*")
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "TWI_WPROT_STATUS,TWI Write Protection Status Register"
|
|
in
|
|
endif
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree "TWI1 PDC (Peripheral DMA Controller)"
|
|
width 11.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "TWI1_RPR,Receive Pointer Register"
|
|
line.long 0x04 "TWI1_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "TWI1_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "TWI1_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "TWI1_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "TWI1_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "TWI1_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "TWI1_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "TWI1_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "TWI1_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "TWI2"
|
|
base ad:0x40040000
|
|
width 16.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TWI_CR,TWI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS Quick Command" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SVDIS ,TWI Slave Mode Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 4. " SVEN ,TWI Slave Mode Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSDIS ,TWI Master Transfer Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 2. " MSEN ,TWI Master Transfer Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP Condition" "No effect,Stop"
|
|
bitfld.long 0x00 0. " START ,Send a START Condition" "No effect,Start"
|
|
sif ((cpu()!="ATSAMG5*")||cpuis("ATSAM4S*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
endif
|
|
sif (cpuis("ATSAM4S*"))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR ,Slave Address"
|
|
endif
|
|
if (((d.l((ad:0x40040000+0x04)))&0x300)==0x300)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x40040000+0x04)))&0x300)==0x200)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x40040000+0x04)))&0x300)==0x100)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IADR ,Internal Address"
|
|
else
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
endif
|
|
sif cpuis("ATSAM4S*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
sif cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 24.--28. " HOLD ,TWD Hold Time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16.--18. " CKDIV ,Clock Divider" "1,2,4,8,16,32,64,128"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TWI_SR,TWI Status Register"
|
|
in
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TWI_IMR,TWI Interrupt Mask Register"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " EOSACC_set/clr ,End Of Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " SCL_WS_set/clr ,Clock Wait State Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " ARBLST_set/clr ,Arbitration Lost Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NACK_set/clr ,Not Acknowledge" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " OVRE_set/clr ,Overrun Error" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " GACC_set/clr ,General Call Access Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " SVACC_set/clr ,Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " TXRDY_set/clr ,Transmit Holding Register Ready" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " RXRDY_set/clr ,Receive Holding Register Ready" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " TXCOMP_set/clr ,Transmission Completed" "Disabled,Enabled"
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "TWI_RHR,TWI Receive Holding Register"
|
|
in
|
|
sif cpuis("ATSAM4S*")
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
endif
|
|
sif cpuis("ATSAM4E*")
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TWI_WPROT_MODE,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " SECURITY_CODE ,Write protection mode security code"
|
|
bitfld.long 0x00 0. " WPROT ,Write protection bit" "Disabled,Enabled"
|
|
sif (cpu()=="ATSAMG5*")
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "TWI_WPROT_STATUS,TWI Write Protection Status Register"
|
|
in
|
|
endif
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree "TWI2 PDC (Peripheral DMA Controller)"
|
|
width 11.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "TWI2_RPR,Receive Pointer Register"
|
|
line.long 0x04 "TWI2_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "TWI2_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "TWI2_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "TWI2_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "TWI2_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "TWI2_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "TWI2_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "TWI2_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "TWI2_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif ((cpu()=="ATSAMG54")||(cpu()=="ATSAMG55")||(cpu()=="ATSAMG53"))
|
|
tree.open "I2SC (Inter-IC Sound Controller)"
|
|
tree "I2SC0"
|
|
base ad:0x40000000
|
|
width 0x0A
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "I2SC_CR,Inter-IC Sound Controller Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 5. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CKDIS ,Clocks Disable" "No effect,Disable"
|
|
bitfld.long 0x00 2. " CKEN ,Clocks Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2SC_MR,Inter-IC Sound Controller Mode Register"
|
|
bitfld.long 0x00 31. " IWS ,I2SWS TDM Slot Width" "32bit,24bit"
|
|
bitfld.long 0x00 30. " IMCKMODE ,Master Clock Mode" "Not generated,Generated"
|
|
bitfld.long 0x00 24.--29. " IMCKFS ,Master Clock to fs Ratio" "M2SF32,M2SF64,M2SF96,M2SF128,,M2SF192,,M2SF256,,,,M2SF384,,,,M2SF512,,,,,,,,M2SF768,,,,,,,,M2SF31024,,,,,,,,,,,,,,,,M2SF1536,,,,,,,,,,,,,,,,M2SF2048"
|
|
textline " "
|
|
sif (cpuis("ATSAMV71*"))
|
|
bitfld.long 0x00 16.--21. " IMCKDIV ,Selected Clock to I2SC Master Clock Ratio" ",/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
|
|
else
|
|
bitfld.long 0x00 16.--21. " IMCKDIV ,Selected Clock to I2SC Master Clock Ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
|
|
endif
|
|
bitfld.long 0x00 14. " TXSAME ,Transmit Data when Underrun" "Zero,Previous"
|
|
bitfld.long 0x00 13. " TXDMA ,Single or Multiple PDC Channels for Transmitter" "Both,Per audio"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TXMONO ,Transmit Mono" "Stereo,Mono"
|
|
bitfld.long 0x00 10. " RXLOOP ,Loop-back Test Mode" "Normal,Internal"
|
|
bitfld.long 0x00 9. " RXDMA ,Single or Multiple PDC Channels for Receiver" "Both,Per audio"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RXMONO ,Receive Mono" "Stereo,Mono"
|
|
sif (cpu()=="ATSAMG55")||(cpu()=="ATSAMG53")||(cpuis("ATSAMV71*"))
|
|
bitfld.long 0x00 6.--7. " FORMAT , Data Format" "I2S,LJ,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " DATALENGTH ,Data Word Length" "32bits,24bits,20bits,18bits,16bits,16bits comp,8bits,8bits comp"
|
|
bitfld.long 0x00 0. " MODE ,Inter-IC Sound Controller Mode" "Slave,Master"
|
|
sif (cpuis("ATSAMV71*"))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2SC_SR,Inter-IC Sound Controller Status Register"
|
|
setclrfld.long 0x00 21. 0x08 21. 0x04 21. " TXURCH[1]_set/clr ,Transmit Underrun Channel 1" "No overrun,Overrun"
|
|
setclrfld.long 0x00 20. 0x08 20. 0x04 20. " TXURCH[0]_set/clr ,Transmit Underrun Channel 0" "No overrun,Overrun"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " RXORCH[1]_set/clr ,Receive Overrun Channel 1" "No overrun,Overrun"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " RXORCH[0]_set/clr ,Receive Overrun Channel 0" "No overrun,Overrun"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " TXUR_set/clr ,Transmit Underrun" "No underrun,Underrun"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " TXRDY_set/clr ,Transmit Ready" "Not ready,Ready"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " TXEN_set/clr ,Transmitter Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " RXOR_set/clr ,Receive Overrun" "No overrun,Overrun"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXRDY_set/clr ,Receive Ready" "Not ready,Ready"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " RXEN_set/slr ,Receiver Enabled" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "I2SC_SR,Inter-IC Sound Controller Status Register"
|
|
textline " "
|
|
bitfld.long 0x00 31. " TXBUFE ,Transmit Buffer Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 21. " TXURCH[1] ,Transmit Underrun Channel 1" "No overrun,Overrun"
|
|
bitfld.long 0x00 20. " TXURCH[0] ,Transmit Underrun Channel 0" "No overrun,Overrun"
|
|
bitfld.long 0x00 19. " RXBUFF ,Receive Buffer Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RXORCH[1] ,Receive Overrun Channel 1" "No overrun,Overrun"
|
|
bitfld.long 0x00 8. " RXORCH[0] ,Receive Overrun Channel 0" "No overrun,Overrun"
|
|
bitfld.long 0x00 7. " ENDTX ,End of Transmitter Transfer" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " TXUR ,Transmit Underrun" "No underrun,Underrun"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TXRDY ,Transmit Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 4. " TXEN ,Transmitter Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENDRX ,End of Receiver Transfer" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RXOR ,Receive Overrun" "No overrun,Overrun"
|
|
bitfld.long 0x00 1. " RXRDY ,Receive Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " RXEN ,Receiver Enabled" "Disabled,Enabled"
|
|
wgroup.long 0x0C++0x07
|
|
line.long 0x00 "I2SC_SCR,Inter-IC Sound Controller Status Clear Register"
|
|
bitfld.long 0x00 21. " TXURCH[1] ,Transmit Underrun Per Channel 1 Status Clear" "No effect,Clear"
|
|
bitfld.long 0x00 20. " TXURCH[0] ,Transmit Underrun Per Channel 0 Status Clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " RXORCH[1] ,Receive Overrun Per Channel 1 Status Clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " RXORCH[0] ,Receive Overrun Per Channel 0 Status Clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " TXUR ,Transmit Underrun Status Clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " RXOR ,Receive Overrun Status Clear" "No effect,Clear"
|
|
line.long 0x04 "I2SC_SSR,Inter-IC Sound Controller Status Set Register"
|
|
bitfld.long 0x04 21. " TXURCH[1] ,Transmit Underrun Per Channel 1 Status Clear" "No effect,Set"
|
|
bitfld.long 0x04 20. " TXURCH[0] ,Transmit Underrun Per Channel 0 Status Clear" "No effect,Set"
|
|
bitfld.long 0x04 9. " RXORCH[1] ,Receive Overrun Per Channel 1 Status Clear" "No effect,Set"
|
|
bitfld.long 0x04 8. " RXORCH[0] ,Receive Overrun Per Channel 0 Status Clear" "No effect,Set"
|
|
bitfld.long 0x04 6. " TXUR ,Transmit Underrun Status Clear" "No effect,Set"
|
|
bitfld.long 0x04 2. " RXOR ,Receive Overrun Status Clear" "No effect,Set"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "I2SC_IMR,Inter-IC Sound Controller Interrupt Mask Register"
|
|
sif (!cpuis("ATSAMV71*"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " TXEMPTY_set/clr ,Transmit Buffer Empty Interrupt Disable" "Masked,Not masked"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " RXFULL_set/clr ,Receive Buffer Full Interrupt Disable" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ENDTX_set/clr ,End of Transmission Interrupt Disable" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " TXUR_set/clr ,Transmit Underflow Interrupt Disable" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " TXRDY_set/clr ,Transmit Ready Interrupt Disable" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,End of Reception Interrupt Disable" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " RXOR_set/clr ,Receiver Overrun Interrupt Disable" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " RXRDY_set/clr ,Receiver Ready Interrupt Disable" "Masked,Not masked"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "I2SC_RHR,Inter-IC Sound Controller Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "I2SC_THR,Inter-IC Sound Controller Transmitter Holding Register"
|
|
width 0x0B
|
|
tree "I2SC Left Side PDC (Peripheral DMA Controller)"
|
|
width 12.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "I2SC_RPR,Receive Pointer Register"
|
|
line.long 0x04 "I2SC_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "I2SC_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "I2SC_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "I2SC_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "I2SC_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "I2SC_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "I2SC_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "I2SC_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "I2SC_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2SC Right Side PDC (Peripheral DMA Controller)"
|
|
width 12.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "I2SC_RPR,Receive Pointer Register"
|
|
line.long 0x04 "I2SC_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "I2SC_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "I2SC_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "I2SC_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "I2SC_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "I2SC_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "I2SC_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "I2SC_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "I2SC_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "I2SC1"
|
|
base ad:0x40004000
|
|
width 0x0A
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "I2SC_CR,Inter-IC Sound Controller Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 5. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CKDIS ,Clocks Disable" "No effect,Disable"
|
|
bitfld.long 0x00 2. " CKEN ,Clocks Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2SC_MR,Inter-IC Sound Controller Mode Register"
|
|
bitfld.long 0x00 31. " IWS ,I2SWS TDM Slot Width" "32bit,24bit"
|
|
bitfld.long 0x00 30. " IMCKMODE ,Master Clock Mode" "Not generated,Generated"
|
|
bitfld.long 0x00 24.--29. " IMCKFS ,Master Clock to fs Ratio" "M2SF32,M2SF64,M2SF96,M2SF128,,M2SF192,,M2SF256,,,,M2SF384,,,,M2SF512,,,,,,,,M2SF768,,,,,,,,M2SF31024,,,,,,,,,,,,,,,,M2SF1536,,,,,,,,,,,,,,,,M2SF2048"
|
|
textline " "
|
|
sif (cpuis("ATSAMV71*"))
|
|
bitfld.long 0x00 16.--21. " IMCKDIV ,Selected Clock to I2SC Master Clock Ratio" ",/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
|
|
else
|
|
bitfld.long 0x00 16.--21. " IMCKDIV ,Selected Clock to I2SC Master Clock Ratio" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
|
|
endif
|
|
bitfld.long 0x00 14. " TXSAME ,Transmit Data when Underrun" "Zero,Previous"
|
|
bitfld.long 0x00 13. " TXDMA ,Single or Multiple PDC Channels for Transmitter" "Both,Per audio"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TXMONO ,Transmit Mono" "Stereo,Mono"
|
|
bitfld.long 0x00 10. " RXLOOP ,Loop-back Test Mode" "Normal,Internal"
|
|
bitfld.long 0x00 9. " RXDMA ,Single or Multiple PDC Channels for Receiver" "Both,Per audio"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RXMONO ,Receive Mono" "Stereo,Mono"
|
|
sif (cpu()=="ATSAMG55")||(cpu()=="ATSAMG53")||(cpuis("ATSAMV71*"))
|
|
bitfld.long 0x00 6.--7. " FORMAT , Data Format" "I2S,LJ,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " DATALENGTH ,Data Word Length" "32bits,24bits,20bits,18bits,16bits,16bits comp,8bits,8bits comp"
|
|
bitfld.long 0x00 0. " MODE ,Inter-IC Sound Controller Mode" "Slave,Master"
|
|
sif (cpuis("ATSAMV71*"))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2SC_SR,Inter-IC Sound Controller Status Register"
|
|
setclrfld.long 0x00 21. 0x08 21. 0x04 21. " TXURCH[1]_set/clr ,Transmit Underrun Channel 1" "No overrun,Overrun"
|
|
setclrfld.long 0x00 20. 0x08 20. 0x04 20. " TXURCH[0]_set/clr ,Transmit Underrun Channel 0" "No overrun,Overrun"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " RXORCH[1]_set/clr ,Receive Overrun Channel 1" "No overrun,Overrun"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " RXORCH[0]_set/clr ,Receive Overrun Channel 0" "No overrun,Overrun"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " TXUR_set/clr ,Transmit Underrun" "No underrun,Underrun"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " TXRDY_set/clr ,Transmit Ready" "Not ready,Ready"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " TXEN_set/clr ,Transmitter Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " RXOR_set/clr ,Receive Overrun" "No overrun,Overrun"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXRDY_set/clr ,Receive Ready" "Not ready,Ready"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " RXEN_set/slr ,Receiver Enabled" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "I2SC_SR,Inter-IC Sound Controller Status Register"
|
|
textline " "
|
|
bitfld.long 0x00 31. " TXBUFE ,Transmit Buffer Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 21. " TXURCH[1] ,Transmit Underrun Channel 1" "No overrun,Overrun"
|
|
bitfld.long 0x00 20. " TXURCH[0] ,Transmit Underrun Channel 0" "No overrun,Overrun"
|
|
bitfld.long 0x00 19. " RXBUFF ,Receive Buffer Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RXORCH[1] ,Receive Overrun Channel 1" "No overrun,Overrun"
|
|
bitfld.long 0x00 8. " RXORCH[0] ,Receive Overrun Channel 0" "No overrun,Overrun"
|
|
bitfld.long 0x00 7. " ENDTX ,End of Transmitter Transfer" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " TXUR ,Transmit Underrun" "No underrun,Underrun"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TXRDY ,Transmit Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 4. " TXEN ,Transmitter Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ENDRX ,End of Receiver Transfer" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RXOR ,Receive Overrun" "No overrun,Overrun"
|
|
bitfld.long 0x00 1. " RXRDY ,Receive Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " RXEN ,Receiver Enabled" "Disabled,Enabled"
|
|
wgroup.long 0x0C++0x07
|
|
line.long 0x00 "I2SC_SCR,Inter-IC Sound Controller Status Clear Register"
|
|
bitfld.long 0x00 21. " TXURCH[1] ,Transmit Underrun Per Channel 1 Status Clear" "No effect,Clear"
|
|
bitfld.long 0x00 20. " TXURCH[0] ,Transmit Underrun Per Channel 0 Status Clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " RXORCH[1] ,Receive Overrun Per Channel 1 Status Clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " RXORCH[0] ,Receive Overrun Per Channel 0 Status Clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " TXUR ,Transmit Underrun Status Clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " RXOR ,Receive Overrun Status Clear" "No effect,Clear"
|
|
line.long 0x04 "I2SC_SSR,Inter-IC Sound Controller Status Set Register"
|
|
bitfld.long 0x04 21. " TXURCH[1] ,Transmit Underrun Per Channel 1 Status Clear" "No effect,Set"
|
|
bitfld.long 0x04 20. " TXURCH[0] ,Transmit Underrun Per Channel 0 Status Clear" "No effect,Set"
|
|
bitfld.long 0x04 9. " RXORCH[1] ,Receive Overrun Per Channel 1 Status Clear" "No effect,Set"
|
|
bitfld.long 0x04 8. " RXORCH[0] ,Receive Overrun Per Channel 0 Status Clear" "No effect,Set"
|
|
bitfld.long 0x04 6. " TXUR ,Transmit Underrun Status Clear" "No effect,Set"
|
|
bitfld.long 0x04 2. " RXOR ,Receive Overrun Status Clear" "No effect,Set"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "I2SC_IMR,Inter-IC Sound Controller Interrupt Mask Register"
|
|
sif (!cpuis("ATSAMV71*"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " TXEMPTY_set/clr ,Transmit Buffer Empty Interrupt Disable" "Masked,Not masked"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " RXFULL_set/clr ,Receive Buffer Full Interrupt Disable" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ENDTX_set/clr ,End of Transmission Interrupt Disable" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " TXUR_set/clr ,Transmit Underflow Interrupt Disable" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " TXRDY_set/clr ,Transmit Ready Interrupt Disable" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,End of Reception Interrupt Disable" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " RXOR_set/clr ,Receiver Overrun Interrupt Disable" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " RXRDY_set/clr ,Receiver Ready Interrupt Disable" "Masked,Not masked"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "I2SC_RHR,Inter-IC Sound Controller Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "I2SC_THR,Inter-IC Sound Controller Transmitter Holding Register"
|
|
width 0x0B
|
|
tree "I2SC Left Side PDC (Peripheral DMA Controller)"
|
|
width 12.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "I2SC_RPR,Receive Pointer Register"
|
|
line.long 0x04 "I2SC_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "I2SC_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "I2SC_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "I2SC_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "I2SC_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "I2SC_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "I2SC_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "I2SC_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "I2SC_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2SC Right Side PDC (Peripheral DMA Controller)"
|
|
width 12.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "I2SC_RPR,Receive Pointer Register"
|
|
line.long 0x04 "I2SC_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "I2SC_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "I2SC_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "I2SC_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "I2SC_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "I2SC_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "I2SC_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "I2SC_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "I2SC_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="ATSAMG55")||(cpu()=="ATSAMG54")||(cpu()=="ATSAMG53")
|
|
tree "PDMIC (Pulse Density Modulation Interface Controller)"
|
|
tree "PDMIC0"
|
|
base ad:0x4002C000
|
|
width 13.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDMIC_CR,PDMIC Control Register"
|
|
bitfld.long 0x00 4. " SWRST ,Software Reset" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENPDM ,Enable PDM" "No effect,Reset"
|
|
textline " "
|
|
sif (cpu()=="ATSAMG54")
|
|
if (((d.l(ad:0x4002C000+0xE4))&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PDMIC_MR,PDMIC Mode Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " PRESCAL ,Prescaler Rate Selection"
|
|
textline " "
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PDMIC_MR,PDMIC Mode Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " PRESCAL ,Prescaler Rate Selection"
|
|
textline " "
|
|
endif
|
|
else
|
|
if (((d.l(ad:0x4002C000+0xE4))&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PDMIC_MR,PDMIC Mode Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " PRESCAL ,Prescaler Rate Selection"
|
|
bitfld.long 0x00 4. " CLKS ,Clock Source Selection" "Peripheral,PCKx"
|
|
textline " "
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PDMIC_MR,PDMIC Mode Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " PRESCAL ,Prescaler Rate Selection"
|
|
bitfld.long 0x00 4. " CLKS ,Clock Source Selection" "Peripheral,PCKx"
|
|
textline " "
|
|
endif
|
|
endif
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "PDMIC_CDR,PDMIC Converted Data Register"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PDMIC_IMR,PDMIC Interrupt Mask Register"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " OVRE_set/clr ,General Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " DRDY_set/clr ,Data Ready Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "PDMIC_ISR,PDMIC Interrupt Status Register"
|
|
in
|
|
if (((d.l(ad:0x4002C000+0xE4))&0x01)==0x00)
|
|
group.long 0x58++0x07
|
|
line.long 0x00 "PDMIC_DSPR0,PDMIC DSP Configuration Register 0"
|
|
bitfld.long 0x00 12.--15. " SHIFT ,Data Shift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " SCALE ,Data Scale" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--6. " OSR ,Oversampling Ratio" "/128,/64,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " SIZE ,Data Size" "16 bits,32 bits"
|
|
bitfld.long 0x00 2. " SINBYP ,SINCC Filter Bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 1. " HPFBYP ,High-Pass Filter Bypass" "Not bypassed,Bypassed"
|
|
line.long 0x04 "PDMIC_DSPR1,PDMIC DSP Configuration Register 1"
|
|
hexmask.long.word 0x04 16.--31. 1. " OFFSET ,Offset correction"
|
|
hexmask.long.word 0x04 0.--14. 1. " DGAIN ,Gain correction"
|
|
textline " "
|
|
else
|
|
rgroup.long 0x58++0x07
|
|
line.long 0x00 "PDMIC_DSPR0,PDMIC DSP Configuration Register 0"
|
|
bitfld.long 0x00 12.--15. " SHIFT ,Data Shift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " SCALE ,Data Scale" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--6. " OSR ,Oversampling Ratio" "/128,/64,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " SIZE ,Data Size" "16 bits,32 bits"
|
|
bitfld.long 0x00 2. " SINBYP ,SINCC Filter Bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 1. " HPFBYP ,High-Pass Filter Bypass" "Not bypassed,Bypassed"
|
|
line.long 0x04 "PDMIC_DSPR1,PDMIC DSP Configuration Register 1"
|
|
hexmask.long.word 0x04 16.--31. 1. " OFFSET ,Offset correction"
|
|
hexmask.long.word 0x04 0.--14. 1. " DGAIN ,Gain correction"
|
|
textline " "
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "PDMIC_WPMR,PDMIC Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "PDMIC_WPSR,PDMIC Write Protection Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree "PDMIC1"
|
|
base ad:0x40030000
|
|
width 13.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDMIC_CR,PDMIC Control Register"
|
|
bitfld.long 0x00 4. " SWRST ,Software Reset" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENPDM ,Enable PDM" "No effect,Reset"
|
|
textline " "
|
|
sif (cpu()=="ATSAMG54")
|
|
if (((d.l(ad:0x40030000+0xE4))&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PDMIC_MR,PDMIC Mode Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " PRESCAL ,Prescaler Rate Selection"
|
|
textline " "
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PDMIC_MR,PDMIC Mode Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " PRESCAL ,Prescaler Rate Selection"
|
|
textline " "
|
|
endif
|
|
else
|
|
if (((d.l(ad:0x40030000+0xE4))&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PDMIC_MR,PDMIC Mode Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " PRESCAL ,Prescaler Rate Selection"
|
|
bitfld.long 0x00 4. " CLKS ,Clock Source Selection" "Peripheral,PCKx"
|
|
textline " "
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PDMIC_MR,PDMIC Mode Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " PRESCAL ,Prescaler Rate Selection"
|
|
bitfld.long 0x00 4. " CLKS ,Clock Source Selection" "Peripheral,PCKx"
|
|
textline " "
|
|
endif
|
|
endif
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "PDMIC_CDR,PDMIC Converted Data Register"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PDMIC_IMR,PDMIC Interrupt Mask Register"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " OVRE_set/clr ,General Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " DRDY_set/clr ,Data Ready Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "PDMIC_ISR,PDMIC Interrupt Status Register"
|
|
in
|
|
if (((d.l(ad:0x40030000+0xE4))&0x01)==0x00)
|
|
group.long 0x58++0x07
|
|
line.long 0x00 "PDMIC_DSPR0,PDMIC DSP Configuration Register 0"
|
|
bitfld.long 0x00 12.--15. " SHIFT ,Data Shift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " SCALE ,Data Scale" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--6. " OSR ,Oversampling Ratio" "/128,/64,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " SIZE ,Data Size" "16 bits,32 bits"
|
|
bitfld.long 0x00 2. " SINBYP ,SINCC Filter Bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 1. " HPFBYP ,High-Pass Filter Bypass" "Not bypassed,Bypassed"
|
|
line.long 0x04 "PDMIC_DSPR1,PDMIC DSP Configuration Register 1"
|
|
hexmask.long.word 0x04 16.--31. 1. " OFFSET ,Offset correction"
|
|
hexmask.long.word 0x04 0.--14. 1. " DGAIN ,Gain correction"
|
|
textline " "
|
|
else
|
|
rgroup.long 0x58++0x07
|
|
line.long 0x00 "PDMIC_DSPR0,PDMIC DSP Configuration Register 0"
|
|
bitfld.long 0x00 12.--15. " SHIFT ,Data Shift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " SCALE ,Data Scale" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--6. " OSR ,Oversampling Ratio" "/128,/64,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " SIZE ,Data Size" "16 bits,32 bits"
|
|
bitfld.long 0x00 2. " SINBYP ,SINCC Filter Bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 1. " HPFBYP ,High-Pass Filter Bypass" "Not bypassed,Bypassed"
|
|
line.long 0x04 "PDMIC_DSPR1,PDMIC DSP Configuration Register 1"
|
|
hexmask.long.word 0x04 16.--31. 1. " OFFSET ,Offset correction"
|
|
hexmask.long.word 0x04 0.--14. 1. " DGAIN ,Gain correction"
|
|
textline " "
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "PDMIC_WPMR,PDMIC Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "PDMIC_WPSR,PDMIC Write Protection Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="ATSAMG55")
|
|
tree "UHP (USB Host Port)"
|
|
base ad:0x4004C000
|
|
width 24.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "UHP_HCREVISION,UHP OHCI Revision Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,OHCI revision number"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "UHP_HCCONTROL,UHP HC Operating Mode Register"
|
|
bitfld.long 0x00 10. " RWE ,Remote wake-up enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RWC ,Remote wake-up connected" "Not supported,Supported"
|
|
bitfld.long 0x00 8. " IR ,Interrupt routing (Controller provide SMI interrupt)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " HCFS ,Host controller functional state" "Reset,Resume,Operational,Suspend"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLE ,Bulk list enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CLE ,Control list enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " IE ,Isochronous enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PLE ,Periodic list enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CBSR ,Control/bulk service ratio" "1ED,2EDs,3EDs,4EDs"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "UHP_HCCOMMANDSTATUS,UHP HC Command and Status Register"
|
|
rbitfld.long 0x00 16.--17. " SOC ,Scheduling overrun count (read-only)" "0,1,2,3"
|
|
bitfld.long 0x00 3. " OCR ,Ownership change request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 2. " BLF ,Bulk list filled" "Not modified,Modified"
|
|
bitfld.long 0x00 1. " CLF ,Control list filled" "Not modified,Modified"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HCR ,Host controller reset" "No effect,Reset"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "UHP_HCINTERRUPTSTATUS,UHP HC Interrupt and Status Register"
|
|
rbitfld.long 0x00 30. " OC ,Ownership change (read-only)" "0,1"
|
|
eventfld.long 0x00 6. " RHSC ,Root hub status change" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " FNO ,Frame number overflow" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " UE ,Unrecoverable error" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RD ,Resume detected" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " SF ,Start of frame" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " WDH ,Write done head" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " SO ,Scheduling overrun" "No interrupt,Interrupt"
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "UHP_HCINTERRUPTENABLE,UHP HC Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " MIE ,Master interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 30. " OC ,Ownership change Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RHSC ,Root hub status change Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FNO ,Frame number overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UE ,Unrecoverable error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RD ,Resume detected Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SF ,Start of frame Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WDH ,Write done head Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SO ,Scheduling overrun Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x04 "UHP_HCINTERRUPTDISABLE,UHP HC Interrupt Disable Register"
|
|
bitfld.long 0x04 31. " MIE ,Master Interrupt Disable" "No effect,Disable"
|
|
rbitfld.long 0x04 30. " OC ,Ownership change Interrupt Disable" "No effect,Disable"
|
|
bitfld.long 0x04 6. " RHSC ,Root hub status change Interrupt Disable" "No effect,Disable"
|
|
bitfld.long 0x04 5. " FNO ,Frame number overflow Interrupt Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x04 4. " UE ,Unrecoverable error Interrupt Disable" "No effect,Disable"
|
|
bitfld.long 0x04 3. " RD ,Resume detected Interrupt Disable" "No effect,Disable"
|
|
bitfld.long 0x04 2. " SF ,Start of frame Interrupt Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x04 1. " WDH ,Write done head Interrupt Disable" "No effect,Disable"
|
|
bitfld.long 0x04 0. " SO ,Scheduling overrun Interrupt Disable" "No effect,Disable"
|
|
textline " "
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "UHP_HCHCCA,UHP HC HCCA Address Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 0x01 " HCCA ,Physical address of the beginning of the HCCA"
|
|
textline " "
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "UHP_HCPERIODCURRENTED,UHP HC Current Periodic Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " PCED ,Physical address of the current ED on the periodic ED list"
|
|
textline " "
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "UHP_HCCONTROLHEADED,UHP HC Head Control Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " CHED ,Physical address of the head ED on the control ED list"
|
|
textline " "
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "UHP_HCCONTROLCURRENTED,UHP HC Current Control Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " CCED ,Physical address of the current ED on the control ED list"
|
|
textline " "
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "UHP_HCBULKHEADED,UHP HC Head Done Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " BHED ,Physical address of the head ED on the bulk ED list"
|
|
textline " "
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "UHP_HCBULKCURRENTED,UHP HC Current Bulk Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " BCED ,Physical address of the current ED on the bulk ED list"
|
|
textline " "
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "UHP_HCDONEHEAD,UHP HC Head Done Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " DH ,Physical address of the last TD that has added to the done queue"
|
|
textline " "
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "UHP_HCFMINTERVAL,UHP HC Frame Interval Register"
|
|
bitfld.long 0x00 31. " FIT ,Frame interval toggle" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " FSMPS ,Largest data packet"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--13. 1. " FRAMEINTERVAL ,Frame interval"
|
|
textline " "
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "UHP_HCFMREMAINING,UHP HC Frame Remaining Register"
|
|
bitfld.long 0x00 31. " FRT ,Frame remaining toggle" "0,1"
|
|
hexmask.long.word 0x00 0.--13. 1. " FR ,Frame remaining"
|
|
textline " "
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "UHP_HCFMNUMBER,UHP HC Frame Number Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " FN ,Frame number"
|
|
textline " "
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "UHP_HCPERIODICSTART,UHP HC Periodic Start Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " PS ,Periodic start"
|
|
textline " "
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "UHP_HCLSTHRESHOLD,UHP HC Low-Speed Threshold Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " LST ,Low-speed threshold"
|
|
textline " "
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "UHP_HCRHDESCRIPTORA,UHP HC Root Hub A Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POTPG ,Power-on to power-good time (read/write)"
|
|
bitfld.long 0x00 12. " NOCP ,No overcurrent protection (read/write)" ",Not protected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OCPM ,Overcurrent protection mode (read/write)" "Not provided,"
|
|
bitfld.long 0x00 10. " DT ,Device type (read-only)" "Non-compound,"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NPS ,No power switching (read/write)" ",No switching"
|
|
bitfld.long 0x00 8. " PSM ,Power switching mode (read/write)" "Not provided,"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " NDP ,Number of downstream ports (read-only)"
|
|
textline " "
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "UHP_HCRHDESCRIPTORB,UHP HC Root Hub B Register"
|
|
bitfld.long 0x00 19. " PPCM[3] ,Port power control mask for downstream port 3" "Global,Per-port"
|
|
bitfld.long 0x00 18. " PPCM[2] ,Port power control mask for downstream port 2" "Global,Per-port"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PPCM[1] ,Port power control mask for downstream port 1" "Global,Per-port"
|
|
bitfld.long 0x00 3. " DR[3] ,Device removable bit for downstream port 3" "Removable,Nonremovable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DR[2] ,Device removable bit for downstream port 2" "Removable,Nonremovable"
|
|
bitfld.long 0x00 1. " DR[1] ,Device removable bit for downstream port 1" "Removable,Nonremovable"
|
|
textline " "
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "UHP_HCRHSTATUS,UHP HC Root Hub Status Register"
|
|
bitfld.long 0x00 31. " CRWE ,Clear remote wake-up enable" "No effect,Clear"
|
|
eventfld.long 0x00 17. " OCIC ,Overcurrent indication change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 16. " LPSC ,Local power status change" "Not supported,"
|
|
bitfld.long 0x00 15. " DRWE ,Device remote wake-up enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OCI ,Overcurrent indicator" "No overcurrent,"
|
|
bitfld.long 0x00 0. " LPS ,Local power status" "Not provided,"
|
|
textline " "
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "UHP_HCRHPORTSTATUS1,UHP HC Port 1 Status and Control Register"
|
|
eventfld.long 0x00 20. " PRSC ,Port 1 reset status change" "Not changed,Changed"
|
|
eventfld.long 0x00 19. " OCIC ,Port 1 overcurrent indicator change" "0,"
|
|
eventfld.long 0x00 18. " PSSC ,Port 1 suspend status change" "Not changed,Changed"
|
|
eventfld.long 0x00 17. " PESC ,Port 1 enable status change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Port 1 connect status change" "Not changed,Changed"
|
|
eventfld.long 0x00 9. " LSDA/CPP ,Port 1 low-speed device attached/clear port power" "Full-speed,Low-speed"
|
|
eventfld.long 0x00 8. " PPS/SPP ,Port 1 port power status/set port power" "Disabled,Enabled"
|
|
eventfld.long 0x00 4. " PRS/SPR ,Port 1 port reset status/set port reset" "No effect,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 3. " POCI/CSS ,Port 1 port overcurrent indicator/clear suspend status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " PSS/SPS ,Port 1 port suspend status/set port suspend" "No effect,Suspend"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PES/SPE ,Port 1 port enable status/set port enable" "Disable,Enable"
|
|
eventfld.long 0x00 0. " CCS/CPE ,Port 1 current connection status/clear port enable" "Disable,Enable"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "UHP_HCRHPORTSTATUS2,UHP HC Port 2 Status and Control Register"
|
|
eventfld.long 0x00 20. " PRSC ,Port 2 reset status change" "Not changed,Changed"
|
|
eventfld.long 0x00 19. " OCIC ,Port 2 overcurrent indicator change" "0,"
|
|
eventfld.long 0x00 18. " PSSC ,Port 2 suspend status change" "Not changed,Changed"
|
|
eventfld.long 0x00 17. " PESC ,Port 2 enable status change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Port 2 connect status change" "Not changed,Changed"
|
|
eventfld.long 0x00 9. " LSDA/CPP ,Port 2 low-speed device attached/clear port power" "Full-speed,Low-speed"
|
|
eventfld.long 0x00 8. " PPS/SPP ,Port 2 port power status/set port power" "Disabled,Enabled"
|
|
eventfld.long 0x00 4. " PRS/SPR ,Port 2 port reset status/set port reset" "No effect,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 3. " POCI/CSS ,Port 2 port overcurrent indicator/clear suspend status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " PSS/SPS ,Port 2 port suspend status/set port suspend" "No suspend,Suspend"
|
|
eventfld.long 0x00 1. " PES/SPE ,Port 2 current connection status/clear port enable " "Disable,Enable"
|
|
eventfld.long 0x00 0. " CCS/CPE ,Port 2 current connection status/clear port enable" "Disable,Enable"
|
|
textline " "
|
|
width 0x0B
|
|
tree.end
|
|
tree "UDP (USB Device Port)"
|
|
base ad:0x40044000
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "UDP_FRM_NUM,UDP Frame Number Register"
|
|
bitfld.long 0x00 17. " FRM_OK ,Frame OK" "SOF_PID,SOF_EOP"
|
|
bitfld.long 0x00 16. " FRM_ERR ,Frame Error" "No error,Error"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " FRM_NUM[10:0] ,Frame Number as Defined In the Packet Field Formats"
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "UDP_GLB_STAT,UDP Global State Register"
|
|
bitfld.long 0x00 4. " RMWUPE ,Remote Wake Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RSMINPR ,A Resume Has Been Sent to the Host" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ESR ,Enable Send Resume" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CONFG ,Configured" "Not configured,Configured"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FADDEN ,Function Address Enable" "Disabled,Enabled"
|
|
line.long 0x4 "UDP_FADDR,UDP Function Address Register"
|
|
bitfld.long 0x4 8. " FEN ,Function Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x4 0.--6. 1. " FADD[6:0] ,Function Address Value"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "UDP_IMR,UDP Interrupt Mask Register"
|
|
setclrfld.long 0x0 13. -0x08 13. -0x4 13. " WAKEUP_set/clr ,USB Bus WAKEUP Interrupt" "Masked,Not masked"
|
|
rbitfld.long 0x0 12. " BIT12 ,UDP_IMR Bit 12" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x08 11. -0x4 11. " SOFINT_set/clr ,Mask Start Of Frame Interrupt" "Masked,Not masked"
|
|
sif cpuis("ATSAM4E*")||cpuis("ATSAM4S*")||cpuis("ATSAMG55")
|
|
setclrfld.long 0x0 10. -0x08 10. -0x4 10. " EXTRSM_set/clr ,Mask External Resume Interrupt" "Masked,Not masked"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x08 9. -0x4 9. " RXRSM_set/clr ,Mask UDP Resume Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " RXSUSP_set/clr ,Mask UDP Suspend Interrupt" "Masked,Not masked"
|
|
textline " "
|
|
sif !cpuis("ATSAMG55")
|
|
setclrfld.long 0x0 7. -0x08 7. -0x4 7. " EP7INT_set/clr ,Mask Endpoint 7 Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " EP6INT_set/clr ,Mask Endpoint 6 Interrupt" "Masked,Not masked"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " EP5INT_set/clr ,Mask Endpoint 5 Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " EP4INT_set/clr ,Mask Endpoint 4 Interrupt" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " EP3INT_set/clr ,Mask Endpoint 3 Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " EP2INT_set/clr ,Mask Endpoint 2 Interrupt" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " EP1INT_set/clr ,Mask Endpoint 1 Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " EP0INT_set/clr ,Mask Endpoint 0 Interrupt" "Masked,Not masked"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "UDP_ISR,UDP Interrupt Status Register"
|
|
bitfld.long 0x0 13. " WAKEUP ,UDP Resume Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 12. " ENDBUSRES ,End of BUS Reset Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 11. " SOFINT ,Start of Frame Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 10. " EXTRSM ,External Resume Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 9. " RXRSM ,UDP Resume Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 8. " RXSUSP ,UDP Suspend Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif !cpuis("ATSAMG55")
|
|
bitfld.long 0x0 7. " EP7INT ,Endpoint 7 Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 6. " EP6INT ,Endpoint 6 Interrupt Status" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 5. " EP5INT ,Endpoint 5 Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 4. " EP4INT ,Endpoint 4 Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 3. " EP3INT ,Endpoint 3 Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 2. " EP2INT ,Endpoint 2 Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EP1INT ,Endpoint 1 Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 0. " EP0INT ,Endpoint 0 Interrupt Status" "No interrupt,Interrupt"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "UDP_ICR,UDP Interrupt Clear Register"
|
|
bitfld.long 0x0 13. " WAKEUP ,Clear Wakeup Interrupt" "No effect,Clear"
|
|
bitfld.long 0x00 12. " ENDBUSRES ,Clear End of BUS Reset Interrupt" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0 11. " SOFINT ,Clear Start Of Frame Interrupt" "No effect,Clear"
|
|
bitfld.long 0x0 10. " EXTRSM ,Clear External Resume Interrupt" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RXRSM ,Clear UDP Resume Interrupt" "No effect,Clear"
|
|
bitfld.long 0x00 8. " RXSUSP ,Clear UDP Suspend Interrupt" "No effect,Clear"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "UDP_RST_EP,UDP Reset Endpoint Register"
|
|
sif !cpuis("ATSAMG55")
|
|
bitfld.long 0x00 7. " EP7 ,Reset Endpoint 7" "No reset,Reset"
|
|
bitfld.long 0x00 6. " EP46 ,Reset Endpoint 6" "No reset,Reset"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " EP5 ,Reset Endpoint 5" "No reset,Reset"
|
|
bitfld.long 0x00 4. " EP4 ,Reset Endpoint 4" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EP3 ,Reset Endpoint 3" "No reset,Reset"
|
|
bitfld.long 0x00 2. " EP2 ,Reset Endpoint 2" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EP1 ,Reset Endpoint 1" "No reset,Reset"
|
|
bitfld.long 0x00 0. " EP0 ,Reset Endpoint 0" "No reset,Reset"
|
|
width 11.
|
|
tree "Endpoint Control and Status Registers"
|
|
if (((d.l((ad:0x40044000+0x30+0x0)))&0x700)==0x000)
|
|
group.long (0x30+0x0)++0x3
|
|
line.long 0x0 "UDP_CSR0,UDP Endpoint 0 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,,Bulk OUT,Interrupt OUT,,,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 7. " DIR ,Transfer Direction" "Data OUT,Data IN"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((d.l((ad:0x40044000+0x30+0x0)))&0x700)==(0x200||0x600)
|
|
group.long (0x30+0x0)++0x3
|
|
line.long 0x0 "UDP_CSR0,UDP Endpoint 0 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,,Bulk OUT,Interrupt OUT,,,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0x0)++0x3
|
|
line.long 0x0 "UDP_CSR0,UDP Endpoint 0 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,,Bulk OUT,Interrupt OUT,,,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
if ((d.l((ad:0x40044000+0x30+0x4)))&0x700)==(0x100||0x500)
|
|
group.long (0x30+0x4)++0x3
|
|
line.long 0x0 "UDP_CSR1,UDP Endpoint 1 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" ",Isochronous OUT,Bulk OUT,Interrupt OUT,,Isochronous IN,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " ISOERROR ,CRC Error in an Isochronous Transfer" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((d.l((ad:0x40044000+0x30+0x4)))&0x700)==(0x200||0x600)
|
|
group.long (0x30+0x4)++0x3
|
|
line.long 0x0 "UDP_CSR1,UDP Endpoint 1 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" ",Isochronous OUT,Bulk OUT,Interrupt OUT,,Isochronous IN,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0x4)++0x3
|
|
line.long 0x0 "UDP_CSR1,UDP Endpoint 1 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" ",Isochronous OUT,Bulk OUT,Interrupt OUT,,Isochronous IN,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
if ((d.l((ad:0x40044000+0x30+0x8)))&0x700)==(0x100||0x500)
|
|
group.long (0x30+0x8)++0x3
|
|
line.long 0x0 "UDP_CSR2,UDP Endpoint 2 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" ",Isochronous OUT,Bulk OUT,Interrupt OUT,,Isochronous IN,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " ISOERROR ,CRC Error in an Isochronous Transfer" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((d.l((ad:0x40044000+0x30+0x8)))&0x700)==(0x200||0x600)
|
|
group.long (0x30+0x8)++0x3
|
|
line.long 0x0 "UDP_CSR2,UDP Endpoint 2 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" ",Isochronous OUT,Bulk OUT,Interrupt OUT,,Isochronous IN,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0x8)++0x3
|
|
line.long 0x0 "UDP_CSR2,UDP Endpoint 2 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" ",Isochronous OUT,Bulk OUT,Interrupt OUT,,Isochronous IN,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
if (((d.l((ad:0x40044000+0x30+0xC)))&0x700)==0x000)
|
|
group.long (0x30+0xC)++0x3
|
|
line.long 0x0 "UDP_CSR3,UDP Endpoint 3 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,,Bulk OUT,Interrupt OUT,,,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 7. " DIR ,Transfer Direction" "Data OUT,Data IN"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((d.l((ad:0x40044000+0x30+0xC)))&0x700)==(0x200||0x600)
|
|
group.long (0x30+0xC)++0x3
|
|
line.long 0x0 "UDP_CSR3,UDP Endpoint 3 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,,Bulk OUT,Interrupt OUT,,,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0xC)++0x3
|
|
line.long 0x0 "UDP_CSR3,UDP Endpoint 3 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,,Bulk OUT,Interrupt OUT,,,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
if ((d.l((ad:0x40044000+0x30+0x10)))&0x700)==(0x100||0x500)
|
|
group.long (0x30+0x10)++0x3
|
|
line.long 0x0 "UDP_CSR4,UDP Endpoint 4 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" ",Isochronous OUT,Bulk OUT,Interrupt OUT,,Isochronous IN,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " ISOERROR ,CRC Error in an Isochronous Transfer" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((d.l((ad:0x40044000+0x30+0x10)))&0x700)==(0x200||0x600)
|
|
group.long (0x30+0x10)++0x3
|
|
line.long 0x0 "UDP_CSR4,UDP Endpoint 4 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" ",Isochronous OUT,Bulk OUT,Interrupt OUT,,Isochronous IN,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0x10)++0x3
|
|
line.long 0x0 "UDP_CSR4,UDP Endpoint 4 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" ",Isochronous OUT,Bulk OUT,Interrupt OUT,,Isochronous IN,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
if ((d.l((ad:0x40044000+0x30+0x14)))&0x700)==(0x100||0x500)
|
|
group.long (0x30+0x14)++0x3
|
|
line.long 0x0 "UDP_CSR5,UDP Endpoint 5 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" ",Isochronous OUT,Bulk OUT,Interrupt OUT,,Isochronous IN,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " ISOERROR ,CRC Error in an Isochronous Transfer" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((d.l((ad:0x40044000+0x30+0x14)))&0x700)==(0x200||0x600)
|
|
group.long (0x30+0x14)++0x3
|
|
line.long 0x0 "UDP_CSR5,UDP Endpoint 5 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" ",Isochronous OUT,Bulk OUT,Interrupt OUT,,Isochronous IN,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0x14)++0x3
|
|
line.long 0x0 "UDP_CSR5,UDP Endpoint 5 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" ",Isochronous OUT,Bulk OUT,Interrupt OUT,,Isochronous IN,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
tree.end
|
|
tree "UDP Endpoint FIFO Data Registers"
|
|
textline " "
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "UDP_FDR0,UDP Endpoint 0 FIFO Data Register"
|
|
in
|
|
hgroup.long 0x54++0x03
|
|
hide.long 0x00 "UDP_FDR1,UDP Endpoint 1 FIFO Data Register"
|
|
in
|
|
hgroup.long 0x58++0x03
|
|
hide.long 0x00 "UDP_FDR2,UDP Endpoint 2 FIFO Data Register"
|
|
in
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "UDP_FDR3,UDP Endpoint 3 FIFO Data Register"
|
|
in
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "UDP_FDR4,UDP Endpoint 4 FIFO Data Register"
|
|
in
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "UDP_FDR5,UDP Endpoint 5 FIFO Data Register"
|
|
in
|
|
; base vm:0x0
|
|
; wgroup 0x0++0x0
|
|
; base ad:0x40044000
|
|
tree.end
|
|
textline " "
|
|
width 14.
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "UDP_TXVC,UDP Transceiver Control Register"
|
|
bitfld.long 0x00 9. " PUON ,Pullup On" "Disconnected,Connected"
|
|
bitfld.long 0x00 8. " TXVDIS ,Transceiver Disable" "Enabled,Disabled"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
sif !cpuis("ATSAMG55")
|
|
tree.open "UART (Universal Asynchronous Receiver Transmitter)"
|
|
tree "UART0"
|
|
base ad:0x400E0600
|
|
width 12.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "UART_CR,UART Control Register"
|
|
sif (cpuis("ATSAMG53")||cpuis("ATSAMG54"))
|
|
bitfld.long 0x00 12. " REQCLR ,Request Clear" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enabled" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
sif (cpuis("ATSAMG53")||cpuis("ATSAMG54"))
|
|
if (((d.l(ad:0x400E0600+0xE4))&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "UART_MR,UART Mode Register"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Space,Mark,No,?..."
|
|
bitfld.long 0x00 4. " FILTER ,Receiver Digital Filter" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "UART_MR,UART Mode Register"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Space,Mark,No,?..."
|
|
bitfld.long 0x00 4. " FILTER ,Receiver Digital Filter" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "UART_MR,UART Mode Register"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Space,Mark,No,?..."
|
|
bitfld.long 0x00 4. " FILTER ,Receiver Digital Filter" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "UART_IMR,UART Interrupt Mask Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG53")
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " CMP_set/clr ,Mask Comparison Interrupt" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF ,Mask RXBUFF Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE ,Mask TXBUFE Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,Mask TXEMPTY Interrupt" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Mask Parity Error Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Mask Framing Error Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Mask Overrun Error Interrupt" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDTX_set/clr ,Mask End of Transmit Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,Mask End of Receive Transfer Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,Disable TXRDY Interrupt" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,Mask RXRDY Interrupt" "Masked,Not masked"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "UART_SR,UART Status Register"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "UART_RHR,UART Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "UART_THR,UART Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXCHR ,Character to be Transmitted"
|
|
sif (cpuis("ATSAMG53")||cpuis("ATSAMG54"))
|
|
if (((d.l(ad:0x400E0600+0xE4))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "UART_BRGR,UART Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divisor"
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "UART_BRGR,UART Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divisor"
|
|
endif
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "UART_BRGR,UART Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divisor"
|
|
endif
|
|
sif (cpuis("ATSAMG53")||cpuis("ATSAMG54"))
|
|
if (((d.l(ad:0x400E0600+0xE4))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "UART_CMPR, UART Comparison Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
bitfld.long 0x00 14. " CMPPAR ,Compare Parity" "Not checked,Checked"
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "Flag only,Start Condition"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
else
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "UART_CMPR, UART Comparison Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
bitfld.long 0x00 14. " CMPPAR ,Compare Parity" "Not checked,Checked"
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "Flag only,Start Condition"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "UART_WPMR,UART Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protection Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
endif
|
|
width 0xB
|
|
tree "UART0 PDC (Peripheral DMA Controller)"
|
|
width 12.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "UART0_RPR,Receive Pointer Register"
|
|
line.long 0x04 "UART0_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "UART0_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "UART0_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "UART0_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "UART0_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "UART0_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "UART0_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "UART0_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "UART0_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "UART1"
|
|
base ad:0x400E0800
|
|
width 12.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "UART_CR,UART Control Register"
|
|
sif (cpuis("ATSAMG53")||cpuis("ATSAMG54"))
|
|
bitfld.long 0x00 12. " REQCLR ,Request Clear" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enabled" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
sif (cpuis("ATSAMG53")||cpuis("ATSAMG54"))
|
|
if (((d.l(ad:0x400E0800+0xE4))&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "UART_MR,UART Mode Register"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Space,Mark,No,?..."
|
|
bitfld.long 0x00 4. " FILTER ,Receiver Digital Filter" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "UART_MR,UART Mode Register"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Space,Mark,No,?..."
|
|
bitfld.long 0x00 4. " FILTER ,Receiver Digital Filter" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "UART_MR,UART Mode Register"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Space,Mark,No,?..."
|
|
bitfld.long 0x00 4. " FILTER ,Receiver Digital Filter" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "UART_IMR,UART Interrupt Mask Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG53")
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " CMP_set/clr ,Mask Comparison Interrupt" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF ,Mask RXBUFF Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE ,Mask TXBUFE Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,Mask TXEMPTY Interrupt" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Mask Parity Error Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Mask Framing Error Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Mask Overrun Error Interrupt" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDTX_set/clr ,Mask End of Transmit Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,Mask End of Receive Transfer Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,Disable TXRDY Interrupt" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,Mask RXRDY Interrupt" "Masked,Not masked"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "UART_SR,UART Status Register"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "UART_RHR,UART Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "UART_THR,UART Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXCHR ,Character to be Transmitted"
|
|
sif (cpuis("ATSAMG53")||cpuis("ATSAMG54"))
|
|
if (((d.l(ad:0x400E0800+0xE4))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "UART_BRGR,UART Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divisor"
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "UART_BRGR,UART Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divisor"
|
|
endif
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "UART_BRGR,UART Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divisor"
|
|
endif
|
|
sif (cpuis("ATSAMG53")||cpuis("ATSAMG54"))
|
|
if (((d.l(ad:0x400E0800+0xE4))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "UART_CMPR, UART Comparison Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
bitfld.long 0x00 14. " CMPPAR ,Compare Parity" "Not checked,Checked"
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "Flag only,Start Condition"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
else
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "UART_CMPR, UART Comparison Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
bitfld.long 0x00 14. " CMPPAR ,Compare Parity" "Not checked,Checked"
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "Flag only,Start Condition"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "UART_WPMR,UART Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protection Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
endif
|
|
width 0xB
|
|
tree "UART1 PDC (Peripheral DMA Controller)"
|
|
width 12.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "UART1_RPR,Receive Pointer Register"
|
|
line.long 0x04 "UART1_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "UART1_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "UART1_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "UART1_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "UART1_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "UART1_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "UART1_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "UART1_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "UART1_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree.open "USART (Universal Synchronous Asynchronous Receiver Transceiver)"
|
|
sif (cpu()=="ATSAMG55")
|
|
tree "USART0"
|
|
base ad:0x4000C200
|
|
width 11.
|
|
if ((d.l((ad:0x4000C200)+0x04)&0x0F)==0x0E)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select (Release Slave Select Line NSS)" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select (Force Slave Select Line NSS to 0)" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((d.l((ad:0x4000C200)+0x04)&0x0F)==0x0F)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((d.l(ad:0x4000C200+0x04)&0x0F)==0x00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Pin Control" "No effect,Drive RTS to 1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Pin Control" "No effect,Drive RTS to 0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((d.l(ad:0x4000C200+0x04)&0x0F)==0x02)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Pin Control" "No effect,Drive RTS to 0"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Pin Control" "No effect,Drive RTS to 1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
if (((d.l((ad:0x400E0514)))&0x100)==0x100)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 28. " REQCLR ,Request to Clear the Comparison Trigger" "No effect,Clear"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 28. " REQCLR ,Request to Clear the Comparison Trigger" "No effect,Restart"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
endif
|
|
if ((d.l(ad:0x4000C200+0xE4)&0x01)==0x00)
|
|
if ((d.l(ad:0x4000C200+0x04)&0x0F)==(0x0E||0x0F))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" ",,,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-Low,Inactive-High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
else
|
|
if (((d.l(ad:0x4000C200+0x04))&0x100)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,1.5,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
endif
|
|
endif
|
|
else
|
|
if ((d.l(ad:0x4000C200+0x04)&0x0F)==(0x0E||0x0F))
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" ",,,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-Low,Inactive-High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
else
|
|
if (((d.l(ad:0x4000C200+0x04))&0x100)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Numer of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,1.5,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Numer of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
endif
|
|
endif
|
|
endif
|
|
if ((d.l(ad:0x4000C200+0x04)&0x0F)==(0x0E||0x0F))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " CMP_set/clr ,Comparison Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " NSSE_set/clr ,NSS Line Event (CTS pin) Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNRE_set/clr ,SPI Underrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Masked,Not masked"
|
|
elif ((d.l(ad:0x4000C200+0x04)&0x0F)==(0x0A||0x0B))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " LINHTE_set/clr , LIN Header Timeout Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " LINSTE_set/clr ,LIN Synch Tolerance Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " LINBK_set/clr ,LIN Break Sent or LIN Break Received Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Masked,Not masked"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " CMP_set/clr ,Comparison Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Masked,Not masked"
|
|
endif
|
|
if ((d.l(ad:0x4000C200+0x04)&0x0F)==(0x0E||0x0F))
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "US_CSR,Channel Status Register"
|
|
bitfld.long 0x00 23. " NSS ,Image Of NSS Line" "Driven low,Driven high"
|
|
bitfld.long 0x00 22. " CMP ,Comparison Match" "No match,Match"
|
|
bitfld.long 0x00 19. " NSSE ,NSS Line Rising Or Falling Edge Event" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 10. " UNRE ,Underrun Error" "No error,Error"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDTX ,End of TX Buffer" "Not reached 0,Reached 0"
|
|
bitfld.long 0x00 3. " ENDRX ,End of RX Buffer" "Not reached 0,Reached 0"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
elif ((d.l(ad:0x4000C200+0x04)&0x0F)==(0x0A||0x0B))
|
|
if ((d.l(ad:0x4000C200+0x04)&0x0F)==0x0A)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "US_CSR,Channel Status Register"
|
|
bitfld.long 0x00 31. " LINHTE ,LIN Header Timeout Error" "No error,Error"
|
|
bitfld.long 0x00 30. " LINSTE ,LIN Synch Tolerance Error" "No error,Error"
|
|
bitfld.long 0x00 29. " LINSNRE ,LIN Slave Not Responding Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 28. " LINCE ,LIN Checksum Error" "No error,Error"
|
|
bitfld.long 0x00 27. " LINIPE ,LIN Identifier Parity Error" "No error,Error"
|
|
bitfld.long 0x00 26. " LINISFE ,LIN Inconsistent Synch Field Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LINBE ,LIN Bit Error" "No error,Error"
|
|
bitfld.long 0x00 23. " LINBLS ,LIN Bus Line Status" "0,1"
|
|
bitfld.long 0x00 15. " LINTC ,LIN Transfer Completed" "Idle,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 14. " LINID ,LIN Identifier Sent or LIN Identifier Received" "No identifier received,Identifier received"
|
|
bitfld.long 0x00 13. " LINBK ,LIN Break Sent or LIN Break Received" "No break received,Break received"
|
|
bitfld.long 0x00 12. " RXBUFF ,RX Buffer Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TXBUFE ,TX Buffer Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 8. " TIMEOUT ,Receiver Time-out" "No time-out,Time-out"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PARE ,Parity Error" "No error,Error"
|
|
bitfld.long 0x00 6. " FRAME ,Framing Error" "No error,Error"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDTX ,End of TX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 3. " ENDRX ,End of RX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "US_CSR,Channel Status Register"
|
|
bitfld.long 0x00 31. " LINHTE ,LIN Header Timeout Error" "No error,Error"
|
|
bitfld.long 0x00 30. " LINSTE ,LIN Synch Tolerance Error" "No error,Error"
|
|
bitfld.long 0x00 29. " LINSNRE ,LIN Slave Not Responding Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 28. " LINCE ,LIN Checksum Error" "No error,Error"
|
|
bitfld.long 0x00 27. " LINIPE ,LIN Identifier Parity Error" "No error,Error"
|
|
bitfld.long 0x00 26. " LINISFE ,LIN Inconsistent Synch Field Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LINBE ,LIN Bit Error" "No error,Error"
|
|
bitfld.long 0x00 23. " LINBLS ,LIN Bus Line Status" "0,1"
|
|
bitfld.long 0x00 15. " LINTC ,LIN Transfer Completed" "Idle,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 14. " LINID ,LIN Identifier Sent or LIN Identifier Received" "No identifier received,Identifier received"
|
|
bitfld.long 0x00 13. " LINBK ,LIN Break Sent or LIN Break Received" "No break received,Break received"
|
|
bitfld.long 0x00 12. " RXBUFF ,RX Buffer Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TXBUFE ,TX Buffer Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 8. " TIMEOUT ,Receiver Time-out" "No time-out,Time-out"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PARE ,Parity Error" "No error,Error"
|
|
bitfld.long 0x00 6. " FRAME ,Framing Error" "No error,Error"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDTX ,End of TX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 3. " ENDRX ,End of RX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
endif
|
|
else
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "US_CSR,Channel Status Register"
|
|
in
|
|
endif
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RHR,Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "US_THR,Transmitter Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be transmitted"
|
|
if ((d.l(ad:0x4000C200+0xE4)&0x01)==0x00)
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "RTOR,Receiver Time-out Register"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TG ,Timeguard Value"
|
|
else
|
|
rgroup.long 0x20++0x07
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "RTOR,Receiver Time-out Register"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TG ,Timeguard Value"
|
|
endif
|
|
if ((d.l(ad:0x4000C200+0xE4)&0x01)==0x00)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 31. " RXIDLEV ,Receiver Idle Value" "0,1"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" ",1"
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0-to-1,1-to-0"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern Detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
else
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 31. " RXIDLEV ,Receiver Idle Value" "0,1"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" ",1"
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0-to-1,1-to-0"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern Detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
endif
|
|
if ((d.l(ad:0x4000C200+0xE4)&0x01)==0x00)
|
|
wgroup.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,USART FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
else
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,USART FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
endif
|
|
if (((d.l(ad:0x4000C200+0x04))&0x0F)==0x04)||(((d.l(ad:0x4000C200+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "US_NER,USART Number of Errors Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NB_ERRORS ,Number of Errors"
|
|
else
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US_NER,USART Number of Errors Register"
|
|
endif
|
|
if (((d.l(ad:0x4000C200+0x04))&0x08)==0x08)
|
|
if ((d.l(ad:0x4000C200+0xE4)&0x01)==0x00)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
else
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
endif
|
|
endif
|
|
if ((d.l(ad:0x4000C200+0x04)&0x0F)==(0x0A||0x0B))
|
|
if ((d.l(ad:0x4000C200+0xE4)&0x01)==0x00)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "US_LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x00 17. " SYNCDIS ,Synchronization Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " PDCM ,DMAC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data Length Control"
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "DLC,Bits 5 and 6 of LINIR"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "Enhanced,Classic"
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
else
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "US_LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x00 17. " SYNCDIS ,Synchronization Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " PDCM ,DMAC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data Length Control"
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "DLC,Bits 5 and 6 of LINIR"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "Enhanced,Classic"
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
endif
|
|
if ((d.l(ad:0x4000C200+0x04)&0x0F)==0x0A)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "US_LINBRR,USART LIN Baud Rate Register"
|
|
bitfld.long 0x00 16.--18. " LINFP ,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--15. 1. " LINCD ,Clock Divider after Synchronization"
|
|
endif
|
|
if ((d.l(ad:0x4000C200+0xE4)&0x01)==0x00)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "US_CMPR,USART Comparison Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
bitfld.long 0x00 14. " CMPPAR ,Compare Parity" "Not checked,Checked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "Flag_only,Start_condition"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
else
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "US_CMPR,USART Comparison Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
bitfld.long 0x00 14. " CMPPAR ,Compare Parity" "Not checked,Checked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "Flag_only,Start_condition"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,USART Write Protect Status Register"
|
|
in
|
|
width 0x0B
|
|
tree "USART0 PDC (Peripheral DMA Controller)"
|
|
width 12.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "USART0_RPR,Receive Pointer Register"
|
|
line.long 0x04 "USART0_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART0_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "USART0_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART0_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "USART0_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART0_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "USART0_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART0_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART0_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "USART1"
|
|
base ad:0x40020200
|
|
width 11.
|
|
if ((d.l((ad:0x40020200)+0x04)&0x0F)==0x0E)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select (Release Slave Select Line NSS)" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select (Force Slave Select Line NSS to 0)" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((d.l((ad:0x40020200)+0x04)&0x0F)==0x0F)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((d.l(ad:0x40020200+0x04)&0x0F)==0x00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Pin Control" "No effect,Drive RTS to 1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Pin Control" "No effect,Drive RTS to 0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((d.l(ad:0x40020200+0x04)&0x0F)==0x02)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Pin Control" "No effect,Drive RTS to 0"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Pin Control" "No effect,Drive RTS to 1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
if (((d.l((ad:0x400E0514)))&0x200)==0x200)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 28. " REQCLR ,Request to Clear the Comparison Trigger" "No effect,Clear"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 28. " REQCLR ,Request to Clear the Comparison Trigger" "No effect,Restart"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
endif
|
|
if ((d.l(ad:0x40020200+0xE4)&0x01)==0x00)
|
|
if ((d.l(ad:0x40020200+0x04)&0x0F)==(0x0E||0x0F))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" ",,,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-Low,Inactive-High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
else
|
|
if (((d.l(ad:0x40020200+0x04))&0x100)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,1.5,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
endif
|
|
endif
|
|
else
|
|
if ((d.l(ad:0x40020200+0x04)&0x0F)==(0x0E||0x0F))
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" ",,,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-Low,Inactive-High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
else
|
|
if (((d.l(ad:0x40020200+0x04))&0x100)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Numer of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,1.5,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Numer of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
endif
|
|
endif
|
|
endif
|
|
if ((d.l(ad:0x40020200+0x04)&0x0F)==(0x0E||0x0F))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " CMP_set/clr ,Comparison Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " NSSE_set/clr ,NSS Line Event (CTS pin) Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNRE_set/clr ,SPI Underrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Masked,Not masked"
|
|
elif ((d.l(ad:0x40020200+0x04)&0x0F)==(0x0A||0x0B))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " LINHTE_set/clr , LIN Header Timeout Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " LINSTE_set/clr ,LIN Synch Tolerance Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " LINBK_set/clr ,LIN Break Sent or LIN Break Received Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Masked,Not masked"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " CMP_set/clr ,Comparison Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Masked,Not masked"
|
|
endif
|
|
if ((d.l(ad:0x40020200+0x04)&0x0F)==(0x0E||0x0F))
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "US_CSR,Channel Status Register"
|
|
bitfld.long 0x00 23. " NSS ,Image Of NSS Line" "Driven low,Driven high"
|
|
bitfld.long 0x00 22. " CMP ,Comparison Match" "No match,Match"
|
|
bitfld.long 0x00 19. " NSSE ,NSS Line Rising Or Falling Edge Event" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 10. " UNRE ,Underrun Error" "No error,Error"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDTX ,End of TX Buffer" "Not reached 0,Reached 0"
|
|
bitfld.long 0x00 3. " ENDRX ,End of RX Buffer" "Not reached 0,Reached 0"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
elif ((d.l(ad:0x40020200+0x04)&0x0F)==(0x0A||0x0B))
|
|
if ((d.l(ad:0x40020200+0x04)&0x0F)==0x0A)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "US_CSR,Channel Status Register"
|
|
bitfld.long 0x00 31. " LINHTE ,LIN Header Timeout Error" "No error,Error"
|
|
bitfld.long 0x00 30. " LINSTE ,LIN Synch Tolerance Error" "No error,Error"
|
|
bitfld.long 0x00 29. " LINSNRE ,LIN Slave Not Responding Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 28. " LINCE ,LIN Checksum Error" "No error,Error"
|
|
bitfld.long 0x00 27. " LINIPE ,LIN Identifier Parity Error" "No error,Error"
|
|
bitfld.long 0x00 26. " LINISFE ,LIN Inconsistent Synch Field Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LINBE ,LIN Bit Error" "No error,Error"
|
|
bitfld.long 0x00 23. " LINBLS ,LIN Bus Line Status" "0,1"
|
|
bitfld.long 0x00 15. " LINTC ,LIN Transfer Completed" "Idle,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 14. " LINID ,LIN Identifier Sent or LIN Identifier Received" "No identifier received,Identifier received"
|
|
bitfld.long 0x00 13. " LINBK ,LIN Break Sent or LIN Break Received" "No break received,Break received"
|
|
bitfld.long 0x00 12. " RXBUFF ,RX Buffer Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TXBUFE ,TX Buffer Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 8. " TIMEOUT ,Receiver Time-out" "No time-out,Time-out"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PARE ,Parity Error" "No error,Error"
|
|
bitfld.long 0x00 6. " FRAME ,Framing Error" "No error,Error"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDTX ,End of TX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 3. " ENDRX ,End of RX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "US_CSR,Channel Status Register"
|
|
bitfld.long 0x00 31. " LINHTE ,LIN Header Timeout Error" "No error,Error"
|
|
bitfld.long 0x00 30. " LINSTE ,LIN Synch Tolerance Error" "No error,Error"
|
|
bitfld.long 0x00 29. " LINSNRE ,LIN Slave Not Responding Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 28. " LINCE ,LIN Checksum Error" "No error,Error"
|
|
bitfld.long 0x00 27. " LINIPE ,LIN Identifier Parity Error" "No error,Error"
|
|
bitfld.long 0x00 26. " LINISFE ,LIN Inconsistent Synch Field Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LINBE ,LIN Bit Error" "No error,Error"
|
|
bitfld.long 0x00 23. " LINBLS ,LIN Bus Line Status" "0,1"
|
|
bitfld.long 0x00 15. " LINTC ,LIN Transfer Completed" "Idle,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 14. " LINID ,LIN Identifier Sent or LIN Identifier Received" "No identifier received,Identifier received"
|
|
bitfld.long 0x00 13. " LINBK ,LIN Break Sent or LIN Break Received" "No break received,Break received"
|
|
bitfld.long 0x00 12. " RXBUFF ,RX Buffer Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TXBUFE ,TX Buffer Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 8. " TIMEOUT ,Receiver Time-out" "No time-out,Time-out"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PARE ,Parity Error" "No error,Error"
|
|
bitfld.long 0x00 6. " FRAME ,Framing Error" "No error,Error"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDTX ,End of TX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 3. " ENDRX ,End of RX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
endif
|
|
else
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "US_CSR,Channel Status Register"
|
|
in
|
|
endif
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RHR,Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "US_THR,Transmitter Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be transmitted"
|
|
if ((d.l(ad:0x40020200+0xE4)&0x01)==0x00)
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "RTOR,Receiver Time-out Register"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TG ,Timeguard Value"
|
|
else
|
|
rgroup.long 0x20++0x07
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "RTOR,Receiver Time-out Register"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TG ,Timeguard Value"
|
|
endif
|
|
if ((d.l(ad:0x40020200+0xE4)&0x01)==0x00)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 31. " RXIDLEV ,Receiver Idle Value" "0,1"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" ",1"
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0-to-1,1-to-0"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern Detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
else
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 31. " RXIDLEV ,Receiver Idle Value" "0,1"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" ",1"
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0-to-1,1-to-0"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern Detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
endif
|
|
if ((d.l(ad:0x40020200+0xE4)&0x01)==0x00)
|
|
wgroup.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,USART FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
else
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,USART FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
endif
|
|
if (((d.l(ad:0x40020200+0x04))&0x0F)==0x04)||(((d.l(ad:0x40020200+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "US_NER,USART Number of Errors Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NB_ERRORS ,Number of Errors"
|
|
else
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US_NER,USART Number of Errors Register"
|
|
endif
|
|
if (((d.l(ad:0x40020200+0x04))&0x08)==0x08)
|
|
if ((d.l(ad:0x40020200+0xE4)&0x01)==0x00)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
else
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
endif
|
|
endif
|
|
if ((d.l(ad:0x40020200+0x04)&0x0F)==(0x0A||0x0B))
|
|
if ((d.l(ad:0x40020200+0xE4)&0x01)==0x00)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "US_LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x00 17. " SYNCDIS ,Synchronization Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " PDCM ,DMAC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data Length Control"
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "DLC,Bits 5 and 6 of LINIR"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "Enhanced,Classic"
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
else
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "US_LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x00 17. " SYNCDIS ,Synchronization Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " PDCM ,DMAC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data Length Control"
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "DLC,Bits 5 and 6 of LINIR"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "Enhanced,Classic"
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
endif
|
|
if ((d.l(ad:0x40020200+0x04)&0x0F)==0x0A)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "US_LINBRR,USART LIN Baud Rate Register"
|
|
bitfld.long 0x00 16.--18. " LINFP ,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--15. 1. " LINCD ,Clock Divider after Synchronization"
|
|
endif
|
|
if ((d.l(ad:0x40020200+0xE4)&0x01)==0x00)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "US_CMPR,USART Comparison Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
bitfld.long 0x00 14. " CMPPAR ,Compare Parity" "Not checked,Checked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "Flag_only,Start_condition"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
else
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "US_CMPR,USART Comparison Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
bitfld.long 0x00 14. " CMPPAR ,Compare Parity" "Not checked,Checked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "Flag_only,Start_condition"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,USART Write Protect Status Register"
|
|
in
|
|
width 0x0B
|
|
tree "USART1 PDC (Peripheral DMA Controller)"
|
|
width 12.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "USART1_RPR,Receive Pointer Register"
|
|
line.long 0x04 "USART1_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART1_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "USART1_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART1_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "USART1_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART1_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "USART1_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART1_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART1_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "USART2"
|
|
base ad:0x40024200
|
|
width 11.
|
|
if ((d.l((ad:0x40024200)+0x04)&0x0F)==0x0E)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select (Release Slave Select Line NSS)" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select (Force Slave Select Line NSS to 0)" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((d.l((ad:0x40024200)+0x04)&0x0F)==0x0F)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((d.l(ad:0x40024200+0x04)&0x0F)==0x00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Pin Control" "No effect,Drive RTS to 1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Pin Control" "No effect,Drive RTS to 0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((d.l(ad:0x40024200+0x04)&0x0F)==0x02)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Pin Control" "No effect,Drive RTS to 0"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Pin Control" "No effect,Drive RTS to 1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
if (((d.l((ad:0x400E0514)))&0x4000)==0x4000)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 28. " REQCLR ,Request to Clear the Comparison Trigger" "No effect,Clear"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 28. " REQCLR ,Request to Clear the Comparison Trigger" "No effect,Restart"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
endif
|
|
if ((d.l(ad:0x40024200+0xE4)&0x01)==0x00)
|
|
if ((d.l(ad:0x40024200+0x04)&0x0F)==(0x0E||0x0F))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" ",,,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-Low,Inactive-High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
else
|
|
if (((d.l(ad:0x40024200+0x04))&0x100)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,1.5,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
endif
|
|
endif
|
|
else
|
|
if ((d.l(ad:0x40024200+0x04)&0x0F)==(0x0E||0x0F))
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" ",,,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-Low,Inactive-High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
else
|
|
if (((d.l(ad:0x40024200+0x04))&0x100)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Numer of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,1.5,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Numer of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
endif
|
|
endif
|
|
endif
|
|
if ((d.l(ad:0x40024200+0x04)&0x0F)==(0x0E||0x0F))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " CMP_set/clr ,Comparison Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " NSSE_set/clr ,NSS Line Event (CTS pin) Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNRE_set/clr ,SPI Underrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Masked,Not masked"
|
|
elif ((d.l(ad:0x40024200+0x04)&0x0F)==(0x0A||0x0B))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " LINHTE_set/clr , LIN Header Timeout Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " LINSTE_set/clr ,LIN Synch Tolerance Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " LINBK_set/clr ,LIN Break Sent or LIN Break Received Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Masked,Not masked"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " CMP_set/clr ,Comparison Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Masked,Not masked"
|
|
endif
|
|
if ((d.l(ad:0x40024200+0x04)&0x0F)==(0x0E||0x0F))
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "US_CSR,Channel Status Register"
|
|
bitfld.long 0x00 23. " NSS ,Image Of NSS Line" "Driven low,Driven high"
|
|
bitfld.long 0x00 22. " CMP ,Comparison Match" "No match,Match"
|
|
bitfld.long 0x00 19. " NSSE ,NSS Line Rising Or Falling Edge Event" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 10. " UNRE ,Underrun Error" "No error,Error"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDTX ,End of TX Buffer" "Not reached 0,Reached 0"
|
|
bitfld.long 0x00 3. " ENDRX ,End of RX Buffer" "Not reached 0,Reached 0"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
elif ((d.l(ad:0x40024200+0x04)&0x0F)==(0x0A||0x0B))
|
|
if ((d.l(ad:0x40024200+0x04)&0x0F)==0x0A)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "US_CSR,Channel Status Register"
|
|
bitfld.long 0x00 31. " LINHTE ,LIN Header Timeout Error" "No error,Error"
|
|
bitfld.long 0x00 30. " LINSTE ,LIN Synch Tolerance Error" "No error,Error"
|
|
bitfld.long 0x00 29. " LINSNRE ,LIN Slave Not Responding Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 28. " LINCE ,LIN Checksum Error" "No error,Error"
|
|
bitfld.long 0x00 27. " LINIPE ,LIN Identifier Parity Error" "No error,Error"
|
|
bitfld.long 0x00 26. " LINISFE ,LIN Inconsistent Synch Field Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LINBE ,LIN Bit Error" "No error,Error"
|
|
bitfld.long 0x00 23. " LINBLS ,LIN Bus Line Status" "0,1"
|
|
bitfld.long 0x00 15. " LINTC ,LIN Transfer Completed" "Idle,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 14. " LINID ,LIN Identifier Sent or LIN Identifier Received" "No identifier received,Identifier received"
|
|
bitfld.long 0x00 13. " LINBK ,LIN Break Sent or LIN Break Received" "No break received,Break received"
|
|
bitfld.long 0x00 12. " RXBUFF ,RX Buffer Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TXBUFE ,TX Buffer Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 8. " TIMEOUT ,Receiver Time-out" "No time-out,Time-out"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PARE ,Parity Error" "No error,Error"
|
|
bitfld.long 0x00 6. " FRAME ,Framing Error" "No error,Error"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDTX ,End of TX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 3. " ENDRX ,End of RX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "US_CSR,Channel Status Register"
|
|
bitfld.long 0x00 31. " LINHTE ,LIN Header Timeout Error" "No error,Error"
|
|
bitfld.long 0x00 30. " LINSTE ,LIN Synch Tolerance Error" "No error,Error"
|
|
bitfld.long 0x00 29. " LINSNRE ,LIN Slave Not Responding Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 28. " LINCE ,LIN Checksum Error" "No error,Error"
|
|
bitfld.long 0x00 27. " LINIPE ,LIN Identifier Parity Error" "No error,Error"
|
|
bitfld.long 0x00 26. " LINISFE ,LIN Inconsistent Synch Field Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LINBE ,LIN Bit Error" "No error,Error"
|
|
bitfld.long 0x00 23. " LINBLS ,LIN Bus Line Status" "0,1"
|
|
bitfld.long 0x00 15. " LINTC ,LIN Transfer Completed" "Idle,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 14. " LINID ,LIN Identifier Sent or LIN Identifier Received" "No identifier received,Identifier received"
|
|
bitfld.long 0x00 13. " LINBK ,LIN Break Sent or LIN Break Received" "No break received,Break received"
|
|
bitfld.long 0x00 12. " RXBUFF ,RX Buffer Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TXBUFE ,TX Buffer Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 8. " TIMEOUT ,Receiver Time-out" "No time-out,Time-out"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PARE ,Parity Error" "No error,Error"
|
|
bitfld.long 0x00 6. " FRAME ,Framing Error" "No error,Error"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDTX ,End of TX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 3. " ENDRX ,End of RX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
endif
|
|
else
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "US_CSR,Channel Status Register"
|
|
in
|
|
endif
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RHR,Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "US_THR,Transmitter Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be transmitted"
|
|
if ((d.l(ad:0x40024200+0xE4)&0x01)==0x00)
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "RTOR,Receiver Time-out Register"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TG ,Timeguard Value"
|
|
else
|
|
rgroup.long 0x20++0x07
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "RTOR,Receiver Time-out Register"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TG ,Timeguard Value"
|
|
endif
|
|
if ((d.l(ad:0x40024200+0xE4)&0x01)==0x00)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 31. " RXIDLEV ,Receiver Idle Value" "0,1"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" ",1"
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0-to-1,1-to-0"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern Detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
else
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 31. " RXIDLEV ,Receiver Idle Value" "0,1"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" ",1"
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0-to-1,1-to-0"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern Detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
endif
|
|
if ((d.l(ad:0x40024200+0xE4)&0x01)==0x00)
|
|
wgroup.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,USART FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
else
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,USART FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
endif
|
|
if (((d.l(ad:0x40024200+0x04))&0x0F)==0x04)||(((d.l(ad:0x40024200+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "US_NER,USART Number of Errors Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NB_ERRORS ,Number of Errors"
|
|
else
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US_NER,USART Number of Errors Register"
|
|
endif
|
|
if (((d.l(ad:0x40024200+0x04))&0x08)==0x08)
|
|
if ((d.l(ad:0x40024200+0xE4)&0x01)==0x00)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
else
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
endif
|
|
endif
|
|
if ((d.l(ad:0x40024200+0x04)&0x0F)==(0x0A||0x0B))
|
|
if ((d.l(ad:0x40024200+0xE4)&0x01)==0x00)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "US_LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x00 17. " SYNCDIS ,Synchronization Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " PDCM ,DMAC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data Length Control"
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "DLC,Bits 5 and 6 of LINIR"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "Enhanced,Classic"
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
else
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "US_LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x00 17. " SYNCDIS ,Synchronization Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " PDCM ,DMAC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data Length Control"
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "DLC,Bits 5 and 6 of LINIR"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "Enhanced,Classic"
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
endif
|
|
if ((d.l(ad:0x40024200+0x04)&0x0F)==0x0A)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "US_LINBRR,USART LIN Baud Rate Register"
|
|
bitfld.long 0x00 16.--18. " LINFP ,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--15. 1. " LINCD ,Clock Divider after Synchronization"
|
|
endif
|
|
if ((d.l(ad:0x40024200+0xE4)&0x01)==0x00)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "US_CMPR,USART Comparison Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
bitfld.long 0x00 14. " CMPPAR ,Compare Parity" "Not checked,Checked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "Flag_only,Start_condition"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
else
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "US_CMPR,USART Comparison Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
bitfld.long 0x00 14. " CMPPAR ,Compare Parity" "Not checked,Checked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "Flag_only,Start_condition"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,USART Write Protect Status Register"
|
|
in
|
|
width 0x0B
|
|
tree "USART2 PDC (Peripheral DMA Controller)"
|
|
width 12.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "USART2_RPR,Receive Pointer Register"
|
|
line.long 0x04 "USART2_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART2_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "USART2_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART2_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "USART2_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART2_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "USART2_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART2_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART2_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "USART3"
|
|
base ad:0x40018200
|
|
width 11.
|
|
if ((d.l((ad:0x40018200)+0x04)&0x0F)==0x0E)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select (Release Slave Select Line NSS)" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select (Force Slave Select Line NSS to 0)" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((d.l((ad:0x40018200)+0x04)&0x0F)==0x0F)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((d.l(ad:0x40018200+0x04)&0x0F)==0x00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Pin Control" "No effect,Drive RTS to 1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Pin Control" "No effect,Drive RTS to 0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((d.l(ad:0x40018200+0x04)&0x0F)==0x02)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Pin Control" "No effect,Drive RTS to 0"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Pin Control" "No effect,Drive RTS to 1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
if (((d.l((ad:0x400E0514)))&0x80000)==0x80000)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 28. " REQCLR ,Request to Clear the Comparison Trigger" "No effect,Clear"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 28. " REQCLR ,Request to Clear the Comparison Trigger" "No effect,Restart"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
endif
|
|
if ((d.l(ad:0x40018200+0xE4)&0x01)==0x00)
|
|
if ((d.l(ad:0x40018200+0x04)&0x0F)==(0x0E||0x0F))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" ",,,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-Low,Inactive-High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
else
|
|
if (((d.l(ad:0x40018200+0x04))&0x100)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,1.5,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
endif
|
|
endif
|
|
else
|
|
if ((d.l(ad:0x40018200+0x04)&0x0F)==(0x0E||0x0F))
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" ",,,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-Low,Inactive-High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
else
|
|
if (((d.l(ad:0x40018200+0x04))&0x100)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Numer of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,1.5,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Numer of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
endif
|
|
endif
|
|
endif
|
|
if ((d.l(ad:0x40018200+0x04)&0x0F)==(0x0E||0x0F))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " CMP_set/clr ,Comparison Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " NSSE_set/clr ,NSS Line Event (CTS pin) Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNRE_set/clr ,SPI Underrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Masked,Not masked"
|
|
elif ((d.l(ad:0x40018200+0x04)&0x0F)==(0x0A||0x0B))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " LINHTE_set/clr , LIN Header Timeout Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " LINSTE_set/clr ,LIN Synch Tolerance Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " LINBK_set/clr ,LIN Break Sent or LIN Break Received Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Masked,Not masked"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " CMP_set/clr ,Comparison Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Masked,Not masked"
|
|
endif
|
|
if ((d.l(ad:0x40018200+0x04)&0x0F)==(0x0E||0x0F))
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "US_CSR,Channel Status Register"
|
|
bitfld.long 0x00 23. " NSS ,Image Of NSS Line" "Driven low,Driven high"
|
|
bitfld.long 0x00 22. " CMP ,Comparison Match" "No match,Match"
|
|
bitfld.long 0x00 19. " NSSE ,NSS Line Rising Or Falling Edge Event" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 10. " UNRE ,Underrun Error" "No error,Error"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDTX ,End of TX Buffer" "Not reached 0,Reached 0"
|
|
bitfld.long 0x00 3. " ENDRX ,End of RX Buffer" "Not reached 0,Reached 0"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
elif ((d.l(ad:0x40018200+0x04)&0x0F)==(0x0A||0x0B))
|
|
if ((d.l(ad:0x40018200+0x04)&0x0F)==0x0A)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "US_CSR,Channel Status Register"
|
|
bitfld.long 0x00 31. " LINHTE ,LIN Header Timeout Error" "No error,Error"
|
|
bitfld.long 0x00 30. " LINSTE ,LIN Synch Tolerance Error" "No error,Error"
|
|
bitfld.long 0x00 29. " LINSNRE ,LIN Slave Not Responding Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 28. " LINCE ,LIN Checksum Error" "No error,Error"
|
|
bitfld.long 0x00 27. " LINIPE ,LIN Identifier Parity Error" "No error,Error"
|
|
bitfld.long 0x00 26. " LINISFE ,LIN Inconsistent Synch Field Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LINBE ,LIN Bit Error" "No error,Error"
|
|
bitfld.long 0x00 23. " LINBLS ,LIN Bus Line Status" "0,1"
|
|
bitfld.long 0x00 15. " LINTC ,LIN Transfer Completed" "Idle,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 14. " LINID ,LIN Identifier Sent or LIN Identifier Received" "No identifier received,Identifier received"
|
|
bitfld.long 0x00 13. " LINBK ,LIN Break Sent or LIN Break Received" "No break received,Break received"
|
|
bitfld.long 0x00 12. " RXBUFF ,RX Buffer Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TXBUFE ,TX Buffer Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 8. " TIMEOUT ,Receiver Time-out" "No time-out,Time-out"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PARE ,Parity Error" "No error,Error"
|
|
bitfld.long 0x00 6. " FRAME ,Framing Error" "No error,Error"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDTX ,End of TX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 3. " ENDRX ,End of RX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "US_CSR,Channel Status Register"
|
|
bitfld.long 0x00 31. " LINHTE ,LIN Header Timeout Error" "No error,Error"
|
|
bitfld.long 0x00 30. " LINSTE ,LIN Synch Tolerance Error" "No error,Error"
|
|
bitfld.long 0x00 29. " LINSNRE ,LIN Slave Not Responding Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 28. " LINCE ,LIN Checksum Error" "No error,Error"
|
|
bitfld.long 0x00 27. " LINIPE ,LIN Identifier Parity Error" "No error,Error"
|
|
bitfld.long 0x00 26. " LINISFE ,LIN Inconsistent Synch Field Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LINBE ,LIN Bit Error" "No error,Error"
|
|
bitfld.long 0x00 23. " LINBLS ,LIN Bus Line Status" "0,1"
|
|
bitfld.long 0x00 15. " LINTC ,LIN Transfer Completed" "Idle,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 14. " LINID ,LIN Identifier Sent or LIN Identifier Received" "No identifier received,Identifier received"
|
|
bitfld.long 0x00 13. " LINBK ,LIN Break Sent or LIN Break Received" "No break received,Break received"
|
|
bitfld.long 0x00 12. " RXBUFF ,RX Buffer Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TXBUFE ,TX Buffer Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 8. " TIMEOUT ,Receiver Time-out" "No time-out,Time-out"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PARE ,Parity Error" "No error,Error"
|
|
bitfld.long 0x00 6. " FRAME ,Framing Error" "No error,Error"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDTX ,End of TX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 3. " ENDRX ,End of RX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
endif
|
|
else
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "US_CSR,Channel Status Register"
|
|
in
|
|
endif
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RHR,Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "US_THR,Transmitter Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be transmitted"
|
|
if ((d.l(ad:0x40018200+0xE4)&0x01)==0x00)
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "RTOR,Receiver Time-out Register"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TG ,Timeguard Value"
|
|
else
|
|
rgroup.long 0x20++0x07
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "RTOR,Receiver Time-out Register"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TG ,Timeguard Value"
|
|
endif
|
|
if ((d.l(ad:0x40018200+0xE4)&0x01)==0x00)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 31. " RXIDLEV ,Receiver Idle Value" "0,1"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" ",1"
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0-to-1,1-to-0"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern Detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
else
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 31. " RXIDLEV ,Receiver Idle Value" "0,1"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" ",1"
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0-to-1,1-to-0"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern Detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
endif
|
|
if ((d.l(ad:0x40018200+0xE4)&0x01)==0x00)
|
|
wgroup.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,USART FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
else
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,USART FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
endif
|
|
if (((d.l(ad:0x40018200+0x04))&0x0F)==0x04)||(((d.l(ad:0x40018200+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "US_NER,USART Number of Errors Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NB_ERRORS ,Number of Errors"
|
|
else
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US_NER,USART Number of Errors Register"
|
|
endif
|
|
if (((d.l(ad:0x40018200+0x04))&0x08)==0x08)
|
|
if ((d.l(ad:0x40018200+0xE4)&0x01)==0x00)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
else
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
endif
|
|
endif
|
|
if ((d.l(ad:0x40018200+0x04)&0x0F)==(0x0A||0x0B))
|
|
if ((d.l(ad:0x40018200+0xE4)&0x01)==0x00)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "US_LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x00 17. " SYNCDIS ,Synchronization Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " PDCM ,DMAC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data Length Control"
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "DLC,Bits 5 and 6 of LINIR"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "Enhanced,Classic"
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
else
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "US_LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x00 17. " SYNCDIS ,Synchronization Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " PDCM ,DMAC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data Length Control"
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "DLC,Bits 5 and 6 of LINIR"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "Enhanced,Classic"
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
endif
|
|
if ((d.l(ad:0x40018200+0x04)&0x0F)==0x0A)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "US_LINBRR,USART LIN Baud Rate Register"
|
|
bitfld.long 0x00 16.--18. " LINFP ,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--15. 1. " LINCD ,Clock Divider after Synchronization"
|
|
endif
|
|
if ((d.l(ad:0x40018200+0xE4)&0x01)==0x00)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "US_CMPR,USART Comparison Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
bitfld.long 0x00 14. " CMPPAR ,Compare Parity" "Not checked,Checked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "Flag_only,Start_condition"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
else
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "US_CMPR,USART Comparison Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
bitfld.long 0x00 14. " CMPPAR ,Compare Parity" "Not checked,Checked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "Flag_only,Start_condition"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,USART Write Protect Status Register"
|
|
in
|
|
width 0x0B
|
|
tree "USART3 PDC (Peripheral DMA Controller)"
|
|
width 12.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "USART3_RPR,Receive Pointer Register"
|
|
line.long 0x04 "USART3_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART3_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "USART3_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART3_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "USART3_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART3_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "USART3_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART3_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART3_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "USART4"
|
|
base ad:0x4001C200
|
|
width 11.
|
|
if ((d.l((ad:0x4001C200)+0x04)&0x0F)==0x0E)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select (Release Slave Select Line NSS)" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select (Force Slave Select Line NSS to 0)" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((d.l((ad:0x4001C200)+0x04)&0x0F)==0x0F)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((d.l(ad:0x4001C200+0x04)&0x0F)==0x00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Pin Control" "No effect,Drive RTS to 1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Pin Control" "No effect,Drive RTS to 0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((d.l(ad:0x4001C200+0x04)&0x0F)==0x02)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Pin Control" "No effect,Drive RTS to 0"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Pin Control" "No effect,Drive RTS to 1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
if (((d.l((ad:0x400E0514)))&0x100000)==0x100000)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 28. " REQCLR ,Request to Clear the Comparison Trigger" "No effect,Clear"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 28. " REQCLR ,Request to Clear the Comparison Trigger" "No effect,Restart"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
endif
|
|
if ((d.l(ad:0x4001C200+0xE4)&0x01)==0x00)
|
|
if ((d.l(ad:0x4001C200+0x04)&0x0F)==(0x0E||0x0F))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" ",,,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-Low,Inactive-High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
else
|
|
if (((d.l(ad:0x4001C200+0x04))&0x100)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,1.5,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
endif
|
|
endif
|
|
else
|
|
if ((d.l(ad:0x4001C200+0x04)&0x0F)==(0x0E||0x0F))
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" ",,,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-Low,Inactive-High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
else
|
|
if (((d.l(ad:0x4001C200+0x04))&0x100)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Numer of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,1.5,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Numer of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
endif
|
|
endif
|
|
endif
|
|
if ((d.l(ad:0x4001C200+0x04)&0x0F)==(0x0E||0x0F))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " CMP_set/clr ,Comparison Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " NSSE_set/clr ,NSS Line Event (CTS pin) Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNRE_set/clr ,SPI Underrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Masked,Not masked"
|
|
elif ((d.l(ad:0x4001C200+0x04)&0x0F)==(0x0A||0x0B))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " LINHTE_set/clr , LIN Header Timeout Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " LINSTE_set/clr ,LIN Synch Tolerance Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " LINBK_set/clr ,LIN Break Sent or LIN Break Received Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Masked,Not masked"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " CMP_set/clr ,Comparison Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Masked,Not masked"
|
|
endif
|
|
if ((d.l(ad:0x4001C200+0x04)&0x0F)==(0x0E||0x0F))
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "US_CSR,Channel Status Register"
|
|
bitfld.long 0x00 23. " NSS ,Image Of NSS Line" "Driven low,Driven high"
|
|
bitfld.long 0x00 22. " CMP ,Comparison Match" "No match,Match"
|
|
bitfld.long 0x00 19. " NSSE ,NSS Line Rising Or Falling Edge Event" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 10. " UNRE ,Underrun Error" "No error,Error"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDTX ,End of TX Buffer" "Not reached 0,Reached 0"
|
|
bitfld.long 0x00 3. " ENDRX ,End of RX Buffer" "Not reached 0,Reached 0"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
elif ((d.l(ad:0x4001C200+0x04)&0x0F)==(0x0A||0x0B))
|
|
if ((d.l(ad:0x4001C200+0x04)&0x0F)==0x0A)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "US_CSR,Channel Status Register"
|
|
bitfld.long 0x00 31. " LINHTE ,LIN Header Timeout Error" "No error,Error"
|
|
bitfld.long 0x00 30. " LINSTE ,LIN Synch Tolerance Error" "No error,Error"
|
|
bitfld.long 0x00 29. " LINSNRE ,LIN Slave Not Responding Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 28. " LINCE ,LIN Checksum Error" "No error,Error"
|
|
bitfld.long 0x00 27. " LINIPE ,LIN Identifier Parity Error" "No error,Error"
|
|
bitfld.long 0x00 26. " LINISFE ,LIN Inconsistent Synch Field Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LINBE ,LIN Bit Error" "No error,Error"
|
|
bitfld.long 0x00 23. " LINBLS ,LIN Bus Line Status" "0,1"
|
|
bitfld.long 0x00 15. " LINTC ,LIN Transfer Completed" "Idle,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 14. " LINID ,LIN Identifier Sent or LIN Identifier Received" "No identifier received,Identifier received"
|
|
bitfld.long 0x00 13. " LINBK ,LIN Break Sent or LIN Break Received" "No break received,Break received"
|
|
bitfld.long 0x00 12. " RXBUFF ,RX Buffer Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TXBUFE ,TX Buffer Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 8. " TIMEOUT ,Receiver Time-out" "No time-out,Time-out"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PARE ,Parity Error" "No error,Error"
|
|
bitfld.long 0x00 6. " FRAME ,Framing Error" "No error,Error"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDTX ,End of TX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 3. " ENDRX ,End of RX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "US_CSR,Channel Status Register"
|
|
bitfld.long 0x00 31. " LINHTE ,LIN Header Timeout Error" "No error,Error"
|
|
bitfld.long 0x00 30. " LINSTE ,LIN Synch Tolerance Error" "No error,Error"
|
|
bitfld.long 0x00 29. " LINSNRE ,LIN Slave Not Responding Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 28. " LINCE ,LIN Checksum Error" "No error,Error"
|
|
bitfld.long 0x00 27. " LINIPE ,LIN Identifier Parity Error" "No error,Error"
|
|
bitfld.long 0x00 26. " LINISFE ,LIN Inconsistent Synch Field Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LINBE ,LIN Bit Error" "No error,Error"
|
|
bitfld.long 0x00 23. " LINBLS ,LIN Bus Line Status" "0,1"
|
|
bitfld.long 0x00 15. " LINTC ,LIN Transfer Completed" "Idle,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 14. " LINID ,LIN Identifier Sent or LIN Identifier Received" "No identifier received,Identifier received"
|
|
bitfld.long 0x00 13. " LINBK ,LIN Break Sent or LIN Break Received" "No break received,Break received"
|
|
bitfld.long 0x00 12. " RXBUFF ,RX Buffer Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TXBUFE ,TX Buffer Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 8. " TIMEOUT ,Receiver Time-out" "No time-out,Time-out"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PARE ,Parity Error" "No error,Error"
|
|
bitfld.long 0x00 6. " FRAME ,Framing Error" "No error,Error"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDTX ,End of TX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 3. " ENDRX ,End of RX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
endif
|
|
else
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "US_CSR,Channel Status Register"
|
|
in
|
|
endif
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RHR,Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "US_THR,Transmitter Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be transmitted"
|
|
if ((d.l(ad:0x4001C200+0xE4)&0x01)==0x00)
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "RTOR,Receiver Time-out Register"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TG ,Timeguard Value"
|
|
else
|
|
rgroup.long 0x20++0x07
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "RTOR,Receiver Time-out Register"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TG ,Timeguard Value"
|
|
endif
|
|
if ((d.l(ad:0x4001C200+0xE4)&0x01)==0x00)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 31. " RXIDLEV ,Receiver Idle Value" "0,1"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" ",1"
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0-to-1,1-to-0"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern Detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
else
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 31. " RXIDLEV ,Receiver Idle Value" "0,1"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" ",1"
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0-to-1,1-to-0"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern Detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
endif
|
|
if ((d.l(ad:0x4001C200+0xE4)&0x01)==0x00)
|
|
wgroup.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,USART FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
else
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,USART FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
endif
|
|
if (((d.l(ad:0x4001C200+0x04))&0x0F)==0x04)||(((d.l(ad:0x4001C200+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "US_NER,USART Number of Errors Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NB_ERRORS ,Number of Errors"
|
|
else
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US_NER,USART Number of Errors Register"
|
|
endif
|
|
if (((d.l(ad:0x4001C200+0x04))&0x08)==0x08)
|
|
if ((d.l(ad:0x4001C200+0xE4)&0x01)==0x00)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
else
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
endif
|
|
endif
|
|
if ((d.l(ad:0x4001C200+0x04)&0x0F)==(0x0A||0x0B))
|
|
if ((d.l(ad:0x4001C200+0xE4)&0x01)==0x00)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "US_LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x00 17. " SYNCDIS ,Synchronization Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " PDCM ,DMAC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data Length Control"
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "DLC,Bits 5 and 6 of LINIR"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "Enhanced,Classic"
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
else
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "US_LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x00 17. " SYNCDIS ,Synchronization Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " PDCM ,DMAC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data Length Control"
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "DLC,Bits 5 and 6 of LINIR"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "Enhanced,Classic"
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
endif
|
|
if ((d.l(ad:0x4001C200+0x04)&0x0F)==0x0A)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "US_LINBRR,USART LIN Baud Rate Register"
|
|
bitfld.long 0x00 16.--18. " LINFP ,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--15. 1. " LINCD ,Clock Divider after Synchronization"
|
|
endif
|
|
if ((d.l(ad:0x4001C200+0xE4)&0x01)==0x00)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "US_CMPR,USART Comparison Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
bitfld.long 0x00 14. " CMPPAR ,Compare Parity" "Not checked,Checked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "Flag_only,Start_condition"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
else
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "US_CMPR,USART Comparison Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
bitfld.long 0x00 14. " CMPPAR ,Compare Parity" "Not checked,Checked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "Flag_only,Start_condition"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,USART Write Protect Status Register"
|
|
in
|
|
width 0x0B
|
|
tree "USART4 PDC (Peripheral DMA Controller)"
|
|
width 12.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "USART4_RPR,Receive Pointer Register"
|
|
line.long 0x04 "USART4_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART4_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "USART4_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART4_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "USART4_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART4_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "USART4_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART4_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART4_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "USART5"
|
|
base ad:0x40008200
|
|
width 11.
|
|
if ((d.l((ad:0x40008200)+0x04)&0x0F)==0x0E)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select (Release Slave Select Line NSS)" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select (Force Slave Select Line NSS to 0)" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((d.l((ad:0x40008200)+0x04)&0x0F)==0x0F)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((d.l(ad:0x40008200+0x04)&0x0F)==0x00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Pin Control" "No effect,Drive RTS to 1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Pin Control" "No effect,Drive RTS to 0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((d.l(ad:0x40008200+0x04)&0x0F)==0x02)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Pin Control" "No effect,Drive RTS to 0"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Pin Control" "No effect,Drive RTS to 1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
if (((d.l((ad:0x400E0514)))&0x200000)==0x200000)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 28. " REQCLR ,Request to Clear the Comparison Trigger" "No effect,Clear"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 28. " REQCLR ,Request to Clear the Comparison Trigger" "No effect,Restart"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
endif
|
|
if ((d.l(ad:0x40008200+0xE4)&0x01)==0x00)
|
|
if ((d.l(ad:0x40008200+0x04)&0x0F)==(0x0E||0x0F))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" ",,,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-Low,Inactive-High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
else
|
|
if (((d.l(ad:0x40008200+0x04))&0x100)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,1.5,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
endif
|
|
endif
|
|
else
|
|
if ((d.l(ad:0x40008200+0x04)&0x0F)==(0x0E||0x0F))
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" ",,,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-Low,Inactive-High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
else
|
|
if (((d.l(ad:0x40008200+0x04))&0x100)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Numer of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,1.5,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Numer of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
endif
|
|
endif
|
|
endif
|
|
if ((d.l(ad:0x40008200+0x04)&0x0F)==(0x0E||0x0F))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " CMP_set/clr ,Comparison Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " NSSE_set/clr ,NSS Line Event (CTS pin) Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNRE_set/clr ,SPI Underrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Masked,Not masked"
|
|
elif ((d.l(ad:0x40008200+0x04)&0x0F)==(0x0A||0x0B))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " LINHTE_set/clr , LIN Header Timeout Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " LINSTE_set/clr ,LIN Synch Tolerance Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " LINBK_set/clr ,LIN Break Sent or LIN Break Received Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Masked,Not masked"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " CMP_set/clr ,Comparison Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Masked,Not masked"
|
|
endif
|
|
if ((d.l(ad:0x40008200+0x04)&0x0F)==(0x0E||0x0F))
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "US_CSR,Channel Status Register"
|
|
bitfld.long 0x00 23. " NSS ,Image Of NSS Line" "Driven low,Driven high"
|
|
bitfld.long 0x00 22. " CMP ,Comparison Match" "No match,Match"
|
|
bitfld.long 0x00 19. " NSSE ,NSS Line Rising Or Falling Edge Event" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 10. " UNRE ,Underrun Error" "No error,Error"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDTX ,End of TX Buffer" "Not reached 0,Reached 0"
|
|
bitfld.long 0x00 3. " ENDRX ,End of RX Buffer" "Not reached 0,Reached 0"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
elif ((d.l(ad:0x40008200+0x04)&0x0F)==(0x0A||0x0B))
|
|
if ((d.l(ad:0x40008200+0x04)&0x0F)==0x0A)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "US_CSR,Channel Status Register"
|
|
bitfld.long 0x00 31. " LINHTE ,LIN Header Timeout Error" "No error,Error"
|
|
bitfld.long 0x00 30. " LINSTE ,LIN Synch Tolerance Error" "No error,Error"
|
|
bitfld.long 0x00 29. " LINSNRE ,LIN Slave Not Responding Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 28. " LINCE ,LIN Checksum Error" "No error,Error"
|
|
bitfld.long 0x00 27. " LINIPE ,LIN Identifier Parity Error" "No error,Error"
|
|
bitfld.long 0x00 26. " LINISFE ,LIN Inconsistent Synch Field Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LINBE ,LIN Bit Error" "No error,Error"
|
|
bitfld.long 0x00 23. " LINBLS ,LIN Bus Line Status" "0,1"
|
|
bitfld.long 0x00 15. " LINTC ,LIN Transfer Completed" "Idle,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 14. " LINID ,LIN Identifier Sent or LIN Identifier Received" "No identifier received,Identifier received"
|
|
bitfld.long 0x00 13. " LINBK ,LIN Break Sent or LIN Break Received" "No break received,Break received"
|
|
bitfld.long 0x00 12. " RXBUFF ,RX Buffer Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TXBUFE ,TX Buffer Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 8. " TIMEOUT ,Receiver Time-out" "No time-out,Time-out"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PARE ,Parity Error" "No error,Error"
|
|
bitfld.long 0x00 6. " FRAME ,Framing Error" "No error,Error"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDTX ,End of TX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 3. " ENDRX ,End of RX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "US_CSR,Channel Status Register"
|
|
bitfld.long 0x00 31. " LINHTE ,LIN Header Timeout Error" "No error,Error"
|
|
bitfld.long 0x00 30. " LINSTE ,LIN Synch Tolerance Error" "No error,Error"
|
|
bitfld.long 0x00 29. " LINSNRE ,LIN Slave Not Responding Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 28. " LINCE ,LIN Checksum Error" "No error,Error"
|
|
bitfld.long 0x00 27. " LINIPE ,LIN Identifier Parity Error" "No error,Error"
|
|
bitfld.long 0x00 26. " LINISFE ,LIN Inconsistent Synch Field Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LINBE ,LIN Bit Error" "No error,Error"
|
|
bitfld.long 0x00 23. " LINBLS ,LIN Bus Line Status" "0,1"
|
|
bitfld.long 0x00 15. " LINTC ,LIN Transfer Completed" "Idle,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 14. " LINID ,LIN Identifier Sent or LIN Identifier Received" "No identifier received,Identifier received"
|
|
bitfld.long 0x00 13. " LINBK ,LIN Break Sent or LIN Break Received" "No break received,Break received"
|
|
bitfld.long 0x00 12. " RXBUFF ,RX Buffer Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TXBUFE ,TX Buffer Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 8. " TIMEOUT ,Receiver Time-out" "No time-out,Time-out"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PARE ,Parity Error" "No error,Error"
|
|
bitfld.long 0x00 6. " FRAME ,Framing Error" "No error,Error"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDTX ,End of TX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 3. " ENDRX ,End of RX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
endif
|
|
else
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "US_CSR,Channel Status Register"
|
|
in
|
|
endif
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RHR,Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "US_THR,Transmitter Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be transmitted"
|
|
if ((d.l(ad:0x40008200+0xE4)&0x01)==0x00)
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "RTOR,Receiver Time-out Register"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TG ,Timeguard Value"
|
|
else
|
|
rgroup.long 0x20++0x07
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "RTOR,Receiver Time-out Register"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TG ,Timeguard Value"
|
|
endif
|
|
if ((d.l(ad:0x40008200+0xE4)&0x01)==0x00)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 31. " RXIDLEV ,Receiver Idle Value" "0,1"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" ",1"
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0-to-1,1-to-0"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern Detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
else
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 31. " RXIDLEV ,Receiver Idle Value" "0,1"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" ",1"
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0-to-1,1-to-0"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern Detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
endif
|
|
if ((d.l(ad:0x40008200+0xE4)&0x01)==0x00)
|
|
wgroup.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,USART FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
else
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,USART FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
endif
|
|
if (((d.l(ad:0x40008200+0x04))&0x0F)==0x04)||(((d.l(ad:0x40008200+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "US_NER,USART Number of Errors Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NB_ERRORS ,Number of Errors"
|
|
else
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US_NER,USART Number of Errors Register"
|
|
endif
|
|
if (((d.l(ad:0x40008200+0x04))&0x08)==0x08)
|
|
if ((d.l(ad:0x40008200+0xE4)&0x01)==0x00)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
else
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
endif
|
|
endif
|
|
if ((d.l(ad:0x40008200+0x04)&0x0F)==(0x0A||0x0B))
|
|
if ((d.l(ad:0x40008200+0xE4)&0x01)==0x00)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "US_LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x00 17. " SYNCDIS ,Synchronization Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " PDCM ,DMAC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data Length Control"
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "DLC,Bits 5 and 6 of LINIR"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "Enhanced,Classic"
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
else
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "US_LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x00 17. " SYNCDIS ,Synchronization Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " PDCM ,DMAC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data Length Control"
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "DLC,Bits 5 and 6 of LINIR"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "Enhanced,Classic"
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
endif
|
|
if ((d.l(ad:0x40008200+0x04)&0x0F)==0x0A)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "US_LINBRR,USART LIN Baud Rate Register"
|
|
bitfld.long 0x00 16.--18. " LINFP ,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--15. 1. " LINCD ,Clock Divider after Synchronization"
|
|
endif
|
|
if ((d.l(ad:0x40008200+0xE4)&0x01)==0x00)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "US_CMPR,USART Comparison Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
bitfld.long 0x00 14. " CMPPAR ,Compare Parity" "Not checked,Checked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "Flag_only,Start_condition"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
else
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "US_CMPR,USART Comparison Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
bitfld.long 0x00 14. " CMPPAR ,Compare Parity" "Not checked,Checked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "Flag_only,Start_condition"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,USART Write Protect Status Register"
|
|
in
|
|
width 0x0B
|
|
tree "USART5 PDC (Peripheral DMA Controller)"
|
|
width 12.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "USART5_RPR,Receive Pointer Register"
|
|
line.long 0x04 "USART5_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART5_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "USART5_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART5_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "USART5_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART5_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "USART5_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART5_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART5_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "USART6"
|
|
base ad:0x40040200
|
|
width 11.
|
|
if ((d.l((ad:0x40040200)+0x04)&0x0F)==0x0E)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select (Release Slave Select Line NSS)" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select (Force Slave Select Line NSS to 0)" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((d.l((ad:0x40040200)+0x04)&0x0F)==0x0F)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((d.l(ad:0x40040200+0x04)&0x0F)==0x00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Pin Control" "No effect,Drive RTS to 1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Pin Control" "No effect,Drive RTS to 0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((d.l(ad:0x40040200+0x04)&0x0F)==0x02)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Pin Control" "No effect,Drive RTS to 0"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Pin Control" "No effect,Drive RTS to 1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
if (((d.l((ad:0x400E0514)))&0x400000)==0x400000)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 28. " REQCLR ,Request to Clear the Comparison Trigger" "No effect,Clear"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 28. " REQCLR ,Request to Clear the Comparison Trigger" "No effect,Restart"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
endif
|
|
if ((d.l(ad:0x40040200+0xE4)&0x01)==0x00)
|
|
if ((d.l(ad:0x40040200+0x04)&0x0F)==(0x0E||0x0F))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" ",,,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-Low,Inactive-High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
else
|
|
if (((d.l(ad:0x40040200+0x04))&0x100)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,1.5,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
endif
|
|
endif
|
|
else
|
|
if ((d.l(ad:0x40040200+0x04)&0x0F)==(0x0E||0x0F))
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" ",,,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-Low,Inactive-High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
else
|
|
if (((d.l(ad:0x40040200+0x04))&0x100)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Numer of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,1.5,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Numer of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
endif
|
|
endif
|
|
endif
|
|
if ((d.l(ad:0x40040200+0x04)&0x0F)==(0x0E||0x0F))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " CMP_set/clr ,Comparison Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " NSSE_set/clr ,NSS Line Event (CTS pin) Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNRE_set/clr ,SPI Underrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Masked,Not masked"
|
|
elif ((d.l(ad:0x40040200+0x04)&0x0F)==(0x0A||0x0B))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " LINHTE_set/clr , LIN Header Timeout Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " LINSTE_set/clr ,LIN Synch Tolerance Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " LINBK_set/clr ,LIN Break Sent or LIN Break Received Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Masked,Not masked"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " CMP_set/clr ,Comparison Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Masked,Not masked"
|
|
endif
|
|
if ((d.l(ad:0x40040200+0x04)&0x0F)==(0x0E||0x0F))
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "US_CSR,Channel Status Register"
|
|
bitfld.long 0x00 23. " NSS ,Image Of NSS Line" "Driven low,Driven high"
|
|
bitfld.long 0x00 22. " CMP ,Comparison Match" "No match,Match"
|
|
bitfld.long 0x00 19. " NSSE ,NSS Line Rising Or Falling Edge Event" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 10. " UNRE ,Underrun Error" "No error,Error"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDTX ,End of TX Buffer" "Not reached 0,Reached 0"
|
|
bitfld.long 0x00 3. " ENDRX ,End of RX Buffer" "Not reached 0,Reached 0"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
elif ((d.l(ad:0x40040200+0x04)&0x0F)==(0x0A||0x0B))
|
|
if ((d.l(ad:0x40040200+0x04)&0x0F)==0x0A)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "US_CSR,Channel Status Register"
|
|
bitfld.long 0x00 31. " LINHTE ,LIN Header Timeout Error" "No error,Error"
|
|
bitfld.long 0x00 30. " LINSTE ,LIN Synch Tolerance Error" "No error,Error"
|
|
bitfld.long 0x00 29. " LINSNRE ,LIN Slave Not Responding Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 28. " LINCE ,LIN Checksum Error" "No error,Error"
|
|
bitfld.long 0x00 27. " LINIPE ,LIN Identifier Parity Error" "No error,Error"
|
|
bitfld.long 0x00 26. " LINISFE ,LIN Inconsistent Synch Field Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LINBE ,LIN Bit Error" "No error,Error"
|
|
bitfld.long 0x00 23. " LINBLS ,LIN Bus Line Status" "0,1"
|
|
bitfld.long 0x00 15. " LINTC ,LIN Transfer Completed" "Idle,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 14. " LINID ,LIN Identifier Sent or LIN Identifier Received" "No identifier received,Identifier received"
|
|
bitfld.long 0x00 13. " LINBK ,LIN Break Sent or LIN Break Received" "No break received,Break received"
|
|
bitfld.long 0x00 12. " RXBUFF ,RX Buffer Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TXBUFE ,TX Buffer Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 8. " TIMEOUT ,Receiver Time-out" "No time-out,Time-out"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PARE ,Parity Error" "No error,Error"
|
|
bitfld.long 0x00 6. " FRAME ,Framing Error" "No error,Error"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDTX ,End of TX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 3. " ENDRX ,End of RX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "US_CSR,Channel Status Register"
|
|
bitfld.long 0x00 31. " LINHTE ,LIN Header Timeout Error" "No error,Error"
|
|
bitfld.long 0x00 30. " LINSTE ,LIN Synch Tolerance Error" "No error,Error"
|
|
bitfld.long 0x00 29. " LINSNRE ,LIN Slave Not Responding Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 28. " LINCE ,LIN Checksum Error" "No error,Error"
|
|
bitfld.long 0x00 27. " LINIPE ,LIN Identifier Parity Error" "No error,Error"
|
|
bitfld.long 0x00 26. " LINISFE ,LIN Inconsistent Synch Field Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LINBE ,LIN Bit Error" "No error,Error"
|
|
bitfld.long 0x00 23. " LINBLS ,LIN Bus Line Status" "0,1"
|
|
bitfld.long 0x00 15. " LINTC ,LIN Transfer Completed" "Idle,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 14. " LINID ,LIN Identifier Sent or LIN Identifier Received" "No identifier received,Identifier received"
|
|
bitfld.long 0x00 13. " LINBK ,LIN Break Sent or LIN Break Received" "No break received,Break received"
|
|
bitfld.long 0x00 12. " RXBUFF ,RX Buffer Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TXBUFE ,TX Buffer Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 8. " TIMEOUT ,Receiver Time-out" "No time-out,Time-out"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PARE ,Parity Error" "No error,Error"
|
|
bitfld.long 0x00 6. " FRAME ,Framing Error" "No error,Error"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDTX ,End of TX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 3. " ENDRX ,End of RX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
endif
|
|
else
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "US_CSR,Channel Status Register"
|
|
in
|
|
endif
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RHR,Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "US_THR,Transmitter Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be transmitted"
|
|
if ((d.l(ad:0x40040200+0xE4)&0x01)==0x00)
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "RTOR,Receiver Time-out Register"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TG ,Timeguard Value"
|
|
else
|
|
rgroup.long 0x20++0x07
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "RTOR,Receiver Time-out Register"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TG ,Timeguard Value"
|
|
endif
|
|
if ((d.l(ad:0x40040200+0xE4)&0x01)==0x00)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 31. " RXIDLEV ,Receiver Idle Value" "0,1"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" ",1"
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0-to-1,1-to-0"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern Detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
else
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 31. " RXIDLEV ,Receiver Idle Value" "0,1"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" ",1"
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0-to-1,1-to-0"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern Detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
endif
|
|
if ((d.l(ad:0x40040200+0xE4)&0x01)==0x00)
|
|
wgroup.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,USART FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
else
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,USART FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
endif
|
|
if (((d.l(ad:0x40040200+0x04))&0x0F)==0x04)||(((d.l(ad:0x40040200+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "US_NER,USART Number of Errors Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NB_ERRORS ,Number of Errors"
|
|
else
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US_NER,USART Number of Errors Register"
|
|
endif
|
|
if (((d.l(ad:0x40040200+0x04))&0x08)==0x08)
|
|
if ((d.l(ad:0x40040200+0xE4)&0x01)==0x00)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
else
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
endif
|
|
endif
|
|
if ((d.l(ad:0x40040200+0x04)&0x0F)==(0x0A||0x0B))
|
|
if ((d.l(ad:0x40040200+0xE4)&0x01)==0x00)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "US_LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x00 17. " SYNCDIS ,Synchronization Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " PDCM ,DMAC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data Length Control"
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "DLC,Bits 5 and 6 of LINIR"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "Enhanced,Classic"
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
else
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "US_LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x00 17. " SYNCDIS ,Synchronization Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " PDCM ,DMAC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data Length Control"
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "DLC,Bits 5 and 6 of LINIR"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "Enhanced,Classic"
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
endif
|
|
if ((d.l(ad:0x40040200+0x04)&0x0F)==0x0A)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "US_LINBRR,USART LIN Baud Rate Register"
|
|
bitfld.long 0x00 16.--18. " LINFP ,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--15. 1. " LINCD ,Clock Divider after Synchronization"
|
|
endif
|
|
if ((d.l(ad:0x40040200+0xE4)&0x01)==0x00)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "US_CMPR,USART Comparison Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
bitfld.long 0x00 14. " CMPPAR ,Compare Parity" "Not checked,Checked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "Flag_only,Start_condition"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
else
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "US_CMPR,USART Comparison Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
bitfld.long 0x00 14. " CMPPAR ,Compare Parity" "Not checked,Checked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "Flag_only,Start_condition"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,USART Write Protect Status Register"
|
|
in
|
|
width 0x0B
|
|
tree "USART6 PDC (Peripheral DMA Controller)"
|
|
width 12.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "USART6_RPR,Receive Pointer Register"
|
|
line.long 0x04 "USART6_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART6_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "USART6_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART6_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "USART6_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART6_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "USART6_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART6_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART6_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "USART7"
|
|
base ad:0x40034200
|
|
width 11.
|
|
if ((d.l((ad:0x40034200)+0x04)&0x0F)==0x0E)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select (Release Slave Select Line NSS)" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select (Force Slave Select Line NSS to 0)" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((d.l((ad:0x40034200)+0x04)&0x0F)==0x0F)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((d.l(ad:0x40034200+0x04)&0x0F)==0x00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Pin Control" "No effect,Drive RTS to 1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Pin Control" "No effect,Drive RTS to 0"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((d.l(ad:0x40034200+0x04)&0x0F)==0x02)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Pin Control" "No effect,Drive RTS to 0"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Pin Control" "No effect,Drive RTS to 1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
if (((d.l((ad:0x400E0514)))&0x80)==0x80)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 28. " REQCLR ,Request to Clear the Comparison Trigger" "No effect,Clear"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
bitfld.long 0x00 28. " REQCLR ,Request to Clear the Comparison Trigger" "No effect,Restart"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort transmission"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RETTO ,Start Time-out Immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT Flag and Start Time-out After Next Character Received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
endif
|
|
if ((d.l(ad:0x40034200+0xE4)&0x01)==0x00)
|
|
if ((d.l(ad:0x40034200+0x04)&0x0F)==(0x0E||0x0F))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" ",,,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-Low,Inactive-High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
else
|
|
if (((d.l(ad:0x40034200+0x04))&0x100)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,1.5,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
endif
|
|
endif
|
|
else
|
|
if ((d.l(ad:0x40034200+0x04)&0x0F)==(0x0E||0x0F))
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" ",,,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-Low,Inactive-High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
else
|
|
if (((d.l(ad:0x40034200+0x04))&0x100)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Numer of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,1.5,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum Numer of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,THR register"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,PCK,SCK"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
endif
|
|
endif
|
|
endif
|
|
if ((d.l(ad:0x40034200+0x04)&0x0F)==(0x0E||0x0F))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " CMP_set/clr ,Comparison Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " NSSE_set/clr ,NSS Line Event (CTS pin) Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNRE_set/clr ,SPI Underrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Masked,Not masked"
|
|
elif ((d.l(ad:0x40034200+0x04)&0x0F)==(0x0A||0x0B))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " LINHTE_set/clr , LIN Header Timeout Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " LINSTE_set/clr ,LIN Synch Tolerance Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " LINBK_set/clr ,LIN Break Sent or LIN Break Received Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Masked,Not masked"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " CMP_set/clr ,Comparison Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Masked,Not masked"
|
|
endif
|
|
if ((d.l(ad:0x40034200+0x04)&0x0F)==(0x0E||0x0F))
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "US_CSR,Channel Status Register"
|
|
bitfld.long 0x00 23. " NSS ,Image Of NSS Line" "Driven low,Driven high"
|
|
bitfld.long 0x00 22. " CMP ,Comparison Match" "No match,Match"
|
|
bitfld.long 0x00 19. " NSSE ,NSS Line Rising Or Falling Edge Event" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 10. " UNRE ,Underrun Error" "No error,Error"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDTX ,End of TX Buffer" "Not reached 0,Reached 0"
|
|
bitfld.long 0x00 3. " ENDRX ,End of RX Buffer" "Not reached 0,Reached 0"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
elif ((d.l(ad:0x40034200+0x04)&0x0F)==(0x0A||0x0B))
|
|
if ((d.l(ad:0x40034200+0x04)&0x0F)==0x0A)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "US_CSR,Channel Status Register"
|
|
bitfld.long 0x00 31. " LINHTE ,LIN Header Timeout Error" "No error,Error"
|
|
bitfld.long 0x00 30. " LINSTE ,LIN Synch Tolerance Error" "No error,Error"
|
|
bitfld.long 0x00 29. " LINSNRE ,LIN Slave Not Responding Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 28. " LINCE ,LIN Checksum Error" "No error,Error"
|
|
bitfld.long 0x00 27. " LINIPE ,LIN Identifier Parity Error" "No error,Error"
|
|
bitfld.long 0x00 26. " LINISFE ,LIN Inconsistent Synch Field Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LINBE ,LIN Bit Error" "No error,Error"
|
|
bitfld.long 0x00 23. " LINBLS ,LIN Bus Line Status" "0,1"
|
|
bitfld.long 0x00 15. " LINTC ,LIN Transfer Completed" "Idle,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 14. " LINID ,LIN Identifier Sent or LIN Identifier Received" "No identifier received,Identifier received"
|
|
bitfld.long 0x00 13. " LINBK ,LIN Break Sent or LIN Break Received" "No break received,Break received"
|
|
bitfld.long 0x00 12. " RXBUFF ,RX Buffer Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TXBUFE ,TX Buffer Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 8. " TIMEOUT ,Receiver Time-out" "No time-out,Time-out"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PARE ,Parity Error" "No error,Error"
|
|
bitfld.long 0x00 6. " FRAME ,Framing Error" "No error,Error"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDTX ,End of TX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 3. " ENDRX ,End of RX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "US_CSR,Channel Status Register"
|
|
bitfld.long 0x00 31. " LINHTE ,LIN Header Timeout Error" "No error,Error"
|
|
bitfld.long 0x00 30. " LINSTE ,LIN Synch Tolerance Error" "No error,Error"
|
|
bitfld.long 0x00 29. " LINSNRE ,LIN Slave Not Responding Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 28. " LINCE ,LIN Checksum Error" "No error,Error"
|
|
bitfld.long 0x00 27. " LINIPE ,LIN Identifier Parity Error" "No error,Error"
|
|
bitfld.long 0x00 26. " LINISFE ,LIN Inconsistent Synch Field Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LINBE ,LIN Bit Error" "No error,Error"
|
|
bitfld.long 0x00 23. " LINBLS ,LIN Bus Line Status" "0,1"
|
|
bitfld.long 0x00 15. " LINTC ,LIN Transfer Completed" "Idle,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 14. " LINID ,LIN Identifier Sent or LIN Identifier Received" "No identifier received,Identifier received"
|
|
bitfld.long 0x00 13. " LINBK ,LIN Break Sent or LIN Break Received" "No break received,Break received"
|
|
bitfld.long 0x00 12. " RXBUFF ,RX Buffer Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TXBUFE ,TX Buffer Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 8. " TIMEOUT ,Receiver Time-out" "No time-out,Time-out"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PARE ,Parity Error" "No error,Error"
|
|
bitfld.long 0x00 6. " FRAME ,Framing Error" "No error,Error"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENDTX ,End of TX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 3. " ENDRX ,End of RX Buffer" "No overrun,Overrun"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver Ready" "Not ready,Ready"
|
|
endif
|
|
else
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "US_CSR,Channel Status Register"
|
|
in
|
|
endif
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RHR,Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "US_THR,Transmitter Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be transmitted"
|
|
if ((d.l(ad:0x40034200+0xE4)&0x01)==0x00)
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "RTOR,Receiver Time-out Register"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TG ,Timeguard Value"
|
|
else
|
|
rgroup.long 0x20++0x07
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "RTOR,Receiver Time-out Register"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TG ,Timeguard Value"
|
|
endif
|
|
if ((d.l(ad:0x40034200+0xE4)&0x01)==0x00)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 31. " RXIDLEV ,Receiver Idle Value" "0,1"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" ",1"
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0-to-1,1-to-0"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern Detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
else
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 31. " RXIDLEV ,Receiver Idle Value" "0,1"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" ",1"
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0-to-1,1-to-0"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern Detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
endif
|
|
if ((d.l(ad:0x40034200+0xE4)&0x01)==0x00)
|
|
wgroup.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,USART FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
else
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,USART FI DI RATIO Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
endif
|
|
if (((d.l(ad:0x40034200+0x04))&0x0F)==0x04)||(((d.l(ad:0x40034200+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "US_NER,USART Number of Errors Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NB_ERRORS ,Number of Errors"
|
|
else
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US_NER,USART Number of Errors Register"
|
|
endif
|
|
if (((d.l(ad:0x40034200+0x04))&0x08)==0x08)
|
|
if ((d.l(ad:0x40034200+0xE4)&0x01)==0x00)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
else
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
endif
|
|
endif
|
|
if ((d.l(ad:0x40034200+0x04)&0x0F)==(0x0A||0x0B))
|
|
if ((d.l(ad:0x40034200+0xE4)&0x01)==0x00)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "US_LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x00 17. " SYNCDIS ,Synchronization Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " PDCM ,DMAC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data Length Control"
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "DLC,Bits 5 and 6 of LINIR"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "Enhanced,Classic"
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
else
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "US_LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x00 17. " SYNCDIS ,Synchronization Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " PDCM ,DMAC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data Length Control"
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "LIN 2.0,LIN 1.3"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "DLC,Bits 5 and 6 of LINIR"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "Enhanced,Classic"
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "Publish,Subscribe,Ignore,?..."
|
|
endif
|
|
if ((d.l(ad:0x40034200+0x04)&0x0F)==0x0A)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "US_LINBRR,USART LIN Baud Rate Register"
|
|
bitfld.long 0x00 16.--18. " LINFP ,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--15. 1. " LINCD ,Clock Divider after Synchronization"
|
|
endif
|
|
if ((d.l(ad:0x40034200+0xE4)&0x01)==0x00)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "US_CMPR,USART Comparison Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
bitfld.long 0x00 14. " CMPPAR ,Compare Parity" "Not checked,Checked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "Flag_only,Start_condition"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
else
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "US_CMPR,USART Comparison Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " VAL2 ,Second Comparison Value for Received Character"
|
|
bitfld.long 0x00 14. " CMPPAR ,Compare Parity" "Not checked,Checked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CMPMODE ,Comparison Mode" "Flag_only,Start_condition"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VAL1 ,First Comparison Value for Received Character"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,USART Write Protect Status Register"
|
|
in
|
|
width 0x0B
|
|
tree "USART7 PDC (Peripheral DMA Controller)"
|
|
width 12.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "USART7_RPR,Receive Pointer Register"
|
|
line.long 0x04 "USART7_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART7_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "USART7_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART7_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "USART7_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART7_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "USART7_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART7_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART7_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
else
|
|
tree "USART"
|
|
base ad:0x40024000
|
|
width 12.
|
|
if ((d.l((ad:0x40024000)+0x4)&0xF)==(0xE||0xF))
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "USART_CR,Control Register"
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select (Release Slave Select Line NSS)" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select (Force Slave Select Line NSS to 0)" "No effect,Force"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
if ((d.l(ad:0x40024000+0x04)&0x0F)==0x01)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "USART_CR,Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Pin Control" "No effect,Drive RTS to 0"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Pin Control" "No effect,Drive RTS to 1"
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
elif ((d.l(ad:0x40024000+0x04)&0x0F)==0x00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "USART_CR,Control Register"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Pin Control" "No effect,Drive RTS to 1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Pin Control" "No effect,Drive RTS to 0"
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "USART_CR,Control Register"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Pin Control" "No effect,Drive RTS to 0"
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
endif
|
|
if ((d.l(ad:0x40024000+0xE4)&0x01)==0x00)
|
|
if ((d.l(ad:0x40024000+0x04)&0x0f)==(0x0e||0x0f))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_MR,Mode Register"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-Low,Inactive-High"
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
elif ((d.l(ad:0x40024000+0x04)&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_MR,Mode Register"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
elif ((d.l(ad:0x40024000+0x04)&0x100)==0x000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_MR,Mode Register"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,1.5,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
endif
|
|
else
|
|
if ((d.l(ad:0x40024000+0x04)&0x0f)==(0x0e||0x0f))
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "USART_MR,Mode Register"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-Low,Inactive-High"
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
elif ((d.l(ad:0x40024000+0x04)&0x100)==0x100)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "USART_MR,Mode Register"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
elif ((d.l(ad:0x40024000+0x04)&0x100)==0x000)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "USART_MR,Mode Register"
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FILTER ,Receive Line Filter" "Not filtered,Filtered"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,1.5,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,,SCK"
|
|
endif
|
|
endif
|
|
if ((d.l(ad:0x40024000+0x4)&0xF)==(0xE||0xF))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USART_IMR,Interrupt Enable/Mask Register"
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " UNRE_set/clr ,SPI Underrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Masked,Not masked"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USART_IMR,Interrupt Enable/Mask Register"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Enable/Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Enable/Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Enable/Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,End of Receive Buffer Interrupt Enable/Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Masked,Not masked"
|
|
endif
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x0 "CSR,Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "USART_RHR,Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "USART_THR,Transmitter Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
if ((d.l(ad:0x40024000+0xE4)&0x01)==0x00)
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "USART_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1 x 1/8,2 x 1/8,3 x 1/8,4 x 1/8,5 x 1/8,6 x 1/8,7 x 1/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "USART_RTOR,Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "USART_TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
else
|
|
rgroup.long 0x20++0x0B
|
|
line.long 0x00 "USART_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1 x 1/8,2 x 1/8,3 x 1/8,4 x 1/8,5 x 1/8,6 x 1/8,7 x 1/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "RTOR,Receiver Time-out Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
line.long 0x08 "TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
endif
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "USART_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x3
|
|
hide.long 0x00 "USART_WPSR,USART Write Protect Status Register"
|
|
in
|
|
width 0xb
|
|
tree "USART PDC (Peripheral DMA Controller)"
|
|
width 12.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "USART_RPR,Receive Pointer Register"
|
|
line.long 0x04 "USART_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "USART_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "USART_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "USART_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree.open "TC (Timer Counter)"
|
|
tree "TC0-Channel 0"
|
|
base ad:0x40010000
|
|
width 10.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC_CCR0,TC Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Started"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Yes"
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((d.l(ad:0x40010000+0xE4))&0x01)==0x00)
|
|
if (((d.l(ad:0x40010000+0x04))&0x8000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR0,TC Channel Mode Register"
|
|
sif !cpuis("ATSAMG53")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading Edge Subsampling Ratio" "One,Half,Fourth,Eight,Sixteenth,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Edge Selection" "None,Rising,Falling,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer Clock 1,Timer Clock 2,Timer Clock 3,Timer Clock 4,Timer Clock 5,XC0,XC1,XC2"
|
|
elif (((d.l(ad:0x40010000+0x04))&0x8000)==0x8000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR0,TC Channel Mode Register: Waveform Mode"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "Up,Up down,Up Rc,Up down Rc"
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "Not disabled,Disabled"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer clock1,Timer clock2,Timer clock3,Timer clock4,Timer clock5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR0,TC Channel Mode Register: Waveform Mode"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "Not disabled,Disabled"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer clock1,Timer clock2,Timer clock3,Timer clock4,Timer clock5,XC0,XC1,XC2"
|
|
endif
|
|
else
|
|
if (((d.l(ad:0x40010000+0x04))&0x8000)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR0,TC Channel Mode Register"
|
|
sif !cpuis("ATSAMG53")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading Edge Subsampling Ratio" "One,Half,Fourth,Eight,Sixteenth,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Edge Selection" "None,Rising,Falling,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer Clock 1,Timer Clock 2,Timer Clock 3,Timer Clock 4,Timer Clock 5,XC0,XC1,XC2"
|
|
elif (((d.l(ad:0x40010000+0x04))&0x8000)==0x8000)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR0,TC Channel Mode Register: Waveform Mode"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "Up,Up down,Up Rc,Up down Rc"
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "Not disabled,Disabled"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer clock1,Timer clock2,Timer clock3,Timer clock4,Timer clock5,XC0,XC1,XC2"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR0,TC Channel Mode Register: Waveform Mode"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "Not disabled,Disabled"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer clock1,Timer clock2,Timer clock3,Timer clock4,Timer clock5,XC0,XC1,XC2"
|
|
endif
|
|
endif
|
|
if (((d.l(ad:0x40010000+0xE4))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Internal counter,2-bit gray counter"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Internal counter,2-bit gray counter"
|
|
endif
|
|
sif (cpu()=="ATSAMG53"||cpu()=="ATSAMG55")
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "TC_RAB,TC Register AB"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC_CV0,TC Counter Value Register"
|
|
if (((d.l(ad:0x40010000+0xE4))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TC_RA0,TC Register A"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "TC_RA0,TC Register A"
|
|
endif
|
|
if (((d.l(ad:0x40010000+0xE4))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TC_RB0,TC Register B"
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "TC_RB0,TC Register B"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TC_RC0,TC Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC_SR0,TC Status Register"
|
|
in
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TC_IMR0,TC Interrupt Mask Register"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " RXBUFF_set/clr ,Reception Buffer Full" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x04 9. -0x08 9. " ENDRX_set/clr ,End of Receiver Transfer" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x04 9. -0x08 9. " ETRGS_set/clr ,External Trigger" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x04 9. -0x08 9. " LDRBS_set/clr ,RB Loading" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x04 9. -0x08 9. " LDRAS_set/clr ,RA Loading" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x04 9. -0x08 9. " CPCS_set/clr ,RC Compare" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 9. -0x08 9. " CPBS_set/clr ,RB Compare" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x04 9. -0x08 9. " CPAS_set/clr ,RA Compare" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x04 9. -0x08 9. " LOVRS_set/clr ,Load Overrun" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x04 9. -0x08 9. " COVFS_set/clr ,Counter Overflow" "Masked,Not masked"
|
|
width 0xB
|
|
tree "TC0-0 PDC (Peripheral DMA Controller)"
|
|
width 10.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "TC0_RPR,Receive Pointer Register"
|
|
line.long 0x04 "TC0_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "TC0_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "TC0_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "TC0_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "TC0_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "TC0_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "TC0_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "TC0_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "TC0_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "TC0-Channel 1"
|
|
base ad:0x40010040
|
|
width 10.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC_CCR1,TC Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Started"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Yes"
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((d.l(ad:0x40010000+0xE4))&0x01)==0x00)
|
|
if (((d.l(ad:0x40010040+0x04))&0x8000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR1,TC Channel Mode Register"
|
|
sif !cpuis("ATSAMG53")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading Edge Subsampling Ratio" "One,Half,Fourth,Eight,Sixteenth,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Edge Selection" "None,Rising,Falling,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer Clock 1,Timer Clock 2,Timer Clock 3,Timer Clock 4,Timer Clock 5,XC0,XC1,XC2"
|
|
elif (((d.l(ad:0x40010040+0x04))&0x8000)==0x8000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR1,TC Channel Mode Register: Waveform Mode"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "Up,Up down,Up Rc,Up down Rc"
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "Not disabled,Disabled"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer clock1,Timer clock2,Timer clock3,Timer clock4,Timer clock5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR1,TC Channel Mode Register: Waveform Mode"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "Not disabled,Disabled"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer clock1,Timer clock2,Timer clock3,Timer clock4,Timer clock5,XC0,XC1,XC2"
|
|
endif
|
|
else
|
|
if (((d.l(ad:0x40010040+0x04))&0x8000)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR1,TC Channel Mode Register"
|
|
sif !cpuis("ATSAMG53")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading Edge Subsampling Ratio" "One,Half,Fourth,Eight,Sixteenth,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Edge Selection" "None,Rising,Falling,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer Clock 1,Timer Clock 2,Timer Clock 3,Timer Clock 4,Timer Clock 5,XC0,XC1,XC2"
|
|
elif (((d.l(ad:0x40010040+0x04))&0x8000)==0x8000)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR1,TC Channel Mode Register: Waveform Mode"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "Up,Up down,Up Rc,Up down Rc"
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "Not disabled,Disabled"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer clock1,Timer clock2,Timer clock3,Timer clock4,Timer clock5,XC0,XC1,XC2"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR1,TC Channel Mode Register: Waveform Mode"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "Not disabled,Disabled"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer clock1,Timer clock2,Timer clock3,Timer clock4,Timer clock5,XC0,XC1,XC2"
|
|
endif
|
|
endif
|
|
if (((d.l(ad:0x40010040+0xE4))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TC_SMMR1,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Internal counter,2-bit gray counter"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TC_SMMR1,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Internal counter,2-bit gray counter"
|
|
endif
|
|
sif (cpu()=="ATSAMG53"||cpu()=="ATSAMG55")
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "TC_RAB,TC Register AB"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC_CV1,TC Counter Value Register"
|
|
if (((d.l(ad:0x40010040+0xE4))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TC_RA1,TC Register A"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "TC_RA1,TC Register A"
|
|
endif
|
|
if (((d.l(ad:0x40010040+0xE4))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TC_RB1,TC Register B"
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "TC_RB1,TC Register B"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TC_RC1,TC Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC_SR1,TC Status Register"
|
|
in
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TC_IMR1,TC Interrupt Mask Register"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " RXBUFF_set/clr ,Reception Buffer Full" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x04 9. -0x08 9. " ENDRX_set/clr ,End of Receiver Transfer" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x04 9. -0x08 9. " ETRGS_set/clr ,External Trigger" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x04 9. -0x08 9. " LDRBS_set/clr ,RB Loading" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x04 9. -0x08 9. " LDRAS_set/clr ,RA Loading" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x04 9. -0x08 9. " CPCS_set/clr ,RC Compare" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 9. -0x08 9. " CPBS_set/clr ,RB Compare" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x04 9. -0x08 9. " CPAS_set/clr ,RA Compare" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x04 9. -0x08 9. " LOVRS_set/clr ,Load Overrun" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x04 9. -0x08 9. " COVFS_set/clr ,Counter Overflow" "Masked,Not masked"
|
|
width 0xB
|
|
tree "TC0-1 PDC (Peripheral DMA Controller)"
|
|
width 10.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "TC1_RPR,Receive Pointer Register"
|
|
line.long 0x04 "TC1_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "TC1_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "TC1_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "TC1_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "TC1_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "TC1_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "TC1_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "TC1_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "TC1_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "TC0-Channel 2"
|
|
base ad:0x40010080
|
|
width 10.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC_CCR2,TC Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Started"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Yes"
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((d.l(ad:0x40010000+0xE4))&0x01)==0x00)
|
|
if (((d.l(ad:0x40010080+0x04))&0x8000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR2,TC Channel Mode Register"
|
|
sif !cpuis("ATSAMG53")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading Edge Subsampling Ratio" "One,Half,Fourth,Eight,Sixteenth,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Edge Selection" "None,Rising,Falling,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer Clock 1,Timer Clock 2,Timer Clock 3,Timer Clock 4,Timer Clock 5,XC0,XC1,XC2"
|
|
elif (((d.l(ad:0x40010080+0x04))&0x8000)==0x8000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR2,TC Channel Mode Register: Waveform Mode"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "Up,Up down,Up Rc,Up down Rc"
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "Not disabled,Disabled"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer clock1,Timer clock2,Timer clock3,Timer clock4,Timer clock5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR2,TC Channel Mode Register: Waveform Mode"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "Not disabled,Disabled"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer clock1,Timer clock2,Timer clock3,Timer clock4,Timer clock5,XC0,XC1,XC2"
|
|
endif
|
|
else
|
|
if (((d.l(ad:0x40010080+0x04))&0x8000)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR2,TC Channel Mode Register"
|
|
sif !cpuis("ATSAMG53")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading Edge Subsampling Ratio" "One,Half,Fourth,Eight,Sixteenth,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Edge Selection" "None,Rising,Falling,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer Clock 1,Timer Clock 2,Timer Clock 3,Timer Clock 4,Timer Clock 5,XC0,XC1,XC2"
|
|
elif (((d.l(ad:0x40010080+0x04))&0x8000)==0x8000)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR2,TC Channel Mode Register: Waveform Mode"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "Up,Up down,Up Rc,Up down Rc"
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "Not disabled,Disabled"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer clock1,Timer clock2,Timer clock3,Timer clock4,Timer clock5,XC0,XC1,XC2"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR2,TC Channel Mode Register: Waveform Mode"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "Not disabled,Disabled"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer clock1,Timer clock2,Timer clock3,Timer clock4,Timer clock5,XC0,XC1,XC2"
|
|
endif
|
|
endif
|
|
if (((d.l(ad:0x40010080+0xE4))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TC_SMMR2,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Internal counter,2-bit gray counter"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TC_SMMR2,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Internal counter,2-bit gray counter"
|
|
endif
|
|
sif (cpu()=="ATSAMG53"||cpu()=="ATSAMG55")
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "TC_RAB,TC Register AB"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC_CV2,TC Counter Value Register"
|
|
if (((d.l(ad:0x40010080+0xE4))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TC_RA2,TC Register A"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "TC_RA2,TC Register A"
|
|
endif
|
|
if (((d.l(ad:0x40010080+0xE4))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TC_RB2,TC Register B"
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "TC_RB2,TC Register B"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TC_RC2,TC Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC_SR2,TC Status Register"
|
|
in
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TC_IMR2,TC Interrupt Mask Register"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " RXBUFF_set/clr ,Reception Buffer Full" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x04 9. -0x08 9. " ENDRX_set/clr ,End of Receiver Transfer" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x04 9. -0x08 9. " ETRGS_set/clr ,External Trigger" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x04 9. -0x08 9. " LDRBS_set/clr ,RB Loading" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x04 9. -0x08 9. " LDRAS_set/clr ,RA Loading" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x04 9. -0x08 9. " CPCS_set/clr ,RC Compare" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 9. -0x08 9. " CPBS_set/clr ,RB Compare" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x04 9. -0x08 9. " CPAS_set/clr ,RA Compare" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x04 9. -0x08 9. " LOVRS_set/clr ,Load Overrun" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x04 9. -0x08 9. " COVFS_set/clr ,Counter Overflow" "Masked,Not masked"
|
|
width 0xB
|
|
tree "TC0-2 PDC (Peripheral DMA Controller)"
|
|
width 10.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "TC2_RPR,Receive Pointer Register"
|
|
line.long 0x04 "TC2_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "TC2_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "TC2_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "TC2_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "TC2_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "TC2_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "TC2_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "TC2_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "TC2_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
sif (cpu()=="ATSAMG53"||cpu()=="ATSAMG54"||cpu()=="ATSAMG55")
|
|
tree "TC1-Channel 0"
|
|
base ad:0x40014000
|
|
width 10.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC_CCR0,TC Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Started"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Yes"
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((d.l(ad:0x40014000+0xE4))&0x01)==0x00)
|
|
if (((d.l(ad:0x40014000+0x04))&0x8000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR0,TC Channel Mode Register"
|
|
sif !cpuis("ATSAMG53")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading Edge Subsampling Ratio" "One,Half,Fourth,Eight,Sixteenth,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Edge Selection" "None,Rising,Falling,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer Clock 1,Timer Clock 2,Timer Clock 3,Timer Clock 4,Timer Clock 5,XC0,XC1,XC2"
|
|
elif (((d.l(ad:0x40014000+0x04))&0x8000)==0x8000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR0,TC Channel Mode Register: Waveform Mode"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "Up,Up down,Up Rc,Up down Rc"
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "Not disabled,Disabled"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer clock1,Timer clock2,Timer clock3,Timer clock4,Timer clock5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR0,TC Channel Mode Register: Waveform Mode"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "Not disabled,Disabled"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer clock1,Timer clock2,Timer clock3,Timer clock4,Timer clock5,XC0,XC1,XC2"
|
|
endif
|
|
else
|
|
if (((d.l(ad:0x40014000+0x04))&0x8000)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR0,TC Channel Mode Register"
|
|
sif !cpuis("ATSAMG53")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading Edge Subsampling Ratio" "One,Half,Fourth,Eight,Sixteenth,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Edge Selection" "None,Rising,Falling,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer Clock 1,Timer Clock 2,Timer Clock 3,Timer Clock 4,Timer Clock 5,XC0,XC1,XC2"
|
|
elif (((d.l(ad:0x40014000+0x04))&0x8000)==0x8000)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR0,TC Channel Mode Register: Waveform Mode"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "Up,Up down,Up Rc,Up down Rc"
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "Not disabled,Disabled"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer clock1,Timer clock2,Timer clock3,Timer clock4,Timer clock5,XC0,XC1,XC2"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR0,TC Channel Mode Register: Waveform Mode"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "Not disabled,Disabled"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer clock1,Timer clock2,Timer clock3,Timer clock4,Timer clock5,XC0,XC1,XC2"
|
|
endif
|
|
endif
|
|
if (((d.l(ad:0x40014000+0xE4))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Internal counter,2-bit gray counter"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Internal counter,2-bit gray counter"
|
|
endif
|
|
sif (cpu()=="ATSAMG53"||cpu()=="ATSAMG55")
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "TC_RAB,TC Register AB"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC_CV0,TC Counter Value Register"
|
|
if (((d.l(ad:0x40014000+0xE4))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TC_RA0,TC Register A"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "TC_RA0,TC Register A"
|
|
endif
|
|
if (((d.l(ad:0x40014000+0xE4))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TC_RB0,TC Register B"
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "TC_RB0,TC Register B"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TC_RC0,TC Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC_SR0,TC Status Register"
|
|
in
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TC_IMR0,TC Interrupt Mask Register"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " RXBUFF_set/clr ,Reception Buffer Full" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x04 9. -0x08 9. " ENDRX_set/clr ,End of Receiver Transfer" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x04 9. -0x08 9. " ETRGS_set/clr ,External Trigger" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x04 9. -0x08 9. " LDRBS_set/clr ,RB Loading" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x04 9. -0x08 9. " LDRAS_set/clr ,RA Loading" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x04 9. -0x08 9. " CPCS_set/clr ,RC Compare" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 9. -0x08 9. " CPBS_set/clr ,RB Compare" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x04 9. -0x08 9. " CPAS_set/clr ,RA Compare" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x04 9. -0x08 9. " LOVRS_set/clr ,Load Overrun" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x04 9. -0x08 9. " COVFS_set/clr ,Counter Overflow" "Masked,Not masked"
|
|
width 0xB
|
|
tree "TC1-0 PDC (Peripheral DMA Controller)"
|
|
width 10.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "TC0_RPR,Receive Pointer Register"
|
|
line.long 0x04 "TC0_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "TC0_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "TC0_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "TC0_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "TC0_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "TC0_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "TC0_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "TC0_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "TC0_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "TC1-Channel 1"
|
|
base ad:0x40014040
|
|
width 10.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC_CCR1,TC Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Started"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Yes"
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((d.l(ad:0x40014000+0xE4))&0x01)==0x00)
|
|
if (((d.l(ad:0x40014040+0x04))&0x8000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR1,TC Channel Mode Register"
|
|
sif !cpuis("ATSAMG53")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading Edge Subsampling Ratio" "One,Half,Fourth,Eight,Sixteenth,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Edge Selection" "None,Rising,Falling,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer Clock 1,Timer Clock 2,Timer Clock 3,Timer Clock 4,Timer Clock 5,XC0,XC1,XC2"
|
|
elif (((d.l(ad:0x40014040+0x04))&0x8000)==0x8000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR1,TC Channel Mode Register: Waveform Mode"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "Up,Up down,Up Rc,Up down Rc"
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "Not disabled,Disabled"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer clock1,Timer clock2,Timer clock3,Timer clock4,Timer clock5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR1,TC Channel Mode Register: Waveform Mode"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "Not disabled,Disabled"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer clock1,Timer clock2,Timer clock3,Timer clock4,Timer clock5,XC0,XC1,XC2"
|
|
endif
|
|
else
|
|
if (((d.l(ad:0x40014040+0x04))&0x8000)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR1,TC Channel Mode Register"
|
|
sif !cpuis("ATSAMG53")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading Edge Subsampling Ratio" "One,Half,Fourth,Eight,Sixteenth,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Edge Selection" "None,Rising,Falling,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer Clock 1,Timer Clock 2,Timer Clock 3,Timer Clock 4,Timer Clock 5,XC0,XC1,XC2"
|
|
elif (((d.l(ad:0x40014040+0x04))&0x8000)==0x8000)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR1,TC Channel Mode Register: Waveform Mode"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "Up,Up down,Up Rc,Up down Rc"
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "Not disabled,Disabled"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer clock1,Timer clock2,Timer clock3,Timer clock4,Timer clock5,XC0,XC1,XC2"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR1,TC Channel Mode Register: Waveform Mode"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "Not disabled,Disabled"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer clock1,Timer clock2,Timer clock3,Timer clock4,Timer clock5,XC0,XC1,XC2"
|
|
endif
|
|
endif
|
|
if (((d.l(ad:0x40014040+0xE4))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TC_SMMR1,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Internal counter,2-bit gray counter"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TC_SMMR1,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Internal counter,2-bit gray counter"
|
|
endif
|
|
sif (cpu()=="ATSAMG53"||cpu()=="ATSAMG55")
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "TC_RAB,TC Register AB"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC_CV1,TC Counter Value Register"
|
|
if (((d.l(ad:0x40014040+0xE4))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TC_RA1,TC Register A"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "TC_RA1,TC Register A"
|
|
endif
|
|
if (((d.l(ad:0x40014040+0xE4))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TC_RB1,TC Register B"
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "TC_RB1,TC Register B"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TC_RC1,TC Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC_SR1,TC Status Register"
|
|
in
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TC_IMR1,TC Interrupt Mask Register"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " RXBUFF_set/clr ,Reception Buffer Full" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x04 9. -0x08 9. " ENDRX_set/clr ,End of Receiver Transfer" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x04 9. -0x08 9. " ETRGS_set/clr ,External Trigger" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x04 9. -0x08 9. " LDRBS_set/clr ,RB Loading" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x04 9. -0x08 9. " LDRAS_set/clr ,RA Loading" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x04 9. -0x08 9. " CPCS_set/clr ,RC Compare" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 9. -0x08 9. " CPBS_set/clr ,RB Compare" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x04 9. -0x08 9. " CPAS_set/clr ,RA Compare" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x04 9. -0x08 9. " LOVRS_set/clr ,Load Overrun" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x04 9. -0x08 9. " COVFS_set/clr ,Counter Overflow" "Masked,Not masked"
|
|
width 0xB
|
|
tree "TC1-1 PDC (Peripheral DMA Controller)"
|
|
width 10.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "TC1_RPR,Receive Pointer Register"
|
|
line.long 0x04 "TC1_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "TC1_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "TC1_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "TC1_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "TC1_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "TC1_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "TC1_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "TC1_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "TC1_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "TC1-Channel 2"
|
|
base ad:0x40014080
|
|
width 10.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TC_CCR2,TC Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Started"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Yes"
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((d.l(ad:0x40014000+0xE4))&0x01)==0x00)
|
|
if (((d.l(ad:0x40014080+0x04))&0x8000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR2,TC Channel Mode Register"
|
|
sif !cpuis("ATSAMG53")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading Edge Subsampling Ratio" "One,Half,Fourth,Eight,Sixteenth,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Edge Selection" "None,Rising,Falling,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer Clock 1,Timer Clock 2,Timer Clock 3,Timer Clock 4,Timer Clock 5,XC0,XC1,XC2"
|
|
elif (((d.l(ad:0x40014080+0x04))&0x8000)==0x8000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR2,TC Channel Mode Register: Waveform Mode"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "Up,Up down,Up Rc,Up down Rc"
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "Not disabled,Disabled"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer clock1,Timer clock2,Timer clock3,Timer clock4,Timer clock5,XC0,XC1,XC2"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR2,TC Channel Mode Register: Waveform Mode"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "Not disabled,Disabled"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer clock1,Timer clock2,Timer clock3,Timer clock4,Timer clock5,XC0,XC1,XC2"
|
|
endif
|
|
else
|
|
if (((d.l(ad:0x40014080+0x04))&0x8000)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR2,TC Channel Mode Register"
|
|
sif !cpuis("ATSAMG53")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading Edge Subsampling Ratio" "One,Half,Fourth,Eight,Sixteenth,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Edge Selection" "None,Rising,Falling,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB External Trigger Selection" "TIOB,TIOA"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stopped with RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer Clock 1,Timer Clock 2,Timer Clock 3,Timer Clock 4,Timer Clock 5,XC0,XC1,XC2"
|
|
elif (((d.l(ad:0x40014080+0x04))&0x8000)==0x8000)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR2,TC Channel Mode Register: Waveform Mode"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "Up,Up down,Up Rc,Up down Rc"
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "Not disabled,Disabled"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer clock1,Timer clock2,Timer clock3,Timer clock4,Timer clock5,XC0,XC1,XC2"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "TC_CMR2,TC Channel Mode Register: Waveform Mode"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "None,Rising,Falling,Edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable with RB Loading" "Not disabled,Disabled"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped with RC Compare" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "None,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "Timer clock1,Timer clock2,Timer clock3,Timer clock4,Timer clock5,XC0,XC1,XC2"
|
|
endif
|
|
endif
|
|
if (((d.l(ad:0x40014080+0xE4))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TC_SMMR2,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Internal counter,2-bit gray counter"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TC_SMMR2,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Internal counter,2-bit gray counter"
|
|
endif
|
|
sif (cpu()=="ATSAMG53"||cpu()=="ATSAMG55")
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "TC_RAB,TC Register AB"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TC_CV2,TC Counter Value Register"
|
|
if (((d.l(ad:0x40014080+0xE4))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TC_RA2,TC Register A"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "TC_RA2,TC Register A"
|
|
endif
|
|
if (((d.l(ad:0x40014080+0xE4))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TC_RB2,TC Register B"
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "TC_RB2,TC Register B"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TC_RC2,TC Register C"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TC_SR2,TC Status Register"
|
|
in
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TC_IMR2,TC Interrupt Mask Register"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " RXBUFF_set/clr ,Reception Buffer Full" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x04 9. -0x08 9. " ENDRX_set/clr ,End of Receiver Transfer" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x04 9. -0x08 9. " ETRGS_set/clr ,External Trigger" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x04 9. -0x08 9. " LDRBS_set/clr ,RB Loading" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x04 9. -0x08 9. " LDRAS_set/clr ,RA Loading" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x04 9. -0x08 9. " CPCS_set/clr ,RC Compare" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 9. -0x08 9. " CPBS_set/clr ,RB Compare" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x04 9. -0x08 9. " CPAS_set/clr ,RA Compare" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x04 9. -0x08 9. " LOVRS_set/clr ,Load Overrun" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x04 9. -0x08 9. " COVFS_set/clr ,Counter Overflow" "Masked,Not masked"
|
|
width 0xB
|
|
tree "TC1-2 PDC (Peripheral DMA Controller)"
|
|
width 10.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "TC2_RPR,Receive Pointer Register"
|
|
line.long 0x04 "TC2_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "TC2_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "TC2_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "TC2_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "TC2_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "TC2_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "TC2_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "TC2_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "TC2_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree "Common"
|
|
base ad:0x40010000
|
|
width 10.
|
|
sif cpuis("ATSAMG51")
|
|
wgroup.long 0xC0++0x03
|
|
line.long 0x00 "TC_BCR,TC Block Control Register"
|
|
bitfld.long 0x00 0. " SYNC ,Synchro Command Assertion" "No effect,Assert"
|
|
else
|
|
wgroup.long 0xC0++0x03
|
|
line.long 0x00 "TC_BCR0,TC Block Control Register"
|
|
bitfld.long 0x00 0. " SYNC ,Synchro Command Assertion" "No effect,Assert"
|
|
wgroup.long 0x40C0++0x03
|
|
line.long 0x00 "TC_BCR1,TC Block Control Register"
|
|
bitfld.long 0x00 0. " SYNC ,Synchro Command Assertion" "No effect,Assert"
|
|
endif
|
|
sif cpuis("ATSAMG51")
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "TC_BMR,TC Block Mode Register"
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External Clock Signal 2 Selection" "TCLK2,,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External Clock Signal 1 Selection" "TCLK1,,TIOA0,TIOA2"
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External Clock Signal 0 Selection" "TCLK0,,TIOA1,TIOA2"
|
|
else
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "TC_BMR0,TC Block Mode Register"
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External Clock Signal 2 Selection" "TCLK2,,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External Clock Signal 1 Selection" "TCLK1,,TIOA0,TIOA2"
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External Clock Signal 0 Selection" "TCLK0,,TIOA1,TIOA2"
|
|
group.long 0x40C4++0x03
|
|
line.long 0x00 "TC_BMR1,TC Block Mode Register"
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External Clock Signal 2 Selection" "TCLK2,,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External Clock Signal 1 Selection" "TCLK1,,TIOA0,TIOA2"
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External Clock Signal 0 Selection" "TCLK0,,TIOA1,TIOA2"
|
|
endif
|
|
sif cpuis("ATSAMG51")
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TC_WPMR,TC Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protection Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TC_WPMR0,TC Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protection Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
group.long 0x40E4++0x03
|
|
line.long 0x00 "TC_WPMR1,TC Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protection Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "ADC (Analog to Digital Converter)"
|
|
base ad:0x40038000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "ADC_CR,ADC Control Register"
|
|
sif ((cpu()=="ATSAMG54")||(cpu()=="ATSAMG55"))
|
|
bitfld.long 0x00 4. " CMPRST ,Comparison Restart" "No effect,Restart"
|
|
sif (cpu()=="ATSAMG54")
|
|
textline " "
|
|
bitfld.long 0x00 3. " AUTOCAL ,Automatic Calibration of ADC" "No effect,Start"
|
|
endif
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 3. " AUTOCAL ,Automatic Calibration of ADC" "No effect,Start"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " START ,Start Conversion" "No effect,Start"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "No effect,Reset"
|
|
textline " "
|
|
if ((d.l(ad:0x40038000+0xE4)&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ADC_MR,ADC Mode Register"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 31. " USEQ ,Use Sequence Enable" "Normal Mode,User Mode"
|
|
bitfld.long 0x00 28.--29. " TRANSFER ,Transfer Period" ",,2,?..."
|
|
bitfld.long 0x00 24.--27. " TRACKTIM ,Tracking Time" "0,1,2,3,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " ANACH ,Analog Change" "None,Allowed"
|
|
bitfld.long 0x00 20.--21. " SETTLING ,Analog Settling Time" "AST3,AST5,AST9,AST17"
|
|
bitfld.long 0x00 16.--19. " STARTUP ,Start Up Time" "SUT0,SUT8,SUT16,SUT24,SUT64,SUT80,SUT96,SUT112,SUT512,SUT576,SUT640,SUT704,SUT768,SUT832,SUT896,SUT960"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCAL ,Prescaler Rate Selection"
|
|
bitfld.long 0x00 7. " FREERUN ,Free Run Mode" "Off,On"
|
|
bitfld.long 0x00 6. " FWUP ,Fast Wake Up" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SLEEP ,Sleep Mode" "Normal,Sleep"
|
|
bitfld.long 0x00 1.--3. " TRGSEL ,Trigger Selection" "ADC TRIG0,ADC TRIG1,ADC TRIG2,ADC TRIG3,ADC TRIG4,ADC TRIG5,ADC TRIG6,?..."
|
|
bitfld.long 0x00 0. " TRGEN ,Trigger Enable" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 31. " USEQ ,Use Sequence Enable" "Normal Mode,User Mode"
|
|
bitfld.long 0x00 30. " DIV3 ,ADCClock Prescaler Division forced to 3" "No DIV3,Force DIV3"
|
|
bitfld.long 0x00 28.--29. " TRANSFER ,Transfer Period" ",,2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " TRACKTIM ,Tracking Time" "0,1,2,3,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x00 22. " DIV1 ,ADCClock Prescaler Division forced to 1" "No DIV1,Force DIV1"
|
|
bitfld.long 0x00 16.--19. " STARTUP ,Start Up Time" "SUT0,SUT8,SUT16,SUT24,SUT64,SUT80,SUT96,SUT112,SUT512,SUT576,SUT640,SUT704,SUT768,SUT832,SUT896,SUT960"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCAL ,Prescaler Rate Selection"
|
|
bitfld.long 0x00 7. " FREERUN ,Free Run Mode" "Off,On"
|
|
bitfld.long 0x00 5. " SLEEP ,Sleep Mode" "Normal,Sleep"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LOWRES ,Resolution" "12-Bits,10-Bits"
|
|
bitfld.long 0x00 4. " LOWRES ,Resolution" "10-Bits,8-Bits"
|
|
bitfld.long 0x00 1.--3. " TRGSEL ,Trigger Selection" "ADC TRIG0,ADC TRIG1,ADC TRIG2,ADC TRIG3,ADC TRIG4,ADC TRIG5,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " TRGEN ,Trigger Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ADC_MR,ADC Mode Register"
|
|
sif (cpu()=="ATSAMG55")
|
|
bitfld.long 0x00 31. " USEQ ,Use Sequence Enable" "Normal Mode,User Mode"
|
|
bitfld.long 0x00 28.--29. " TRANSFER ,Transfer Period" ",,2,?..."
|
|
bitfld.long 0x00 24.--27. " TRACKTIM ,Tracking Time" "0,1,2,3,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " ANACH ,Analog Change" "None,Allowed"
|
|
bitfld.long 0x00 20.--21. " SETTLING ,Analog Settling Time" "AST3,AST5,AST9,AST17"
|
|
bitfld.long 0x00 16.--19. " STARTUP ,Start Up Time" "SUT0,SUT8,SUT16,SUT24,SUT64,SUT80,SUT96,SUT112,SUT512,SUT576,SUT640,SUT704,SUT768,SUT832,SUT896,SUT960"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCAL ,Prescaler Rate Selection"
|
|
bitfld.long 0x00 7. " FREERUN ,Free Run Mode" "Off,On"
|
|
bitfld.long 0x00 6. " FWUP ,Fast Wake Up" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SLEEP ,Sleep Mode" "Normal,Sleep"
|
|
bitfld.long 0x00 1.--3. " TRGSEL ,Trigger Selection" "ADC TRIG0,ADC TRIG1,ADC TRIG2,ADC TRIG3,ADC TRIG4,ADC TRIG5,ADC TRIG6,?..."
|
|
bitfld.long 0x00 0. " TRGEN ,Trigger Enable" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 31. " USEQ ,Use Sequence Enable" "Normal Mode,User Mode"
|
|
bitfld.long 0x00 30. " DIV3 ,ADCClock Prescaler Division forced to 3" "No DIV3,Force DIV3"
|
|
bitfld.long 0x00 28.--29. " TRANSFER ,Transfer Period" ",,2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " TRACKTIM ,Tracking Time" "0,1,2,3,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x00 22. " DIV1 ,ADCClock Prescaler Division forced to 1" "No DIV1,Force DIV1"
|
|
bitfld.long 0x00 16.--19. " STARTUP ,Start Up Time" "SUT0,SUT8,SUT16,SUT24,SUT64,SUT80,SUT96,SUT112,SUT512,SUT576,SUT640,SUT704,SUT768,SUT832,SUT896,SUT960"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCAL ,Prescaler Rate Selection"
|
|
bitfld.long 0x00 7. " FREERUN ,Free Run Mode" "Off,On"
|
|
bitfld.long 0x00 5. " SLEEP ,Sleep Mode" "Normal,Sleep"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LOWRES ,Resolution" "12-Bits,10-Bits"
|
|
bitfld.long 0x00 4. " LOWRES ,Resolution" "10-Bits,8-Bits"
|
|
bitfld.long 0x00 1.--3. " TRGSEL ,Trigger Selection" "ADC TRIG0,ADC TRIG1,ADC TRIG2,ADC TRIG3,ADC TRIG4,ADC TRIG5,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " TRGEN ,Trigger Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if ((d.l(ad:0x40038000+0xE4)&0x01)==0x00)
|
|
if (((d.l(ad:0x40038000+0x04))&0x80000000)==0x80000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC_SEQR1,ADC Channel Sequence 1 Register"
|
|
bitfld.long 0x00 24.--27. " USCH7 ,User Sequence Number 7" "0,1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x00 20.--23. " USCH6 ,User Sequence Number 6" "0,1,2,3,4,5,6,7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " USCH5 ,User Sequence Number 5" "0,1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x00 12.--15. " USCH4 ,User Sequence Number 4" "0,1,2,3,4,5,6,7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " USCH3 ,User Sequence Number 3" "0,1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x00 4.--7. " USCH2 ,User Sequence Number 2" "0,1,2,3,4,5,6,7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USCH1 ,User Sequence Number 1" "0,1,2,3,4,5,6,7,?..."
|
|
else
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "ADC_SEQR1,ADC Channel Sequence 1 Register"
|
|
endif
|
|
else
|
|
if (((d.l(ad:0x40038000+0x04))&0x80000000)==0x80000000)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "ADC_SEQR1,ADC Channel Sequence 1 Register"
|
|
bitfld.long 0x00 24.--27. " USCH7 ,User Sequence Number 7" "0,1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x00 20.--23. " USCH6 ,User Sequence Number 6" "0,1,2,3,4,5,6,7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " USCH5 ,User Sequence Number 5" "0,1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x00 12.--15. " USCH4 ,User Sequence Number 4" "0,1,2,3,4,5,6,7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " USCH3 ,User Sequence Number 3" "0,1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x00 4.--7. " USCH2 ,User Sequence Number 2" "0,1,2,3,4,5,6,7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " USCH1 ,User Sequence Number 1" "0,1,2,3,4,5,6,7,?..."
|
|
else
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "ADC_SEQR1,ADC Channel Sequence 1 Register"
|
|
endif
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ADC_CHSR,Channel Status Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " CH7_set/clr ,Channel 7 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " CH6_set/clr ,Channel 6 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " CH5_set/clr ,Channel 5 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CH4_set/clr ,Channel 4 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CH3_set/clr ,Channel 3 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CH2_set/clr ,Channel 2 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " CH1_set/clr ,Channel 1 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " CH0_set/clr ,Channel 0 Status" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="ATSAMG55")
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "ADC_LCDR,ADC Last Converted Data Register"
|
|
bitfld.long 0x00 24.--28. " CHNBOSR ,Channel Number" "0,1,2,3,4,5,6,7,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " LDATA ,Last Data Converted"
|
|
textline " "
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "ADC_LCDR,ADC Last Converted Data Register"
|
|
bitfld.long 0x00 12.--15. " CHNB ,Channel Number" "0,1,2,3,4,5,6,7,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " LDATA ,Last Data Converted"
|
|
textline " "
|
|
endif
|
|
if (((d.l(ad:0x40038000+0x40))&0x1000000)==0x1000000)
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "ADC_LCDR,ADC Last Converted Data Register"
|
|
bitfld.long 0x00 12.--15. " CHNB ,Channel Number" "0,1,2,3,4,5,6,7,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " LDATA ,Last Data Converted"
|
|
textline " "
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "ADC_LCDR,ADC Last Converted Data Register"
|
|
bitfld.long 0x00 12.--15. " CHNB ,Channel Number" "0,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " LDATA ,Last Data Converted"
|
|
textline " "
|
|
endif
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ADC_IMR,ADC Interrupt Mask Register"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " RXBUFF ,Receive Buffer Full Interrupt Disabled" "Masked,Not masked"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " ENDRX ,End of Receive Buffer Interrupt Disabled" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " COMPE ,Comparison Event Interrupt Disabled" "Masked,Not masked"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " GOVRE ,General Overrun Error Interrupt Disabled" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x04 24. -0x04 24. " DRDY ,Data Ready Interrupt Disabled" "Masked,Not masked"
|
|
sif ((cpu()=="ATSAMG54")||(cpu()=="ATSAMG51"))
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " EOCAL ,End of Calibration Sequence" "Masked,Not masked"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " LCCHG ,Last Channel Change Interrupt Disabled" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " EOC7 ,End of Conversion Interrupt Disabled 7" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " EOC6 ,End of Conversion Interrupt Disabled 6" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " EOC5 ,End of Conversion Interrupt Disabled 5" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " EOC4 ,End of Conversion Interrupt Disabled 4" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " EOC3 ,End of Conversion Interrupt Disabled 3" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " EOC2 ,End of Conversion Interrupt Disabled 2" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " EOC1 ,End of Conversion Interrupt Disabled 1" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EOC0 ,End of Conversion Interrupt Disabled 0" "Masked,Not masked"
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "ADC_ISR,ADC Interrupt Status Register"
|
|
in
|
|
if ((d.l(ad:0x40038000+0xE4)&0x01)==0x00)
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "ADC_LCTMR,ADC Last Channel Trigger Mode Register"
|
|
bitfld.long 0x00 4.--5. " CMPMOD ,Last Channel Comparison Mode" "Low,High,In,Out"
|
|
bitfld.long 0x00 0. " DUALTRIG ,Dual Trigger ON" "All channels,Last channel"
|
|
line.long 0x04 "ADC_LCCWR,ADC Last Channel Compare Window Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " HIGHTHRES ,High Threshold"
|
|
hexmask.long.word 0x04 0.--11. 1. " LOWTHRES ,Low Threshold"
|
|
textline " "
|
|
else
|
|
rgroup.long 0x34++0x07
|
|
line.long 0x00 "ADC_LCTMR,ADC Last Channel Trigger Mode Register"
|
|
bitfld.long 0x00 4.--5. " CMPMOD ,Last Channel Comparison Mode" "Low,High,In,Out"
|
|
bitfld.long 0x00 0. " DUALTRIG ,Dual Trigger ON" "All channels,Last channel"
|
|
line.long 0x04 "ADC_LCCWR,ADC Last Channel Compare Window Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " HIGHTHRES ,High Threshold"
|
|
hexmask.long.word 0x04 0.--11. 1. " LOWTHRES ,Low Threshold"
|
|
textline " "
|
|
endif
|
|
hgroup.long 0x3C++0x03
|
|
hide.long 0x00 "ADC_OVER,ADC Overrun Status Register"
|
|
in
|
|
if ((d.l(ad:0x40038000+0xE4)&0x01)==0x00)
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "ADC_EMR,ADC Extended Mode Register"
|
|
bitfld.long 0x00 24. " TAG ,Tag of the ADC_LDCR" "CHNB = 0,Appends"
|
|
textline " "
|
|
sif ((cpu()=="ATSAMG54")||(cpu()=="ATSAMG55")||(cpu()=="ATSAMG53"))
|
|
bitfld.long 0x00 21. " SRCCLK ,External Clock Selection" "PERIPH_CLK,PMC_PCK"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " ASTE ,Averaging on Single Trigger Event" "Multi,Single"
|
|
sif (cpu()=="ATSAMG55")
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " OSR ,Over Sampling Rate" "NO_AVERAGE,OSR4,OSR16,OSR64,OSR256,?..."
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " OSR ,Over Sampling Rate" "No Average,OSR4,OSR16,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " CMPFILTER ,Compare Event Filtering" "0,1,2,3"
|
|
bitfld.long 0x00 9. " CMPALL ,Compare All Channels" "One channel,All channels"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CMPSEL ,Comparison Selected Channel" "0,1,2,3,4,5,6,7,?..."
|
|
textline " "
|
|
sif ((cpu()=="ATSAMG54")||(cpu()=="ATSAMG55")||(cpu()=="ATSAMG53"))
|
|
bitfld.long 0x00 2. " CMPTYPE ,Comparison Type" "FLAG_ONLY,Start_Cond"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CMPMODE ,Comparison Mode" "Low,High,In,Out"
|
|
else
|
|
rgroup.long 0x40++0x07
|
|
line.long 0x00 "ADC_EMR,ADC Extended Mode Register"
|
|
bitfld.long 0x00 24. " TAG ,Tag of the ADC_LDCR" "CHNB = 0,Appends"
|
|
textline " "
|
|
sif ((cpu()=="ATSAMG54")||(cpu()=="ATSAMG55")||(cpu()=="ATSAMG53"))
|
|
bitfld.long 0x00 21. " SRCCLK ,External Clock Selection" "PERIPH_CLK,PMC_PCK"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " ASTE ,Averaging on Single Trigger Event" "Multi,Single"
|
|
sif (cpu()=="ATSAMG55")
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " OSR ,Over Sampling Rate" "NO_AVERAGE,OSR4,OSR16,OSR64,OSR256,?..."
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " OSR ,Over Sampling Rate" "No Average,OSR4,OSR16,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " CMPFILTER ,Compare Event Filtering" "0,1,2,3"
|
|
bitfld.long 0x00 9. " CMPALL ,Compare All Channels" "One channel,All channels"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CMPSEL ,Comparison Selected Channel" "0,1,2,3,4,5,6,7,?..."
|
|
textline " "
|
|
sif ((cpu()=="ATSAMG54")||(cpu()=="ATSAMG55")||(cpu()=="ATSAMG53"))
|
|
bitfld.long 0x00 2. " CMPTYPE ,Comparison Type" "FLAG_ONLY,Start_Cond"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CMPMODE ,Comparison Mode" "Low,High,In,Out"
|
|
endif
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "ADC_CWR,ADC Compare Window Register"
|
|
sif (cpu()=="ATSAMG55")
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGHTHRES ,High Threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOWTHRES ,Low Threshold"
|
|
textline " "
|
|
else
|
|
hexmask.long.word 0x00 16.--27. 1. " HIGHTHRES ,High Threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWTHRES ,Low Threshold"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="ATSAMG55")
|
|
if ((d.l(ad:0x40038000+0xE4)&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ADC_COR,ADC Channel Offset Register"
|
|
bitfld.long 0x00 23. " DIFF7 ,Differential Inputs for Channel 7" "Single-ended mode,Fully differential mode"
|
|
bitfld.long 0x00 22. " DIFF6 ,Differential Inputs for Channel 6" "Single-ended mode,Fully differential mode"
|
|
bitfld.long 0x00 21. " DIFF5 ,Differential Inputs for Channel 5" "Single-ended mode,Fully differential mode"
|
|
textline " "
|
|
bitfld.long 0x00 20. " DIFF4 ,Differential Inputs for Channel 4" "Single-ended mode,Fully differential mode"
|
|
bitfld.long 0x00 19. " DIFF3 ,Differential Inputs for Channel 3" "Single-ended mode,Fully differential mode"
|
|
bitfld.long 0x00 18. " DIFF2 ,Differential Inputs for Channel 2" "Single-ended mode,Fully differential mode"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DIFF1 ,Differential Inputs for Channel 1" "Single-ended mode,Fully differential mode"
|
|
bitfld.long 0x00 16. " DIFF0 ,Differential Inputs for Channel 0" "Single-ended mode,Fully differential mode"
|
|
bitfld.long 0x00 7. " OFF7 ,Offset for Channel 7" "No offset,Signal on VADVREF/2"
|
|
textline " "
|
|
bitfld.long 0x00 6. " OFF6 ,Offset for Channel 6" "No offset,Signal on VADVREF/2"
|
|
bitfld.long 0x00 5. " OFF5 ,Offset for Channel 5" "No offset,Signal on VADVREF/2"
|
|
bitfld.long 0x00 4. " OFF4 ,Offset for Channel 4" "No offset,Signal on VADVREF/2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OFF3 ,Offset for Channel 3" "No offset,Signal on VADVREF/2"
|
|
bitfld.long 0x00 2. " OFF2 ,Offset for Channel 2" "No offset,Signal on VADVREF/2"
|
|
bitfld.long 0x00 1. " OFF1 ,Offset for Channel 1" "No offset,Signal on VADVREF/2"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OFF0 ,Offset for Channel 0" "No offset,Signal on VADVREF/2"
|
|
else
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ADC_COR,ADC Channel Offset Register"
|
|
bitfld.long 0x00 23. " DIFF7 ,Differential Inputs for Channel 7" "Single-ended mode,Fully differential mode"
|
|
bitfld.long 0x00 22. " DIFF6 ,Differential Inputs for Channel 6" "Single-ended mode,Fully differential mode"
|
|
bitfld.long 0x00 21. " DIFF5 ,Differential Inputs for Channel 5" "Single-ended mode,Fully differential mode"
|
|
textline " "
|
|
bitfld.long 0x00 20. " DIFF4 ,Differential Inputs for Channel 4" "Single-ended mode,Fully differential mode"
|
|
bitfld.long 0x00 19. " DIFF3 ,Differential Inputs for Channel 3" "Single-ended mode,Fully differential mode"
|
|
bitfld.long 0x00 18. " DIFF2 ,Differential Inputs for Channel 2" "Single-ended mode,Fully differential mode"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DIFF1 ,Differential Inputs for Channel 1" "Single-ended mode,Fully differential mode"
|
|
bitfld.long 0x00 16. " DIFF0 ,Differential Inputs for Channel 0" "Single-ended mode,Fully differential mode"
|
|
bitfld.long 0x00 7. " OFF7 ,Offset for Channel 7" "No offset,Signal on VADVREF/2"
|
|
textline " "
|
|
bitfld.long 0x00 6. " OFF6 ,Offset for Channel 6" "No offset,Signal on VADVREF/2"
|
|
bitfld.long 0x00 5. " OFF5 ,Offset for Channel 5" "No offset,Signal on VADVREF/2"
|
|
bitfld.long 0x00 4. " OFF4 ,Offset for Channel 4" "No offset,Signal on VADVREF/2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OFF3 ,Offset for Channel 3" "No offset,Signal on VADVREF/2"
|
|
bitfld.long 0x00 2. " OFF2 ,Offset for Channel 2" "No offset,Signal on VADVREF/2"
|
|
bitfld.long 0x00 1. " OFF1 ,Offset for Channel 1" "No offset,Signal on VADVREF/2"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OFF0 ,Offset for Channel 0" "No offset,Signal on VADVREF/2"
|
|
endif
|
|
endif
|
|
sif (cpu()=="ATSAMG55")
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "ADC_CDR0,ADC Channel Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Converted Data"
|
|
textline " "
|
|
else
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "ADC_CDR0,ADC Channel Data Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA ,Converted Data"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="ATSAMG55")
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "ADC_CDR1,ADC Channel Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Converted Data"
|
|
textline " "
|
|
else
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "ADC_CDR1,ADC Channel Data Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA ,Converted Data"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="ATSAMG55")
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "ADC_CDR2,ADC Channel Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Converted Data"
|
|
textline " "
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "ADC_CDR2,ADC Channel Data Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA ,Converted Data"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="ATSAMG55")
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "ADC_CDR3,ADC Channel Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Converted Data"
|
|
textline " "
|
|
else
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "ADC_CDR3,ADC Channel Data Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA ,Converted Data"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="ATSAMG55")
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "ADC_CDR4,ADC Channel Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Converted Data"
|
|
textline " "
|
|
else
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "ADC_CDR4,ADC Channel Data Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA ,Converted Data"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="ATSAMG55")
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "ADC_CDR5,ADC Channel Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Converted Data"
|
|
textline " "
|
|
else
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "ADC_CDR5,ADC Channel Data Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA ,Converted Data"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="ATSAMG55")
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "ADC_CDR6,ADC Channel Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Converted Data"
|
|
textline " "
|
|
else
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "ADC_CDR6,ADC Channel Data Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA ,Converted Data"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="ATSAMG55")
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "ADC_CDR7,ADC Channel Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Converted Data"
|
|
textline " "
|
|
else
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "ADC_CDR7,ADC Channel Data Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DATA ,Converted Data"
|
|
textline " "
|
|
endif
|
|
if ((d.l(ad:0x40038000+0xE4)&0x01)==0x00)
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "ADC_ACR,ADC Analog Control Register"
|
|
bitfld.long 0x00 30.--31. " AUTOTEST ,ADC Auto-test Modes" "NO_AUTOTEST,OFFSET_ ERROR,GAIN_ERROR_HIGH,GAIN_ERROR_LOW"
|
|
else
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "ADC_ACR,ADC Analog Control Register"
|
|
bitfld.long 0x00 30.--31. " AUTOTEST ,ADC Auto-test Modes" "NO_AUTOTEST,OFFSET_ ERROR,GAIN_ERROR_HIGH,GAIN_ERROR_LOW"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "ADC_WPMR,ADC Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protection Key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "ADC_WPSR,ADC Write Protection Status Register"
|
|
in
|
|
textline " "
|
|
width 0xB
|
|
tree "ADC PDC (Peripheral DMA Controller)"
|
|
width 10.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "ADC_RPR,Receive Pointer Register"
|
|
line.long 0x04 "ADC_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "ADC_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "ADC_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "ADC_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "ADC_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "ADC_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "ADC_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "ADC_PTCR,PDC Transfer Control Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERRCLR ,Transfer Bus Error Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " TXCBDIS ,Transmitter Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " RXCBDIS ,Receiver Circular Buffer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "No effect,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enabled"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "ADC_PTSR,PDC Transfer Status Register"
|
|
sif (cpu()=="ATSAMG54"||cpu()=="ATSAMG55"||cpu()=="ATSAMG53")
|
|
bitfld.long 0x00 24. " ERR ,Transfer Bus Error" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " TXCBEN ,Transmitter Circular Buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXCBEN ,Receiver Circular Buffer Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
sif (cpu()=="ATSAMG55")
|
|
tree "CMCC (Cortex-M Cache Controller)"
|
|
base ad:0x4003C000
|
|
width 13.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CMCC_TYPE,Cache Controller Type Register"
|
|
bitfld.long 0x00 11.--13. " CLSIZE ,Cache Line Size" "CLSIZE_1KB,CLSIZE_2KB,CLSIZE_4KB,CLSIZE_8KB,?..."
|
|
bitfld.long 0x00 8.--10. " CSIZE ,Data Cache Size" "CSIZE_1KB,CSIZE_2KB,CSIZE_4KB,CSIZE_8KB,?..."
|
|
bitfld.long 0x00 7. " LCKDOWN ,Lockdown Supported" "Not supported,Supported"
|
|
bitfld.long 0x00 5.--6. " WAYNUM ,Number of Ways" "DMAPPED,ARCH2WAY,ARCH4WAY,ARCH8WAY"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RRP ,Random Selection Policy Supported" "Not supported,Supported"
|
|
bitfld.long 0x00 3. " LRUP ,Least Recently Used Policy Supported" "Not supported,Supported"
|
|
bitfld.long 0x00 2. " RANDP ,Random Selection Policy Supported" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GCLK ,Dynamic Clock Gating Supported" "Not supported,Dynamic CLK"
|
|
bitfld.long 0x00 0. " AP ,Access Port Access Allowed" "Disabled,Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CMCC_CFG,Cache Controller Configuration Register"
|
|
bitfld.long 0x00 4.--6. " PRGCSIZE ,Programmable Cache Size" ",PRGCSIZE_2KB,PRGCSIZE_4KB,PRGCSIZE_8KB,?..."
|
|
bitfld.long 0x00 2. " DCDIS ,Data Caching Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 1. " ICDIS ,Instruction Caching Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " GCLKDIS ,Disable Clock Gating" "Activated,Disabled"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "CMCC_CTRL,Cache Controller Control Register"
|
|
bitfld.long 0x00 0. " CEN ,Cache Controller Enable" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CMCC_SR,Cache Controller Status Register"
|
|
bitfld.long 0x00 0. " CSTS ,Cache Controller Status" "Disabled,Enabled"
|
|
wgroup.long 0x20++0x07
|
|
line.long 0x00 "CMCC_MAINT0,Cache Controller Maintenance Register 0"
|
|
bitfld.long 0x00 0. " INVALL ,Cache Controller Invalidate All" "No effect,Invalidate"
|
|
line.long 0x04 "CMCC_MAINT1,Cache Controller Maintenance Register 1"
|
|
bitfld.long 0x04 30.--31. " WAY ,Invalidate Way" "WAY0,WAY1,WAY2,WAY3"
|
|
bitfld.long 0x04 4.--8. " INDEX ,Invalidate Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x28++0x07
|
|
line.long 0x00 "CMCC_MCFG,Cache Controller Monitor Configuration Register"
|
|
bitfld.long 0x00 0.--1. " MODE ,Cache Controller Monitor Counter Mode" "CYCLE_COUNT,IHIT_COUNT,DHIT_COUNT,?..."
|
|
line.long 0x04 "CMCC_MEN,Cache Controller Monitor Enable Register"
|
|
bitfld.long 0x04 0. " MENABLE , Cache Controller Monitor Enable" "Disabled,Enabled"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "CMCC_MCTRL,Cache Controller Monitor Control Register"
|
|
bitfld.long 0x00 0. " SWRST ,Monitor" "No effect,Reset"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "CMCC_MSR,Cache Controller Monitor Status Register"
|
|
width 0xB
|
|
tree.end
|
|
tree "CRCCU (Cyclic Redundancy Check Calculation Unit)"
|
|
base ad:0x40048000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CRCCU_DSCR,CRCCU Descriptor Base Address Register"
|
|
hexmask.long.tbyte 0x00 9.--31. 0x02 " DSCR ,Descriptor Base Address"
|
|
wgroup.long 0x08++0x07
|
|
line.long 0x00 "CRCCU_DMA_EN,CRCCU DMA Enable Register"
|
|
bitfld.long 0x00 0. " DMAEN ,DMA Enable" "No effect,Enable"
|
|
line.long 0x04 "CRCCU_DMA_DIS,CRCCU DMA Disable Register"
|
|
bitfld.long 0x04 0. " DMADIS ,DMA Disable" "No effect,Disable"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CRCCU_DMA_SR,CRCCU DMA Status Register"
|
|
bitfld.long 0x00 0. " DMASR ,DMA Status" "Disabled,Enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CRCCU_DMA_IMR,CRCCU DMA Interrupt Mask Register"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DMAIMR_set/clr ,Interrupt Mask" "Masked,Not masked"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "CRCCU_DMA_ISR,CRCCU DMA Interrupt Status Register"
|
|
in
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "CRCCU_CR,CRCCU Control Register"
|
|
bitfld.long 0x00 0. " RESET ,CRC Computation Reset" "No effect,Reset"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CRCCU_MR,CRCCU Mode Register"
|
|
bitfld.long 0x00 17. " BITORDER ,Precomputation Bit Swap Operation of the CRC" "MSBFIRST,LSBFIRST"
|
|
bitfld.long 0x00 4.--7. " DIVIDER ,Request Divider" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " PTYPE ,Primitive Polynomial" "CCITT8023,CASTAGNOLI,CCITT16,?..."
|
|
bitfld.long 0x00 1. " COMPARE ,CRC Compare" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,CRC Enable" ",Enabled"
|
|
if (((d.l(ad:0x40048000+0x38))&0x02)==0x02)
|
|
hgroup.long 0x3C++0x03
|
|
hide.long 0x00 "CRCCU_SR,CRCCU Status Register"
|
|
else
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "CRCCU_SR,CRCCU Status Register"
|
|
hexmask.long 0x00 0.--31. 1. " CRC ,Cyclic Redundancy Check Value"
|
|
endif
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CRCCU_IMR,CRCCU Interrupt Mask Register"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " ERRIMR ,CRC Error Interrupt Mask" "Masked,Not masked"
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "CRCCU_ISR,CRCCU Interrupt Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
textline ""
|