22432 lines
1.1 MiB
22432 lines
1.1 MiB
; --------------------------------------------------------------------------------
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; @Title: ATSAMA5D29 On-Chip Peripherals
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; @Props: Released
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; @Author: JDU, NEJ
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; @Changelog: 2023-06-23 JDU
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; 2023-11-07 NEJ
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; 2023-11-23 NEJ
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; @Manufacturer: MICROCHIP - Microchip Technology Inc.
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; @Doc: Generated (TRACE32, build: 164623.), based on:
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; ATSAMA5D29_fixed.svd (Ver. 0)
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; @Core: Cortex-A5
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; @Chip: ATSAMA5D29
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; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: peratsama5d29.per 17103 2023-11-25 11:20:10Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "Core Registers (Cortex-A5)"
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width 0x8
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; --------------------------------------------------------------------------------
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; Identification registers
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; --------------------------------------------------------------------------------
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tree "ID Registers"
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rgroup.long c15:0x0++0x0
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line.long 0x0 "MIDR,Main ID Register"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
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bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 16.--19. " ARCH , Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7"
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textline " "
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hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number"
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bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long c15:0x100++0x0
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line.long 0x0 "CTR,Cache Type Register"
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bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7"
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bitfld.long 0x0 24.--27. " CWG ,Cache Writeback Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x0 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
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textline " "
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bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical"
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bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
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rgroup.long c15:0x200++0x0
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line.long 0x0 "TCMTR,Tighly-Coupled Memory Type Register"
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rgroup.long c15:0x300++0x0
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line.long 0x0 "TLBTR,TLB Type Register"
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hexmask.long.byte 0x0 16.--23. 0x1 " ILSIZE ,Specifies the number of instruction TLB lockable entries"
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hexmask.long.byte 0x0 8.--15. 0x1 " DLSIZE ,Specifies the number of unified or data TLB lockable entries"
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bitfld.long 0x0 1. " TLB_SIZE ,TLB Size" "64,128"
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textline " "
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bitfld.long 0x0 0. " NU ,Unified or Separate TLBs" "Unified,Separate"
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rgroup.long c15:0x500++0x0
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line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
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bitfld.long 0x00 30. " U ,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor"
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bitfld.long 0x00 8.--11. " CLUSTERID ,Value read in CLUSTERID configuration pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--1. " CPUID ,Value depends on the number of configured CPUs" "0,1,2,3"
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rgroup.long c15:0x0410++0x00
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line.long 0x00 "MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " OSS ,Outer Shareable Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support" "Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
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rgroup.long c15:0x0510++0x00
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line.long 0x00 "MMFR1,Memory Model Feature Register 1"
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bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Reserved,Reserved,Required,?..."
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bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
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bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
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rgroup.long c15:0x0610++0x00
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line.long 0x00 "MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
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bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
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bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
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rgroup.long c15:0x0710++0x00
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line.long 0x00 "MMFR3,Memory Model Feature Register 3"
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bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..."
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bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..."
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bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 8.--11. " BPM ,Invalidate Branch predictor Support" "Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache MVA Support" "Reserved,Supported,?..."
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rgroup.long c15:0x0020++0x00
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line.long 0x00 "ISAR0,Instruction Set Attribute Register 0"
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bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Reserved,Supported,?..."
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rgroup.long c15:0x0120++0x00
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line.long 0x00 "ISAR1,Instruction Set Attribute Register 1"
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bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " EXTI ,Extend Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..."
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rgroup.long c15:0x0220++0x00
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line.long 0x00 "ISAR2,Instruction Set Attribute Register 2"
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bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
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rgroup.long c15:0x0320++0x00
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line.long 0x00 "ISAR3,Instruction Set Attribute Register 3"
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bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
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rgroup.long c15:0x0420++0x00
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line.long 0x00 "ISAR4,Instruction Set Attribute Register 4"
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bitfld.long 0x00 28.--31. " SWP_FRAC ,SWAP_frac" "Supported,?..."
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bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " SPRI ,Synchronization Primitive instructions" "Not supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " SMCI ,SMC Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
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rgroup.long c15:0x0520++0x00
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line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)"
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rgroup.long c15:0x0620++0x00
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line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)"
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rgroup.long c15:0x0720++0x00
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line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)"
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rgroup.long c15:0x0010++0x00
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line.long 0x00 "PFR0,Processor Feature Register 0"
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bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
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rgroup.long c15:0x0110++0x00
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line.long 0x00 "PFR1,Processor Feature Register 1"
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bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Not supported,?..."
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bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
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rgroup.long c15:0x0210++0x00
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line.long 0x00 "DFR0,Debug Feature Register 0"
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bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
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bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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rgroup.long c15:0x0310++0x00
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line.long 0x00 "AFR0,Auxiliary Feature Register 0"
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hexmask.long 0x00 0.--31. 1. " AF ,Auxiliary Feature"
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tree.end
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width 0x8
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tree "System Control and Configuration"
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group.long c15:0x1++0x0
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line.long 0x0 "SCTLR,Control Register"
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bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
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bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled"
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bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x0 27. " NMFI ,DNonmaskable Fast Interrupt enable" "Disabled,Enabled"
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bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
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bitfld.long 0x0 14. " RR ,Replacement strategy for caches, BTAC, and micro TLBs" "Random,Round robin"
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textline " "
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bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
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bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled"
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bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled"
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bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled"
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bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled"
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textline " "
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bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled"
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group.long c15:0x101++0x0
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line.long 0x0 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 28. " DBDI ,Disable branch dual issue" "No,Yes"
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bitfld.long 0x00 18. " BTDIS ,Disable indirect Branch Target Address Cache" "No,Yes"
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bitfld.long 0x00 17. " RSDIS ,Disable return stack operation" "No,Yes"
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textline " "
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bitfld.long 0x00 15.--16. " BP ,Branch prediction policy" "Normal,Taken,Not taken,?..."
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bitfld.long 0x00 13.--14. " L1PCTL ,L1 Data prefetch control" "Disabled,1 prefetch,2 prefetches,3 prefetches"
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bitfld.long 0x00 12. " RADIS ,Disable Data Cache read-allocate mode" "No,Yes"
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textline " "
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bitfld.long 0x00 11. " DWBST ,Disable data write bursts to normal non-cacheable memory" "No,Yes"
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bitfld.long 0x00 10. " DODMBS ,Disable optimized Data Memory Barrier behavior" "No,Yes"
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bitfld.long 0x00 7. " EXCL ,Exclusive L1/L2 cache control" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 6. " SMP ,Data requests with Inner Cacheable Shared attributes are treated as cacheable" "Disabled,Enabled"
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bitfld.long 0x00 0. " FW ,FW" "Low,High"
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group.long c15:0x201++0x0
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line.long 0x0 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes"
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bitfld.long 0x0 30. " D32DIS ,Disable use of D16-D31 of the VFP register file" "No,Yes"
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bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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group.long c15:0x11++0x0
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line.long 0x0 "SCR,Secure Configuration Register"
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bitfld.long 0x00 6. " NET ,Not early termination" "Not early,Early"
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bitfld.long 0x00 5. " AW ,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed"
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bitfld.long 0x00 4. " FW ,FW-bit controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed"
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textline " "
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bitfld.long 0x00 3. " EA ,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
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bitfld.long 0x00 2. " FIQ ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
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bitfld.long 0x00 1. " IRQ ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
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textline " "
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bitfld.long 0x00 0. " NS ,Secure mode " "Secure,Non-secure"
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group.long c15:0x111++0x0
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line.long 0x0 "SDER,Secure Debug Enable Register"
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bitfld.long 0x00 1. " SUNIDEN ,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted"
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bitfld.long 0x00 0. " SUIDEN ,Invasive Secure User Debug Enable bit" "Denied,Permitted"
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group.long c15:0x0211++0x00
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line.long 0x00 "NSACR,Non-Secure Access Control Register"
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bitfld.long 0x00 18. " NS_SMP ,Determines if the SMP bit of the Auxiliary Control Register is writable in Non-secure state" "Disabled,Enabled"
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bitfld.long 0x00 17. " TL ,Lockable Page Table Entries Allocation in Nonsecure World" "Denied,Permitted"
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bitfld.long 0x00 15. " NSASEDIS ,Disable Non-secure Advanced SIMD Extension functionality" "Denied,Permitted"
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textline " "
|
|
bitfld.long 0x00 14. " NSD32DIS ,Disable the Non-secure use of D16-D31 of the VFP register" "Denied,Permitted"
|
|
bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
group.long c15:0x0311++0x00
|
|
line.long 0x00 "VCR,Virtualization Control Register"
|
|
bitfld.long 0x00 8. " AMO ,Abort Mask Override" "0,1"
|
|
bitfld.long 0x00 7. " IMO ,IRQ Mask Override" "0,1"
|
|
bitfld.long 0x00 6. " IFO ,FIQ Mask Override" "0,1"
|
|
textline " "
|
|
group.long c15:0x000c++0x00
|
|
line.long 0x00 "VBAR,Secure or Nonsecure Vector Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " VBA ,Base Address"
|
|
group.long c15:0x10c++0x00
|
|
line.long 0x0 "MVBAR,Monitor Vector Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " MVBA , Monitor Vector Base Address"
|
|
rgroup.long c15:0x1C++0x0
|
|
line.long 0x0 "ISR,Interrupt status Register"
|
|
bitfld.long 0x0 8. " A ,Pending External Abort" "Not pending,Pending"
|
|
bitfld.long 0x0 7. " I ,Pending IRQ" "Not pending,Pending"
|
|
bitfld.long 0x0 6. " F ,Pending FIQ" "Not pending,Pending"
|
|
group.long c15:0x11c++0x0
|
|
line.long 0x00 "VIR,Virtualization Interrupt Register"
|
|
bitfld.long 0x00 8. " VA ,Virtual Abort" "0,1"
|
|
bitfld.long 0x00 7. " VI ,Virtual IRQ" "0,1"
|
|
bitfld.long 0x00 6. " VF ,Virtual FIQ" "0,1"
|
|
group.long c15:0x400f++0x0
|
|
line.long 0x00 "CBAR,Configuration Base Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " CBA ,Configuration Base Address"
|
|
tree.end
|
|
width 0x08
|
|
tree "Memory Management Unit"
|
|
group.long c15:0x1++0x0
|
|
line.long 0x0 "SCTLR,Control Register"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 27. " NMFI ,DNonmaskable Fast Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
|
|
bitfld.long 0x0 14. " RR ,Replacement strategy for caches, BTAC, and micro TLBs" "Random,Round robin"
|
|
textline " "
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled"
|
|
textline " "
|
|
group.long c15:0x0002++0x00
|
|
line.long 0x00 "TTBR0,Translation Table Base Register 0"
|
|
hexmask.long 0x00 14.--31. 0x4000 " TTB0 ,Translation Table Base Address"
|
|
bitfld.long 0x00 6. 0. " IRGN[1:0] ,Indicates inner cacheability" "Noncacheable,Back/allocated,Through,Back/not allocated"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated"
|
|
bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared"
|
|
group.long c15:0x0102++0x00
|
|
line.long 0x00 "TTBR1,Translation Table Base Register 1"
|
|
hexmask.long 0x00 14.--31. 0x4000 " TTB1 ,Translation Table Base Address"
|
|
bitfld.long 0x00 6. 0. " IRGN[1:0] ,Indicates inner cacheability" "Noncacheable,Back/allocated,Through,Back/not allocated"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated"
|
|
bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared"
|
|
group.long c15:0x0202++0x00
|
|
line.long 0x00 "TTBCR,Translation Table Base Control Register"
|
|
bitfld.long 0x00 5. " PD1 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 1" "Enable,Disable"
|
|
bitfld.long 0x00 4. " PD0 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 0" "Enable,Disable"
|
|
bitfld.long 0x0 0.--2. " N ,Translation Table Base Register 0 page table boundary size" "Off,0x80000000,0x40000000,0x20000000,0x10000000,0x08000000,0x04000000,0x02000000"
|
|
textline " "
|
|
group.long c15:0x3--0x3
|
|
line.long 0x0 "DACR,Domain Access Control Register"
|
|
bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
group.long c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
group.long c15:0x0006++0x00
|
|
line.long 0x00 "DFAR,Data Fault Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " DFA ,Data Fault Address"
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " SD ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
group.long c15:0x0206++0x00
|
|
line.long 0x00 "IFAR,Instruction Fault Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " IFA ,Instruction Fault Address"
|
|
group.long c15:0x0015++0x00
|
|
line.long 0x00 "DAFSR,Data Auxiliary Fault Status Register"
|
|
hexmask.long 0x00 0.--31. 1. " DAFS ,Data Auxiliary Fault Status"
|
|
group.long c15:0x0115++0x00
|
|
line.long 0x00 "IAFSR,Instruction Auxiliary Fault Status Register"
|
|
hexmask.long 0x00 0.--31. 1. " IAFS ,Instruction Auxiliary Fault Status"
|
|
textline " "
|
|
group.long c15:0x0047++0x00
|
|
line.long 0x00 "PAR,PA Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " PA ,Physical Adress"
|
|
bitfld.long 0x00 9. " NS ,Non-secure" "Not secured,Secured"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SH ,Shareable attribute" "Non-shareable,Shareable"
|
|
bitfld.long 0x00 4.--6. " Inner ,Signals region inner attributes" "Noncacheable,Strongly-ordered,Reserved,Device,Reserved,Write-back allocate,Write-through,Write-back"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " Outer ,Signals region outer attributes for normal memory type" "Noncacheable,Write-back allocate,Write-through,Write-back"
|
|
bitfld.long 0x00 1. " SS ,Supersection Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " F ,Translation Successful" "Successful,No successful"
|
|
textline " "
|
|
group.long c15:0x002A++0x0
|
|
line.long 0x00 "PRRR,Primary Region Remap Register"
|
|
bitfld.long 0x00 19. " NS1 ,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped"
|
|
bitfld.long 0x00 18. " NS0 ,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DS1 ,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped"
|
|
bitfld.long 0x00 16. " DS0 ,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " TR7 ,{TEX[0] C B} = b111 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 12.--13. " TR6 ,{TEX[0] C B} = b110 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " TR5 ,{TEX[0] C B} = b101 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 8.--9. " TR4 ,{TEX[0] C B} = b100 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TR3 ,{TEX[0] C B} = b011 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 4.--5. " TR2 ,{TEX[0] C B} = b010 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " TR1 ,{TEX[0] C B} = b001 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 0.--1. " TR0 ,{TEX[0] C B} = b000 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
group.long c15:0x012A++0x0
|
|
line.long 0x00 "NMRR,Normal Memory Remap Register"
|
|
bitfld.long 0x00 30.--31. " OR7 ,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 28.--29. " OR6 ,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " OR5 ,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 24.--25. " OR4 ,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " OR3 ,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 20.--21. " OR2 ,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " OR1 ,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 16.--17. " OR0 ,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " IR7 ,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 12.--13. " IR6 ,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IR5 ,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 8.--9. " IR4 ,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " IR3 ,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 4.--5. " IR2 ,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " IR1 ,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 0.--1. " IR0 ,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
group.long c15:0x500f++0x0
|
|
line.long 0x00 "TLBHR,TLB Hitmap Register"
|
|
bitfld.long 0x00 3. " 16MB ,16MB supersections are present in the TLB" "no,yes"
|
|
bitfld.long 0x00 2. " 1MB ,1MB sections are present in the TLB" "no,yes"
|
|
bitfld.long 0x00 1. " 16kB ,16kB pages are present in the TLB" "no,yes"
|
|
bitfld.long 0x00 0. " 4kB ,4kB pages are present in the TLB" "no,yes"
|
|
textline " "
|
|
group.long c15:0x10d++0x0
|
|
line.long 0x0 "CONTEXT,Context ID Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. " PROCID ,Process ID"
|
|
hexmask.long.byte 0x0 0.--7. 1. " ASID ,Application Space ID"
|
|
group.long c15:0x020d++0x00
|
|
line.long 0x00 "URWTPID,User Read/Write Thread and Process ID Register"
|
|
hexmask.long 0x00 0.--31. 1. " URWTPID ,User Read/Write Thread and Process ID"
|
|
group.long c15:0x030d++0x00
|
|
line.long 0x00 "UROTPID,User Read-Only Thread and Process ID Register"
|
|
hexmask.long 0x00 0.--31. 1. " UROTPID ,User Read-Only Thread and Process ID"
|
|
group.long c15:0x040d++0x00
|
|
line.long 0x00 "POTPID,Privileged Only Thread and Process ID Register"
|
|
hexmask.long 0x00 0.--31. 1. " POTPID ,Privileged Only Thread and Process ID"
|
|
tree.end
|
|
width 0x8
|
|
tree "Cache Control and Configuration"
|
|
rgroup.long c15:0x1100++0x0
|
|
line.long 0x0 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " CTYPE8 ,Cache type for levels 8" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 18.--20. " CTYPE7 ,Cache type for levels 7" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " CTYPE6 ,Cache type for levels 6" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 12.--14. " CTYPE5 ,Cache type for levels 5" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " CTYPE4 ,Cache type for levels 4" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 6.--8. " CTYPE3 ,Cache type for levels 3" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CTYPE2 ,Cache type for levels 2" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 0.--2. " CTYPE1 ,Cache type for levels 1" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
rgroup.long c15:0x1700++0x0
|
|
line.long 0x0 "AIDR,Auxiliary ID Register"
|
|
hexmask.long 0x00 0.--31. 1. " AID ,Auxiliary ID"
|
|
rgroup.long c15:0x1000++0x0
|
|
line.long 0x0 "CCSIDR,Current Cache Size ID Register"
|
|
bitfld.long 0x00 31. " WT ,Write-Through" "Not Supported,Supported"
|
|
bitfld.long 0x00 30. " WB ,Write-Back" "Not Supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 29. " RA ,Read-Allocate" "Not Supported,Supported"
|
|
bitfld.long 0x00 28. " WA ,Write-Allocate" "Not Supported,Supported"
|
|
textline " "
|
|
hexmask.long.word 0x00 13.--27. 1. " SETS ,Number of Sets"
|
|
hexmask.long.word 0x00 3.--12. 1. " ASSOC ,Associativity"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words"
|
|
group.long c15:0x2000++0x0
|
|
line.long 0x0 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Level" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
bitfld.long 0x00 0. " IND ,Instruction/Not Data" "Data,Instruction"
|
|
tree.end
|
|
width 0x8
|
|
tree "L2 Preload Engine"
|
|
rgroup c15:0x000b++0x00
|
|
line.long 0x00 "PLEIDR,PLE Identification Register 0"
|
|
bitfld.long 0x00 0. " CH0P ,Channel 0 Present" "Not present,Present"
|
|
rgroup c15:0x020b++0x00
|
|
line.long 0x00 "PLESR,PLE Status Register"
|
|
bitfld.long 0x00 0. " CH0R ,Channel 0 Run" "Not running,Running"
|
|
rgroup c15:0x040b++0x00
|
|
line.long 0x00 "PLEFSR,PLE FIFO Status Register"
|
|
group c15:0x001b++0x00
|
|
line.long 0x00 "PLEUAR,PLE User Accessibility Register"
|
|
bitfld.long 0x00 0. " U0 ,User Mode Process Access Registers for Channel 0 Permission" "Not permitted,Permitted"
|
|
group c15:0x011b++0x00
|
|
line.long 0x00 "PLEPCR,PLE Parameters Control Register"
|
|
tree.end
|
|
width 12.
|
|
tree "System Performance Monitor"
|
|
group.long c15:0xC9++0x0
|
|
line.long 0x0 "PMCR,Performance Monitor Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code"
|
|
bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. " DP ,Disable CCNT when prohibited" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " X ,Export Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " D ,Clock Divider" "Every cycle,64th cycle"
|
|
bitfld.long 0x00 2. " C ,Clock Counter Reset" "No action,Reset"
|
|
bitfld.long 0x00 1. " P ,Performance Counter Reset" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " E ,Counters Enable" "Disabled,Enabled"
|
|
group.long c15:0x1C9++0x0
|
|
line.long 0x0 "PMCNTENSET,Count Enable Set Register"
|
|
bitfld.long 0x00 31. " C ,CCNT Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,PMN5 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,PMN5 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,PMN3 Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,PMN2 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,PMN1 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,PMN0 Enabled" "Disabled,Enabled"
|
|
group.long c15:0x2C9++0x0
|
|
line.long 0x0 "PMCNTENCLR,Count Enable Clear Register"
|
|
bitfld.long 0x00 31. " C ,CCNT Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,PMN5 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,PMN5 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,PMN3 Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,PMN2 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,PMN1 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,PMN0 Enabled" "Disabled,Enabled"
|
|
group.long c15:0x3C9++0x0
|
|
line.long 0x0 "PMOVSR,Overflow Flag Status Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 5. " P5 ,PMN5 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 4. " P4 ,PMN5 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 2. " P2 ,PMN2 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 overflow" "No overflow,Overflow"
|
|
wgroup.long c15:0x4C9++0x0
|
|
line.long 0x0 "PMSWINC,Software Increment Register"
|
|
eventfld.long 0x00 5. " P5 ,Increment PMN2" "No action,Increment"
|
|
eventfld.long 0x00 4. " P4 ,Increment PMN1" "No action,Increment"
|
|
eventfld.long 0x00 3. " P3 ,Increment PMN3" "No action,Increment"
|
|
eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment"
|
|
textline " "
|
|
eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment"
|
|
eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment"
|
|
group.long c15:0x5C9++0x0
|
|
line.long 0x0 "PMSELR,Performance Counter Selection Register"
|
|
bitfld.long 0x00 0.--5. " SEL ,Selection value" "CNT0,CNT1,CNT2,CNT3,CNT4,CNT5,?..."
|
|
group.long c15:0xD9++0x0
|
|
line.long 0x00 "PMCCNTR,Cycle Count Register"
|
|
group.long c15:0x01d9++0x00
|
|
line.long 0x00 "PMXEVTYPER,Event Selection Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group.long c15:0x02d9++0x00
|
|
line.long 0x00 "PMCNT,Performance Monitor Count Register"
|
|
group.long c15:0xE9++0x0
|
|
line.long 0x0 "PMUSERENR,User Enable Register"
|
|
bitfld.long 0x00 0. " EN ,User Mode Enable" "Disabled,Enabled"
|
|
group.long c15:0x1E9++0x0
|
|
line.long 0x0 "PMINTENSET,Interrupt Enable Set Register"
|
|
bitfld.long 0x00 31. " C ,CCNT Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
group.long c15:0x2E9++0x0
|
|
line.long 0x0 "PMINTENCLR,Interrupt Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Overflow Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 5. " P5 ,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 4. " P4 ,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 2. " P2 ,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 0xb
|
|
tree "Debug"
|
|
width 10.
|
|
tree "Debug Registers"
|
|
rgroup c14:0x000--0x000
|
|
line.long 0x0 "DBGDIDR,Debug ID Register"
|
|
bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 20.--23. " Context ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " Version ,Debug Architecture Version" "Reserved,ARMv6,ARMv6.1,ARMv7,?..."
|
|
textline " "
|
|
bitfld.long 0x0 13. " PCSAMPLE ,PC Sample register implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x0 12. " Security ,Security Extensions implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x0 4.--7. " Variant ,Implementation-defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " Revision ,Implementation-defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
group c14:0x22--0x22
|
|
line.long 0x0 "DBGDSCR,Debug Status and Control Register"
|
|
bitfld.long 0x0 30. " DTRRXfull ,The DTRRX Full Flag" "Empty,Full"
|
|
bitfld.long 0x0 29. " DTRTXfull ,The DTRTX Full Flag" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DTRRXfull_l ,The DTRRX Full Flag 1" "Empty,Full"
|
|
bitfld.long 0x00 26. " DTRTXfull_l ,The DTRTX Full Flag 1" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SPA ,Sticky Pipeline Advance" "No effect,Instruction retired"
|
|
bitfld.long 0x0 24. " IC ,Instruction Complete" "Executing,Not executing"
|
|
textline " "
|
|
bitfld.long 0x0 20.--21. " DTR ,DTR Access Mode" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x0 19. " NSWS ,Imprecise Data Aborts discarded" "Not discarded,Discarded"
|
|
textline " "
|
|
bitfld.long 0x0 18. " NS ,Non-secure World Status" "Secured,Not secured"
|
|
bitfld.long 0x0 17. " nSPNIDEN ,Secure Non-invasive Debug Disabled" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 16. " nSPIDEN ,Secure Invasive Debug Disabled" "Enabled,Disabled"
|
|
bitfld.long 0x0 15. " MONITOR ,Monitor Debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 14. " HDEn ,Halting Debug-mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 13. " EXECUTE ,Execute instruction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " COMMS ,User mode access to Comms Channel disable" "Enabled,Disabled"
|
|
bitfld.long 0x0 11. " IntDis ,Disable Interrupts" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " DbgAck ,Force Debug Acknowledge" "Not forced,Forced"
|
|
bitfld.long 0x0 8. " uExt ,Sticky Undefined Exception" "No exception,Exception"
|
|
textline " "
|
|
bitfld.long 0x0 7. " IABORT ,Sticky Imprecise Abort" "Not aborted,Aborted"
|
|
bitfld.long 0x0 6. " PABORT ,Sticky Precise Abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x0 2.--5. " MOE ,Method of Debug Entry" "Debug Entry,Breakpoint,Imprecise Watchpoint,BKPT instruction,External debug,Vector catch,Reserved,Reserved,OS Unlock,?..."
|
|
bitfld.long 0x0 1. " RESTARTED ,Core Restarted" "Debug not exited,Debug exited"
|
|
textline " "
|
|
bitfld.long 0x0 0. " HALTED ,Core Halted" "Normal state,Debug state"
|
|
textline " "
|
|
if (((per.long(c14:0x00))&0x01000)==0x00000)
|
|
group c14:0x007--0x007
|
|
line.long 0x0 "DBGVCR,Vector Catch Register"
|
|
bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " DABORT ,Vector Catch Enable Data Abort" "Disabled,Enabled"
|
|
bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled"
|
|
else
|
|
group c14:0x007--0x007
|
|
line.long 0x0 "DBGVCR,Vector Catch Register"
|
|
bitfld.long 0x0 31. " FIQN ,Vector Catch Enable FIQ (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 30. " IRQN ,Vector Catch Enable IRQ (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 28. " DABORTN ,Vector Catch Enable Data Abort (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 27. " PABORTN ,Vector Catch Enable Prefetch abort (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 26. " SWIN ,Vector Catch Enable SWI (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 25. " UNDEFS ,Vector Catch Enable Undefined (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 15. " FIQS ,Vector Catch Enable FIQ (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " IRQS ,Vector Catch Enable IRQ (Secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " DABORTS ,Vector Catch Enable Data Abort (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PABORTS ,Vector Catch Enable Prefetch abort (Secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " SMI ,Vector Catch Enable SMI (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " DABORT0 ,Vector Catch Enable Data Abort" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled"
|
|
endif
|
|
hgroup c14:0x020--0x020
|
|
hide.long 0x0 "DBGDTRRX,Debug Receive Register (External View)"
|
|
in
|
|
group c14:0x023--0x023
|
|
line.long 0x0 "DBGDTRTX,Debug Transmit Register (External View)"
|
|
group c14:0x09++0x00
|
|
line.long 0x00 "DBGECR,Event Catch Register"
|
|
bitfld.long 0x00 0. " OSUC ,OS Unlock Catch" "Disabled,Enabled"
|
|
group c14:0x0a++0x00
|
|
line.long 0x00 "DBGDSCCR,Debug State Cache Control Register"
|
|
bitfld.long 0x00 2. " NWT ,Not Write-Through" "Forced,Normal"
|
|
bitfld.long 0x00 0. " DUCL ,Data and Unified Cache Linefill" "Disabled,Normal"
|
|
wgroup c14:0x21++0x00
|
|
line.long 0x00 "DBGITR,Instruction Transfer Register"
|
|
rgroup c14:0x21++0x00
|
|
line.long 0x00 "DBGPCSR,Program Counter Sampling Register"
|
|
hexmask.long 0x00 2.--31. 1. " PCSV ,Program Counter sample value"
|
|
bitfld.long 0x00 0.--1. " MPCSV ,Meaning of PC sample value" "ARM,Thumb,Jazelle,Thumb"
|
|
wgroup c14:0x24++0x00
|
|
line.long 0x00 "DBGDRCR,Debug Run Control Register"
|
|
bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RR ,Restart Request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " HR ,Halt Request" "Not requested,Requested"
|
|
rgroup c14:0x28++0x00
|
|
line.long 0x00 "DBGPCSR,Program Counter Sampling Register"
|
|
hexmask.long 0x00 2.--31. 1. " PCSV ,Program Counter sample value"
|
|
bitfld.long 0x00 0.--1. " MPCSV ,Meaning of PC sample value" "ARM,Thumb,Jazelle,Thumb"
|
|
rgroup c14:0x29++0x00
|
|
line.long 0x00 "DBGCIDSR,Context ID Sampling Register"
|
|
wgroup c14:0xc0++0x00
|
|
line.long 0x00 "DBGOSLAR,Operating System Lock Access Register"
|
|
rgroup c14:0xc1++0x00
|
|
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
|
|
bitfld.long 0x00 2. " 32_BA ,32-Bit Access" "Not required,Required"
|
|
bitfld.long 0x00 1. " LB ,Locked Bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LIB ,Lock Implemented Bit" "Not implemented,Implemented"
|
|
group c14:0xc2++0x00
|
|
line.long 0x00 "DBGOSSRR,Operating System Save and Restore Register"
|
|
hexmask.long 0x00 0.--31. 1. " OSSR ,OS Save and Restore"
|
|
group c14:0xc4++0x00
|
|
line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register"
|
|
bitfld.long 0x00 2. " HNDLR ,Hold non-debug logic reset" "Not held,Held"
|
|
bitfld.long 0x00 0. " DBGNOPWRDWN ,DBGNOPWRDWN output signal" "Low,High"
|
|
group c14:0xc5++0x00
|
|
line.long 0x00 "DBGPRSR,Device Power-Down and Reset Status Register"
|
|
bitfld.long 0x00 3. " SR ,Sticky Reset Status" "Not reset,Reset"
|
|
bitfld.long 0x00 2. " R ,Reset Status" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPD ,Sticky Power-down Status" "Not reset,Reset"
|
|
bitfld.long 0x00 0. " PU ,Power-up Status" "Powered down,Powered up"
|
|
width 11.
|
|
tree "Processor Identifier Registers"
|
|
rgroup c14:0x340--0x340
|
|
line.long 0x00 "CPUID,Main ID Register"
|
|
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
|
|
hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture"
|
|
hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision"
|
|
rgroup c14:0x341--0x341
|
|
line.long 0x00 "CACHETYPE,Cache Type Register"
|
|
bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7"
|
|
bitfld.long 0x0 24.--27. " CWG ,Cache Writeback Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " DMinLine ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " L1_Ipolicy ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " IMinLine ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
rgroup c14:0x343--0x343
|
|
line.long 0x00 "TLBTYPE,TLB Type Register"
|
|
hexmask.long.byte 0x0 16.--23. 0x1 " ILsize ,Specifies the number of instruction TLB lockable entries"
|
|
hexmask.long.byte 0x0 8.--15. 0x1 " DLsize ,Specifies the number of unified or data TLB lockable entries"
|
|
textline " "
|
|
bitfld.long 0x0 1. " TLB_size ,TLB Size" "64,128"
|
|
bitfld.long 0x0 0. " U ,Unified or separate instruction TLBs" "Unified,Separate"
|
|
rgroup c14:0x348--0x348
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 12.--15. " State3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " State2 ,Java Extension Interface Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " State1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " State0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x349--0x349
|
|
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x34a--0x34a
|
|
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
rgroup c14:0x34b--0x34b
|
|
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " AF ,Auxiliary Feature"
|
|
rgroup c14:0x34c--0x34c
|
|
line.long 0x00 "ID_MMFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
|
|
bitfld.long 0x00 12.--15. " OSS ,Outer Shareable Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
rgroup c14:0x34d--0x34d
|
|
line.long 0x00 "ID_MMFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Reserved,Reserved,Required,?..."
|
|
bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
|
|
rgroup c14:0x34e--0x34e
|
|
line.long 0x00 "ID_MMFR2,Processor Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
|
|
bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
rgroup c14:0x34f--0x34f
|
|
line.long 0x00 "ID_MMFR3,Processor Feature Register 3"
|
|
bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..."
|
|
bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " BPM ,Invalidate Branch predictor Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache MVA Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x350--0x350
|
|
line.long 0x00 "ID_ISAR0,ISA Feature Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x351--0x351
|
|
line.long 0x00 "ID_ISAR1,ISA Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " INTI ,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " EXTI ,Extend Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " ENDI ,Endian Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x352--0x352
|
|
line.long 0x00 "ID_ISAR2,ISA Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x353--0x353
|
|
line.long 0x00 "ID_ISAR3,ISA Feature Register 3"
|
|
bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x354--0x354
|
|
line.long 0x00 "ID_ISAR4,ISA Feature Register 4"
|
|
bitfld.long 0x00 28.--31. " SWP_frac ,SWAP_frac" "Supported,?..."
|
|
bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " SPRI ,Synchronization Primitive instructions" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SMCI ,SMC Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
rgroup c14:0x355--0x355
|
|
line.long 0x00 "ID_ISAR5,ISA Feature Register 5 (Reserved)"
|
|
tree.end
|
|
width 17.
|
|
tree "Coresight Management Registers"
|
|
textline " "
|
|
group c14:0x03bd++0x00
|
|
line.long 0x00 "DBGITCTRL_IOC,Integration Internal Output Control Register"
|
|
bitfld.long 0x00 5. " I_DBGTRIGGER ,Internal DBGTRIGGER" "0,1"
|
|
bitfld.long 0x00 4. " I_DBGRESTARTED ,Internal DBGRESTARTED" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I_nPMUIRQ ,Internal nPMUIRQ" "0,1"
|
|
bitfld.long 0x00 2. " InternalCOMMTX ,Internal COMMTX" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I_COMMRX ,Internal COMMRX" "0,1"
|
|
bitfld.long 0x00 0. " I_DBGACK ,Internal DBGACK" "0,1"
|
|
group c14:0x03be++0x00
|
|
line.long 0x00 "DBGITCTRL_EOC,Integration External Output Control Register"
|
|
bitfld.long 0x00 7. " nDMAEXTERRIQ ,External nDMAEXTERRIRQ" "0,1"
|
|
bitfld.long 0x00 6. " nDMASIRQ ,External nDMASIRQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " nDMAIRQ ,External nDMAIRQ" "0,1"
|
|
bitfld.long 0x00 4. " nPMUIRQ ,External nPMUIRQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STANDBYWFI ,External STANDBYWFI" "0,1"
|
|
bitfld.long 0x00 2. " COMMTX ,External COMMTX" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " COMMRX ,External COMMRX" "0,1"
|
|
bitfld.long 0x00 0. " DBGACK ,External DBGACK" "0,1"
|
|
rgroup c14:0x03bf++0x00
|
|
line.long 0x00 "DBGITCTRL_IS,Integration Input Status Register"
|
|
bitfld.long 0x00 11. " CTI_DBGRESTART ,CTI Debug Restart" "0,1"
|
|
bitfld.long 0x00 10. " CTI_EDBGRQ ,CTI Debug Request" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CTI_PMUEXTIN[1] ,CTI PMUEXTIN[1] Signal" "0,1"
|
|
bitfld.long 0x00 8. " CTI_PMUEXTIN[0] ,CTI PMUEXTIN[0] Signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " nFIQ ,nFIQ Input" "0,1"
|
|
bitfld.long 0x00 1. " nIRQ ,nIRQ Input" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EDBGRQ ,EDBGRQ Input" "0,1"
|
|
group c14:0x3c0--0x3c0
|
|
line.long 0x0 "DBGITCTRL,Integration Mode Control Register"
|
|
bitfld.long 0x0 0. " IME ,Integration Mode Enable" "Disabled,Enabled"
|
|
group c14:0x3e8--0x3e8
|
|
line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Set"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Set"
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Set"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Set"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Set"
|
|
group c14:0x3e9--0x3e9
|
|
line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Cleared"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Cleared"
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Cleared"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Cleared"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Cleared"
|
|
wgroup c14:0x3ec--0x3ec
|
|
line.long 0x0 "DBGLAR,Lock Access Register"
|
|
rgroup c14:0x3ed--0x3ed
|
|
line.long 0x0 "DBGLSR,Lock Status Register"
|
|
bitfld.long 0x00 2. " NTT ,Not 32-bit access" "32-bit,Not 32-bit"
|
|
bitfld.long 0x00 1. " SLK ,Software Lock status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SLI ,Software Lock Implemented" "Not implemented,Implemented"
|
|
rgroup c14:0x3ee--0x3ee
|
|
line.long 0x0 "DBGAUTHSTATUS,Debug Authentication Status Register"
|
|
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug features implementation" "No effect,Implemented"
|
|
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enable (DBGEN OR NIDEN) AND (SPIDEN OR SPNIDEN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SI ,Secure invasive debug features implementation" "No effect,Implemented"
|
|
bitfld.long 0x00 4. " SE ,Secure invasive debug enable (DBGEN AND SPIDEN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implementation" "Not implemented,Implemented"
|
|
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enable (DBGEN OR NIDEN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implementation" "Not implemented,Implemented"
|
|
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enable (DBGEN)" "Disabled,Enabled"
|
|
hgroup c14:0x3f2--0x3f2
|
|
hide.long 0x0 "DBGDEVID,Device Identifier (RESERVED)"
|
|
rgroup c14:0x3f3--0x3f3
|
|
line.long 0x0 "DBGDEVTYPE,Device Type"
|
|
bitfld.long 0x00 4.--7. " T ,Sub type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " C ,Main class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup c14:0x3f8--0x3f8
|
|
line.long 0x00 "DBGPID0,Debug Peripheral ID 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PN[7:0] ,Part Number [7:0]"
|
|
rgroup c14:0x3f9--0x3f9
|
|
line.long 0x00 "DBGPID1,Debug Peripheral ID 1"
|
|
hexmask.long.byte 0x00 4.--7. 1. " JEPID[3:0] ,JEP Identity Code[3:0]"
|
|
hexmask.long.byte 0x00 0.--3. 1. " PN[11:8] ,Part Number [11:8]"
|
|
rgroup c14:0x3fa--0x3fa
|
|
line.long 0x00 "DBGPID2,Debug Peripheral ID 2"
|
|
hexmask.long.byte 0x00 4.--7. 1. " REV ,Revision"
|
|
bitfld.long 0x00 3. " UJEPCODE ,Uses JEP Code" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--2. 1. " JEPID[6:4] ,JEP Identity Code[6:4]"
|
|
rgroup c14:0x3fb--0x3fb
|
|
line.long 0x00 "DBGPID3,Debug Peripheral ID 3"
|
|
hexmask.long.byte 0x00 4.--7. 1. " REVAND ,Manufacturing revision"
|
|
hexmask.long.byte 0x00 0.--3. 1. " CM ,Customer modified"
|
|
rgroup c14:0x3f4--0x3f4
|
|
line.long 0x00 "DBGPID4,Debug Peripheral ID 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " 4KB_COUNT ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CONT_CODE ,JEP 106 Continuation code"
|
|
rgroup c14:0x3fc--0x3fc
|
|
line.long 0x00 "DBGCID0,Debug Component ID 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 0"
|
|
rgroup c14:0x3fd--0x3fd
|
|
line.long 0x00 "DBGCID1,Debug Component ID 1"
|
|
hexmask.long.byte 0x00 4.--7. 1. " CC ,Component class"
|
|
hexmask.long.byte 0x00 0.--3. 1. " PREAMBLE ,Preamble byte 1"
|
|
rgroup c14:0x3fe--0x3fe
|
|
line.long 0x00 "DBGCID2,Debug Component ID 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 2"
|
|
rgroup c14:0x3ff--0x3ff
|
|
line.long 0x00 "DBGCID3,Debug Component ID 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 3"
|
|
tree.end
|
|
tree.end
|
|
width 6.
|
|
tree "Breakpoint Registers"
|
|
group c14:0x40++0x00
|
|
line.long 0x00 "BVR0,Breakpoint Value Register 0"
|
|
group c14:0x50++0x00
|
|
line.long 0x00 "BCR0,Breakpoint Control Register 0"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x41++0x00
|
|
line.long 0x00 "BVR1,Breakpoint Value Register 1"
|
|
group c14:0x51++0x00
|
|
line.long 0x00 "BCR1,Breakpoint Control Register 1"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x42++0x00
|
|
line.long 0x00 "BVR2,Breakpoint Value Register 2"
|
|
group c14:0x52++0x00
|
|
line.long 0x00 "BCR2,Breakpoint Control Register 2"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 6.
|
|
tree "Watchpoint Control Registers"
|
|
group c14:0x60++0x00
|
|
line.long 0x00 "WVR0,Watchpoint Value Register 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group c14:0x70--0x70
|
|
line.long 0x0 "WCR0,Watchpoint Control Register 0"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x61++0x00
|
|
line.long 0x00 "WVR1,Watchpoint Value Register 1"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA1 ,Watchpoint Address 1"
|
|
group c14:0x71--0x71
|
|
line.long 0x0 "WCR1,Watchpoint Control Register 1"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x006--0x006
|
|
line.long 0x0 "WFAR,Watchpoint Fault Address Register"
|
|
hexmask.long.long 0x00 1.--31. 0x02 " WFAR ,Address of the watchpointed instruction"
|
|
textline " "
|
|
tree.end
|
|
tree.end
|
|
width 0x0B
|
|
sif corename()=="CORTEXA5MPCORE"
|
|
width 9.
|
|
base ad:(d.l(c15:0x400f))
|
|
tree "Snoop Control Unit (SCU)"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SCUCR,SCU Control Register"
|
|
bitfld.long 0x00 2. " PON ,Parity ON" "Off,On"
|
|
bitfld.long 0x00 1. " AFEN ,Address filtering enable" "Off,On"
|
|
bitfld.long 0x00 0. " SCUEN ,SCU enable" "Disabled,Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SCUCON,SCU Configuration Register"
|
|
bitfld.long 0x00 14.--15. " RAM3 ,Cortex-A9 CPU3 Tag RAM Size" "16KB,32KB,Reserved,64KB"
|
|
bitfld.long 0x00 12.--13. " RAM2 ,Cortex-A9 CPU2 Tag RAM Size" "16KB,32KB,Reserved,64KB"
|
|
bitfld.long 0x00 10.--11. " RAM1 ,Cortex-A9 CPU1 Tag RAM Size" "16KB,32KB,Reserved,64KB"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RAM0 ,Cortex-A9 CPU0 Tag RAM Size" "16KB,32KB,Reserved,64KB"
|
|
bitfld.long 0x00 7. " MOD3 ,CPU3 Mode" "AMP,SMP"
|
|
bitfld.long 0x00 6. " MOD2 ,CPU2 Mode" "AMP,SMP"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MOD1 ,CPU1 Mode" "AMP,SMP"
|
|
bitfld.long 0x00 4. " MOD0 ,CPU0 Mode" "AMP,SMP"
|
|
bitfld.long 0x00 0.--1. " NUM ,CPU Number" "CPU0,CPU0-CPU1,CPU0-CPU2,CPU0-CPU3"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SCUSTAT,SCU CPU Power Status Register"
|
|
bitfld.long 0x00 24.--25. " STAT3 ,CPU3 Status" "Normal,Reserved,Dormant,Powered-off"
|
|
bitfld.long 0x00 16.--17. " STAT2 ,CPU2 Status" "Normal,Reserved,Dormant,Powered-off"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " STAT1 ,CPU1 Status" "Normal,Reserved,Dormant,Powered-off"
|
|
bitfld.long 0x00 0.--1. " STAT0 ,CPU0 Status" "Normal,Reserved,Dormant,Powered-off"
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "INV,SCU Invalidate All Register"
|
|
bitfld.long 0x00 12.--15. " WAY3 ,Cortex-A9 CPU3 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " WAY2 ,Cortex-A9 CPU2 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " WAY1 ,Cortex-A9 CPU1 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " WAY0 ,Cortex-A9 CPU0 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FSAR,Filtering Start Address Register"
|
|
hexmask.long.word 0x00 20.--31. 0x10 " FSA ,Filtering start address"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "FEAR,Filtering End Address Register"
|
|
hexmask.long.word 0x00 20.--31. 0x10 " FEA ,Filtering end address"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "SAC,SCU Access Control Register"
|
|
bitfld.long 0x00 3. " CPU3 ,CPU3 Access the SAC" "No access,Access"
|
|
bitfld.long 0x00 2. " CPU2 ,CPU2 Access the SAC" "No access,Access"
|
|
bitfld.long 0x00 1. " CPU1 ,CPU1 Access the SAC" "No access,Access"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CPU0 ,CPU0 Access the SAC" "No access,Access"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SSAC,SCU Secure Access Control Register"
|
|
bitfld.long 0x00 11. " GCPU3 ,Global timer for CPU3" "Secure only,Secure/Non-secure"
|
|
bitfld.long 0x00 10. " GCPU2 ,Global timer for CPU2" "Secure only,Secure/Non-secure"
|
|
bitfld.long 0x00 9. " GCPU1 ,Global timer for CPU1" "Secure only,Secure/Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 8. " GCPU0 ,Global timer for CPU0" "Secure only,Secure/Non-secure"
|
|
bitfld.long 0x00 7. " TCPU3 ,Private timer for CPU3 Access" "Secure only,Secure/Non-secure"
|
|
bitfld.long 0x00 6. " TCPU2 ,Private timer for CPU2 Access" "Secure only,Secure/Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TCPU1 ,Private timer for CPU1 Access" "Secure only,Secure/Non-secure"
|
|
bitfld.long 0x00 4. " TCPU0 ,Private timer for CPU0 Access" "Secure only,Secure/Non-secure"
|
|
bitfld.long 0x00 3. " CPU3 ,CPU3 Access the SAC" "No access,Access"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CPU2 ,CPU2 Access the SAC" "No access,Access"
|
|
bitfld.long 0x00 1. " CPU1 ,CPU1 Access the SAC" "No access,Access"
|
|
bitfld.long 0x00 0. " CPU0 ,CPU0 Access the SAC" "No access,Access"
|
|
tree.end
|
|
width 0xb
|
|
width 8.
|
|
tree "Timer and Watchdog Blocks"
|
|
base ad:(d.l(c15:0x400f))+0x600
|
|
group.long 0x00++0xb "Timer"
|
|
line.long 0x00 "TLR,Timer Load Register"
|
|
line.long 0x04 "TCR,Timer Counter Register"
|
|
line.long 0x08 "TCONR,Timer Control Register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " PRES ,Prescaler"
|
|
bitfld.long 0x08 3. " AINC ,Auto Increment" "Single shot,Auto increment"
|
|
bitfld.long 0x08 2. " IRQEN ,IRQ Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " COMPEN ,Comp Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " TEN ,Global Timer Enable" "Disabled,Enabled"
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TISR,Timer Interrupt Status Register"
|
|
eventfld.long 0x00 0. " EFLAG ,Event Flag" "0,1"
|
|
group.long 0x20++0x13 "Watchdog"
|
|
line.long 0x00 "WLR,Watchdog Load Register"
|
|
line.long 0x04 "WCR,Watchdog Counter Register"
|
|
line.long 0x08 "WCONR,Watchdog Control Register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " PRES ,Prescaler"
|
|
bitfld.long 0x08 3. " WDM ,WD Mode" "Timer,Watchdog"
|
|
bitfld.long 0x08 2. " ITEN ,IT Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " AREL ,Auto-Reload" "Single shot,Auto-reload"
|
|
textline " "
|
|
bitfld.long 0x08 0. " WEN ,Watchdog Enable" "Disabled,Enabled"
|
|
line.long 0x0c "WISR,Watchdog Interrupt Status Register"
|
|
eventfld.long 0x0C 0. " EFLAG ,Event Flag" "0,1"
|
|
line.long 0x10 "WRSR,Watchdog Reset Sent Register"
|
|
eventfld.long 0x10 0. " RFLAG ,Reset Flag" "No effect,Reset"
|
|
wgroup.long 0x34++0x3
|
|
line.long 0x00 "WDR,Watchdog Disable Register"
|
|
base ad:(d.l(c15:0x400f))+0x200
|
|
group.long 0x00++0xb "Global Timer"
|
|
line.long 0x00 "GTLCR,Lower 32-bit Timer Counter Register"
|
|
line.long 0x04 "GTUCR,Upper 32-bit Timer Counter Register"
|
|
line.long 0x08 "GTCONR,Timer Control Register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " PRES ,Prescaler"
|
|
bitfld.long 0x08 3. " AINC ,Auto Increment" "Single shot,Auto increment"
|
|
bitfld.long 0x08 2. " IRQEN ,IRQ Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " COMPEN ,Comp Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " TEN ,Global Timer Enable" "Disabled,Enabled"
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "GTSR,Timer Status Register"
|
|
eventfld.long 0x00 0. " EFLAG ,Event Flag" "0,1"
|
|
group.long 0x10++0xb
|
|
line.long 0x00 "GTLCOMR,Lower 32-bit Comparator Register"
|
|
line.long 0x04 "GTUCOMR,Upper 32-bit Comparator Register"
|
|
line.long 0x08 "GTINCR,Auto-increment Register for Comparator"
|
|
tree.end
|
|
width 11.
|
|
endif
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree "ACC (Analog Comparator Controller)"
|
|
base ad:0xF804A000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 12. "INV,Invert Comparator Output" "0: Analog comparator output is directly processed.,1: Analog comparator output is inverted prior to.."
|
|
bitfld.long 0x0 8. "ACEN,Analog Comparator Enable" "0: Analog comparator disabled.,1: Analog comparator enabled."
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
tree "ADC (Analog-to-Digital Converter)"
|
|
base ad:0xFC030000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 4. "CMPRST,Comparison Restart" "0,1"
|
|
bitfld.long 0x0 2. "TSCALIB,Touchscreen Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "START,Start Conversion" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
group.long 0x4++0xB
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 31. "USEQ,Use Sequence Enable" "0: Normal mode: The controller converts channels in..,1: User Sequence mode: The sequence respects what.."
|
|
bitfld.long 0x0 30. "MAXSPEED,Maximum Sampling Rate Enable in Freerun Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28.--29. "TRANSFER,Transfer Time" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "TRACKTIM,Tracking Time"
|
|
newline
|
|
bitfld.long 0x0 23. "ANACH,Analog Change" "0: No analog change on channel switching: DIFF0 is..,1: Allows different analog settings for each.."
|
|
hexmask.long.byte 0x0 16.--19. 1. "STARTUP,Startup Time"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "PRESCAL,Prescaler Rate Selection"
|
|
bitfld.long 0x0 6. "FWUP,Fast Wakeup" "0: If SLEEP is 1 then both ADC core and reference..,1: If SLEEP is 1 then Fast Wakeup Sleep mode: The.."
|
|
newline
|
|
bitfld.long 0x0 5. "SLEEP,Sleep Mode" "0: Normal Mode: The ADC core and reference voltage..,1: Sleep Mode: The wakeup time can be modified by.."
|
|
bitfld.long 0x0 1.--3. "TRGSEL,Trigger Selection" "0: ADTRG,1: TIOA0,2: TIOA1,3: TIOA2,4: PWM event line 0,5: PWM event line 1,6: TIOA3,7: RTCOUT0"
|
|
line.long 0x4 "SEQR1,Channel Sequence Register 1"
|
|
hexmask.long.byte 0x4 28.--31. 1. "USCH8,User Sequence Number 8"
|
|
hexmask.long.byte 0x4 24.--27. 1. "USCH7,User Sequence Number 7"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "USCH6,User Sequence Number 6"
|
|
hexmask.long.byte 0x4 16.--19. 1. "USCH5,User Sequence Number 5"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "USCH4,User Sequence Number 4"
|
|
hexmask.long.byte 0x4 8.--11. 1. "USCH3,User Sequence Number 3"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "USCH2,User Sequence Number 2"
|
|
hexmask.long.byte 0x4 0.--3. 1. "USCH1,User Sequence Number 1"
|
|
line.long 0x8 "SEQR2,Channel Sequence Register 2"
|
|
hexmask.long.byte 0x8 8.--11. 1. "USCH11,User Sequence Number 11"
|
|
hexmask.long.byte 0x8 4.--7. 1. "USCH10,User Sequence Number 10"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "USCH9,User Sequence Number 9"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "CHER,Channel Enable Register"
|
|
bitfld.long 0x0 11. "CH11,Channel 11 Enable" "0,1"
|
|
bitfld.long 0x0 10. "CH10,Channel 10 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CH9,Channel 9 Enable" "0,1"
|
|
bitfld.long 0x0 8. "CH8,Channel 8 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CH7,Channel 7 Enable" "0,1"
|
|
bitfld.long 0x0 6. "CH6,Channel 6 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CH5,Channel 5 Enable" "0,1"
|
|
bitfld.long 0x0 4. "CH4,Channel 4 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CH3,Channel 3 Enable" "0,1"
|
|
bitfld.long 0x0 2. "CH2,Channel 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CH1,Channel 1 Enable" "0,1"
|
|
bitfld.long 0x0 0. "CH0,Channel 0 Enable" "0,1"
|
|
line.long 0x4 "CHDR,Channel Disable Register"
|
|
bitfld.long 0x4 11. "CH11,Channel 11 Disable" "0,1"
|
|
bitfld.long 0x4 10. "CH10,Channel 10 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CH9,Channel 9 Disable" "0,1"
|
|
bitfld.long 0x4 8. "CH8,Channel 8 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CH7,Channel 7 Disable" "0,1"
|
|
bitfld.long 0x4 6. "CH6,Channel 6 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CH5,Channel 5 Disable" "0,1"
|
|
bitfld.long 0x4 4. "CH4,Channel 4 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CH3,Channel 3 Disable" "0,1"
|
|
bitfld.long 0x4 2. "CH2,Channel 2 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CH1,Channel 1 Disable" "0,1"
|
|
bitfld.long 0x4 0. "CH0,Channel 0 Disable" "0,1"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "CHSR,Channel Status Register"
|
|
bitfld.long 0x0 11. "CH11,Channel 11 Status" "0,1"
|
|
bitfld.long 0x0 10. "CH10,Channel 10 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CH9,Channel 9 Status" "0,1"
|
|
bitfld.long 0x0 8. "CH8,Channel 8 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CH7,Channel 7 Status" "0,1"
|
|
bitfld.long 0x0 6. "CH6,Channel 6 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CH5,Channel 5 Status" "0,1"
|
|
bitfld.long 0x0 4. "CH4,Channel 4 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CH3,Channel 3 Status" "0,1"
|
|
bitfld.long 0x0 2. "CH2,Channel 2 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CH1,Channel 1 Status" "0,1"
|
|
bitfld.long 0x0 0. "CH0,Channel 0 Status" "0,1"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "LCDR,Last Converted Data Register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "CHNBOSR,Channel Number in Oversampling Mode"
|
|
hexmask.long.word 0x0 0.--15. 1. "LDATA,Last Data Converted"
|
|
wgroup.long 0x24++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 30. "NOPEN,No Pen Contact Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 29. "PEN,Pen Contact Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "COMPE,Comparison Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 25. "GOVRE,General Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "DRDY,Data Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 22. "PRDY,Touchscreen Measure Pressure Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "YRDY,Touchscreen Measure YPOS Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 20. "XRDY,Touchscreen Measure XPOS Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "LCCHG,Last Channel Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 11. "EOC11,End of Conversion Interrupt Enable 11" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EOC10,End of Conversion Interrupt Enable 10" "0,1"
|
|
bitfld.long 0x0 9. "EOC9,End of Conversion Interrupt Enable 9" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "EOC8,End of Conversion Interrupt Enable 8" "0,1"
|
|
bitfld.long 0x0 7. "EOC7,End of Conversion Interrupt Enable 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "EOC6,End of Conversion Interrupt Enable 6" "0,1"
|
|
bitfld.long 0x0 5. "EOC5,End of Conversion Interrupt Enable 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EOC4,End of Conversion Interrupt Enable 4" "0,1"
|
|
bitfld.long 0x0 3. "EOC3,End of Conversion Interrupt Enable 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EOC2,End of Conversion Interrupt Enable 2" "0,1"
|
|
bitfld.long 0x0 1. "EOC1,End of Conversion Interrupt Enable 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EOC0,End of Conversion Interrupt Enable 0" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 30. "NOPEN,No Pen Contact Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 29. "PEN,Pen Contact Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "COMPE,Comparison Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 25. "GOVRE,General Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "DRDY,Data Ready Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 22. "PRDY,Touchscreen Measure Pressure Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "YRDY,Touchscreen Measure YPOS Ready Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 20. "XRDY,Touchscreen Measure XPOS Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "LCCHG,Last Channel Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 11. "EOC11,End of Conversion Interrupt Disable 11" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "EOC10,End of Conversion Interrupt Disable 10" "0,1"
|
|
bitfld.long 0x4 9. "EOC9,End of Conversion Interrupt Disable 9" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "EOC8,End of Conversion Interrupt Disable 8" "0,1"
|
|
bitfld.long 0x4 7. "EOC7,End of Conversion Interrupt Disable 7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "EOC6,End of Conversion Interrupt Disable 6" "0,1"
|
|
bitfld.long 0x4 5. "EOC5,End of Conversion Interrupt Disable 5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EOC4,End of Conversion Interrupt Disable 4" "0,1"
|
|
bitfld.long 0x4 3. "EOC3,End of Conversion Interrupt Disable 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "EOC2,End of Conversion Interrupt Disable 2" "0,1"
|
|
bitfld.long 0x4 1. "EOC1,End of Conversion Interrupt Disable 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "EOC0,End of Conversion Interrupt Disable 0" "0,1"
|
|
rgroup.long 0x2C++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 30. "NOPEN,No Pen Contact Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 29. "PEN,Pen Contact Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "COMPE,Comparison Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 25. "GOVRE,General Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "DRDY,Data Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 22. "PRDY,Touchscreen Measure Pressure Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "YRDY,Touchscreen Measure YPOS Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 20. "XRDY,Touchscreen Measure XPOS Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "LCCHG,Last Channel Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x0 11. "EOC11,End of Conversion Interrupt Mask 11" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EOC10,End of Conversion Interrupt Mask 10" "0,1"
|
|
bitfld.long 0x0 9. "EOC9,End of Conversion Interrupt Mask 9" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "EOC8,End of Conversion Interrupt Mask 8" "0,1"
|
|
bitfld.long 0x0 7. "EOC7,End of Conversion Interrupt Mask 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "EOC6,End of Conversion Interrupt Mask 6" "0,1"
|
|
bitfld.long 0x0 5. "EOC5,End of Conversion Interrupt Mask 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EOC4,End of Conversion Interrupt Mask 4" "0,1"
|
|
bitfld.long 0x0 3. "EOC3,End of Conversion Interrupt Mask 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EOC2,End of Conversion Interrupt Mask 2" "0,1"
|
|
bitfld.long 0x0 1. "EOC1,End of Conversion Interrupt Mask 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EOC0,End of Conversion Interrupt Mask 0" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 31. "PENS,Pen Detect Status" "0,1"
|
|
bitfld.long 0x4 30. "NOPEN,No Pen Contact (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "PEN,Pen contact (cleared on read)" "0,1"
|
|
bitfld.long 0x4 26. "COMPE,Comparison Event (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "GOVRE,General Overrun Error (cleared on read)" "0,1"
|
|
bitfld.long 0x4 24. "DRDY,Data Ready (automatically set / cleared)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "PRDY,Touchscreen Pressure Measure Ready (cleared on read)" "0,1"
|
|
bitfld.long 0x4 21. "YRDY,Touchscreen YPOS Measure Ready (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "XRDY,Touchscreen XPOS Measure Ready (cleared on read)" "0,1"
|
|
bitfld.long 0x4 19. "LCCHG,Last Channel Change (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "EOC11,End of Conversion 11 (automatically set / cleared)" "0,1"
|
|
bitfld.long 0x4 10. "EOC10,End of Conversion 10 (automatically set / cleared)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "EOC9,End of Conversion 9 (automatically set / cleared)" "0,1"
|
|
bitfld.long 0x4 8. "EOC8,End of Conversion 8 (automatically set / cleared)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "EOC7,End of Conversion 7 (automatically set / cleared)" "0,1"
|
|
bitfld.long 0x4 6. "EOC6,End of Conversion 6 (automatically set / cleared)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "EOC5,End of Conversion 5 (automatically set / cleared)" "0,1"
|
|
bitfld.long 0x4 4. "EOC4,End of Conversion 4 (automatically set / cleared)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "EOC3,End of Conversion 3 (automatically set / cleared)" "0,1"
|
|
bitfld.long 0x4 2. "EOC2,End of Conversion 2 (automatically set / cleared)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "EOC1,End of Conversion 1 (automatically set / cleared)" "0,1"
|
|
bitfld.long 0x4 0. "EOC0,End of Conversion 0 (automatically set / cleared)" "0,1"
|
|
group.long 0x34++0x7
|
|
line.long 0x0 "LCTMR,Last Channel Trigger Mode Register"
|
|
bitfld.long 0x0 4.--5. "CMPMOD,Last Channel Comparison Mode" "0: Generates the LCCHG flag in ADC_ISR when the..,1: Generates the LCCHG flag in ADC_ISR when the..,2: Generates the LCCHG flag in ADC_ISR when the..,3: Generates the LCCHG flag in ADC_ISR when the.."
|
|
bitfld.long 0x0 0. "DUALTRIG,Dual Trigger ON" "0,1"
|
|
line.long 0x4 "LCCWR,Last Channel Compare Window Register"
|
|
hexmask.long.word 0x4 16.--27. 1. "HIGHTHRES,High Threshold"
|
|
hexmask.long.word 0x4 0.--11. 1. "LOWTHRES,Low Threshold"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "OVER,Overrun Status Register"
|
|
bitfld.long 0x0 11. "OVRE11,Overrun Error 11" "0,1"
|
|
bitfld.long 0x0 10. "OVRE10,Overrun Error 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "OVRE9,Overrun Error 9" "0,1"
|
|
bitfld.long 0x0 8. "OVRE8,Overrun Error 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "OVRE7,Overrun Error 7" "0,1"
|
|
bitfld.long 0x0 6. "OVRE6,Overrun Error 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE5,Overrun Error 5" "0,1"
|
|
bitfld.long 0x0 4. "OVRE4,Overrun Error 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRE3,Overrun Error 3" "0,1"
|
|
bitfld.long 0x0 2. "OVRE2,Overrun Error 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OVRE1,Overrun Error 1" "0,1"
|
|
bitfld.long 0x0 0. "OVRE0,Overrun Error 0" "0,1"
|
|
group.long 0x40++0x7
|
|
line.long 0x0 "EMR,Extended Mode Register"
|
|
bitfld.long 0x0 28.--29. "ADCMODE,ADC Running Mode" "0: Normal mode of operation.,1: Offset Error mode to measure the offset error.,2: Gain Error mode to measure the gain error. See..,3: Gain Error mode to measure the gain error. See.."
|
|
bitfld.long 0x0 25.--26. "SIGNMODE,Sign Mode" "0: Single-Ended channels: Unsigned..,1: Single-Ended channels: Signed..,2: All channels: Unsigned conversions.,3: All channels: Signed conversions."
|
|
newline
|
|
bitfld.long 0x0 24. "TAG,Tag of ADC_LCDR" "0,1"
|
|
bitfld.long 0x0 21. "SRCCLK,External Clock Selection" "0: The peripheral clock is the source for the ADC..,1: GCLK is the source clock for the ADC prescaler.."
|
|
newline
|
|
bitfld.long 0x0 20. "ASTE,Averaging on Single Trigger Event" "0: The average requests several trigger events.,1: The average requests only one trigger event."
|
|
bitfld.long 0x0 16.--17. "OSR,Over Sampling Rate" "0: No averaging. ADC sample rate is maximum.,1: 1-bit enhanced resolution by averaging. ADC..,2: 2-bit enhanced resolution by averaging. ADC..,?"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "CMPFILTER,Compare Event Filtering" "0,1,2,3"
|
|
bitfld.long 0x0 9. "CMPALL,Compare All Channels" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "CMPSEL,Comparison Selected Channel"
|
|
bitfld.long 0x0 2. "CMPTYPE,Comparison Type" "0: Any conversion is performed and comparison..,1: Comparison conditions must be met to start the.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CMPMODE,Comparison Mode" "0: When the converted data is lower than the low..,1: When the converted data is higher than the high..,2: When the converted data is in the comparison..,3: When the converted data is out of the comparison.."
|
|
line.long 0x4 "CWR,Compare Window Register"
|
|
hexmask.long.word 0x4 16.--29. 1. "HIGHTHRES,High Threshold"
|
|
hexmask.long.word 0x4 0.--13. 1. "LOWTHRES,Low Threshold"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "COR,Channel Offset Register"
|
|
bitfld.long 0x0 27. "DIFF11,Differential Inputs for Channel 11" "0,1"
|
|
bitfld.long 0x0 26. "DIFF10,Differential Inputs for Channel 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "DIFF9,Differential Inputs for Channel 9" "0,1"
|
|
bitfld.long 0x0 24. "DIFF8,Differential Inputs for Channel 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DIFF7,Differential Inputs for Channel 7" "0,1"
|
|
bitfld.long 0x0 22. "DIFF6,Differential Inputs for Channel 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DIFF5,Differential Inputs for Channel 5" "0,1"
|
|
bitfld.long 0x0 20. "DIFF4,Differential Inputs for Channel 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "DIFF3,Differential Inputs for Channel 3" "0,1"
|
|
bitfld.long 0x0 18. "DIFF2,Differential Inputs for Channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "DIFF1,Differential Inputs for Channel 1" "0,1"
|
|
bitfld.long 0x0 16. "DIFF0,Differential Inputs for Channel 0" "0,1"
|
|
repeat 12. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x50)++0x3
|
|
line.long 0x0 "CDR[$1],Channel Data Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "DATA,Converted Data"
|
|
repeat.end
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "ACR,Analog Control Register"
|
|
bitfld.long 0x0 8.--9. "IBCTL,ADC Bias Current Control" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "PENDETSENS,Pen Detection Sensitivity" "0,1,2,3"
|
|
group.long 0xB0++0x3
|
|
line.long 0x0 "TSMR,Touchscreen Mode Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "PENDBC,Pen Detect Debouncing Period"
|
|
bitfld.long 0x0 24. "PENDET,Pen Contact Detection Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "NOTSDMA,No TouchScreen DMA" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "TSSCTIM,Touchscreen Switches Closure Time"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "TSFREQ,Touchscreen Frequency"
|
|
bitfld.long 0x0 4.--5. "TSAV,Touchscreen Average" "0: No Filtering. Only one ADC conversion per measure,1: Averages 2 ADC conversions,2: Averages 4 ADC conversions,3: Averages 8 ADC conversions"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TSMODE,Touchscreen Mode" "0: No Touchscreen,1: 4-wire Touchscreen without pressure measurement,2: 4-wire Touchscreen with pressure measurement,3: 5-wire Touchscreen"
|
|
rgroup.long 0xB4++0xB
|
|
line.long 0x0 "XPOSR,Touchscreen X Position Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "XSCALE,Scale of XPOS"
|
|
hexmask.long.word 0x0 0.--11. 1. "XPOS,X Position"
|
|
line.long 0x4 "YPOSR,Touchscreen Y Position Register"
|
|
hexmask.long.word 0x4 16.--27. 1. "YSCALE,Scale of YPOS"
|
|
hexmask.long.word 0x4 0.--11. 1. "YPOS,Y Position"
|
|
line.long 0x8 "PRESSR,Touchscreen Pressure Register"
|
|
hexmask.long.word 0x8 16.--27. 1. "Z2,Data of Z2 Measurement"
|
|
hexmask.long.word 0x8 0.--11. 1. "Z1,Data of Z1 Measurement"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "TRGR,Trigger Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TRGPER,Trigger Period"
|
|
bitfld.long 0x0 0.--2. "TRGMOD,Trigger Mode" "0: No trigger only software trigger can start..,1: External trigger rising edge,2: External trigger falling edge,3: External trigger any edge,4: Pen Detect Trigger (shall be selected only if..,5: ADC internal periodic trigger (see field TRGPER),6: Continuous mode,?"
|
|
group.long 0xD4++0xB
|
|
line.long 0x0 "CVR,Correction Values Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "GAINCORR,Gain Correction"
|
|
hexmask.long.word 0x0 0.--15. 1. "OFFSETCORR,Offset Correction"
|
|
line.long 0x4 "CECR,Channel Error Correction Register"
|
|
bitfld.long 0x4 11. "ECORR11,Error Correction Enable for channel 11" "0,1"
|
|
bitfld.long 0x4 10. "ECORR10,Error Correction Enable for channel 10" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "ECORR9,Error Correction Enable for channel 9" "0,1"
|
|
bitfld.long 0x4 8. "ECORR8,Error Correction Enable for channel 8" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "ECORR7,Error Correction Enable for channel 7" "0,1"
|
|
bitfld.long 0x4 6. "ECORR6,Error Correction Enable for channel 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "ECORR5,Error Correction Enable for channel 5" "0,1"
|
|
bitfld.long 0x4 4. "ECORR4,Error Correction Enable for channel 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ECORR3,Error Correction Enable for channel 3" "0,1"
|
|
bitfld.long 0x4 2. "ECORR2,Error Correction Enable for channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ECORR1,Error Correction Enable for channel 1" "0,1"
|
|
bitfld.long 0x4 0. "ECORR0,Error Correction Enable for channel 0" "0,1"
|
|
line.long 0x8 "TSCVR,Touchscreen Correction Values Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "TSGAINCORR,Touchscreen Gain Correction"
|
|
hexmask.long.word 0x8 0.--15. 1. "TSOFFSETCORR,Touchscreen Offset Correction"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
tree "AES (Advanced Encryption Standard)"
|
|
base ad:0xF002C000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 8. "SWRST,Software Reset" "0,1"
|
|
bitfld.long 0x0 0. "START,Start Processing" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.byte 0x0 20.--23. 1. "CKEY,Key"
|
|
bitfld.long 0x0 16.--18. "CFBS,Cipher Feedback Data Size" "0: 128-bit,1: 64-bit,2: 32-bit,3: 16-bit,4: 8-bit,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 15. "LOD,Last Output Data Mode" "0,1"
|
|
bitfld.long 0x0 12.--14. "OPMOD,Operating Mode" "0: ECB: Electronic Codebook mode,1: CBC: Cipher Block Chaining mode,2: OFB: Output Feedback mode,3: CFB: Cipher Feedback mode,4: CTR: Counter mode (16-bit internal counter),5: GCM: Galois/Counter mode,6: XTS: XEX-based tweaked-codebook mode,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "KEYSIZE,Key Size" "0: AES Key Size is 128 bits,1: AES Key Size is 192 bits,2: AES Key Size is 256 bits,?"
|
|
bitfld.long 0x0 8.--9. "SMOD,Start Mode" "0: Manual Mode,1: Auto Mode,2: AES_IDATAR0 access only Auto Mode (DMA),?"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "PROCDLY,Processing Delay"
|
|
bitfld.long 0x0 3. "DUALBUFF,Dual Input Buffer" "0: AES_IDATARx cannot be written during processing..,1: AES_IDATARx can be written during processing of.."
|
|
newline
|
|
bitfld.long 0x0 1. "GTAGEN,GCM Automatic Tag Generation Enable" "0,1"
|
|
bitfld.long 0x0 0. "CIPHER,Processing Mode" "0,1"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 18. "PLENERR,Padding Length Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 17. "EOPAD,End of Padding Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "TAGRDY,GCM Tag Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "URAD,Unspecified Register Access Detection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 18. "PLENERR,Padding Length Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 17. "EOPAD,End of Padding Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "TAGRDY,GCM Tag Ready Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "URAD,Unspecified Register Access Detection Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 18. "PLENERR,Padding Length Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 17. "EOPAD,End of Padding Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "TAGRDY,GCM Tag Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "URAD,Unspecified Register Access Detection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 18. "PLENERR,Padding Length Error" "0,1"
|
|
bitfld.long 0x4 17. "EOPAD,End of Padding" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "TAGRDY,GCM Tag Ready" "0,1"
|
|
hexmask.long.byte 0x4 12.--15. 1. "URAT,Unspecified Register Access (cleared by writing SWRST in AES_CR)"
|
|
newline
|
|
bitfld.long 0x4 8. "URAD,Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR)" "0,1"
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx)" "0,1"
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "KEYWR[$1],Key Word Register"
|
|
hexmask.long 0x0 0.--31. 1. "KEYW,Key Word"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x40)++0x3
|
|
line.long 0x0 "IDATAR[$1],Input Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "IDATA,Input Data Word"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x50)++0x3
|
|
line.long 0x0 "ODATAR[$1],Output Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "ODATA,Output Data"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x60)++0x3
|
|
line.long 0x0 "IVR[$1],Initialization Vector Register"
|
|
hexmask.long 0x0 0.--31. 1. "IV,Initialization Vector"
|
|
repeat.end
|
|
group.long 0x70++0x7
|
|
line.long 0x0 "AADLENR,Additional Authenticated Data Length Register"
|
|
hexmask.long 0x0 0.--31. 1. "AADLEN,Additional Authenticated Data Length"
|
|
line.long 0x4 "CLENR,Plaintext/Ciphertext Length Register"
|
|
hexmask.long 0x4 0.--31. 1. "CLEN,Plaintext/Ciphertext Length"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x78)++0x3
|
|
line.long 0x0 "GHASHR[$1],GCM Intermediate Hash Word Register"
|
|
hexmask.long 0x0 0.--31. 1. "GHASH,Intermediate GCM Hash Word x"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x88)++0x3
|
|
line.long 0x0 "TAGR[$1],GCM Authentication Tag Word Register"
|
|
hexmask.long 0x0 0.--31. 1. "TAG,GCM Authentication Tag x"
|
|
repeat.end
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "CTRR,GCM Encryption Counter Value Register"
|
|
hexmask.long 0x0 0.--31. 1. "CTR,GCM Encryption Counter"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x9C)++0x3
|
|
line.long 0x0 "GCMHR[$1],GCM H Word Register"
|
|
hexmask.long 0x0 0.--31. 1. "H,GCM H Word x"
|
|
repeat.end
|
|
group.long 0xB0++0x7
|
|
line.long 0x0 "EMR,Extended Mode Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "NHEAD,IPSEC Next Header"
|
|
hexmask.long.byte 0x0 8.--15. 1. "PADLEN,Auto Padding Length"
|
|
newline
|
|
bitfld.long 0x0 5. "PLIPD,Protocol Layer Improved Performance Decipher" "0,1"
|
|
bitfld.long 0x0 4. "PLIPEN,Protocol Layer Improved Performance Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "APM,Auto Padding Mode" "0,1"
|
|
bitfld.long 0x0 0. "APEN,Auto Padding Enable" "0,1"
|
|
line.long 0x4 "BCNT,Byte Counter Register"
|
|
hexmask.long 0x4 0.--31. 1. "BCNT,Auto Padding Byte Counter"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xC0)++0x3
|
|
line.long 0x0 "TWR[$1],Tweak Word Register"
|
|
hexmask.long 0x0 0.--31. 1. "TWEAK,Tweak Word x"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0xD0)++0x3
|
|
line.long 0x0 "ALPHAR[$1],Alpha Word Register"
|
|
hexmask.long 0x0 0.--31. 1. "ALPHA,Alpha Word x"
|
|
repeat.end
|
|
tree.end
|
|
tree "AESB (Advanced Encryption Standard Bridge)"
|
|
base ad:0xF001C000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 8. "SWRST,Software Reset" "0,1"
|
|
bitfld.long 0x0 0. "START,Start Processing" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.byte 0x0 20.--23. 1. "CKEY,Key"
|
|
bitfld.long 0x0 15. "LOD,Last Output Data Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "OPMOD,Operating Mode" "0: Electronic Code Book mode,1: Cipher Block Chaining mode,?,?,4: Counter mode (16-bit internal counter),?,?,?"
|
|
bitfld.long 0x0 8.--9. "SMOD,Start Mode" "0: Manual mode,1: Auto mode,2: AESB_IDATAR0 access only Auto mode,?"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "PROCDLY,Processing Delay"
|
|
bitfld.long 0x0 3. "DUALBUFF,Dual Input Buffer" "0: AESB_IDATARx cannot be written during processing..,1: AESB_IDATARx can be written during processing of.."
|
|
newline
|
|
bitfld.long 0x0 2. "AAHB,Automatic Bridge Mode" "0,1"
|
|
bitfld.long 0x0 0. "CIPHER,Processing Mode" "0,1"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 8. "URAD,Unspecified Register Access Detection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 8. "URAD,Unspecified Register Access Detection Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 8. "URAD,Unspecified Register Access Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
hexmask.long.byte 0x4 12.--15. 1. "URAT,Unspecified Register Access"
|
|
bitfld.long 0x4 8. "URAD,Unspecified Register Access Detection Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "KEYWR[$1],Key Word Register"
|
|
hexmask.long 0x0 0.--31. 1. "KEYW,Key Word"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x40)++0x3
|
|
line.long 0x0 "IDATAR[$1],Input Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "IDATA,Input Data Word"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x50)++0x3
|
|
line.long 0x0 "ODATAR[$1],Output Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "ODATA,Output Data"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x60)++0x3
|
|
line.long 0x0 "IVR[$1],Initialization Vector Register"
|
|
hexmask.long 0x0 0.--31. 1. "IV,Initialization Vector"
|
|
repeat.end
|
|
tree.end
|
|
tree "AIC (Advanced Interrupt Controller)"
|
|
base ad:0x0
|
|
tree "AIC"
|
|
base ad:0xFC020000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "SSR,Source Select Register"
|
|
hexmask.long.byte 0x0 0.--6. 1. "INTSEL,Interrupt Line Selection"
|
|
line.long 0x4 "SMR,Source Mode Register"
|
|
bitfld.long 0x4 5.--6. "SRCTYPE,Interrupt Source Type" "0: High-level sensitive for internal source.,1: Negative-edge triggered for external source,2: High-level sensitive for internal source.,3: Positive-edge triggered for external source"
|
|
bitfld.long 0x4 0.--2. "PRIORITY,Priority Level" "0: Minimum priority,1: Very low priority,2: Low priority,3: Medium priority,4: Medium-high priority,5: High priority,6: Very high priority,7: Maximum priority"
|
|
line.long 0x8 "SVR,Source Vector Register"
|
|
hexmask.long 0x8 0.--31. 1. "VECTOR,Source Vector"
|
|
rgroup.long 0x10++0xB
|
|
line.long 0x0 "IVR,Interrupt Vector Register"
|
|
hexmask.long 0x0 0.--31. 1. "IRQV,Interrupt Vector Register"
|
|
line.long 0x4 "FVR,FIQ Vector Register"
|
|
hexmask.long 0x4 0.--31. 1. "FIQV,FIQ Vector Register"
|
|
line.long 0x8 "ISR,Interrupt Status Register"
|
|
hexmask.long.byte 0x8 0.--6. 1. "IRQID,Current Interrupt Identifier"
|
|
rgroup.long 0x20++0x17
|
|
line.long 0x0 "IPR0,Interrupt Pending Register 0"
|
|
bitfld.long 0x0 31. "PID31,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 30. "PID30,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 29. "PID29,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 28. "PID28,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 27. "PID27,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 26. "PID26,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "PID25,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 24. "PID24,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 23. "PID23,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 22. "PID22,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 21. "PID21,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 20. "PID20,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PID19,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 18. "PID18,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 17. "PID17,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 16. "PID16,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 15. "PID15,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 14. "PID14,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PID13,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 12. "PID12,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 11. "PID11,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 10. "PID10,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 9. "PID9,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 8. "PID8,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PID7,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 6. "PID6,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 5. "PID5,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 4. "PID4,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 3. "PID3,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 2. "PID2,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PID1,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 0. "FIQ,Interrupt Pending" "0,1"
|
|
line.long 0x4 "IPR1,Interrupt Pending Register 1"
|
|
bitfld.long 0x4 31. "PID63,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 30. "PID62,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 29. "PID61,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 28. "PID60,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 27. "PID59,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 26. "PID58,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "PID57,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 24. "PID56,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 23. "PID55,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 22. "PID54,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 21. "PID53,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 20. "PID52,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PID51,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 18. "PID50,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 17. "PID49,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 16. "PID48,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 15. "PID47,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 14. "PID46,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "PID45,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 12. "PID44,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 11. "PID43,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 10. "PID42,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 9. "PID41,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 8. "PID40,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PID39,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 6. "PID38,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 5. "PID37,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 4. "PID36,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 3. "PID35,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 2. "PID34,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "PID33,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 0. "PID32,Interrupt Pending" "0,1"
|
|
line.long 0x8 "IPR2,Interrupt Pending Register 2"
|
|
bitfld.long 0x8 31. "PID95,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 30. "PID94,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 29. "PID93,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 28. "PID92,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 27. "PID91,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 26. "PID90,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "PID89,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 24. "PID88,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 23. "PID87,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 22. "PID86,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 21. "PID85,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 20. "PID84,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "PID83,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 18. "PID82,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 17. "PID81,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 16. "PID80,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 15. "PID79,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 14. "PID78,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "PID77,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 12. "PID76,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 11. "PID75,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 10. "SYS,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 9. "PID73,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 8. "PID72,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "PID71,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 6. "PID70,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 5. "PID69,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 4. "PID68,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 3. "PID67,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 2. "PID66,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "PID65,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 0. "PID64,Interrupt Pending" "0,1"
|
|
line.long 0xC "IPR3,Interrupt Pending Register 3"
|
|
bitfld.long 0xC 31. "PID127,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 30. "PID126,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 29. "PID125,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 28. "PID124,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 27. "PID123,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 26. "PID122,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "PID121,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 24. "PID120,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 23. "PID119,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 22. "PID118,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 21. "PID117,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 20. "PID116,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "PID115,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 18. "PID114,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 17. "PID113,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 16. "PID112,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 15. "PID111,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 14. "PID110,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "PID109,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 12. "PID108,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 11. "PID107,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 10. "PID106,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 9. "PID105,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 8. "PID104,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "PID103,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 6. "PID102,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 5. "PID101,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 4. "PID100,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 3. "PID99,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 2. "PID98,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "PID97,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 0. "PID96,Interrupt Pending" "0,1"
|
|
line.long 0x10 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x10 0. "INTM,Interrupt Mask" "0,1"
|
|
line.long 0x14 "CISR,Core Interrupt Status Register"
|
|
bitfld.long 0x14 1. "NIRQ,NIRQ Status" "0,1"
|
|
bitfld.long 0x14 0. "NFIQ,NFIQ Status" "0,1"
|
|
wgroup.long 0x38++0x3
|
|
line.long 0x0 "EOICR,End of Interrupt Command Register"
|
|
bitfld.long 0x0 0. "ENDIT,Interrupt Processing Complete Command" "0,1"
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "SPU,Spurious Interrupt Vector Register"
|
|
hexmask.long 0x0 0.--31. 1. "SIVR,Spurious Interrupt Vector Register"
|
|
wgroup.long 0x40++0xF
|
|
line.long 0x0 "IECR,Interrupt Enable Command Register"
|
|
bitfld.long 0x0 0. "INTEN,Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDCR,Interrupt Disable Command Register"
|
|
bitfld.long 0x4 0. "INTD,Interrupt Disable" "0,1"
|
|
line.long 0x8 "ICCR,Interrupt Clear Command Register"
|
|
bitfld.long 0x8 0. "INTCLR,Interrupt Clear" "0,1"
|
|
line.long 0xC "ISCR,Interrupt Set Command Register"
|
|
bitfld.long 0xC 0. "INTSET,Interrupt Set" "0,1"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "DCR,Debug Control Register"
|
|
bitfld.long 0x0 1. "GMSK,General Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "PROT,Protection Mode" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
tree "SAIC"
|
|
base ad:0xF803C000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "SSR,Source Select Register"
|
|
hexmask.long.byte 0x0 0.--6. 1. "INTSEL,Interrupt Line Selection"
|
|
line.long 0x4 "SMR,Source Mode Register"
|
|
bitfld.long 0x4 5.--6. "SRCTYPE,Interrupt Source Type" "0: High-level sensitive for internal source.,1: Negative-edge triggered for external source,2: High-level sensitive for internal source.,3: Positive-edge triggered for external source"
|
|
bitfld.long 0x4 0.--2. "PRIORITY,Priority Level" "0: Minimum priority,1: Very low priority,2: Low priority,3: Medium priority,4: Medium-high priority,5: High priority,6: Very high priority,7: Maximum priority"
|
|
line.long 0x8 "SVR,Source Vector Register"
|
|
hexmask.long 0x8 0.--31. 1. "VECTOR,Source Vector"
|
|
rgroup.long 0x10++0xB
|
|
line.long 0x0 "IVR,Interrupt Vector Register"
|
|
hexmask.long 0x0 0.--31. 1. "IRQV,Interrupt Vector Register"
|
|
line.long 0x4 "FVR,FIQ Vector Register"
|
|
hexmask.long 0x4 0.--31. 1. "FIQV,FIQ Vector Register"
|
|
line.long 0x8 "ISR,Interrupt Status Register"
|
|
hexmask.long.byte 0x8 0.--6. 1. "IRQID,Current Interrupt Identifier"
|
|
rgroup.long 0x20++0x17
|
|
line.long 0x0 "IPR0,Interrupt Pending Register 0"
|
|
bitfld.long 0x0 31. "PID31,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 30. "PID30,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 29. "PID29,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 28. "PID28,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 27. "PID27,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 26. "PID26,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "PID25,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 24. "PID24,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 23. "PID23,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 22. "PID22,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 21. "PID21,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 20. "PID20,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PID19,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 18. "PID18,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 17. "PID17,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 16. "PID16,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 15. "PID15,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 14. "PID14,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PID13,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 12. "PID12,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 11. "PID11,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 10. "PID10,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 9. "PID9,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 8. "PID8,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PID7,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 6. "PID6,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 5. "PID5,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 4. "PID4,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 3. "PID3,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 2. "PID2,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PID1,Interrupt Pending" "0,1"
|
|
bitfld.long 0x0 0. "FIQ,Interrupt Pending" "0,1"
|
|
line.long 0x4 "IPR1,Interrupt Pending Register 1"
|
|
bitfld.long 0x4 31. "PID63,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 30. "PID62,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 29. "PID61,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 28. "PID60,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 27. "PID59,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 26. "PID58,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "PID57,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 24. "PID56,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 23. "PID55,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 22. "PID54,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 21. "PID53,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 20. "PID52,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PID51,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 18. "PID50,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 17. "PID49,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 16. "PID48,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 15. "PID47,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 14. "PID46,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "PID45,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 12. "PID44,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 11. "PID43,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 10. "PID42,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 9. "PID41,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 8. "PID40,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PID39,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 6. "PID38,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 5. "PID37,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 4. "PID36,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 3. "PID35,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 2. "PID34,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "PID33,Interrupt Pending" "0,1"
|
|
bitfld.long 0x4 0. "PID32,Interrupt Pending" "0,1"
|
|
line.long 0x8 "IPR2,Interrupt Pending Register 2"
|
|
bitfld.long 0x8 31. "PID95,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 30. "PID94,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 29. "PID93,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 28. "PID92,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 27. "PID91,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 26. "PID90,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "PID89,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 24. "PID88,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 23. "PID87,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 22. "PID86,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 21. "PID85,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 20. "PID84,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "PID83,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 18. "PID82,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 17. "PID81,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 16. "PID80,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 15. "PID79,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 14. "PID78,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "PID77,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 12. "PID76,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 11. "PID75,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 10. "SYS,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 9. "PID73,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 8. "PID72,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "PID71,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 6. "PID70,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 5. "PID69,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 4. "PID68,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 3. "PID67,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 2. "PID66,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "PID65,Interrupt Pending" "0,1"
|
|
bitfld.long 0x8 0. "PID64,Interrupt Pending" "0,1"
|
|
line.long 0xC "IPR3,Interrupt Pending Register 3"
|
|
bitfld.long 0xC 31. "PID127,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 30. "PID126,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 29. "PID125,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 28. "PID124,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 27. "PID123,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 26. "PID122,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "PID121,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 24. "PID120,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 23. "PID119,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 22. "PID118,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 21. "PID117,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 20. "PID116,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "PID115,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 18. "PID114,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 17. "PID113,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 16. "PID112,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 15. "PID111,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 14. "PID110,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "PID109,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 12. "PID108,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 11. "PID107,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 10. "PID106,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 9. "PID105,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 8. "PID104,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "PID103,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 6. "PID102,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 5. "PID101,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 4. "PID100,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 3. "PID99,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 2. "PID98,Interrupt Pending" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "PID97,Interrupt Pending" "0,1"
|
|
bitfld.long 0xC 0. "PID96,Interrupt Pending" "0,1"
|
|
line.long 0x10 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x10 0. "INTM,Interrupt Mask" "0,1"
|
|
line.long 0x14 "CISR,Core Interrupt Status Register"
|
|
bitfld.long 0x14 1. "NIRQ,NIRQ Status" "0,1"
|
|
bitfld.long 0x14 0. "NFIQ,NFIQ Status" "0,1"
|
|
wgroup.long 0x38++0x3
|
|
line.long 0x0 "EOICR,End of Interrupt Command Register"
|
|
bitfld.long 0x0 0. "ENDIT,Interrupt Processing Complete Command" "0,1"
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "SPU,Spurious Interrupt Vector Register"
|
|
hexmask.long 0x0 0.--31. 1. "SIVR,Spurious Interrupt Vector Register"
|
|
wgroup.long 0x40++0xF
|
|
line.long 0x0 "IECR,Interrupt Enable Command Register"
|
|
bitfld.long 0x0 0. "INTEN,Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDCR,Interrupt Disable Command Register"
|
|
bitfld.long 0x4 0. "INTD,Interrupt Disable" "0,1"
|
|
line.long 0x8 "ICCR,Interrupt Clear Command Register"
|
|
bitfld.long 0x8 0. "INTCLR,Interrupt Clear" "0,1"
|
|
line.long 0xC "ISCR,Interrupt Set Command Register"
|
|
bitfld.long 0xC 0. "INTSET,Interrupt Set" "0,1"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "DCR,Debug Control Register"
|
|
bitfld.long 0x0 1. "GMSK,General Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "PROT,Protection Mode" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "AXIMX (AXI Matrix)"
|
|
base ad:0x600000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "REMAP,AXI Matrix Remap Register"
|
|
bitfld.long 0x0 0. "REMAP0,Remap State 0" "0,1"
|
|
tree.end
|
|
tree "CHIPID (Chip Identifier)"
|
|
base ad:0xFC069000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "CIDR,Chip ID Register"
|
|
bitfld.long 0x0 31. "EXT,Extension Flag" "0,1"
|
|
bitfld.long 0x0 28.--30. "NVPTYP,Nonvolatile Program Memory Type" "0: ROM,1: ROMless or on-chip Flash,2: Embedded Flash Memory,3: ROM and Embedded Flash Memory- NVPSIZ is ROM..,4: SRAM emulating ROM,?,?,?"
|
|
hexmask.long.byte 0x0 20.--27. 1. "ARCH,Architecture Identifier"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SRAMSIZ,Internal SRAM Size"
|
|
hexmask.long.byte 0x0 12.--15. 1. "NVPSIZ2,Second Nonvolatile Program Memory Size"
|
|
hexmask.long.byte 0x0 8.--11. 1. "NVPSIZ,Nonvolatile Program Memory Size"
|
|
newline
|
|
bitfld.long 0x0 5.--7. "EPROC,Embedded Processor" "0: Cortex-M7,1: ARM946ES,2: ARM7TDMI,3: Cortex-M3,4: ARM920T,5: ARM926EJS,6: Cortex-A5,7: Cortex-M4"
|
|
hexmask.long.byte 0x0 0.--4. 1. "VERSION,Version of the Device"
|
|
line.long 0x4 "EXID,Chip ID Extension Register"
|
|
hexmask.long 0x4 0.--31. 1. "EXID,Chip ID Extension"
|
|
tree.end
|
|
tree "CLASSD (Audio Class D Amplifier)"
|
|
base ad:0xFC048000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 20.--21. "NOVRVAL,Non-Overlapping Value" "0: Non-overlapping time is 5 ns,1: Non-overlapping time is 10 ns,2: Non-overlapping time is 15 ns,3: Non-overlapping time is 20 ns"
|
|
bitfld.long 0x0 16. "NON_OVERLAP,Non-Overlapping Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "PWMTYP,PWM Modulation Type" "0,1"
|
|
bitfld.long 0x0 5. "RMUTE,Right Channel Mute" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "REN,Right Channel Enable" "0,1"
|
|
bitfld.long 0x0 1. "LMUTE,Left Channel Mute" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "LEN,Left Channel Enable" "0,1"
|
|
line.long 0x4 "INTPMR,Interpolator Mode Register"
|
|
bitfld.long 0x4 29.--30. "MONOMODE,Mono Mode Selection" "0: (left + right) / 2 is sent on both channels,1: (left + right) is sent to both channels. If the..,2: THR[15:0] is sent on both left and right channels,3: THR[31:16] is sent on both left and right channels"
|
|
bitfld.long 0x4 28. "MONO,Mono Signal" "0: The signal is sent stereo to the left and right..,1: The same signal is sent on both left and right.."
|
|
newline
|
|
hexmask.long.byte 0x4 24.--27. 1. "EQCFG,Equalization Selection"
|
|
bitfld.long 0x4 20.--22. "FRAME,CLASSD Incoming Data Sampling Frequency" "0: 8 kHz,1: 16 kHz,2: 32 kHz,3: 48 kHz,4: 96 kHz,5: 22.05 kHz,6: 44.1 kHz,7: 88.2 kHz"
|
|
newline
|
|
bitfld.long 0x4 19. "SWAP,Swap Left and Right Channels" "0: Left channel is on CLASSD_THR[15:0] right..,1: Right channel is on CLASSD_THR[15:0] left.."
|
|
bitfld.long 0x4 18. "DEEMP,Enable De-emphasis Filter" "0: De-emphasis filter is disabled.,1: De-emphasis filter is enabled."
|
|
newline
|
|
bitfld.long 0x4 16. "DSPCLKFREQ,DSP Clock Frequency" "0: DSP Clock (DSPCLK) is 12.288 MHz.,1: DSP Clock (DSPCLK) is 11.2896 MHz."
|
|
hexmask.long.byte 0x4 8.--14. 1. "ATTR,Right Channel Attenuation"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "ATTL,Left Channel Attenuation"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "INTSR,Interpolator Status Register"
|
|
bitfld.long 0x0 0. "CFGERR,Configuration Error" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "THR,Transmit Holding Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RDATA,Right Channel Data"
|
|
hexmask.long.word 0x0 0.--15. 1. "LDATA,Left Channel Data"
|
|
wgroup.long 0x14++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready" "0,1"
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready" "0,1"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
tree.end
|
|
tree "FLEXCOM (Flexible Serial Communication Controller)"
|
|
base ad:0x0
|
|
tree "FLEXCOM0"
|
|
base ad:0xF8034000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected.USART/TWI related..,3: All TWI related protocols are selected (TWI.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
|
|
wgroup.long 0x200++0x3
|
|
line.long 0x0 "FLEX_US_CR,USART Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SENDA,Send Address" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "STPBRK,Stop Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "STTBRK,Start Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
wgroup.long 0x200++0x3
|
|
line.long 0x0 "FLEX_US_CR_SPI_MODE_MODE,USART Control Register"
|
|
bitfld.long 0x0 19. "RCS,Release SPI Chip Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "FCS,Force SPI Chip Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
|
bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 23. "INVDATA,Inverted Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
|
|
newline
|
|
bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
|
|
newline
|
|
bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR_SPI_MODE_MODE,USART Mode Register"
|
|
bitfld.long 0x0 20. "WRDBT,Wait Read Data Before Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CPOL,SPI Clock Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "CPHA,SPI Clock Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CHRL,Character Length" "?,?,?,3: Character length is 8 bits"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock Divided (DIV= 8) is selected,2: A PMC generic clock is selected,3: External pin SCK is selected"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "FLEX_US_IER_SPI_MODE_MODE,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "NSSE,NSS Line (Driving CTS Pin) Rising or Falling Edge Event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,SPI Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
wgroup.long 0x208++0x7
|
|
line.long 0x0 "FLEX_US_IER_LIN_MODE_MODE,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
wgroup.long 0x20C++0x3
|
|
line.long 0x0 "FLEX_US_IDR_SPI_MODE_MODE,USART Interrupt Disable Register"
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "NSSE,NSS Line (Driving CTS Pin) Rising or Falling Edge Event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,SPI Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
wgroup.long 0x20C++0x3
|
|
line.long 0x0 "FLEX_US_IDR_LIN_MODE_MODE,USART Interrupt Disable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
rgroup.long 0x210++0x3
|
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line.long 0x0 "FLEX_US_IMR_SPI_MODE_MODE,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 19. "NSSE,NSS Line (Driving CTS Pin) Rising or Falling Edge Event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,SPI Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
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rgroup.long 0x210++0x7
|
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line.long 0x0 "FLEX_US_IMR_LIN_MODE_MODE,USART Interrupt Mask Register"
|
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
|
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newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error" "0,1"
|
|
newline
|
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bitfld.long 0x4 23. "CTS,Image of CTS Input" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x3
|
|
line.long 0x0 "FLEX_US_CSR_SPI_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 23. "NSS,NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Match" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "NSSE,NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x7
|
|
line.long 0x0 "FLEX_US_CSR_LIN_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
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line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
|
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bitfld.long 0x4 15. "RXSYNH,Received Sync" "0,1"
|
|
newline
|
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hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
|
|
rgroup.long 0x218++0x3
|
|
line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Character"
|
|
newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Character"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Character"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Character"
|
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wgroup.long 0x21C++0x3
|
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line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
|
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bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0,1"
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
|
|
newline
|
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hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
|
|
group.long 0x220++0xB
|
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line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
|
|
bitfld.long 0x0 16.--18. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
|
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line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
|
|
hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
|
|
line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
|
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hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
|
|
group.long 0x240++0x3
|
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line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
|
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hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
|
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rgroup.long 0x244++0x3
|
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line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
|
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hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
|
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group.long 0x24C++0xF
|
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line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
|
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hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
|
|
line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
|
|
newline
|
|
bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
|
|
newline
|
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hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
|
|
line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "PDCM,DMAC Mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
|
|
newline
|
|
bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "DLM,Data Length Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "PARDIS,Parity Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
|
|
line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
|
|
rgroup.long 0x25C++0x3
|
|
line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
|
|
bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
|
|
group.long 0x290++0x3
|
|
line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
|
|
hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
|
bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x2A0++0x3
|
|
line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x2A4++0x3
|
|
line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
wgroup.long 0x2A8++0x7
|
|
line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x2B0++0x7
|
|
line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
group.long 0x2E4++0x3
|
|
line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x2E8++0x3
|
|
line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x400++0x3
|
|
line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
|
|
group.long 0x404++0x3
|
|
line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "PCS,Peripheral Chip Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
newline
|
|
bitfld.long 0x0 8. "LBHPC,Last Bit Half Period Compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0,1"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RD8_3,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD8_2,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RD8_1,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RD8_0,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RD16_1,Receive Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD16_0,Receive Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
|
|
rgroup.long 0x410++0x3
|
|
line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0,1"
|
|
wgroup.long 0x414++0x7
|
|
line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
repeat.end
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
|
|
rgroup.long 0x444++0x3
|
|
line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
group.long 0x448++0x3
|
|
line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x4E4++0x3
|
|
line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x4E8++0x3
|
|
line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
group.long 0x604++0xF
|
|
line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
|
newline
|
|
bitfld.long 0x0 12. "MREAD,Master Read Direction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
|
line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
|
|
bitfld.long 0x4 31. "DATAMEN,Data Matching Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "SADR3EN,Slave Address 3 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "SADR2EN,Slave Address 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "SADR1EN,Slave Address 1 Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
|
|
newline
|
|
bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0,1"
|
|
line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--28. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
|
newline
|
|
bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
wgroup.long 0x624++0x7
|
|
line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
|
|
bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
|
|
rgroup.long 0x62C++0x7
|
|
line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
|
|
rgroup.long 0x630++0x3
|
|
line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
|
|
group.long 0x638++0x3
|
|
line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
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|
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|
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hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
|
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
|
|
group.long 0x640++0x7
|
|
line.long 0x0 "FLEX_TWI_ACR,TWI Alternative Command Register"
|
|
bitfld.long 0x0 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
|
|
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|
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bitfld.long 0x0 24. "NDIR,Next Transfer Direction" "0,1"
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|
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hexmask.long.byte 0x0 16.--23. 1. "NDATAL,Next Data Length"
|
|
newline
|
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bitfld.long 0x0 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
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|
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bitfld.long 0x0 8. "DIR,Transfer Direction" "0,1"
|
|
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|
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hexmask.long.byte 0x0 0.--7. 1. "DATAL,Data Length"
|
|
line.long 0x4 "FLEX_TWI_FILTR,TWI Filter Register"
|
|
bitfld.long 0x4 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
|
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newline
|
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bitfld.long 0x4 2. "PADFCFG,PAD Filter Config" "0,1"
|
|
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|
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bitfld.long 0x4 1. "PADFEN,PAD Filter Enable" "0,1"
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|
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|
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bitfld.long 0x4 0. "FILT,RX Digital Filter" "0,1"
|
|
group.long 0x64C++0x7
|
|
line.long 0x0 "FLEX_TWI_SWMR,TWI SleepWalking Matching Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DATAM,Data Match"
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|
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hexmask.long.byte 0x0 16.--22. 1. "SADR3,Slave Address 3"
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|
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hexmask.long.byte 0x0 8.--14. 1. "SADR2,Slave Address 2"
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|
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hexmask.long.byte 0x0 0.--6. 1. "SADR1,Slave Address 1"
|
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line.long 0x4 "FLEX_TWI_FMR,TWI FIFO Mode Register"
|
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hexmask.long.byte 0x4 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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|
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hexmask.long.byte 0x4 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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|
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bitfld.long 0x4 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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newline
|
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bitfld.long 0x4 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x654++0x3
|
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line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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newline
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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rgroup.long 0x660++0x3
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line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
|
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bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
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|
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bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
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|
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bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
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|
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bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
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|
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bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
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|
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bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
wgroup.long 0x664++0x7
|
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line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
|
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
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|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
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|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
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|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
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|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
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line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
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|
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
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|
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
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|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
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|
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
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|
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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|
newline
|
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
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rgroup.long 0x66C++0x3
|
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line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
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|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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|
newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
rgroup.long 0x6D0++0x3
|
|
line.long 0x0 "FLEX_TWI_DR,TWI Debug Register"
|
|
bitfld.long 0x0 3. "TRP,Transfer Pending" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "SWMATCH,SleepWalking Match" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "CLKRQ,Clock Request" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "SWEN,SleepWalking Enable" "0,1"
|
|
group.long 0x6E4++0x3
|
|
line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x6E8++0x3
|
|
line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
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bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0,1"
|
|
tree.end
|
|
tree "FLEXCOM1"
|
|
base ad:0xF8038000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected.USART/TWI related..,3: All TWI related protocols are selected (TWI.."
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|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
|
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group.long 0x20++0x3
|
|
line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
|
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wgroup.long 0x200++0x3
|
|
line.long 0x0 "FLEX_US_CR,USART Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SENDA,Send Address" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "STPBRK,Stop Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "STTBRK,Start Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
wgroup.long 0x200++0x3
|
|
line.long 0x0 "FLEX_US_CR_SPI_MODE_MODE,USART Control Register"
|
|
bitfld.long 0x0 19. "RCS,Release SPI Chip Select" "0,1"
|
|
newline
|
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bitfld.long 0x0 18. "FCS,Force SPI Chip Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
|
bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 23. "INVDATA,Inverted Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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|
newline
|
|
bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
|
|
newline
|
|
bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR_SPI_MODE_MODE,USART Mode Register"
|
|
bitfld.long 0x0 20. "WRDBT,Wait Read Data Before Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CPOL,SPI Clock Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "CPHA,SPI Clock Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CHRL,Character Length" "?,?,?,3: Character length is 8 bits"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock Divided (DIV= 8) is selected,2: A PMC generic clock is selected,3: External pin SCK is selected"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "FLEX_US_IER_SPI_MODE_MODE,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "NSSE,NSS Line (Driving CTS Pin) Rising or Falling Edge Event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,SPI Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
wgroup.long 0x208++0x7
|
|
line.long 0x0 "FLEX_US_IER_LIN_MODE_MODE,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
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newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
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newline
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bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
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wgroup.long 0x20C++0x3
|
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line.long 0x0 "FLEX_US_IDR_SPI_MODE_MODE,USART Interrupt Disable Register"
|
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Disable" "0,1"
|
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newline
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bitfld.long 0x0 19. "NSSE,NSS Line (Driving CTS Pin) Rising or Falling Edge Event" "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "UNRE,SPI Underrun Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
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wgroup.long 0x20C++0x3
|
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line.long 0x0 "FLEX_US_IDR_LIN_MODE_MODE,USART Interrupt Disable Register"
|
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
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rgroup.long 0x210++0x3
|
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line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
|
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
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rgroup.long 0x210++0x3
|
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line.long 0x0 "FLEX_US_IMR_SPI_MODE_MODE,USART Interrupt Mask Register"
|
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 19. "NSSE,NSS Line (Driving CTS Pin) Rising or Falling Edge Event" "0,1"
|
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newline
|
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bitfld.long 0x0 10. "UNRE,SPI Underrun Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
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rgroup.long 0x210++0x7
|
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line.long 0x0 "FLEX_US_IMR_LIN_MODE_MODE,USART Interrupt Mask Register"
|
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
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line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
|
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bitfld.long 0x4 24. "MANE,Manchester Error" "0,1"
|
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newline
|
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bitfld.long 0x4 23. "CTS,Image of CTS Input" "0,1"
|
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newline
|
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bitfld.long 0x4 22. "CMP,Comparison Status" "0,1"
|
|
newline
|
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0,1"
|
|
newline
|
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0,1"
|
|
newline
|
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0,1"
|
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newline
|
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bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0,1"
|
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newline
|
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bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
|
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newline
|
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bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
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rgroup.long 0x214++0x3
|
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line.long 0x0 "FLEX_US_CSR_SPI_MODE_MODE,USART Channel Status Register"
|
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bitfld.long 0x0 23. "NSS,NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read)" "0,1"
|
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newline
|
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bitfld.long 0x0 22. "CMP,Comparison Match" "0,1"
|
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newline
|
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bitfld.long 0x0 19. "NSSE,NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "UNRE,Underrun Error" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
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rgroup.long 0x214++0x7
|
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line.long 0x0 "FLEX_US_CSR_LIN_MODE_MODE,USART Channel Status Register"
|
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0,1"
|
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newline
|
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0,1"
|
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newline
|
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error" "0,1"
|
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newline
|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0,1"
|
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newline
|
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0,1"
|
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newline
|
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0,1"
|
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newline
|
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bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0,1"
|
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newline
|
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0,1"
|
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newline
|
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0,1"
|
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newline
|
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "PARE,Parity Error" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
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line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
|
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bitfld.long 0x4 15. "RXSYNH,Received Sync" "0,1"
|
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newline
|
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hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
|
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rgroup.long 0x218++0x3
|
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line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Character"
|
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Character"
|
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Character"
|
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newline
|
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hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Character"
|
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wgroup.long 0x21C++0x3
|
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line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
|
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bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0,1"
|
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newline
|
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hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
|
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wgroup.long 0x21C++0x3
|
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line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
|
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
|
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
|
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group.long 0x220++0xB
|
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line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
|
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bitfld.long 0x0 16.--18. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
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newline
|
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hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
|
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line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
|
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hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
|
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line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
|
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hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
|
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group.long 0x240++0x3
|
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line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
|
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hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
|
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rgroup.long 0x244++0x3
|
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line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
|
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hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
|
|
group.long 0x24C++0xF
|
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line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
|
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hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
|
|
line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0,1"
|
|
newline
|
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bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0,1"
|
|
newline
|
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bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
|
|
newline
|
|
bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
|
|
line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "PDCM,DMAC Mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
|
|
newline
|
|
bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "DLM,Data Length Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "PARDIS,Parity Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
|
|
line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
|
|
rgroup.long 0x25C++0x3
|
|
line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
|
|
bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
|
|
group.long 0x290++0x3
|
|
line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
|
|
hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
|
bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x2A0++0x3
|
|
line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x2A4++0x3
|
|
line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
wgroup.long 0x2A8++0x7
|
|
line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x2B0++0x7
|
|
line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
group.long 0x2E4++0x3
|
|
line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x2E8++0x3
|
|
line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x400++0x3
|
|
line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
|
|
group.long 0x404++0x3
|
|
line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "PCS,Peripheral Chip Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
newline
|
|
bitfld.long 0x0 8. "LBHPC,Last Bit Half Period Compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0,1"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RD8_3,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD8_2,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RD8_1,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RD8_0,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RD16_1,Receive Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD16_0,Receive Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
|
|
rgroup.long 0x410++0x3
|
|
line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0,1"
|
|
wgroup.long 0x414++0x7
|
|
line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
repeat.end
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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newline
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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newline
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bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
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newline
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bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
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rgroup.long 0x444++0x3
|
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line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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newline
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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group.long 0x448++0x3
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line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
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hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
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newline
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hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x4E4++0x3
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line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
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rgroup.long 0x4E8++0x3
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line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
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hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
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newline
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
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wgroup.long 0x600++0x3
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line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
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bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
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newline
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bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
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newline
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bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
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newline
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bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
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newline
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bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
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newline
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bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
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newline
|
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bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
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newline
|
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bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
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newline
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bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
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newline
|
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bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
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newline
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bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
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newline
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bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
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newline
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bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
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newline
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bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
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newline
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bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
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newline
|
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bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
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newline
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bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
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newline
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bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
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newline
|
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bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
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newline
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bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
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newline
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bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
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wgroup.long 0x600++0x3
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line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
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bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
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newline
|
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
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newline
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
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newline
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bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
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newline
|
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bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
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newline
|
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bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
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newline
|
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bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
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newline
|
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bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
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newline
|
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bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
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newline
|
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bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
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newline
|
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bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
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newline
|
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bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
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newline
|
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bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
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newline
|
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bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
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newline
|
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bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
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newline
|
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bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
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newline
|
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bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
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newline
|
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bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
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newline
|
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bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
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newline
|
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bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
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newline
|
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bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
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group.long 0x604++0xF
|
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line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
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hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
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newline
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bitfld.long 0x0 12. "MREAD,Master Read Direction" "0,1"
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newline
|
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bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
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line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
|
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bitfld.long 0x4 31. "DATAMEN,Data Matching Enable" "0,1"
|
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newline
|
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bitfld.long 0x4 30. "SADR3EN,Slave Address 3 Enable" "0,1"
|
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newline
|
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bitfld.long 0x4 29. "SADR2EN,Slave Address 2 Enable" "0,1"
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newline
|
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bitfld.long 0x4 28. "SADR1EN,Slave Address 1 Enable" "0,1"
|
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newline
|
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hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
|
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newline
|
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hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
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newline
|
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bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
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newline
|
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bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
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newline
|
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bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0,1"
|
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line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
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hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
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line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
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hexmask.long.byte 0xC 24.--28. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
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newline
|
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bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
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newline
|
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bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
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newline
|
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hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
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hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
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rgroup.long 0x620++0x3
|
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line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
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newline
|
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bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
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newline
|
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bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0,1"
|
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newline
|
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
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newline
|
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bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
rgroup.long 0x620++0x3
|
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line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
|
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
wgroup.long 0x624++0x7
|
|
line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
|
|
bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
|
|
rgroup.long 0x62C++0x7
|
|
line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
|
|
rgroup.long 0x630++0x3
|
|
line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
|
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|
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hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
|
|
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|
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hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
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|
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hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
|
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|
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hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
|
|
group.long 0x638++0x3
|
|
line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
|
|
newline
|
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hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
|
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
|
|
group.long 0x640++0x7
|
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line.long 0x0 "FLEX_TWI_ACR,TWI Alternative Command Register"
|
|
bitfld.long 0x0 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
|
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newline
|
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bitfld.long 0x0 24. "NDIR,Next Transfer Direction" "0,1"
|
|
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|
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hexmask.long.byte 0x0 16.--23. 1. "NDATAL,Next Data Length"
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newline
|
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bitfld.long 0x0 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "DIR,Transfer Direction" "0,1"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "DATAL,Data Length"
|
|
line.long 0x4 "FLEX_TWI_FILTR,TWI Filter Register"
|
|
bitfld.long 0x4 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
|
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newline
|
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bitfld.long 0x4 2. "PADFCFG,PAD Filter Config" "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "PADFEN,PAD Filter Enable" "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "FILT,RX Digital Filter" "0,1"
|
|
group.long 0x64C++0x7
|
|
line.long 0x0 "FLEX_TWI_SWMR,TWI SleepWalking Matching Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DATAM,Data Match"
|
|
newline
|
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hexmask.long.byte 0x0 16.--22. 1. "SADR3,Slave Address 3"
|
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|
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hexmask.long.byte 0x0 8.--14. 1. "SADR2,Slave Address 2"
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|
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hexmask.long.byte 0x0 0.--6. 1. "SADR1,Slave Address 1"
|
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line.long 0x4 "FLEX_TWI_FMR,TWI FIFO Mode Register"
|
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hexmask.long.byte 0x4 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
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newline
|
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hexmask.long.byte 0x4 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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newline
|
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bitfld.long 0x4 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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newline
|
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bitfld.long 0x4 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x654++0x3
|
|
line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
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newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
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rgroup.long 0x660++0x3
|
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line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
wgroup.long 0x664++0x7
|
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line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
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rgroup.long 0x66C++0x3
|
|
line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
rgroup.long 0x6D0++0x3
|
|
line.long 0x0 "FLEX_TWI_DR,TWI Debug Register"
|
|
bitfld.long 0x0 3. "TRP,Transfer Pending" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "SWMATCH,SleepWalking Match" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKRQ,Clock Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWEN,SleepWalking Enable" "0,1"
|
|
group.long 0x6E4++0x3
|
|
line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x6E8++0x3
|
|
line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0,1"
|
|
tree.end
|
|
tree "FLEXCOM2"
|
|
base ad:0xFC010000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected.USART/TWI related..,3: All TWI related protocols are selected (TWI.."
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|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
|
|
wgroup.long 0x200++0x3
|
|
line.long 0x0 "FLEX_US_CR,USART Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SENDA,Send Address" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "STPBRK,Stop Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "STTBRK,Start Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
wgroup.long 0x200++0x3
|
|
line.long 0x0 "FLEX_US_CR_SPI_MODE_MODE,USART Control Register"
|
|
bitfld.long 0x0 19. "RCS,Release SPI Chip Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "FCS,Force SPI Chip Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
|
bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 23. "INVDATA,Inverted Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
|
|
newline
|
|
bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
|
|
newline
|
|
bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR_SPI_MODE_MODE,USART Mode Register"
|
|
bitfld.long 0x0 20. "WRDBT,Wait Read Data Before Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CPOL,SPI Clock Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "CPHA,SPI Clock Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CHRL,Character Length" "?,?,?,3: Character length is 8 bits"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock Divided (DIV= 8) is selected,2: A PMC generic clock is selected,3: External pin SCK is selected"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "FLEX_US_IER_SPI_MODE_MODE,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "NSSE,NSS Line (Driving CTS Pin) Rising or Falling Edge Event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,SPI Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
wgroup.long 0x208++0x7
|
|
line.long 0x0 "FLEX_US_IER_LIN_MODE_MODE,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
wgroup.long 0x20C++0x3
|
|
line.long 0x0 "FLEX_US_IDR_SPI_MODE_MODE,USART Interrupt Disable Register"
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "NSSE,NSS Line (Driving CTS Pin) Rising or Falling Edge Event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,SPI Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
wgroup.long 0x20C++0x3
|
|
line.long 0x0 "FLEX_US_IDR_LIN_MODE_MODE,USART Interrupt Disable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x0 "FLEX_US_IMR_SPI_MODE_MODE,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "NSSE,NSS Line (Driving CTS Pin) Rising or Falling Edge Event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,SPI Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
rgroup.long 0x210++0x7
|
|
line.long 0x0 "FLEX_US_IMR_LIN_MODE_MODE,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CTS,Image of CTS Input" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x3
|
|
line.long 0x0 "FLEX_US_CSR_SPI_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 23. "NSS,NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Match" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "NSSE,NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x7
|
|
line.long 0x0 "FLEX_US_CSR_LIN_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
|
|
bitfld.long 0x4 15. "RXSYNH,Received Sync" "0,1"
|
|
newline
|
|
hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
|
|
rgroup.long 0x218++0x3
|
|
line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Character"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
|
|
bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
|
|
group.long 0x220++0xB
|
|
line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
|
|
bitfld.long 0x0 16.--18. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
|
|
line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
|
|
hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
|
|
line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
|
|
rgroup.long 0x244++0x3
|
|
line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
|
|
group.long 0x24C++0xF
|
|
line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
|
|
line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0,1"
|
|
newline
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bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
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bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0,1"
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bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
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line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
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bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0,1"
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bitfld.long 0x8 16. "PDCM,DMAC Mode" "0,1"
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hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
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bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0,1"
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bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0,1"
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bitfld.long 0x8 5. "DLM,Data Length Mode" "0,1"
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bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0,1"
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bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0,1"
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bitfld.long 0x8 2. "PARDIS,Parity Disable" "0,1"
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bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
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line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
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hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
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rgroup.long 0x25C++0x3
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line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
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bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
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group.long 0x290++0x3
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line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
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hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0,1"
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bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x2A0++0x3
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line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0,1"
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x2A4++0x3
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line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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wgroup.long 0x2A8++0x7
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line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
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bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x2B0++0x7
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line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
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bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
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bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0,1"
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bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
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bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
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bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
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bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
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bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
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bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
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bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
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bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
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group.long 0x2E4++0x3
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line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
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rgroup.long 0x2E8++0x3
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line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
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hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
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wgroup.long 0x400++0x3
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line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
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bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
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bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
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bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
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bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
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bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
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bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
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group.long 0x404++0x3
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line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
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hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
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bitfld.long 0x0 16.--17. "PCS,Peripheral Chip Select" "0,1,2,3"
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bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
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bitfld.long 0x0 8. "LBHPC,Last Bit Half Period Compatibility" "0,1"
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bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
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bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
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bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
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bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
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bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
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bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
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bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0,1"
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
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hexmask.long.byte 0x0 24.--31. 1. "RD8_3,Receive Data"
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hexmask.long.byte 0x0 16.--23. 1. "RD8_2,Receive Data"
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hexmask.long.byte 0x0 8.--15. 1. "RD8_1,Receive Data"
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hexmask.long.byte 0x0 0.--7. 1. "RD8_0,Receive Data"
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
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hexmask.long.word 0x0 16.--31. 1. "RD16_1,Receive Data"
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hexmask.long.word 0x0 0.--15. 1. "RD16_0,Receive Data"
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wgroup.long 0x40C++0x3
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line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
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wgroup.long 0x40C++0x3
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line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
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hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
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hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
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rgroup.long 0x410++0x3
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line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
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bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
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bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
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bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
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bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
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bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
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bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
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bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
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bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
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bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
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bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
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bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
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bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
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bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
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bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
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bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0,1"
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wgroup.long 0x414++0x7
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line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
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bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
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|
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bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
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|
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
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|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
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|
|
bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
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|
|
bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
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|
|
bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
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|
|
bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
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|
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bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
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|
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bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
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|
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bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
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|
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bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
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|
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bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
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newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
newline
|
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hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
repeat.end
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
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newline
|
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
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newline
|
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bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
|
|
newline
|
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bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
|
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rgroup.long 0x444++0x3
|
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line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
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newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
group.long 0x448++0x3
|
|
line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x4E4++0x3
|
|
line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x4E8++0x3
|
|
line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
group.long 0x604++0xF
|
|
line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
|
newline
|
|
bitfld.long 0x0 12. "MREAD,Master Read Direction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
|
line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
|
|
bitfld.long 0x4 31. "DATAMEN,Data Matching Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "SADR3EN,Slave Address 3 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "SADR2EN,Slave Address 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "SADR1EN,Slave Address 1 Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
|
|
newline
|
|
bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0,1"
|
|
line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--28. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
|
newline
|
|
bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
wgroup.long 0x624++0x7
|
|
line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
|
|
bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
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|
newline
|
|
bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
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|
newline
|
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bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
|
|
rgroup.long 0x62C++0x7
|
|
line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
|
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line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
|
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hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
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rgroup.long 0x630++0x3
|
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line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
|
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wgroup.long 0x634++0x3
|
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line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
|
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
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wgroup.long 0x634++0x3
|
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line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
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group.long 0x638++0x3
|
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line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
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newline
|
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hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
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group.long 0x640++0x7
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line.long 0x0 "FLEX_TWI_ACR,TWI Alternative Command Register"
|
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bitfld.long 0x0 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
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newline
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bitfld.long 0x0 24. "NDIR,Next Transfer Direction" "0,1"
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "NDATAL,Next Data Length"
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newline
|
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bitfld.long 0x0 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
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newline
|
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bitfld.long 0x0 8. "DIR,Transfer Direction" "0,1"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "DATAL,Data Length"
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line.long 0x4 "FLEX_TWI_FILTR,TWI Filter Register"
|
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bitfld.long 0x4 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
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newline
|
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bitfld.long 0x4 2. "PADFCFG,PAD Filter Config" "0,1"
|
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newline
|
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bitfld.long 0x4 1. "PADFEN,PAD Filter Enable" "0,1"
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newline
|
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bitfld.long 0x4 0. "FILT,RX Digital Filter" "0,1"
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group.long 0x64C++0x7
|
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line.long 0x0 "FLEX_TWI_SWMR,TWI SleepWalking Matching Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "DATAM,Data Match"
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newline
|
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hexmask.long.byte 0x0 16.--22. 1. "SADR3,Slave Address 3"
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newline
|
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hexmask.long.byte 0x0 8.--14. 1. "SADR2,Slave Address 2"
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newline
|
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hexmask.long.byte 0x0 0.--6. 1. "SADR1,Slave Address 1"
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line.long 0x4 "FLEX_TWI_FMR,TWI FIFO Mode Register"
|
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hexmask.long.byte 0x4 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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newline
|
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hexmask.long.byte 0x4 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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newline
|
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bitfld.long 0x4 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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newline
|
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bitfld.long 0x4 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x654++0x3
|
|
line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
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rgroup.long 0x660++0x3
|
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line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
wgroup.long 0x664++0x7
|
|
line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x66C++0x3
|
|
line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
rgroup.long 0x6D0++0x3
|
|
line.long 0x0 "FLEX_TWI_DR,TWI Debug Register"
|
|
bitfld.long 0x0 3. "TRP,Transfer Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "SWMATCH,SleepWalking Match" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKRQ,Clock Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWEN,SleepWalking Enable" "0,1"
|
|
group.long 0x6E4++0x3
|
|
line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x6E8++0x3
|
|
line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0,1"
|
|
tree.end
|
|
tree "FLEXCOM3"
|
|
base ad:0xFC014000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected.USART/TWI related..,3: All TWI related protocols are selected (TWI.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
|
|
wgroup.long 0x200++0x3
|
|
line.long 0x0 "FLEX_US_CR,USART Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SENDA,Send Address" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "STPBRK,Stop Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "STTBRK,Start Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
wgroup.long 0x200++0x3
|
|
line.long 0x0 "FLEX_US_CR_SPI_MODE_MODE,USART Control Register"
|
|
bitfld.long 0x0 19. "RCS,Release SPI Chip Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "FCS,Force SPI Chip Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
|
bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 23. "INVDATA,Inverted Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
|
|
newline
|
|
bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
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newline
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bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
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newline
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bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
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newline
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bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
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group.long 0x204++0x3
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line.long 0x0 "FLEX_US_MR_SPI_MODE_MODE,USART Mode Register"
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bitfld.long 0x0 20. "WRDBT,Wait Read Data Before Transfer" "0,1"
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newline
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bitfld.long 0x0 16. "CPOL,SPI Clock Polarity" "0,1"
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newline
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bitfld.long 0x0 8. "CPHA,SPI Clock Phase" "0,1"
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newline
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bitfld.long 0x0 6.--7. "CHRL,Character Length" "?,?,?,3: Character length is 8 bits"
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newline
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bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock Divided (DIV= 8) is selected,2: A PMC generic clock is selected,3: External pin SCK is selected"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
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wgroup.long 0x208++0x3
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line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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wgroup.long 0x208++0x3
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line.long 0x0 "FLEX_US_IER_SPI_MODE_MODE,USART Interrupt Enable Register"
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 19. "NSSE,NSS Line (Driving CTS Pin) Rising or Falling Edge Event" "0,1"
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newline
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bitfld.long 0x0 10. "UNRE,SPI Underrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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wgroup.long 0x208++0x7
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line.long 0x0 "FLEX_US_IER_LIN_MODE_MODE,USART Interrupt Enable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
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bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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wgroup.long 0x20C++0x3
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line.long 0x0 "FLEX_US_IDR_SPI_MODE_MODE,USART Interrupt Disable Register"
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 19. "NSSE,NSS Line (Driving CTS Pin) Rising or Falling Edge Event" "0,1"
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newline
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bitfld.long 0x0 10. "UNRE,SPI Underrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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wgroup.long 0x20C++0x3
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line.long 0x0 "FLEX_US_IDR_LIN_MODE_MODE,USART Interrupt Disable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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rgroup.long 0x210++0x3
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line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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rgroup.long 0x210++0x3
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line.long 0x0 "FLEX_US_IMR_SPI_MODE_MODE,USART Interrupt Mask Register"
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 19. "NSSE,NSS Line (Driving CTS Pin) Rising or Falling Edge Event" "0,1"
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newline
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bitfld.long 0x0 10. "UNRE,SPI Underrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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rgroup.long 0x210++0x7
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line.long 0x0 "FLEX_US_IMR_LIN_MODE_MODE,USART Interrupt Mask Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
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bitfld.long 0x4 24. "MANE,Manchester Error" "0,1"
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newline
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bitfld.long 0x4 23. "CTS,Image of CTS Input" "0,1"
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newline
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bitfld.long 0x4 22. "CMP,Comparison Status" "0,1"
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newline
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0,1"
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newline
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0,1"
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newline
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0,1"
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newline
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bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
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newline
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bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0,1"
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newline
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bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
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newline
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bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
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newline
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bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
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newline
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bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0,1"
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newline
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bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
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newline
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bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
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rgroup.long 0x214++0x3
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line.long 0x0 "FLEX_US_CSR_SPI_MODE_MODE,USART Channel Status Register"
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bitfld.long 0x0 23. "NSS,NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 22. "CMP,Comparison Match" "0,1"
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newline
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bitfld.long 0x0 19. "NSSE,NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 10. "UNRE,Underrun Error" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
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rgroup.long 0x214++0x7
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line.long 0x0 "FLEX_US_CSR_LIN_MODE_MODE,USART Channel Status Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0,1"
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newline
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0,1"
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newline
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error" "0,1"
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newline
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0,1"
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newline
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0,1"
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newline
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0,1"
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newline
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bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0,1"
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newline
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bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0,1"
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newline
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0,1"
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0,1"
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newline
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
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newline
|
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bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
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line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
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bitfld.long 0x4 15. "RXSYNH,Received Sync" "0,1"
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newline
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hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
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rgroup.long 0x218++0x3
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line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Character"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Character"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Character"
|
|
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|
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hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Character"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
|
|
bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0,1"
|
|
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|
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hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
|
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|
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hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
|
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|
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hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
|
|
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|
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hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
|
|
group.long 0x220++0xB
|
|
line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
|
|
bitfld.long 0x0 16.--18. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
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|
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hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
|
|
line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
|
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hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
|
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line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
|
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hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
|
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group.long 0x240++0x3
|
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line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
|
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hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
|
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rgroup.long 0x244++0x3
|
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line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
|
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hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
|
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group.long 0x24C++0xF
|
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line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
|
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hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
|
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line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0,1"
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|
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bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0,1"
|
|
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|
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bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
|
|
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|
|
bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0,1"
|
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|
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bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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|
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hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
|
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|
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bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0,1"
|
|
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|
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bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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|
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hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
|
|
line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
|
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bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0,1"
|
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|
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bitfld.long 0x8 16. "PDCM,DMAC Mode" "0,1"
|
|
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|
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hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
|
|
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|
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bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0,1"
|
|
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|
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bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0,1"
|
|
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|
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bitfld.long 0x8 5. "DLM,Data Length Mode" "0,1"
|
|
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|
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bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0,1"
|
|
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|
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bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0,1"
|
|
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|
|
bitfld.long 0x8 2. "PARDIS,Parity Disable" "0,1"
|
|
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|
|
bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
|
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line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
|
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hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
|
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rgroup.long 0x25C++0x3
|
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line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
|
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bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
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|
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hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
|
|
group.long 0x290++0x3
|
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line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
|
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hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
|
|
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|
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0,1"
|
|
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|
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bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
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|
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
|
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group.long 0x2A0++0x3
|
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line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
|
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
|
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|
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
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|
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
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|
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0,1"
|
|
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|
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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newline
|
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x2A4++0x3
|
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line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
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newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
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wgroup.long 0x2A8++0x7
|
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line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
|
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
|
|
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|
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
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|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
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|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
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rgroup.long 0x2B0++0x7
|
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line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
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line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
group.long 0x2E4++0x3
|
|
line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
|
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
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newline
|
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x2E8++0x3
|
|
line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x400++0x3
|
|
line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
|
|
group.long 0x404++0x3
|
|
line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
|
|
newline
|
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bitfld.long 0x0 16.--17. "PCS,Peripheral Chip Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
newline
|
|
bitfld.long 0x0 8. "LBHPC,Last Bit Half Period Compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0,1"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RD8_3,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD8_2,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RD8_1,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RD8_0,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RD16_1,Receive Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD16_0,Receive Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
|
|
rgroup.long 0x410++0x3
|
|
line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0,1"
|
|
wgroup.long 0x414++0x7
|
|
line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
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newline
|
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hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
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newline
|
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bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
repeat.end
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
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newline
|
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bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
|
|
newline
|
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bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
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|
rgroup.long 0x444++0x3
|
|
line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
group.long 0x448++0x3
|
|
line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x4E4++0x3
|
|
line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
|
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x4E8++0x3
|
|
line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
group.long 0x604++0xF
|
|
line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
|
newline
|
|
bitfld.long 0x0 12. "MREAD,Master Read Direction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
|
line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
|
|
bitfld.long 0x4 31. "DATAMEN,Data Matching Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "SADR3EN,Slave Address 3 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "SADR2EN,Slave Address 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "SADR1EN,Slave Address 1 Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
|
|
newline
|
|
bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0,1"
|
|
line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--28. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
|
newline
|
|
bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
wgroup.long 0x624++0x7
|
|
line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
|
|
bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
|
|
rgroup.long 0x62C++0x7
|
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line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
|
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newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
|
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hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
|
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rgroup.long 0x630++0x3
|
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line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
|
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
|
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
|
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wgroup.long 0x634++0x3
|
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line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
|
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
|
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wgroup.long 0x634++0x3
|
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line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
|
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
|
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
|
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newline
|
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
|
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group.long 0x638++0x3
|
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line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
|
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
|
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group.long 0x640++0x7
|
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line.long 0x0 "FLEX_TWI_ACR,TWI Alternative Command Register"
|
|
bitfld.long 0x0 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
|
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newline
|
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bitfld.long 0x0 24. "NDIR,Next Transfer Direction" "0,1"
|
|
newline
|
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hexmask.long.byte 0x0 16.--23. 1. "NDATAL,Next Data Length"
|
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newline
|
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bitfld.long 0x0 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DIR,Transfer Direction" "0,1"
|
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newline
|
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hexmask.long.byte 0x0 0.--7. 1. "DATAL,Data Length"
|
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line.long 0x4 "FLEX_TWI_FILTR,TWI Filter Register"
|
|
bitfld.long 0x4 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x4 2. "PADFCFG,PAD Filter Config" "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "PADFEN,PAD Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "FILT,RX Digital Filter" "0,1"
|
|
group.long 0x64C++0x7
|
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line.long 0x0 "FLEX_TWI_SWMR,TWI SleepWalking Matching Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DATAM,Data Match"
|
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newline
|
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hexmask.long.byte 0x0 16.--22. 1. "SADR3,Slave Address 3"
|
|
newline
|
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hexmask.long.byte 0x0 8.--14. 1. "SADR2,Slave Address 2"
|
|
newline
|
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hexmask.long.byte 0x0 0.--6. 1. "SADR1,Slave Address 1"
|
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line.long 0x4 "FLEX_TWI_FMR,TWI FIFO Mode Register"
|
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hexmask.long.byte 0x4 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
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newline
|
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hexmask.long.byte 0x4 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
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bitfld.long 0x4 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
|
|
newline
|
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bitfld.long 0x4 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x654++0x3
|
|
line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
rgroup.long 0x660++0x3
|
|
line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
wgroup.long 0x664++0x7
|
|
line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x66C++0x3
|
|
line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
rgroup.long 0x6D0++0x3
|
|
line.long 0x0 "FLEX_TWI_DR,TWI Debug Register"
|
|
bitfld.long 0x0 3. "TRP,Transfer Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "SWMATCH,SleepWalking Match" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKRQ,Clock Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWEN,SleepWalking Enable" "0,1"
|
|
group.long 0x6E4++0x3
|
|
line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x6E8++0x3
|
|
line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0,1"
|
|
tree.end
|
|
tree "FLEXCOM4"
|
|
base ad:0xFC018000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected.USART/TWI related..,3: All TWI related protocols are selected (TWI.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
|
|
wgroup.long 0x200++0x3
|
|
line.long 0x0 "FLEX_US_CR,USART Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SENDA,Send Address" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "STPBRK,Stop Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "STTBRK,Start Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
wgroup.long 0x200++0x3
|
|
line.long 0x0 "FLEX_US_CR_SPI_MODE_MODE,USART Control Register"
|
|
bitfld.long 0x0 19. "RCS,Release SPI Chip Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "FCS,Force SPI Chip Select" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
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newline
|
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bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
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newline
|
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bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
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newline
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bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
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newline
|
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bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
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newline
|
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bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
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newline
|
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bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
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group.long 0x204++0x3
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line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
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bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0,1"
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newline
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bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0,1"
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newline
|
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bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0,1"
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newline
|
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bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
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newline
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bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
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newline
|
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bitfld.long 0x0 23. "INVDATA,Inverted Data" "0,1"
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newline
|
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bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0,1"
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newline
|
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bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0,1"
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newline
|
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bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0,1"
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newline
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bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
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newline
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bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
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newline
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bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
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newline
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bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
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newline
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bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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newline
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bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
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newline
|
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bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
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newline
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bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
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newline
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bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
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newline
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bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
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group.long 0x204++0x3
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line.long 0x0 "FLEX_US_MR_SPI_MODE_MODE,USART Mode Register"
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bitfld.long 0x0 20. "WRDBT,Wait Read Data Before Transfer" "0,1"
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newline
|
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bitfld.long 0x0 16. "CPOL,SPI Clock Polarity" "0,1"
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newline
|
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bitfld.long 0x0 8. "CPHA,SPI Clock Phase" "0,1"
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newline
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bitfld.long 0x0 6.--7. "CHRL,Character Length" "?,?,?,3: Character length is 8 bits"
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newline
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bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock Divided (DIV= 8) is selected,2: A PMC generic clock is selected,3: External pin SCK is selected"
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newline
|
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
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wgroup.long 0x208++0x3
|
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line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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wgroup.long 0x208++0x3
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line.long 0x0 "FLEX_US_IER_SPI_MODE_MODE,USART Interrupt Enable Register"
|
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 19. "NSSE,NSS Line (Driving CTS Pin) Rising or Falling Edge Event" "0,1"
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newline
|
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bitfld.long 0x0 10. "UNRE,SPI Underrun Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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wgroup.long 0x208++0x7
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line.long 0x0 "FLEX_US_IER_LIN_MODE_MODE,USART Interrupt Enable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
|
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newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
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newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
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line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
|
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bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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wgroup.long 0x20C++0x3
|
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line.long 0x0 "FLEX_US_IDR_SPI_MODE_MODE,USART Interrupt Disable Register"
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 19. "NSSE,NSS Line (Driving CTS Pin) Rising or Falling Edge Event" "0,1"
|
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newline
|
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bitfld.long 0x0 10. "UNRE,SPI Underrun Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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wgroup.long 0x20C++0x3
|
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line.long 0x0 "FLEX_US_IDR_LIN_MODE_MODE,USART Interrupt Disable Register"
|
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
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rgroup.long 0x210++0x3
|
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line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
|
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
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rgroup.long 0x210++0x3
|
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line.long 0x0 "FLEX_US_IMR_SPI_MODE_MODE,USART Interrupt Mask Register"
|
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 19. "NSSE,NSS Line (Driving CTS Pin) Rising or Falling Edge Event" "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "UNRE,SPI Underrun Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
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rgroup.long 0x210++0x7
|
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line.long 0x0 "FLEX_US_IMR_LIN_MODE_MODE,USART Interrupt Mask Register"
|
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
|
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newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
|
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newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CTS,Image of CTS Input" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x3
|
|
line.long 0x0 "FLEX_US_CSR_SPI_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 23. "NSS,NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Match" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "NSSE,NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNRE,Underrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x7
|
|
line.long 0x0 "FLEX_US_CSR_LIN_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
|
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bitfld.long 0x4 15. "RXSYNH,Received Sync" "0,1"
|
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newline
|
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hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
|
|
rgroup.long 0x218++0x3
|
|
line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Character"
|
|
newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Character"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Character"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Character"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
|
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bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0,1"
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newline
|
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hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
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wgroup.long 0x21C++0x3
|
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line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
|
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
|
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
|
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group.long 0x220++0xB
|
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line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
|
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bitfld.long 0x0 16.--18. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
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newline
|
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hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
|
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line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
|
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hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
|
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line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
|
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hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
|
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group.long 0x240++0x3
|
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line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
|
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hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
|
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rgroup.long 0x244++0x3
|
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line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
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hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
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group.long 0x24C++0xF
|
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line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
|
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hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
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line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
|
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bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0,1"
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newline
|
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bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0,1"
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newline
|
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bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
|
|
newline
|
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bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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newline
|
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hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
|
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newline
|
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bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0,1"
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newline
|
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bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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newline
|
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hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
|
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line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
|
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bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0,1"
|
|
newline
|
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bitfld.long 0x8 16. "PDCM,DMAC Mode" "0,1"
|
|
newline
|
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hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
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|
newline
|
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bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0,1"
|
|
newline
|
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bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0,1"
|
|
newline
|
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bitfld.long 0x8 5. "DLM,Data Length Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "PARDIS,Parity Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
|
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line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
|
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hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
|
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rgroup.long 0x25C++0x3
|
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line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
|
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bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
|
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group.long 0x290++0x3
|
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line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
|
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hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
|
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newline
|
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
|
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group.long 0x2A0++0x3
|
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line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
|
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
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newline
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0,1"
|
|
newline
|
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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newline
|
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x2A4++0x3
|
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line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
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newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
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wgroup.long 0x2A8++0x7
|
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line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
|
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
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line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x2B0++0x7
|
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line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
group.long 0x2E4++0x3
|
|
line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x2E8++0x3
|
|
line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x400++0x3
|
|
line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
|
|
group.long 0x404++0x3
|
|
line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "PCS,Peripheral Chip Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
newline
|
|
bitfld.long 0x0 8. "LBHPC,Last Bit Half Period Compatibility" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0,1"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RD8_3,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD8_2,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RD8_1,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RD8_0,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RD16_1,Receive Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD16_0,Receive Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
|
|
rgroup.long 0x410++0x3
|
|
line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0,1"
|
|
wgroup.long 0x414++0x7
|
|
line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
newline
|
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hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
repeat.end
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
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newline
|
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
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bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
|
|
newline
|
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bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
|
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rgroup.long 0x444++0x3
|
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line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
group.long 0x448++0x3
|
|
line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
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hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x4E4++0x3
|
|
line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
|
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
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newline
|
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x4E8++0x3
|
|
line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
group.long 0x604++0xF
|
|
line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
|
newline
|
|
bitfld.long 0x0 12. "MREAD,Master Read Direction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
|
line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
|
|
bitfld.long 0x4 31. "DATAMEN,Data Matching Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "SADR3EN,Slave Address 3 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "SADR2EN,Slave Address 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "SADR1EN,Slave Address 1 Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
|
|
newline
|
|
bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0,1"
|
|
line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--28. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
|
newline
|
|
bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
wgroup.long 0x624++0x7
|
|
line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
|
|
bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
|
|
rgroup.long 0x62C++0x7
|
|
line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
|
|
rgroup.long 0x630++0x3
|
|
line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
|
|
group.long 0x638++0x3
|
|
line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
|
|
group.long 0x640++0x7
|
|
line.long 0x0 "FLEX_TWI_ACR,TWI Alternative Command Register"
|
|
bitfld.long 0x0 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "NDIR,Next Transfer Direction" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "NDATAL,Next Data Length"
|
|
newline
|
|
bitfld.long 0x0 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DIR,Transfer Direction" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATAL,Data Length"
|
|
line.long 0x4 "FLEX_TWI_FILTR,TWI Filter Register"
|
|
bitfld.long 0x4 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 2. "PADFCFG,PAD Filter Config" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "PADFEN,PAD Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "FILT,RX Digital Filter" "0,1"
|
|
group.long 0x64C++0x7
|
|
line.long 0x0 "FLEX_TWI_SWMR,TWI SleepWalking Matching Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DATAM,Data Match"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "SADR3,Slave Address 3"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "SADR2,Slave Address 2"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "SADR1,Slave Address 1"
|
|
line.long 0x4 "FLEX_TWI_FMR,TWI FIFO Mode Register"
|
|
hexmask.long.byte 0x4 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x654++0x3
|
|
line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
rgroup.long 0x660++0x3
|
|
line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
wgroup.long 0x664++0x7
|
|
line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x66C++0x3
|
|
line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
rgroup.long 0x6D0++0x3
|
|
line.long 0x0 "FLEX_TWI_DR,TWI Debug Register"
|
|
bitfld.long 0x0 3. "TRP,Transfer Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "SWMATCH,SleepWalking Match" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKRQ,Clock Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWEN,SleepWalking Enable" "0,1"
|
|
group.long 0x6E4++0x3
|
|
line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x6E8++0x3
|
|
line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "GMAC (Ethernet MAC)"
|
|
base ad:0xF8008000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "NCR,Network Control Register"
|
|
bitfld.long 0x0 30. "IFGQAVCRED,Credit-Based Shaping Algorithm Modification" "0: No modification of the CBS algorithm.,1: Modifies the CBS algorithm so the IFG/IPG.."
|
|
bitfld.long 0x0 28. "MIIONRGMII,MII Control" "0: Disables MII operation.,?"
|
|
newline
|
|
bitfld.long 0x0 27. "OSSCORR,OSS Correction Field" "0,1"
|
|
bitfld.long 0x0 26. "EXTSELRQEN,External Selection of Receive Queue Enable" "0: Disables external selection of receive queue.,1: Enables external selection of receive queue."
|
|
newline
|
|
bitfld.long 0x0 25. "PFCCTL,Multiple PFC Pause quantum Enable" "0: Disables multiple PFC pause quantums.,1: Enables multiple PFC pause quantums one per.."
|
|
bitfld.long 0x0 24. "OSSMODE,One Step Sync Mode" "0: 1588 One Step Sync Mode is disabled.,1: 1588 One Step Sync Mode is enabled. Replaces.."
|
|
newline
|
|
bitfld.long 0x0 22. "STUDPOFFSET,Store UDP Offset" "0: Normal operations.,1: The upper 16 bits of the CRC of every received.."
|
|
bitfld.long 0x0 20. "PTPUNIENA,Detection of Unicast PTP Frames Enable" "0: Disables detection of unicast PTP frames.,1: Enables detection of unicast PTP frames."
|
|
newline
|
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bitfld.long 0x0 19. "TXLPIEN,Enable LPI Transmission" "0,1"
|
|
bitfld.long 0x0 18. "FNP,Flush Next Packet" "0: No effect.,1: Flushes the next packet from the receive memory."
|
|
newline
|
|
bitfld.long 0x0 17. "TXPBPF,Transmit PFC Priority-based Pause Frame" "0: No effect.,1: Takes the values stored in the Transmit PFC.."
|
|
bitfld.long 0x0 16. "ENPBPR,Enable PFC Priority-based Pause Reception" "0,1"
|
|
newline
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bitfld.long 0x0 15. "SRTSM,Store Receive Timestamp to Memory" "0: No effect.,1: Causes the CRC of every received frame to be.."
|
|
bitfld.long 0x0 12. "TXZQPF,Transmit Zero Quantum Pause Frame (Write-only)" "0: No effect.,1: Generates a pause frame with zero quantum to be.."
|
|
newline
|
|
bitfld.long 0x0 11. "TXPF,Transmit Pause Frame (Write-only)" "0: No effect.,1: Generates a pause frame to be transmitted."
|
|
bitfld.long 0x0 10. "THALT,Transmit Halt (Write-only)" "0: No effect.,1: Halts transmission as soon as any ongoing frame.."
|
|
newline
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bitfld.long 0x0 9. "TSTART,Start Transmission (Write-only)" "0: No effect.,1: Starts transmission."
|
|
bitfld.long 0x0 8. "BP,Back Pressure" "0: No effect,1: When the MAC is set in 10M or 100M Half Duplex.."
|
|
newline
|
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bitfld.long 0x0 7. "WESTAT,Write Enable for Statistics Registers" "0: Forces the statistics registers to be in..,1: Makes the statistics registers writable for.."
|
|
bitfld.long 0x0 6. "INCSTAT,Increment Statistics Registers (Write-only)" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "CLRSTAT,Clear Statistics Registers (Write-only)" "0: No effect.,1: Clears the statistics registers."
|
|
bitfld.long 0x0 4. "MPE,Management Port Enable" "0: Forces GMDIO to high impedance state and MDC low.,1: Enables the management port."
|
|
newline
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bitfld.long 0x0 3. "TXEN,Transmit Enable" "0: Stops transmission immediately the transmit..,1: Enables the GMAC transmitter to send data."
|
|
bitfld.long 0x0 2. "RXEN,Receive Enable" "0: Stops frame reception immediately and the..,1: Enables the GMAC to receive data."
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|
newline
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bitfld.long 0x0 1. "LBL,Loop Back Local" "0: Normal operating mode (no loop back).,1: Connects GTX to GRX GTXEN to GRXDV and forces.."
|
|
line.long 0x4 "NCFGR,Network Configuration Register"
|
|
bitfld.long 0x4 30. "IRXER,Ignore Receive Error from PHY" "0,1"
|
|
bitfld.long 0x4 29. "RXBP,Receive Bad Preamble" "0,1"
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|
newline
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bitfld.long 0x4 28. "IPGSEN,IP Stretch Enable" "0,1"
|
|
bitfld.long 0x4 26. "IRXFCS,Ignore RX FCS" "0,1"
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|
newline
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bitfld.long 0x4 25. "EFRHD,Enable Frames Received in Half Duplex" "0,1"
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|
bitfld.long 0x4 24. "RXCOEN,Receive Checksum Offload Enable" "0,1"
|
|
newline
|
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bitfld.long 0x4 23. "DCPF,Disable Copy of Pause Frames" "0,1"
|
|
bitfld.long 0x4 21.--22. "DBW,Data Bus Width" "0,1,2,3"
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newline
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bitfld.long 0x4 18.--20. "CLK,MDC CLock Division" "0: MCK divided by 8 (MCK up to 20 MHz),1: MCK divided by 16 (MCK up to 40 MHz),2: MCK divided by 32 (MCK up to 80 MHz),3: MCK divided by 48 (MCK up to 120 MHz),4: MCK divided by 64 (MCK up to 160 MHz),5: MCK divided by 96 (MCK up to 240 MHz),?,?"
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bitfld.long 0x4 17. "RFCS,Remove FCS" "0,1"
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newline
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bitfld.long 0x4 16. "LFERD,Length Field Error Frame Discard" "0,1"
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bitfld.long 0x4 14.--15. "RXBUFO,Receive Buffer Offset" "0,1,2,3"
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newline
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bitfld.long 0x4 13. "PEN,Pause Enable" "0,1"
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bitfld.long 0x4 12. "RTY,Retry Test0" "0,1"
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newline
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bitfld.long 0x4 8. "MAXFS,1536 Maximum Frame Size" "0,1"
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|
bitfld.long 0x4 7. "UNIHEN,Unicast Hash Enable" "0,1"
|
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newline
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bitfld.long 0x4 6. "MTIHEN,Multicast Hash Enable" "0,1"
|
|
bitfld.long 0x4 5. "NBC,No Broadcast" "0,1"
|
|
newline
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bitfld.long 0x4 4. "CAF,Copy All Frames" "0,1"
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|
bitfld.long 0x4 3. "JFRAME,Jumbo Frame Size" "0,1"
|
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newline
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bitfld.long 0x4 2. "DNVLAN,Discard Non-VLAN FRAMES" "0,1"
|
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bitfld.long 0x4 1. "FD,Full Duplex" "0,1"
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newline
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bitfld.long 0x4 0. "SPD,Speed" "0,1"
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rgroup.long 0x8++0x3
|
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line.long 0x0 "NSR,Network Status Register"
|
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bitfld.long 0x0 7. "RXLPIS,LPI Indication" "0,1"
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bitfld.long 0x0 6. "PFCPAUSN,PFC Pause Negotiated" "0,1"
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newline
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bitfld.long 0x0 2. "IDLE,PHY Management Logic Idle" "0,1"
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bitfld.long 0x0 1. "MDIO,MDIO Input Status" "0,1"
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group.long 0xC++0x17
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line.long 0x0 "UR,User Register"
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bitfld.long 0x0 6. "HDFLCTLEN,Half Duplex Flow Control Enable" "0: Half duplex flow control is disabled.,1: Half duplex flow control is enabled."
|
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bitfld.long 0x0 0. "RMII,Reduced MII Mode" "?,1: RMII mode is selected."
|
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line.long 0x4 "DCFGR,DMA Configuration Register"
|
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bitfld.long 0x4 29. "TXBD_EXTENDED,Transmit Buffer Descriptor Extended Mode" "0: Disables Transmit Buffer Data Extended mode.,1: Enables Transmit Buffer Data Extended mode."
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bitfld.long 0x4 28. "RXBD_EXTENDED,Receive Buffer Descriptor Extended Mode" "0: Disables Receive Buffer Data Extended mode.,1: Enables Receive Buffer Data Extended mode."
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newline
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bitfld.long 0x4 26. "TXFOMAXB,Force Transmit Max Burst Length" "0,1"
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bitfld.long 0x4 25. "RXFOMAXB,Force Receive Max Burst Length" "0,1"
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newline
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bitfld.long 0x4 24. "DDRP,DMA Discard Receive Packets" "0,1"
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hexmask.long.byte 0x4 16.--23. 1. "DRBS,DMA Receive Buffer Size"
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newline
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bitfld.long 0x4 13. "CRCERRREP,CRC Errors Report" "0: Bit 16 of the receive buffer descriptor..,1: Bit 16 of the receive buffer descriptor.."
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bitfld.long 0x4 12. "INFLASTEN,Infinite Size for Last Buffer Enable" "0,1"
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newline
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bitfld.long 0x4 11. "TXCOEN,Transmitter Checksum Generation Offload Enable" "0,1"
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bitfld.long 0x4 10. "TXPBMS,Transmitter Packet Buffer Memory Size Select" "0: Do not use top address bit (2 Kbytes).,1: Use full configured addressable space (4 Kbytes)."
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newline
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bitfld.long 0x4 8.--9. "RXBMS,Receiver Packet Buffer Memory Size Select" "0: 4/8 Kbyte Memory Size,1: 4/4 Kbytes Memory Size,2: 4/2 Kbytes Memory Size,3: 4 Kbytes Memory Size"
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bitfld.long 0x4 7. "ESPA,Endian Swap Mode Enable for Packet Data Accesses" "0: Selects Little-endian endianism for system bus..,1: Selects swapped endianism for system bus.."
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newline
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bitfld.long 0x4 6. "ESMA,Endian Swap Mode Enable for Management Descriptor Accesses" "0: Selects Little-endian endianism for system bus..,1: Selects swapped endianism for system bus.."
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hexmask.long.byte 0x4 0.--4. 1. "FBLDO,Fixed Burst Length for DMA Data Operations:"
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line.long 0x8 "TSR,Transmit Status Register"
|
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bitfld.long 0x8 8. "HRESP,System Bus Response" "0,1"
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bitfld.long 0x8 5. "TXCOMP,Transmit Complete" "0,1"
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newline
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bitfld.long 0x8 4. "TFC,Transmit Frame Corruption Due to System Bus Error" "0,1"
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bitfld.long 0x8 3. "TXGO,Transmit Go (Read only)" "0,1"
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newline
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bitfld.long 0x8 2. "RLE,Retry Limit Exceeded" "0,1"
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bitfld.long 0x8 1. "COL,Collision Occurred" "0,1"
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newline
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bitfld.long 0x8 0. "UBR,Used Bit Read" "0,1"
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line.long 0xC "RBQB,Receive Buffer Queue Base Address Register"
|
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hexmask.long 0xC 2.--31. 1. "ADDR,Receive Buffer Queue Base Address"
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bitfld.long 0xC 0. "RXQDIS,Receive Queue Disable" "0: Queue is enabled.,1: Queue is disabled. Used to reduce the number of.."
|
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line.long 0x10 "TBQB,Transmit Buffer Queue Base Address Register"
|
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hexmask.long 0x10 2.--31. 1. "ADDR,Transmit Buffer Queue Base Address"
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bitfld.long 0x10 0. "TXQDIS,Transmit Queue Disable" "0: Queue is enabled.,1: Queue is disabled. Used to reduce the number of.."
|
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line.long 0x14 "RSR,Receive Status Register"
|
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bitfld.long 0x14 3. "HNO,System Bus Error" "0,1"
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bitfld.long 0x14 2. "RXOVR,Receive Overrun" "0,1"
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newline
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bitfld.long 0x14 1. "REC,Frame Received" "0,1"
|
|
bitfld.long 0x14 0. "BNA,Buffer Not Available" "0,1"
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rgroup.long 0x24++0x3
|
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line.long 0x0 "ISR,Interrupt Status Register"
|
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bitfld.long 0x0 29. "TSUTIMCOMP,TSU Timer Comparison (Cleared on read)" "0,1"
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bitfld.long 0x0 28. "WOL,Wake On LAN" "0,1"
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newline
|
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bitfld.long 0x0 27. "RXLPISBC,Receive LPI indication Status Bit Change (Cleared on read)" "0,1"
|
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bitfld.long 0x0 26. "SRI,TSU Seconds Register Increment (Cleared on read)" "0,1"
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|
newline
|
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bitfld.long 0x0 25. "PDRSFT,PDelay Response Frame Transmitted (Cleared on read)" "0,1"
|
|
bitfld.long 0x0 24. "PDRQFT,PDelay Request Frame Transmitted (Cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 23. "PDRSFR,PDelay Response Frame Received (Cleared on read)" "0,1"
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bitfld.long 0x0 22. "PDRQFR,PDelay Request Frame Received (Cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 21. "SFT,PTP Sync Frame Transmitted (Cleared on read)" "0,1"
|
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bitfld.long 0x0 20. "DRQFT,PTP Delay Request Frame Transmitted (Cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 19. "SFR,PTP Sync Frame Received (Cleared on read)" "0,1"
|
|
bitfld.long 0x0 18. "DRQFR,PTP Delay Request Frame Received (Cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 14. "PFTR,Pause Frame Transmitted (Cleared on read)" "0,1"
|
|
bitfld.long 0x0 13. "PTZ,Pause Time Zero (Cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 12. "PFNZ,Pause Frame with Non-zero Pause Quantum Received (Cleared on read)" "0,1"
|
|
bitfld.long 0x0 11. "HRESP,System Bus Error (Cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "ROVR,Receive Overrun (Cleared on read)" "0,1"
|
|
bitfld.long 0x0 7. "TCOMP,Transmit Complete (Cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TFC,Transmit Frame Corruption Due to System Bus Error (Cleared on read)" "0,1"
|
|
bitfld.long 0x0 5. "RLEX,Retry Limit Exceeded(Cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TUR,Transmit Underrun (Cleared on read)" "0,1"
|
|
bitfld.long 0x0 3. "TXUBR,TX Used Bit Read (Cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXUBR,RX Used Bit Read (Cleared on read)" "0,1"
|
|
bitfld.long 0x0 1. "RCOMP,Receive Complete (Cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MFS,Management Frame Sent (Cleared on read)" "0,1"
|
|
wgroup.long 0x28++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 29. "TSUTIMCOMP,TSU Timer Comparison" "0,1"
|
|
bitfld.long 0x0 28. "WOL,Wake On LAN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXLPISBC,Enable RX LPI Indication" "0,1"
|
|
bitfld.long 0x0 26. "SRI,TSU Seconds Register Increment" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "PDRSFT,PDelay Response Frame Transmitted" "0,1"
|
|
bitfld.long 0x0 24. "PDRQFT,PDelay Request Frame Transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "PDRSFR,PDelay Response Frame Received" "0,1"
|
|
bitfld.long 0x0 22. "PDRQFR,PDelay Request Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SFT,PTP Sync Frame Transmitted" "0,1"
|
|
bitfld.long 0x0 20. "DRQFT,PTP Delay Request Frame Transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "SFR,PTP Sync Frame Received" "0,1"
|
|
bitfld.long 0x0 18. "DRQFR,PTP Delay Request Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EXINT,External Interrupt" "0,1"
|
|
bitfld.long 0x0 14. "PFTR,Pause Frame Transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PTZ,Pause Time Zero" "0,1"
|
|
bitfld.long 0x0 12. "PFNZ,Pause Frame with Non-zero Pause Quantum Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "HRESP,System Bus Error" "0,1"
|
|
bitfld.long 0x0 10. "ROVR,Receive Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TCOMP,Transmit Complete" "0,1"
|
|
bitfld.long 0x0 6. "TFC,Transmit Frame Corruption Due to System Bus Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RLEX,Retry Limit Exceeded or Late Collision" "0,1"
|
|
bitfld.long 0x0 4. "TUR,Transmit Underrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TXUBR,TX Used Bit Read" "0,1"
|
|
bitfld.long 0x0 2. "RXUBR,RX Used Bit Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RCOMP,Receive Complete" "0,1"
|
|
bitfld.long 0x0 0. "MFS,Management Frame Sent" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 29. "TSUTIMCOMP,TSU Timer Comparison" "0,1"
|
|
bitfld.long 0x4 28. "WOL,Wake On LAN" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RXLPISBC,Enable RX LPI Indication" "0,1"
|
|
bitfld.long 0x4 26. "SRI,TSU Seconds Register Increment" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "PDRSFT,PDelay Response Frame Transmitted" "0,1"
|
|
bitfld.long 0x4 24. "PDRQFT,PDelay Request Frame Transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "PDRSFR,PDelay Response Frame Received" "0,1"
|
|
bitfld.long 0x4 22. "PDRQFR,PDelay Request Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "SFT,PTP Sync Frame Transmitted" "0,1"
|
|
bitfld.long 0x4 20. "DRQFT,PTP Delay Request Frame Transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "SFR,PTP Sync Frame Received" "0,1"
|
|
bitfld.long 0x4 18. "DRQFR,PTP Delay Request Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "EXINT,External Interrupt" "0,1"
|
|
bitfld.long 0x4 14. "PFTR,Pause Frame Transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "PTZ,Pause Time Zero" "0,1"
|
|
bitfld.long 0x4 12. "PFNZ,Pause Frame with Non-zero Pause Quantum Received" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "HRESP,System Bus Error" "0,1"
|
|
bitfld.long 0x4 10. "ROVR,Receive Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "TCOMP,Transmit Complete" "0,1"
|
|
bitfld.long 0x4 6. "TFC,Transmit Frame Corruption Due to System Bus Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RLEX,Retry Limit Exceeded or Late Collision" "0,1"
|
|
bitfld.long 0x4 4. "TUR,Transmit Underrun" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TXUBR,TX Used Bit Read" "0,1"
|
|
bitfld.long 0x4 2. "RXUBR,RX Used Bit Read" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RCOMP,Receive Complete" "0,1"
|
|
bitfld.long 0x4 0. "MFS,Management Frame Sent" "0,1"
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 29. "TSUTIMCOMP,TSU Timer Comparison" "0,1"
|
|
bitfld.long 0x0 28. "WOL,Wake On LAN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXLPISBC,Enable RX LPI Indication" "0,1"
|
|
bitfld.long 0x0 26. "SRI,TSU Seconds Register Increment" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "PDRSFT,PDelay Response Frame Transmitted" "0,1"
|
|
bitfld.long 0x0 24. "PDRQFT,PDelay Request Frame Transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "PDRSFR,PDelay Response Frame Received" "0,1"
|
|
bitfld.long 0x0 22. "PDRQFR,PDelay Request Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SFT,PTP Sync Frame Transmitted" "0,1"
|
|
bitfld.long 0x0 20. "DRQFT,PTP Delay Request Frame Transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "SFR,PTP Sync Frame Received" "0,1"
|
|
bitfld.long 0x0 18. "DRQFR,PTP Delay Request Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EXINT,External Interrupt" "0,1"
|
|
bitfld.long 0x0 14. "PFTR,Pause Frame Transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PTZ,Pause Time Zero" "0,1"
|
|
bitfld.long 0x0 12. "PFNZ,Pause Frame with Non-zero Pause Quantum Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "HRESP,System Bus Error" "0,1"
|
|
bitfld.long 0x0 10. "ROVR,Receive Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TCOMP,Transmit Complete" "0,1"
|
|
bitfld.long 0x0 6. "TFC,Transmit Frame Corruption Due to System Bus Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RLEX,Retry Limit Exceeded" "0,1"
|
|
bitfld.long 0x0 4. "TUR,Transmit Underrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TXUBR,TX Used Bit Read" "0,1"
|
|
bitfld.long 0x0 2. "RXUBR,RX Used Bit Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RCOMP,Receive Complete" "0,1"
|
|
bitfld.long 0x0 0. "MFS,Management Frame Sent" "0,1"
|
|
line.long 0x4 "MAN,PHY Maintenance Register"
|
|
bitfld.long 0x4 31. "WZO,Write ZERO" "0,1"
|
|
bitfld.long 0x4 30. "CLTTO,Clause 22 Operation" "0: Clause 45 operation,1: Clause 22 operation"
|
|
newline
|
|
bitfld.long 0x4 28.--29. "OP,Operation" "?,1: Write,2: Read,?"
|
|
hexmask.long.byte 0x4 23.--27. 1. "PHYA,PHY Address"
|
|
newline
|
|
hexmask.long.byte 0x4 18.--22. 1. "REGA,Register Address"
|
|
bitfld.long 0x4 16.--17. "WTN,Write Ten" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "DATA,PHY Data"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "RPQ,Receive Pause Quantum Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RPQ,Received Pause Quantum"
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "TPQ,Transmit Pause Quantum Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "P1TPQ,Priority 1 Transmit Pause Quantum"
|
|
hexmask.long.word 0x0 0.--15. 1. "TPQ,Transmit Pause Quantum"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "RJFML,RX Jumbo Frame Max Length Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "FML,Frame Max Length"
|
|
group.long 0x5C++0x7
|
|
line.long 0x0 "INTM,Interrupt Moderation Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "TXINTMOD,Transmit Interrupt Moderation"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXINTMOD,Receive Interrupt Moderation"
|
|
line.long 0x4 "SYSWT,System Wake-Up Time Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "SYSWKUPTIME,System Wake-up Time"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "HRB,Hash Register Bottom"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Hash Address"
|
|
line.long 0x4 "HRT,Hash Register Top"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,Hash Address"
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0xF8008088 ad:0xF8008090 ad:0xF8008098 ad:0xF80080A0)
|
|
tree "GMAC_SA$1"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "SAB,Specific Address 1 Bottom Register"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Specific Address 1"
|
|
line.long 0x4 "SAT,Specific Address 1 Top Register"
|
|
hexmask.long.byte 0x4 24.--29. 1. "FILTBMASK,Filter Bytes Mask"
|
|
bitfld.long 0x4 16. "FILTSORD,Filter Source or Destination MAC Address" "0: The filter is a destination address filter.,1: The filter is a source address filter."
|
|
hexmask.long.word 0x4 0.--15. 1. "ADDR,Specific Address 2"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0xF8008000
|
|
group.long 0xA8++0x3F
|
|
line.long 0x0 "TIDM1,Type ID Match 1 Register"
|
|
bitfld.long 0x0 31. "ENID1,Enable Copying of TID Matched Frames" "0: TID is not part of the comparison match.,1: TID is processed for the comparison match."
|
|
hexmask.long.word 0x0 0.--15. 1. "TID,Type ID Match 1"
|
|
line.long 0x4 "TIDM2,Type ID Match 2 Register"
|
|
bitfld.long 0x4 31. "ENID2,Enable Copying of TID Matched Frames" "0: TID is not part of the comparison match.,1: TID is processed for the comparison match."
|
|
hexmask.long.word 0x4 0.--15. 1. "TID,Type ID Match 2"
|
|
line.long 0x8 "TIDM3,Type ID Match 3 Register"
|
|
bitfld.long 0x8 31. "ENID3,Enable Copying of TID Matched Frames" "0: TID is not part of the comparison match.,1: TID is processed for the comparison match."
|
|
hexmask.long.word 0x8 0.--15. 1. "TID,Type ID Match 3"
|
|
line.long 0xC "TIDM4,Type ID Match 4 Register"
|
|
bitfld.long 0xC 31. "ENID4,Enable Copying of TID Matched Frames" "0: TID is not part of the comparison match.,1: TID is processed for the comparison match."
|
|
hexmask.long.word 0xC 0.--15. 1. "TID,Type ID Match 4"
|
|
line.long 0x10 "WOL,Wake on LAN Register"
|
|
bitfld.long 0x10 19. "MTI,Multicast Hash Event Enable" "0,1"
|
|
bitfld.long 0x10 18. "SA1,Specific Address Register 1 Event Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 17. "ARP,ARP Request Event Enable" "0,1"
|
|
bitfld.long 0x10 16. "MAG,Magic Packet Event Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x10 0.--15. 1. "IP,ARP Request IP Address"
|
|
line.long 0x14 "IPGS,IPG Stretch Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "FL,Frame Length"
|
|
line.long 0x18 "SVLAN,Stacked VLAN Register"
|
|
bitfld.long 0x18 31. "ESVLAN,Enable Stacked VLAN Processing Mode" "0: Disable the stacked VLAN Processing mode,1: Enable the stacked VLAN Processing mode"
|
|
hexmask.long.word 0x18 0.--15. 1. "VLAN_TYPE,User Defined VLAN_TYPE Field"
|
|
line.long 0x1C "TPFCP,Transmit PFC Pause Register"
|
|
hexmask.long.byte 0x1C 8.--15. 1. "PQ,Pause Quantum"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "PEV,Priority Enable Vector"
|
|
line.long 0x20 "SAMB1,Specific Address 1 Mask Bottom Register"
|
|
hexmask.long 0x20 0.--31. 1. "ADDR,Specific Address 1 Mask"
|
|
line.long 0x24 "SAMT1,Specific Address 1 Mask Top Register"
|
|
hexmask.long.word 0x24 0.--15. 1. "ADDR,Specific Address 1 Mask"
|
|
line.long 0x28 "AMRX,System Memory Address Mask for RX Data Buffer Accesses Register"
|
|
hexmask.long.byte 0x28 28.--31. 1. "MSBADDR,MSB of the Receive Data Buffer Address"
|
|
hexmask.long.byte 0x28 0.--3. 1. "MSBADDRMSK,Mask of the Receive Data Buffer Address"
|
|
line.long 0x2C "RXUDAR,PTP RX Unicast IP Destination Address Register"
|
|
hexmask.long 0x2C 0.--31. 1. "RXUDA,Receive Unicast Destination Address"
|
|
line.long 0x30 "TXUDAR,PTP TX Unicast IP Destination Address Register"
|
|
hexmask.long 0x30 0.--31. 1. "TXUDA,Transmit Unicast Destination Address"
|
|
line.long 0x34 "NSC,1588 Timer Nanosecond Comparison Register"
|
|
hexmask.long.tbyte 0x34 0.--21. 1. "NANOSEC,1588 Timer Nanosecond Comparison Value"
|
|
line.long 0x38 "SCL,1588 Timer Second Comparison Low Register"
|
|
hexmask.long 0x38 0.--31. 1. "SEC,1588 Timer Second Comparison Value"
|
|
line.long 0x3C "SCH,1588 Timer Second Comparison High Register"
|
|
hexmask.long.word 0x3C 0.--15. 1. "SEC,1588 Timer Second Comparison Value"
|
|
rgroup.long 0xE8++0xF
|
|
line.long 0x0 "EFTSH,PTP Event Frame Transmitted Seconds High Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RUD,Register Update"
|
|
line.long 0x4 "EFRSH,PTP Event Frame Received Seconds High Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RUD,Register Update"
|
|
line.long 0x8 "PEFTSH,PTP Peer Event Frame Transmitted Seconds High Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "RUD,Register Update"
|
|
line.long 0xC "PEFRSH,PTP Peer Event Frame Received Seconds High Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "RUD,Register Update"
|
|
rgroup.long 0x100++0xB7
|
|
line.long 0x0 "OTLO,Octets Transmitted Low Register"
|
|
hexmask.long 0x0 0.--31. 1. "TXO,Transmitted Octets"
|
|
line.long 0x4 "OTHI,Octets Transmitted High Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TXO,Transmitted Octets"
|
|
line.long 0x8 "FT,Frames Transmitted Register"
|
|
hexmask.long 0x8 0.--31. 1. "FTX,Frames Transmitted without Error"
|
|
line.long 0xC "BCFT,Broadcast Frames Transmitted Register"
|
|
hexmask.long 0xC 0.--31. 1. "BFTX,Broadcast Frames Transmitted without Error"
|
|
line.long 0x10 "MFT,Multicast Frames Transmitted Register"
|
|
hexmask.long 0x10 0.--31. 1. "MFTX,Multicast Frames Transmitted without Error"
|
|
line.long 0x14 "PFT,Pause Frames Transmitted Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "PFTX,Pause Frames Transmitted Register"
|
|
line.long 0x18 "BFT64,64 Byte Frames Transmitted Register"
|
|
hexmask.long 0x18 0.--31. 1. "NFTX,64 Byte Frames Transmitted without Error"
|
|
line.long 0x1C "TBFT127,65 to 127 Byte Frames Transmitted Register"
|
|
hexmask.long 0x1C 0.--31. 1. "NFTX,65 to 127 Byte Frames Transmitted without Error"
|
|
line.long 0x20 "TBFT255,128 to 255 Byte Frames Transmitted Register"
|
|
hexmask.long 0x20 0.--31. 1. "NFTX,128 to 255 Byte Frames Transmitted without Error"
|
|
line.long 0x24 "TBFT511,256 to 511 Byte Frames Transmitted Register"
|
|
hexmask.long 0x24 0.--31. 1. "NFTX,256 to 511 Byte Frames Transmitted without Error"
|
|
line.long 0x28 "TBFT1023,512 to 1023 Byte Frames Transmitted Register"
|
|
hexmask.long 0x28 0.--31. 1. "NFTX,512 to 1023 Byte Frames Transmitted without Error"
|
|
line.long 0x2C "TBFT1518,1024 to 1518 Byte Frames Transmitted Register"
|
|
hexmask.long 0x2C 0.--31. 1. "NFTX,1024 to 1518 Byte Frames Transmitted without Error"
|
|
line.long 0x30 "GTBFT1518,Greater Than 1518 Byte Frames Transmitted Register"
|
|
hexmask.long 0x30 0.--31. 1. "NFTX,Greater than 1518 Byte Frames Transmitted without Error"
|
|
line.long 0x34 "TUR,Transmit Underruns Register"
|
|
hexmask.long.word 0x34 0.--9. 1. "TXUNR,Transmit Underruns"
|
|
line.long 0x38 "SCF,Single Collision Frames Register"
|
|
hexmask.long.tbyte 0x38 0.--17. 1. "SCOL,Single Collision"
|
|
line.long 0x3C "MCF,Multiple Collision Frames Register"
|
|
hexmask.long.tbyte 0x3C 0.--17. 1. "MCOL,Multiple Collision"
|
|
line.long 0x40 "EC,Excessive Collisions Register"
|
|
hexmask.long.word 0x40 0.--9. 1. "XCOL,Excessive Collisions"
|
|
line.long 0x44 "LC,Late Collisions Register"
|
|
hexmask.long.word 0x44 0.--9. 1. "LCOL,Late Collisions"
|
|
line.long 0x48 "DTF,Deferred Transmission Frames Register"
|
|
hexmask.long.tbyte 0x48 0.--17. 1. "DEFT,Deferred Transmission"
|
|
line.long 0x4C "CSE,Carrier Sense Errors Register"
|
|
hexmask.long.word 0x4C 0.--9. 1. "CSR,Carrier Sense Error"
|
|
line.long 0x50 "ORLO,Octets Received Low Received Register"
|
|
hexmask.long 0x50 0.--31. 1. "RXO,Received Octets"
|
|
line.long 0x54 "ORHI,Octets Received High Received Register"
|
|
hexmask.long.word 0x54 0.--15. 1. "RXO,Received Octets"
|
|
line.long 0x58 "FR,Frames Received Register"
|
|
hexmask.long 0x58 0.--31. 1. "FRX,Frames Received without Error"
|
|
line.long 0x5C "BCFR,Broadcast Frames Received Register"
|
|
hexmask.long 0x5C 0.--31. 1. "BFRX,Broadcast Frames Received without Error"
|
|
line.long 0x60 "MFR,Multicast Frames Received Register"
|
|
hexmask.long 0x60 0.--31. 1. "MFRX,Multicast Frames Received without Error"
|
|
line.long 0x64 "PFR,Pause Frames Received Register"
|
|
hexmask.long.word 0x64 0.--15. 1. "PFRX,Pause Frames Received Register"
|
|
line.long 0x68 "BFR64,64 Byte Frames Received Register"
|
|
hexmask.long 0x68 0.--31. 1. "NFRX,64 Byte Frames Received without Error"
|
|
line.long 0x6C "TBFR127,65 to 127 Byte Frames Received Register"
|
|
hexmask.long 0x6C 0.--31. 1. "NFRX,65 to 127 Byte Frames Received without Error"
|
|
line.long 0x70 "TBFR255,128 to 255 Byte Frames Received Register"
|
|
hexmask.long 0x70 0.--31. 1. "NFRX,128 to 255 Byte Frames Received without Error"
|
|
line.long 0x74 "TBFR511,256 to 511 Byte Frames Received Register"
|
|
hexmask.long 0x74 0.--31. 1. "NFRX,256 to 511 Byte Frames Received without Error"
|
|
line.long 0x78 "TBFR1023,512 to 1023 Byte Frames Received Register"
|
|
hexmask.long 0x78 0.--31. 1. "NFRX,512 to 1023 Byte Frames Received without Error"
|
|
line.long 0x7C "TBFR1518,1024 to 1518 Byte Frames Received Register"
|
|
hexmask.long 0x7C 0.--31. 1. "NFRX,1024 to 1518 Byte Frames Received without Error"
|
|
line.long 0x80 "TMXBFR,1519 to Maximum Byte Frames Received Register"
|
|
hexmask.long 0x80 0.--31. 1. "NFRX,1519 to Maximum Byte Frames Received without Error"
|
|
line.long 0x84 "UFR,Undersize Frames Received Register"
|
|
hexmask.long.word 0x84 0.--9. 1. "UFRX,Undersize Frames Received"
|
|
line.long 0x88 "OFR,Oversize Frames Received Register"
|
|
hexmask.long.word 0x88 0.--9. 1. "OFRX,Oversized Frames Received"
|
|
line.long 0x8C "JR,Jabbers Received Register"
|
|
hexmask.long.word 0x8C 0.--9. 1. "JRX,Jabbers Received"
|
|
line.long 0x90 "FCSE,Frame Check Sequence Errors Register"
|
|
hexmask.long.word 0x90 0.--9. 1. "FCKR,Frame Check Sequence Errors"
|
|
line.long 0x94 "LFFE,Length Field Frame Errors Register"
|
|
hexmask.long.word 0x94 0.--9. 1. "LFER,Length Field Frame Errors"
|
|
line.long 0x98 "RSE,Receive Symbol Errors Register"
|
|
hexmask.long.word 0x98 0.--9. 1. "RXSE,Receive Symbol Errors"
|
|
line.long 0x9C "AE,Alignment Errors Register"
|
|
hexmask.long.word 0x9C 0.--9. 1. "AER,Alignment Errors"
|
|
line.long 0xA0 "RRE,Receive Resource Errors Register"
|
|
hexmask.long.tbyte 0xA0 0.--17. 1. "RXRER,Receive Resource Errors"
|
|
line.long 0xA4 "ROE,Receive Overrun Register"
|
|
hexmask.long.word 0xA4 0.--9. 1. "RXOVR,Receive Overruns"
|
|
line.long 0xA8 "IHCE,IP Header Checksum Errors Register"
|
|
hexmask.long.byte 0xA8 0.--7. 1. "HCKER,IP Header Checksum Errors"
|
|
line.long 0xAC "TCE,TCP Checksum Errors Register"
|
|
hexmask.long.byte 0xAC 0.--7. 1. "TCKER,TCP Checksum Errors"
|
|
line.long 0xB0 "UCE,UDP Checksum Errors Register"
|
|
hexmask.long.byte 0xB0 0.--7. 1. "UCKER,UDP Checksum Errors"
|
|
line.long 0xB4 "FLRXPCR,Flushed Received Packets Counter Register"
|
|
hexmask.long.word 0xB4 0.--15. 1. "COUNT,Flushed Received Packets Count (cleared on read)"
|
|
group.long 0x1BC++0x7
|
|
line.long 0x0 "TISUBN,1588 Timer Increment Sub-nanoseconds Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "LSBTIR,Lower Significant Bits of Timer Increment Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "MSBTIR,Most Significant Bits of Timer Increment Register"
|
|
line.long 0x4 "TSH,1588 Timer Seconds High Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TCS,Timer Count in Seconds"
|
|
group.long 0x1D0++0x7
|
|
line.long 0x0 "TSL,1588 Timer Seconds Low Register"
|
|
hexmask.long 0x0 0.--31. 1. "TCS,Timer Count in Seconds"
|
|
line.long 0x4 "TN,1588 Timer Nanoseconds Register"
|
|
hexmask.long 0x4 0.--29. 1. "TNS,Timer Count in Nanoseconds"
|
|
wgroup.long 0x1D8++0x3
|
|
line.long 0x0 "TA,1588 Timer Adjust Register"
|
|
bitfld.long 0x0 31. "ADJ,Adjust 1588 Timer" "0,1"
|
|
hexmask.long 0x0 0.--29. 1. "ITDT,Increment/Decrement"
|
|
group.long 0x1DC++0x3
|
|
line.long 0x0 "TI,1588 Timer Increment Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "NIT,Number of Increments"
|
|
hexmask.long.byte 0x0 8.--15. 1. "ACNS,Alternative Count Nanoseconds"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "CNS,Count Nanoseconds"
|
|
rgroup.long 0x1E0++0x1F
|
|
line.long 0x0 "EFTSL,PTP Event Frame Transmitted Seconds Low Register"
|
|
hexmask.long 0x0 0.--31. 1. "RUD,Register Update"
|
|
line.long 0x4 "EFTN,PTP Event Frame Transmitted Nanoseconds Register"
|
|
hexmask.long 0x4 0.--29. 1. "RUD,Register Update"
|
|
line.long 0x8 "EFRSL,PTP Event Frame Received Seconds Low Register"
|
|
hexmask.long 0x8 0.--31. 1. "RUD,Register Update"
|
|
line.long 0xC "EFRN,PTP Event Frame Received Nanoseconds Register"
|
|
hexmask.long 0xC 0.--29. 1. "RUD,Register Update"
|
|
line.long 0x10 "PEFTSL,PTP Peer Event Frame Transmitted Seconds Low Register"
|
|
hexmask.long 0x10 0.--31. 1. "RUD,Register Update"
|
|
line.long 0x14 "PEFTN,PTP Peer Event Frame Transmitted Nanoseconds Register"
|
|
hexmask.long 0x14 0.--29. 1. "RUD,Register Update"
|
|
line.long 0x18 "PEFRSL,PTP Peer Event Frame Received Seconds Low Register"
|
|
hexmask.long 0x18 0.--31. 1. "RUD,Register Update"
|
|
line.long 0x1C "PEFRN,PTP Peer Event Frame Received Nanoseconds Register"
|
|
hexmask.long 0x1C 0.--29. 1. "RUD,Register Update"
|
|
rgroup.long 0x270++0xF
|
|
line.long 0x0 "RXLPI,Received LPI Transitions"
|
|
hexmask.long.word 0x0 0.--15. 1. "COUNT,Count of Received LPI transitions (cleared on read)"
|
|
line.long 0x4 "RXLPITIME,Received LPI Time"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "LPITIME,Time in LPI (cleared on read)"
|
|
line.long 0x8 "TXLPI,Transmit LPI Transitions"
|
|
hexmask.long.word 0x8 0.--15. 1. "COUNT,Count of LPI transitions (cleared on read)"
|
|
line.long 0xC "TXLPITIME,Transmit LPI Time"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "LPITIME,Time in LPI (cleared on read)"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x400)++0x3
|
|
line.long 0x0 "ISRPQ[$1],Interrupt Status Register Priority Queue (index = 1)"
|
|
bitfld.long 0x0 11. "HRESP,System Bus Error" "0,1"
|
|
bitfld.long 0x0 7. "TCOMP,Transmit Complete" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TFC,Transmit Frame Corruption Due to System Bus Error" "0,1"
|
|
bitfld.long 0x0 5. "RLEX,Retry Limit Exceeded or Late Collision" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXUBR,RX Used Bit Read" "0,1"
|
|
bitfld.long 0x0 1. "RCOMP,Receive Complete" "0,1"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x440)++0x3
|
|
line.long 0x0 "TBQBAPQ[$1],Transmit Buffer Queue Base Address Register Priority Queue (index = 1)"
|
|
hexmask.long 0x0 2.--31. 1. "TXBQBA,Transmit Buffer Queue Base Address"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x480)++0x3
|
|
line.long 0x0 "RBQBAPQ[$1],Receive Buffer Queue Base Address Register Priority Queue (index = 1)"
|
|
hexmask.long 0x0 2.--31. 1. "RXBQBA,Receive Buffer Queue Base Address"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x4A0)++0x3
|
|
line.long 0x0 "RBSRPQ[$1],Receive Buffer Size Register Priority Queue (index = 1)"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RBS,Receive Buffer Size"
|
|
repeat.end
|
|
group.long 0x4BC++0x1B
|
|
line.long 0x0 "CBSCR,Credit-Based Shaping Control Register"
|
|
bitfld.long 0x0 1. "QBE,Queue B CBS Enable" "0: Credit-based shaping on the highest priority..,1: Credit-based shaping on the highest priority.."
|
|
bitfld.long 0x0 0. "QAE,Queue A CBS Enable" "0: Credit-based shaping on the second highest..,1: Credit-based shaping on the second highest.."
|
|
line.long 0x4 "CBSISQA,Credit-Based Shaping IdleSlope Register for Queue A"
|
|
hexmask.long 0x4 0.--31. 1. "IS,IdleSlope"
|
|
line.long 0x8 "CBSISQB,Credit-Based Shaping IdleSlope Register for Queue B"
|
|
hexmask.long 0x8 0.--31. 1. "IS,IdleSlope"
|
|
line.long 0xC "TQUBA,32 MSB Transmit Buffer Descriptor Queue Base Address Register"
|
|
hexmask.long 0xC 0.--31. 1. "TQUBA,Transmit Queue Upper Buffer Address"
|
|
line.long 0x10 "TXBDCTRL,Transmit Buffer Data Control Register"
|
|
bitfld.long 0x10 4.--5. "TSMODE,Transmit Descriptor Timestamp Insertion Mode" "0: Timestamp insertion disable.,1: Timestamp inserted for PTP Event Frames only.,2: Timestamp inserted for All PTP Frames only.,3: Timestamp inserted for All Frames."
|
|
line.long 0x14 "RXBDCTRL,Receive Buffer Data Control Register"
|
|
bitfld.long 0x14 4.--5. "TSMODE,Receive Descriptor Timestamp Insertion Mode" "0: Timestamp insertion disable.,1: Timestamp inserted for PTP Event Frames only.,2: Timestamp inserted for All PTP Frames only.,3: Timestamp inserted for All Frames."
|
|
line.long 0x18 "RQUBA,32 MSB Receive Buffer Descriptor Queue Base Address Register"
|
|
hexmask.long 0x18 0.--31. 1. "RQUBA,Receive Queue Upper Buffer Address"
|
|
group.long 0x500++0x3
|
|
line.long 0x0 "ST1RPQ,Screening Type 1 Register Priority Queue (index = 0)"
|
|
bitfld.long 0x0 29. "UDPE,UDP Port Match Enable" "0,1"
|
|
bitfld.long 0x0 28. "DSTCE,Differentiated Services or Traffic Class Match Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 12.--27. 1. "UDPM,UDP Port Match"
|
|
hexmask.long.byte 0x0 4.--11. 1. "DSTCM,Differentiated Services or Traffic Class Match"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "QNB,Queue Number (0-2)" "0,1,2,3,4,5,6,7"
|
|
group.long 0x540++0x3
|
|
line.long 0x0 "ST2RPQ,Screening Type 2 Register Priority Queue (index = 0)"
|
|
bitfld.long 0x0 30. "COMPCE,Compare C Enable" "0: Comparison via the register designated by index..,1: Comparison via the register designated by index.."
|
|
hexmask.long.byte 0x0 25.--29. 1. "COMPC,Index of Screening Type 2 Compare Word 0/Word 1 register"
|
|
newline
|
|
bitfld.long 0x0 24. "COMPBE,Compare B Enable" "0: Comparison via the register designated by index..,1: Comparison via the register designated by index.."
|
|
hexmask.long.byte 0x0 19.--23. 1. "COMPB,Index of Screening Type 2 Compare Word 0/Word 1 register"
|
|
newline
|
|
bitfld.long 0x0 18. "COMPAE,Compare A Enable" "0: Comparison via the register designated by index..,1: Comparison via the register designated by index.."
|
|
hexmask.long.byte 0x0 13.--17. 1. "COMPA,Index of Screening Type 2 Compare Word 0/Word 1 register"
|
|
newline
|
|
bitfld.long 0x0 12. "ETHE,EtherType Enable" "0: EtherType match with bits 15:0 in the register..,1: EtherType match with bits 15:0 in the register.."
|
|
bitfld.long 0x0 9.--11. "I2ETH,Index of Screening Type 2 EtherType register" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 8. "VLANE,VLAN Enable" "0: VLAN match is disabled.,1: VLAN match is enabled."
|
|
bitfld.long 0x0 4.--6. "VLANP,VLAN Priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "QNB,Queue Number (0-2)" "0,1,2,3,4,5,6,7"
|
|
group.long 0x580++0x3
|
|
line.long 0x0 "TSCTL,Transmit Schedule Control Register"
|
|
bitfld.long 0x0 10.--11. "TXSQ5,Transmit Schedule for Qx" "0: Fixed Priority,1: CBS Enabled only valid for top two enabled..,2: DWRR enabled,3: ETS enabled"
|
|
bitfld.long 0x0 8.--9. "TXSQ4,Transmit Schedule for Qx" "0: Fixed Priority,1: CBS Enabled only valid for top two enabled..,2: DWRR enabled,3: ETS enabled"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "TXSQ3,Transmit Schedule for Qx" "0: Fixed Priority,1: CBS Enabled only valid for top two enabled..,2: DWRR enabled,3: ETS enabled"
|
|
bitfld.long 0x0 4.--5. "TXSQ2,Transmit Schedule for Qx" "0: Fixed Priority,1: CBS Enabled only valid for top two enabled..,2: DWRR enabled,3: ETS enabled"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "TXSQ1,Transmit Schedule for Qx" "0: Fixed Priority,1: CBS Enabled only valid for top two enabled..,2: DWRR enabled,3: ETS enabled"
|
|
bitfld.long 0x0 0.--1. "TXSQ0,Transmit Schedule for Qx" "0: Fixed Priority,1: CBS Enabled only valid for top two enabled..,2: DWRR enabled,3: ETS enabled"
|
|
group.long 0x590++0x3
|
|
line.long 0x0 "TQBWRL0,Transmit Queue Bandwidth Rate Limit 0 Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ALLOCQ3,DWRR Weighting or ETS Bandwidth Allocation for Qx"
|
|
hexmask.long.byte 0x0 16.--23. 1. "ALLOCQ2,DWRR Weighting or ETS Bandwidth Allocation for Qx"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "ALLOCQ1,DWRR Weighting or ETS Bandwidth Allocation for Qx"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ALLOCQ0,DWRR Weighting or ETS Bandwidth Allocation for Qx"
|
|
group.long 0x5A0++0x3
|
|
line.long 0x0 "TQSA,Transmit Queue Segment Allocation Register"
|
|
bitfld.long 0x0 20.--22. "SEGALLOCQ5,Segment Allocation for Qx" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--18. "SEGALLOCQ4,Segment Allocation for Qx" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "SEGALLOCQ3,Segment Allocation for Qx" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 8.--10. "SEGALLOCQ2,Segment Allocation for Qx" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "SEGALLOCQ1,Segment Allocation for Qx" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--2. "SEGALLOCQ0,Segment Allocation for Qx" "0,1,2,3,4,5,6,7"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x600)++0x3
|
|
line.long 0x0 "IERPQ[$1],Interrupt Enable Register Priority Queue (index = 1)"
|
|
bitfld.long 0x0 11. "HRESP,System Bus Error" "0,1"
|
|
bitfld.long 0x0 7. "TCOMP,Transmit Complete" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TFC,Transmit Frame Corruption Due to System Bus Error" "0,1"
|
|
bitfld.long 0x0 5. "RLEX,Retry Limit Exceeded or Late Collision" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXUBR,RX Used Bit Read" "0,1"
|
|
bitfld.long 0x0 1. "RCOMP,Receive Complete" "0,1"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x620)++0x3
|
|
line.long 0x0 "IDRPQ[$1],Interrupt Disable Register Priority Queue (index = 1)"
|
|
bitfld.long 0x0 11. "HRESP,System Bus Error" "0,1"
|
|
bitfld.long 0x0 7. "TCOMP,Transmit Complete" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TFC,Transmit Frame Corruption Due to System Bus Error" "0,1"
|
|
bitfld.long 0x0 5. "RLEX,Retry Limit Exceeded or Late Collision" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXUBR,RX Used Bit Read" "0,1"
|
|
bitfld.long 0x0 1. "RCOMP,Receive Complete" "0,1"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x640)++0x3
|
|
line.long 0x0 "IMRPQ[$1],Interrupt Mask Register Priority Queue (index = 1)"
|
|
bitfld.long 0x0 11. "HRESP,System Bus Error" "0,1"
|
|
bitfld.long 0x0 7. "TCOMP,Transmit Complete" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "AHB,Transmit Frame Corruption Due to System Bus Error" "0,1"
|
|
bitfld.long 0x0 5. "RLEX,Retry Limit Exceeded or Late Collision" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXUBR,RX Used Bit Read" "0,1"
|
|
bitfld.long 0x0 1. "RCOMP,Receive Complete" "0,1"
|
|
repeat.end
|
|
group.long 0x6E0++0x3
|
|
line.long 0x0 "ST2ER,Screening Type 2 Ethertype Register (index = 0)"
|
|
hexmask.long.word 0x0 0.--15. 1. "COMPVAL,Ethertype Compare Value"
|
|
tree "GMAC_ST2CW"
|
|
base ad:0xF8008700
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "ST2CW0,Screening Type 2 Compare Word 0 Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "COMPVAL,Compare Value"
|
|
hexmask.long.word 0x0 0.--15. 1. "MASKVAL,Mask Value"
|
|
line.long 0x4 "ST2CW1,Screening Type 2 Compare Word 1 Register"
|
|
bitfld.long 0x4 9. "DISMASK,Disable Mask" "0: GMAC_ST2CW0R contains a 2-byte compare value..,1: GMAC_ST2CW0R contains a 4-byte compare value."
|
|
bitfld.long 0x4 7.--8. "OFFSSTRT,Ethernet Frame Offset Start" "0: Offset from the start of the frame,1: Offset from the byte after the EtherType field,2: Offset from the byte after the IP header field,3: Offset from the byte after the TCP/UDP header.."
|
|
hexmask.long.byte 0x4 0.--6. 1. "OFFSVAL,Offset Value in Bytes"
|
|
tree.end
|
|
tree.end
|
|
tree "HSMC (Static Memory Controller)"
|
|
base ad:0xF8014000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "HSMC_CFG,NFC Configuration Register"
|
|
hexmask.long.byte 0x0 24.--30. 1. "NFCSPARESIZE,NAND Flash Spare Area Size Retrieved by the Host Controller"
|
|
bitfld.long 0x0 20.--22. "DTOMUL,Data Timeout Multiplier" "0: DTOCYC,1: DTOCYC x 16,2: DTOCYC x 128,3: DTOCYC x 256,4: DTOCYC x 1024,5: DTOCYC x 4096,6: DTOCYC x 65536,7: DTOCYC x 1048576"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "DTOCYC,Data Timeout Cycle Number"
|
|
bitfld.long 0x0 13. "RBEDGE,Ready/Busy Signal Edge Detection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "EDGECTRL,Rising/Falling Edge Detection Control" "0,1"
|
|
bitfld.long 0x0 9. "RSPARE,Read Spare Area" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "WSPARE,Write Spare Area" "0,1"
|
|
bitfld.long 0x0 0.--2. "PAGESIZE,Page Size of the NAND Flash Device" "0: Main area 512 bytes,1: Main area 1024 bytes,2: Main area 2048 bytes,3: Main area 4096 bytes,4: Main area 8192 bytes,?,?,?"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "HSMC_CTRL,NFC Control Register"
|
|
bitfld.long 0x0 1. "NFCDIS,NAND Flash Controller Disable" "0,1"
|
|
bitfld.long 0x0 0. "NFCEN,NAND Flash Controller Enable" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "HSMC_SR,NFC Status Register"
|
|
bitfld.long 0x0 24. "RB_EDGE0,Ready/Busy Line 0 Edge Detected" "0,1"
|
|
bitfld.long 0x0 23. "NFCASE,NFC Access Size Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "AWB,Accessing While Busy" "0,1"
|
|
bitfld.long 0x0 21. "UNDEF,Undefined Area Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "DTOE,Data Timeout Error" "0,1"
|
|
bitfld.long 0x0 17. "CMDDONE,Command Done" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "XFRDONE,NFC Data Transfer Terminated" "0,1"
|
|
bitfld.long 0x0 12.--14. "NFCSID,NFC Chip Select ID (this field cannot be reset)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 11. "NFCWR,NFC Write/Read Operation (this field cannot be reset)" "0,1"
|
|
bitfld.long 0x0 8. "NFCBUSY,NFC Busy (this field cannot be reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RB_FALL,Selected Ready Busy Falling Edge Detected" "0,1"
|
|
bitfld.long 0x0 4. "RB_RISE,Selected Ready Busy Rising Edge Detected" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SMCSTS,NAND Flash Controller Status (this field cannot be reset)" "0,1"
|
|
wgroup.long 0xC++0x7
|
|
line.long 0x0 "HSMC_IER,NFC Interrupt Enable Register"
|
|
bitfld.long 0x0 24. "RB_EDGE0,Ready/Busy Line 0 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 23. "NFCASE,NFC Access Size Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "AWB,Accessing While Busy Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 21. "UNDEF,Undefined Area Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "DTOE,Data Timeout Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 17. "CMDDONE,Command Done Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "XFRDONE,Transfer Done Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 5. "RB_FALL,Ready Busy Falling Edge Detection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RB_RISE,Ready Busy Rising Edge Detection Interrupt Enable" "0,1"
|
|
line.long 0x4 "HSMC_IDR,NFC Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "RB_EDGE0,Ready/Busy Line 0 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 23. "NFCASE,NFC Access Size Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "AWB,Accessing While Busy Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 21. "UNDEF,Undefined Area Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "DTOE,Data Timeout Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 17. "CMDDONE,Command Done Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "XFRDONE,Transfer Done Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 5. "RB_FALL,Ready Busy Falling Edge Detection Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RB_RISE,Ready Busy Rising Edge Detection Interrupt Disable" "0,1"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "HSMC_IMR,NFC Interrupt Mask Register"
|
|
bitfld.long 0x0 24. "RB_EDGE0,Ready/Busy Line 0 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 23. "NFCASE,NFC Access Size Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "AWB,Accessing While Busy Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 21. "UNDEF,Undefined Area Access Interrupt Mask5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "DTOE,Data Timeout Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 17. "CMDDONE,Command Done Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "XFRDONE,Transfer Done Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "RB_FALL,Ready Busy Falling Edge Detection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RB_RISE,Ready Busy Rising Edge Detection Interrupt Mask" "0,1"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "HSMC_ADDR,NFC Address Cycle Zero Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ADDR_CYCLE0,NAND Flash Array Address Cycle 0"
|
|
line.long 0x4 "HSMC_BANK,Bank Address Register"
|
|
bitfld.long 0x4 0. "BANK,Bank Identifier" "0,1"
|
|
group.long 0x70++0xF
|
|
line.long 0x0 "HSMC_PMECCFG,PMECC Configuration Register"
|
|
bitfld.long 0x0 20. "AUTO,Automatic Mode Enable" "0,1"
|
|
bitfld.long 0x0 16. "SPAREEN,Spare Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "NANDWR,NAND Write Access" "0,1"
|
|
bitfld.long 0x0 8.--9. "PAGESIZE,Number of Sectors in the Page" "0: 1 sector for main area (512 or 1024 bytes),1: 2 sectors for main area (1024 or 2048 bytes),2: 4 sectors for main area (2048 or 4096 bytes),3: 8 sectors for main area (4096 or 8192 bytes)"
|
|
newline
|
|
bitfld.long 0x0 4. "SECTORSZ,Sector Size" "0: Use 512 Byte Sector in ECC Computation,1: Use 1024 Byte Sector in ECC Computation"
|
|
bitfld.long 0x0 0.--2. "BCH_ERR,Error Correcting Capability" "0: 2 errors,1: 4 errors,2: 8 errors,3: 12 errors,4: 24 errors,5: 32 errors,?,?"
|
|
line.long 0x4 "HSMC_PMECCSAREA,PMECC Spare Area Size Register"
|
|
hexmask.long.word 0x4 0.--8. 1. "SPARESIZE,Spare Area Size"
|
|
line.long 0x8 "HSMC_PMECCSADDR,PMECC Start Address Register"
|
|
hexmask.long.word 0x8 0.--8. 1. "STARTADDR,ECC Area Start Address"
|
|
line.long 0xC "HSMC_PMECCEADDR,PMECC End Address Register"
|
|
hexmask.long.word 0xC 0.--8. 1. "ENDADDR,ECC Area End Address"
|
|
wgroup.long 0x84++0x3
|
|
line.long 0x0 "HSMC_PMECCTRL,PMECC Control Register"
|
|
bitfld.long 0x0 5. "DISABLE,PMECC Enable" "0,1"
|
|
bitfld.long 0x0 4. "ENABLE,PMECC Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "USER,Start a User Mode Phase" "0,1"
|
|
bitfld.long 0x0 1. "DATA,Start a Data Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RST,Reset the PMECC Module" "0,1"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "HSMC_PMECCSR,PMECC Status Register"
|
|
bitfld.long 0x0 4. "ENABLE,PMECC Enable bit" "0,1"
|
|
bitfld.long 0x0 0. "BUSY,The kernel of the PMECC is busy" "0,1"
|
|
wgroup.long 0x8C++0x7
|
|
line.long 0x0 "HSMC_PMECCIER,PMECC Interrupt Enable register"
|
|
bitfld.long 0x0 0. "ERRIE,Error Interrupt Enable" "0,1"
|
|
line.long 0x4 "HSMC_PMECCIDR,PMECC Interrupt Disable Register"
|
|
bitfld.long 0x4 0. "ERRID,Error Interrupt Disable" "0,1"
|
|
rgroup.long 0x94++0x7
|
|
line.long 0x0 "HSMC_PMECCIMR,PMECC Interrupt Mask Register"
|
|
bitfld.long 0x0 0. "ERRIM,Error Interrupt Mask" "0,1"
|
|
line.long 0x4 "HSMC_PMECCISR,PMECC Interrupt Status Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "ERRIS,Error Interrupt Status Register"
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0xF80140B0 ad:0xF80140F0 ad:0xF8014130 ad:0xF8014170 ad:0xF80141B0 ad:0xF80141F0 ad:0xF8014230 ad:0xF8014270)
|
|
tree "SMC_PMECC[$1]"
|
|
base $2
|
|
repeat 14. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "HSMC_PMECC[$1],PMECC Redundancy 0 Register (sec_num = 0)"
|
|
hexmask.long 0x0 0.--31. 1. "ECC,BCH Redundancy"
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0xF80142B0 ad:0xF80142F0 ad:0xF8014330 ad:0xF8014370 ad:0xF80143B0 ad:0xF80143F0 ad:0xF8014430 ad:0xF8014470)
|
|
tree "SMC_REM[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3F
|
|
line.long 0x0 "HSMC_REM0_,PMECC Remainder 0 Register (sec_num = 0)"
|
|
hexmask.long.word 0x0 16.--29. 1. "REM2NP3,BCH Remainder 2 * N + 3"
|
|
hexmask.long.word 0x0 0.--13. 1. "REM2NP1,BCH Remainder 2 * N + 1"
|
|
line.long 0x4 "HSMC_REM1_,PMECC Remainder 1 Register (sec_num = 0)"
|
|
hexmask.long.word 0x4 16.--29. 1. "REM2NP3,BCH Remainder 2 * N + 3"
|
|
hexmask.long.word 0x4 0.--13. 1. "REM2NP1,BCH Remainder 2 * N + 1"
|
|
line.long 0x8 "HSMC_REM2_,PMECC Remainder 2 Register (sec_num = 0)"
|
|
hexmask.long.word 0x8 16.--29. 1. "REM2NP3,BCH Remainder 2 * N + 3"
|
|
hexmask.long.word 0x8 0.--13. 1. "REM2NP1,BCH Remainder 2 * N + 1"
|
|
line.long 0xC "HSMC_REM3_,PMECC Remainder 3 Register (sec_num = 0)"
|
|
hexmask.long.word 0xC 16.--29. 1. "REM2NP3,BCH Remainder 2 * N + 3"
|
|
hexmask.long.word 0xC 0.--13. 1. "REM2NP1,BCH Remainder 2 * N + 1"
|
|
line.long 0x10 "HSMC_REM4_,PMECC Remainder 4 Register (sec_num = 0)"
|
|
hexmask.long.word 0x10 16.--29. 1. "REM2NP3,BCH Remainder 2 * N + 3"
|
|
hexmask.long.word 0x10 0.--13. 1. "REM2NP1,BCH Remainder 2 * N + 1"
|
|
line.long 0x14 "HSMC_REM5_,PMECC Remainder 5 Register (sec_num = 0)"
|
|
hexmask.long.word 0x14 16.--29. 1. "REM2NP3,BCH Remainder 2 * N + 3"
|
|
hexmask.long.word 0x14 0.--13. 1. "REM2NP1,BCH Remainder 2 * N + 1"
|
|
line.long 0x18 "HSMC_REM6_,PMECC Remainder 6 Register (sec_num = 0)"
|
|
hexmask.long.word 0x18 16.--29. 1. "REM2NP3,BCH Remainder 2 * N + 3"
|
|
hexmask.long.word 0x18 0.--13. 1. "REM2NP1,BCH Remainder 2 * N + 1"
|
|
line.long 0x1C "HSMC_REM7_,PMECC Remainder 7 Register (sec_num = 0)"
|
|
hexmask.long.word 0x1C 16.--29. 1. "REM2NP3,BCH Remainder 2 * N + 3"
|
|
hexmask.long.word 0x1C 0.--13. 1. "REM2NP1,BCH Remainder 2 * N + 1"
|
|
line.long 0x20 "HSMC_REM8_,PMECC Remainder 8 Register (sec_num = 0)"
|
|
hexmask.long.word 0x20 16.--29. 1. "REM2NP3,BCH Remainder 2 * N + 3"
|
|
hexmask.long.word 0x20 0.--13. 1. "REM2NP1,BCH Remainder 2 * N + 1"
|
|
line.long 0x24 "HSMC_REM9_,PMECC Remainder 9 Register (sec_num = 0)"
|
|
hexmask.long.word 0x24 16.--29. 1. "REM2NP3,BCH Remainder 2 * N + 3"
|
|
hexmask.long.word 0x24 0.--13. 1. "REM2NP1,BCH Remainder 2 * N + 1"
|
|
line.long 0x28 "HSMC_REM10_,PMECC Remainder 10 Register (sec_num = 0)"
|
|
hexmask.long.word 0x28 16.--29. 1. "REM2NP3,BCH Remainder 2 * N + 3"
|
|
hexmask.long.word 0x28 0.--13. 1. "REM2NP1,BCH Remainder 2 * N + 1"
|
|
line.long 0x2C "HSMC_REM11_,PMECC Remainder 11 Register (sec_num = 0)"
|
|
hexmask.long.word 0x2C 16.--29. 1. "REM2NP3,BCH Remainder 2 * N + 3"
|
|
hexmask.long.word 0x2C 0.--13. 1. "REM2NP1,BCH Remainder 2 * N + 1"
|
|
line.long 0x30 "HSMC_REM12_,PMECC Remainder 12 Register (sec_num = 0)"
|
|
hexmask.long.word 0x30 16.--29. 1. "REM2NP3,BCH Remainder 2 * N + 3"
|
|
hexmask.long.word 0x30 0.--13. 1. "REM2NP1,BCH Remainder 2 * N + 1"
|
|
line.long 0x34 "HSMC_REM13_,PMECC Remainder 13 Register (sec_num = 0)"
|
|
hexmask.long.word 0x34 16.--29. 1. "REM2NP3,BCH Remainder 2 * N + 3"
|
|
hexmask.long.word 0x34 0.--13. 1. "REM2NP1,BCH Remainder 2 * N + 1"
|
|
line.long 0x38 "HSMC_REM14_,PMECC Remainder 14 Register (sec_num = 0)"
|
|
hexmask.long.word 0x38 16.--29. 1. "REM2NP3,BCH Remainder 2 * N + 3"
|
|
hexmask.long.word 0x38 0.--13. 1. "REM2NP1,BCH Remainder 2 * N + 1"
|
|
line.long 0x3C "HSMC_REM15_,PMECC Remainder 15 Register (sec_num = 0)"
|
|
hexmask.long.word 0x3C 16.--29. 1. "REM2NP3,BCH Remainder 2 * N + 3"
|
|
hexmask.long.word 0x3C 0.--13. 1. "REM2NP1,BCH Remainder 2 * N + 1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0xF8014000
|
|
group.long 0x500++0x3
|
|
line.long 0x0 "HSMC_ELCFG,PMECC Error Location Configuration Register"
|
|
hexmask.long.byte 0x0 16.--20. 1. "ERRNUM,Number of Errors"
|
|
bitfld.long 0x0 0. "SECTORSZ,Sector Size" "0: Use 512 Byte Sector in Location Computation,1: Use 1024 Byte Sector in Location Computation"
|
|
rgroup.long 0x504++0x3
|
|
line.long 0x0 "HSMC_ELPRIM,PMECC Error Location Primitive Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "PRIMITIV,Primitive Polynomial"
|
|
wgroup.long 0x508++0x7
|
|
line.long 0x0 "HSMC_ELEN,PMECC Error Location Enable Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "ENINIT,Error Location Enable"
|
|
line.long 0x4 "HSMC_ELDIS,PMECC Error Location Disable Register"
|
|
bitfld.long 0x4 0. "DIS,Disable Error Location Engine" "0,1"
|
|
rgroup.long 0x510++0x3
|
|
line.long 0x0 "HSMC_ELSR,PMECC Error Location Status Register"
|
|
bitfld.long 0x0 0. "BUSY,Error Location Engine Busy" "0,1"
|
|
wgroup.long 0x514++0x7
|
|
line.long 0x0 "HSMC_ELIER,PMECC Error Location Interrupt Enable register"
|
|
bitfld.long 0x0 0. "DONE,Computation Terminated Interrupt Enable" "0,1"
|
|
line.long 0x4 "HSMC_ELIDR,PMECC Error Location Interrupt Disable Register"
|
|
bitfld.long 0x4 0. "DONE,Computation Terminated Interrupt Disable" "0,1"
|
|
rgroup.long 0x51C++0x7
|
|
line.long 0x0 "HSMC_ELIMR,PMECC Error Location Interrupt Mask Register"
|
|
bitfld.long 0x0 0. "DONE,Computation Terminated Interrupt Mask" "0,1"
|
|
line.long 0x4 "HSMC_ELISR,PMECC Error Location Interrupt Status Register"
|
|
hexmask.long.byte 0x4 8.--13. 1. "ERR_CNT,Error Counter value"
|
|
bitfld.long 0x4 0. "DONE,Computation Terminated Interrupt Status" "0,1"
|
|
rgroup.long 0x528++0x3
|
|
line.long 0x0 "HSMC_SIGMA0,PMECC Error Location SIGMA 0 Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "SIGMA0,Coefficient of degree 0 in the SIGMA polynomial"
|
|
group.long 0x52C++0x7F
|
|
line.long 0x0 "HSMC_SIGMA1,PMECC Error Location SIGMA 1 Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "SIGMA1,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x4 "HSMC_SIGMA2,PMECC Error Location SIGMA 2 Register"
|
|
hexmask.long.word 0x4 0.--13. 1. "SIGMA2,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x8 "HSMC_SIGMA3,PMECC Error Location SIGMA 3 Register"
|
|
hexmask.long.word 0x8 0.--13. 1. "SIGMA3,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0xC "HSMC_SIGMA4,PMECC Error Location SIGMA 4 Register"
|
|
hexmask.long.word 0xC 0.--13. 1. "SIGMA4,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x10 "HSMC_SIGMA5,PMECC Error Location SIGMA 5 Register"
|
|
hexmask.long.word 0x10 0.--13. 1. "SIGMA5,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x14 "HSMC_SIGMA6,PMECC Error Location SIGMA 6 Register"
|
|
hexmask.long.word 0x14 0.--13. 1. "SIGMA6,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x18 "HSMC_SIGMA7,PMECC Error Location SIGMA 7 Register"
|
|
hexmask.long.word 0x18 0.--13. 1. "SIGMA7,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x1C "HSMC_SIGMA8,PMECC Error Location SIGMA 8 Register"
|
|
hexmask.long.word 0x1C 0.--13. 1. "SIGMA8,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x20 "HSMC_SIGMA9,PMECC Error Location SIGMA 9 Register"
|
|
hexmask.long.word 0x20 0.--13. 1. "SIGMA9,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x24 "HSMC_SIGMA10,PMECC Error Location SIGMA 10 Register"
|
|
hexmask.long.word 0x24 0.--13. 1. "SIGMA10,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x28 "HSMC_SIGMA11,PMECC Error Location SIGMA 11 Register"
|
|
hexmask.long.word 0x28 0.--13. 1. "SIGMA11,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x2C "HSMC_SIGMA12,PMECC Error Location SIGMA 12 Register"
|
|
hexmask.long.word 0x2C 0.--13. 1. "SIGMA12,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x30 "HSMC_SIGMA13,PMECC Error Location SIGMA 13 Register"
|
|
hexmask.long.word 0x30 0.--13. 1. "SIGMA13,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x34 "HSMC_SIGMA14,PMECC Error Location SIGMA 14 Register"
|
|
hexmask.long.word 0x34 0.--13. 1. "SIGMA14,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x38 "HSMC_SIGMA15,PMECC Error Location SIGMA 15 Register"
|
|
hexmask.long.word 0x38 0.--13. 1. "SIGMA15,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x3C "HSMC_SIGMA16,PMECC Error Location SIGMA 16 Register"
|
|
hexmask.long.word 0x3C 0.--13. 1. "SIGMA16,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x40 "HSMC_SIGMA17,PMECC Error Location SIGMA 17 Register"
|
|
hexmask.long.word 0x40 0.--13. 1. "SIGMA17,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x44 "HSMC_SIGMA18,PMECC Error Location SIGMA 18 Register"
|
|
hexmask.long.word 0x44 0.--13. 1. "SIGMA18,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x48 "HSMC_SIGMA19,PMECC Error Location SIGMA 19 Register"
|
|
hexmask.long.word 0x48 0.--13. 1. "SIGMA19,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x4C "HSMC_SIGMA20,PMECC Error Location SIGMA 20 Register"
|
|
hexmask.long.word 0x4C 0.--13. 1. "SIGMA20,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x50 "HSMC_SIGMA21,PMECC Error Location SIGMA 21 Register"
|
|
hexmask.long.word 0x50 0.--13. 1. "SIGMA21,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x54 "HSMC_SIGMA22,PMECC Error Location SIGMA 22 Register"
|
|
hexmask.long.word 0x54 0.--13. 1. "SIGMA22,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x58 "HSMC_SIGMA23,PMECC Error Location SIGMA 23 Register"
|
|
hexmask.long.word 0x58 0.--13. 1. "SIGMA23,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x5C "HSMC_SIGMA24,PMECC Error Location SIGMA 24 Register"
|
|
hexmask.long.word 0x5C 0.--13. 1. "SIGMA24,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x60 "HSMC_SIGMA25,PMECC Error Location SIGMA 25 Register"
|
|
hexmask.long.word 0x60 0.--13. 1. "SIGMA25,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x64 "HSMC_SIGMA26,PMECC Error Location SIGMA 26 Register"
|
|
hexmask.long.word 0x64 0.--13. 1. "SIGMA26,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x68 "HSMC_SIGMA27,PMECC Error Location SIGMA 27 Register"
|
|
hexmask.long.word 0x68 0.--13. 1. "SIGMA27,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x6C "HSMC_SIGMA28,PMECC Error Location SIGMA 28 Register"
|
|
hexmask.long.word 0x6C 0.--13. 1. "SIGMA28,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x70 "HSMC_SIGMA29,PMECC Error Location SIGMA 29 Register"
|
|
hexmask.long.word 0x70 0.--13. 1. "SIGMA29,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x74 "HSMC_SIGMA30,PMECC Error Location SIGMA 30 Register"
|
|
hexmask.long.word 0x74 0.--13. 1. "SIGMA30,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x78 "HSMC_SIGMA31,PMECC Error Location SIGMA 31 Register"
|
|
hexmask.long.word 0x78 0.--13. 1. "SIGMA31,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x7C "HSMC_SIGMA32,PMECC Error Location SIGMA 32 Register"
|
|
hexmask.long.word 0x7C 0.--13. 1. "SIGMA32,Coefficient of degree x in the SIGMA polynomial"
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x5AC)++0x3
|
|
line.long 0x0 "HSMC_ERRLOC[$1],PMECC Error Location 0 Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "ERRLOCN,Error Position within the Set {sector area spare area}"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0xF8014700 ad:0xF8014714 ad:0xF8014728 ad:0xF801473C)
|
|
tree "SMC_CS_NUMBER[$1]"
|
|
base $2
|
|
group.long ($2)++0x13
|
|
line.long 0x0 "HSMC_SETUP,Setup Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "NCS_RD_SETUP,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x0 16.--21. 1. "NRD_SETUP,NRD Setup Length"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "NCS_WR_SETUP,NCS Setup Length in Write Access"
|
|
hexmask.long.byte 0x0 0.--5. 1. "NWE_SETUP,NWE Setup Length"
|
|
line.long 0x4 "HSMC_PULSE,Pulse Register"
|
|
hexmask.long.byte 0x4 24.--30. 1. "NCS_RD_PULSE,NCS Pulse Length in READ Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. "NRD_PULSE,NRD Pulse Length"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--14. 1. "NCS_WR_PULSE,NCS Pulse Length in WRITE Access"
|
|
hexmask.long.byte 0x4 0.--6. 1. "NWE_PULSE,NWE Pulse Length"
|
|
line.long 0x8 "HSMC_CYCLE,Cycle Register"
|
|
hexmask.long.word 0x8 16.--24. 1. "NRD_CYCLE,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. "NWE_CYCLE,Total Write Cycle Length"
|
|
line.long 0xC "HSMC_TIMINGS,Timings Register"
|
|
bitfld.long 0xC 31. "NFSEL,NAND Flash Selection" "0,1"
|
|
hexmask.long.byte 0xC 24.--27. 1. "TWB,WEN High to REN to Busy"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--19. 1. "TRR,Ready to REN Low Delay"
|
|
bitfld.long 0xC 12. "OCMS,Off Chip Memory Scrambling Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--11. 1. "TAR,ALE to REN Low Delay"
|
|
hexmask.long.byte 0xC 4.--7. 1. "TADL,ALE to Data Start"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--3. 1. "TCLR,CLE to REN Low Delay"
|
|
line.long 0x10 "HSMC_MODE,Mode Register"
|
|
bitfld.long 0x10 20. "TDF_MODE,TDF Optimization" "0,1"
|
|
hexmask.long.byte 0x10 16.--19. 1. "TDF_CYCLES,Data Float Time"
|
|
newline
|
|
bitfld.long 0x10 12. "DBW,Data Bus Width" "0: 8-bit bus,1: 16-bit bus"
|
|
bitfld.long 0x10 8. "BAT,Byte Access Type" "0: Byte select access type:- Write operation is..,1: Byte write access type:- Write operation is.."
|
|
newline
|
|
bitfld.long 0x10 4.--5. "EXNW_MODE,NWAIT Mode" "0: Disabled-The NWAIT input signal is ignored on..,?,2: Frozen Mode-If asserted the NWAIT signal freezes..,3: Ready Mode-The NWAIT signal indicates the.."
|
|
bitfld.long 0x10 1. "WRITE_MODE,Selection of the Control Signal for Write Operation" "0: The Write operation is controller by the NCS..,1: The Write operation is controlled by the NWE.."
|
|
newline
|
|
bitfld.long 0x10 0. "READ_MODE,Selection of the Control Signal for Read Operation" "0: The Read operation is controlled by the NCS..,1: The Read operation is controlled by the NRD.."
|
|
tree.end
|
|
repeat.end
|
|
base ad:0xF8014000
|
|
group.long 0x7A0++0x3
|
|
line.long 0x0 "HSMC_OCMS,Off Chip Memory Scrambling Register"
|
|
bitfld.long 0x0 1. "SRSE,NFC Internal SRAM Scrambling Enable" "0,1"
|
|
bitfld.long 0x0 0. "SMSE,Static Memory Controller Scrambling Enable" "0,1"
|
|
wgroup.long 0x7A4++0x7
|
|
line.long 0x0 "HSMC_KEY1,Off Chip Memory Scrambling KEY1 Register"
|
|
hexmask.long 0x0 0.--31. 1. "KEY1,Off Chip Memory Scrambling (OCMS) Key Part 1"
|
|
line.long 0x4 "HSMC_KEY2,Off Chip Memory Scrambling KEY2 Register"
|
|
hexmask.long 0x4 0.--31. 1. "KEY2,Off Chip Memory Scrambling (OCMS) Key Part 2"
|
|
group.long 0x7E4++0x3
|
|
line.long 0x0 "HSMC_WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x7E8++0x3
|
|
line.long 0x0 "HSMC_WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
tree "I2SC (Inter-IC Sound Controller)"
|
|
base ad:0x0
|
|
tree "I2SC0"
|
|
base ad:0xF8050000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
bitfld.long 0x0 5. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TXEN,Transmitter Enable" "0,1"
|
|
bitfld.long 0x0 3. "CKDIS,Clocks Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CKEN,Clocks Enable" "0,1"
|
|
bitfld.long 0x0 1. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXEN,Receiver Enable" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 31. "IWS,I2SC_WS Slot Width" "0,1"
|
|
bitfld.long 0x0 30. "IMCKMODE,Master Clock Mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--29. 1. "IMCKFS,Master Clock to fs Ratio"
|
|
hexmask.long.byte 0x0 16.--21. 1. "IMCKDIV,Selected Clock to I2SC Master Clock Ratio"
|
|
newline
|
|
bitfld.long 0x0 14. "TXSAME,Transmit Data when Underrun" "0,1"
|
|
bitfld.long 0x0 12. "TXMONO,Transmit Mono" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "RXLOOP,Loopback Test Mode" "0,1"
|
|
bitfld.long 0x0 8. "RXMONO,Receive Mono" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "FORMAT,Data Format" "0: I2S format stereo with I2SC_WS low for left..,1: Left-justified format stereo with I2SC_WS high..,?,?"
|
|
bitfld.long 0x0 2.--4. "DATALENGTH,Data Word Length" "0: Data length is set to 32 bits,1: Data length is set to 24 bits,2: Data length is set to 20 bits,3: Data length is set to 18 bits,4: Data length is set to 16 bits,5: Data length is set to 16-bit compact stereo.,6: Data length is set to 8 bits,7: Data length is set to 8-bit compact stereo. Left.."
|
|
newline
|
|
bitfld.long 0x0 0. "MODE,Inter-IC Sound Controller Mode" "0: I2SC_CK and I2SC_WS pin inputs used as bit clock..,1: Bit clock and word select/frame synchronization.."
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 20.--21. "TXURCH,Transmit Underrun Channel" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "RXORCH,Receive Overrun Channel" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 6. "TXUR,Transmit Underrun" "0,1"
|
|
bitfld.long 0x0 5. "TXRDY,Transmit Ready" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TXEN,Transmitter Enabled" "0,1"
|
|
bitfld.long 0x0 2. "RXOR,Receive Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Ready" "0,1"
|
|
bitfld.long 0x0 0. "RXEN,Receiver Enabled" "0,1"
|
|
wgroup.long 0xC++0xF
|
|
line.long 0x0 "SCR,Status Clear Register"
|
|
bitfld.long 0x0 20.--21. "TXURCH,Transmit Underrun Per Channel Status Clear" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "RXORCH,Receive Overrun Per Channel Status Clear" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 6. "TXUR,Transmit Underrun Status Clear" "0,1"
|
|
bitfld.long 0x0 2. "RXOR,Receive Overrun Status Clear" "0,1"
|
|
line.long 0x4 "SSR,Status Set Register"
|
|
bitfld.long 0x4 20.--21. "TXURCH,Transmit Underrun Per Channel Status Set" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "RXORCH,Receive Overrun Per Channel Status Set" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 6. "TXUR,Transmit Underrun Status Set" "0,1"
|
|
bitfld.long 0x4 2. "RXOR,Receive Overrun Status Set" "0,1"
|
|
line.long 0x8 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x8 6. "TXUR,Transmit Underflow Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 5. "TXRDY,Transmit Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "RXOR,Receiver Overrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 1. "RXRDY,Receiver Ready Interrupt Enable" "0,1"
|
|
line.long 0xC "IDR,Interrupt Disable Register"
|
|
bitfld.long 0xC 6. "TXUR,Transmit Underflow Interrupt Disable" "0,1"
|
|
bitfld.long 0xC 5. "TXRDY,Transmit Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "RXOR,Receiver Overrun Interrupt Disable" "0,1"
|
|
bitfld.long 0xC 1. "RXRDY,Receiver Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0x1C++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 6. "TXUR,Transmit Underflow Interrupt Disable" "0,1"
|
|
bitfld.long 0x0 5. "TXRDY,Transmit Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXOR,Receiver Overrun Interrupt Disable" "0,1"
|
|
bitfld.long 0x0 1. "RXRDY,Receiver Ready Interrupt Disable" "0,1"
|
|
line.long 0x4 "RHR,Receiver Holding Register"
|
|
hexmask.long 0x4 0.--31. 1. "RHR,Receiver Holding Register"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "THR,Transmitter Holding Register"
|
|
hexmask.long 0x0 0.--31. 1. "THR,Transmitter Holding Register"
|
|
tree.end
|
|
tree "I2SC1"
|
|
base ad:0xFC04C000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
bitfld.long 0x0 5. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TXEN,Transmitter Enable" "0,1"
|
|
bitfld.long 0x0 3. "CKDIS,Clocks Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CKEN,Clocks Enable" "0,1"
|
|
bitfld.long 0x0 1. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXEN,Receiver Enable" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 31. "IWS,I2SC_WS Slot Width" "0,1"
|
|
bitfld.long 0x0 30. "IMCKMODE,Master Clock Mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--29. 1. "IMCKFS,Master Clock to fs Ratio"
|
|
hexmask.long.byte 0x0 16.--21. 1. "IMCKDIV,Selected Clock to I2SC Master Clock Ratio"
|
|
newline
|
|
bitfld.long 0x0 14. "TXSAME,Transmit Data when Underrun" "0,1"
|
|
bitfld.long 0x0 12. "TXMONO,Transmit Mono" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "RXLOOP,Loopback Test Mode" "0,1"
|
|
bitfld.long 0x0 8. "RXMONO,Receive Mono" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "FORMAT,Data Format" "0: I2S format stereo with I2SC_WS low for left..,1: Left-justified format stereo with I2SC_WS high..,?,?"
|
|
bitfld.long 0x0 2.--4. "DATALENGTH,Data Word Length" "0: Data length is set to 32 bits,1: Data length is set to 24 bits,2: Data length is set to 20 bits,3: Data length is set to 18 bits,4: Data length is set to 16 bits,5: Data length is set to 16-bit compact stereo.,6: Data length is set to 8 bits,7: Data length is set to 8-bit compact stereo. Left.."
|
|
newline
|
|
bitfld.long 0x0 0. "MODE,Inter-IC Sound Controller Mode" "0: I2SC_CK and I2SC_WS pin inputs used as bit clock..,1: Bit clock and word select/frame synchronization.."
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 20.--21. "TXURCH,Transmit Underrun Channel" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "RXORCH,Receive Overrun Channel" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 6. "TXUR,Transmit Underrun" "0,1"
|
|
bitfld.long 0x0 5. "TXRDY,Transmit Ready" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TXEN,Transmitter Enabled" "0,1"
|
|
bitfld.long 0x0 2. "RXOR,Receive Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Ready" "0,1"
|
|
bitfld.long 0x0 0. "RXEN,Receiver Enabled" "0,1"
|
|
wgroup.long 0xC++0xF
|
|
line.long 0x0 "SCR,Status Clear Register"
|
|
bitfld.long 0x0 20.--21. "TXURCH,Transmit Underrun Per Channel Status Clear" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "RXORCH,Receive Overrun Per Channel Status Clear" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 6. "TXUR,Transmit Underrun Status Clear" "0,1"
|
|
bitfld.long 0x0 2. "RXOR,Receive Overrun Status Clear" "0,1"
|
|
line.long 0x4 "SSR,Status Set Register"
|
|
bitfld.long 0x4 20.--21. "TXURCH,Transmit Underrun Per Channel Status Set" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "RXORCH,Receive Overrun Per Channel Status Set" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 6. "TXUR,Transmit Underrun Status Set" "0,1"
|
|
bitfld.long 0x4 2. "RXOR,Receive Overrun Status Set" "0,1"
|
|
line.long 0x8 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x8 6. "TXUR,Transmit Underflow Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 5. "TXRDY,Transmit Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "RXOR,Receiver Overrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 1. "RXRDY,Receiver Ready Interrupt Enable" "0,1"
|
|
line.long 0xC "IDR,Interrupt Disable Register"
|
|
bitfld.long 0xC 6. "TXUR,Transmit Underflow Interrupt Disable" "0,1"
|
|
bitfld.long 0xC 5. "TXRDY,Transmit Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "RXOR,Receiver Overrun Interrupt Disable" "0,1"
|
|
bitfld.long 0xC 1. "RXRDY,Receiver Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0x1C++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 6. "TXUR,Transmit Underflow Interrupt Disable" "0,1"
|
|
bitfld.long 0x0 5. "TXRDY,Transmit Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXOR,Receiver Overrun Interrupt Disable" "0,1"
|
|
bitfld.long 0x0 1. "RXRDY,Receiver Ready Interrupt Disable" "0,1"
|
|
line.long 0x4 "RHR,Receiver Holding Register"
|
|
hexmask.long 0x4 0.--31. 1. "RHR,Receiver Holding Register"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "THR,Transmitter Holding Register"
|
|
hexmask.long 0x0 0.--31. 1. "THR,Transmitter Holding Register"
|
|
tree.end
|
|
tree.end
|
|
tree "ICM (Integrity Check Monitor)"
|
|
base ad:0xF8040000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CFG,Configuration Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "DAPROT,Region Descriptor Area Protection"
|
|
hexmask.long.byte 0x0 16.--21. 1. "HAPROT,Region Hash Area Protection"
|
|
bitfld.long 0x0 13.--15. "UALGO,User SHA Algorithm" "0: SHA1 algorithm processed,1: SHA256 algorithm processed,?,?,4: SHA224 algorithm processed,?,?,?"
|
|
bitfld.long 0x0 12. "UIHASH,User Initial Hash Value" "0,1"
|
|
bitfld.long 0x0 9. "DUALBUFF,Dual Input Buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ASCD,Automatic Switch To Compare Digest" "0,1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "BBC,Bus Burden Control"
|
|
bitfld.long 0x0 2. "SLBDIS,Secondary List Branching Disable" "0,1"
|
|
bitfld.long 0x0 1. "EOMDIS,End of Monitoring Disable" "0,1"
|
|
bitfld.long 0x0 0. "WBDIS,Write Back Disable" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "CTRL,Control Register"
|
|
hexmask.long.byte 0x0 12.--15. 1. "RMEN,Region Monitoring Enable"
|
|
hexmask.long.byte 0x0 8.--11. 1. "RMDIS,Region Monitoring Disable"
|
|
hexmask.long.byte 0x0 4.--7. 1. "REHASH,Recompute Internal Hash"
|
|
bitfld.long 0x0 2. "SWRST,Software Reset" "0,1"
|
|
bitfld.long 0x0 1. "DISABLE,ICM Disable Register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ENABLE,ICM Enable" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
hexmask.long.byte 0x0 12.--15. 1. "RMDIS,Region Monitoring Disabled Status"
|
|
hexmask.long.byte 0x0 8.--11. 1. "RAWRMDIS,Region Monitoring Disabled Raw Status"
|
|
bitfld.long 0x0 0. "ENABLE,ICM Enable Register" "0,1"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 24. "URAD,Undefined Register Access Detection Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x0 20.--23. 1. "RSU,Region Status Updated Interrupt Disable"
|
|
hexmask.long.byte 0x0 16.--19. 1. "REC,Region End bit Condition Detected Interrupt Enable"
|
|
hexmask.long.byte 0x0 12.--15. 1. "RWC,Region Wrap Condition detected Interrupt Enable"
|
|
hexmask.long.byte 0x0 8.--11. 1. "RBE,Region Bus Error Interrupt Enable"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "RDM,Region Digest Mismatch Interrupt Enable"
|
|
hexmask.long.byte 0x0 0.--3. 1. "RHC,Region Hash Completed Interrupt Enable"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "URAD,Undefined Register Access Detection Interrupt Disable" "0,1"
|
|
hexmask.long.byte 0x4 20.--23. 1. "RSU,Region Status Updated Interrupt Disable"
|
|
hexmask.long.byte 0x4 16.--19. 1. "REC,Region End bit Condition detected Interrupt Disable"
|
|
hexmask.long.byte 0x4 12.--15. 1. "RWC,Region Wrap Condition Detected Interrupt Disable"
|
|
hexmask.long.byte 0x4 8.--11. 1. "RBE,Region Bus Error Interrupt Disable"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "RDM,Region Digest Mismatch Interrupt Disable"
|
|
hexmask.long.byte 0x4 0.--3. 1. "RHC,Region Hash Completed Interrupt Disable"
|
|
rgroup.long 0x18++0xB
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 24. "URAD,Undefined Register Access Detection Interrupt Mask" "0,1"
|
|
hexmask.long.byte 0x0 20.--23. 1. "RSU,Region Status Updated Interrupt Mask"
|
|
hexmask.long.byte 0x0 16.--19. 1. "REC,Region End bit Condition Detected Interrupt Mask"
|
|
hexmask.long.byte 0x0 12.--15. 1. "RWC,Region Wrap Condition Detected Interrupt Mask"
|
|
hexmask.long.byte 0x0 8.--11. 1. "RBE,Region Bus Error Interrupt Mask"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "RDM,Region Digest Mismatch Interrupt Mask"
|
|
hexmask.long.byte 0x0 0.--3. 1. "RHC,Region Hash Completed Interrupt Mask"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 24. "URAD,Undefined Register Access Detection Status" "0,1"
|
|
hexmask.long.byte 0x4 20.--23. 1. "RSU,Region Status Updated Detected"
|
|
hexmask.long.byte 0x4 16.--19. 1. "REC,Region End Bit Condition Detected"
|
|
hexmask.long.byte 0x4 12.--15. 1. "RWC,Region Wrap Condition Detected"
|
|
hexmask.long.byte 0x4 8.--11. 1. "RBE,Region Bus Error"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "RDM,Region Digest Mismatch"
|
|
hexmask.long.byte 0x4 0.--3. 1. "RHC,Region Hash Completed"
|
|
line.long 0x8 "UASR,Undefined Access Status Register"
|
|
bitfld.long 0x8 0.--2. "URAT,Undefined Register Access Trace" "0: Unspecified structure member set to one detected..,1: ICM_CFG modified during active monitoring.,2: ICM_DSCR modified during active monitoring.,3: ICM_HASH modified during active monitoring,4: Write-only register read access,?,?,?"
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "DSCR,Region Descriptor Area Start Address Register"
|
|
hexmask.long 0x0 6.--31. 1. "DASA,Descriptor Area Start Address"
|
|
line.long 0x4 "HASH,Region Hash Area Start Address Register"
|
|
hexmask.long 0x4 7.--31. 1. "HASA,Hash Area Start Address"
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x38)++0x3
|
|
line.long 0x0 "UIHVAL[$1],User Initial Hash Value 0 Register"
|
|
hexmask.long 0x0 0.--31. 1. "VAL,Initial Hash Value"
|
|
repeat.end
|
|
tree.end
|
|
tree "ISC (Image Sensor Controller)"
|
|
base ad:0xF0008000
|
|
wgroup.long 0x0++0x7
|
|
line.long 0x0 "CTRLEN,Control Enable Register"
|
|
bitfld.long 0x0 3. "HISCLR,Histogram Clear" "0,1"
|
|
bitfld.long 0x0 2. "HISREQ,Histogram Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "UPPRO,Update Profile" "0,1"
|
|
bitfld.long 0x0 0. "CAPTURE,Capture Input Stream Command" "0,1"
|
|
line.long 0x4 "CTRLDIS,Control Disable Register"
|
|
bitfld.long 0x4 8. "SWRST,Software Reset" "0,1"
|
|
bitfld.long 0x4 0. "DISABLE,Capture Disable" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "CTRLSR,Control Status Register"
|
|
bitfld.long 0x0 31. "SIP,Synchronization In Progress" "0,1"
|
|
bitfld.long 0x0 4. "FIELD,Field Status (only relevant when the video stream is interlaced)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "HISREQ,Histogram Request Pending" "0,1"
|
|
bitfld.long 0x0 1. "UPPRO,Profile Update Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CAPTURE,Capture pending" "0,1"
|
|
group.long 0xC++0xB
|
|
line.long 0x0 "PFE_CFG0,Parallel Front End Configuration 0 Register"
|
|
bitfld.long 0x0 31. "REP,Up Multiply with Replication" "0,1"
|
|
bitfld.long 0x0 28.--30. "BPS,Bits Per Sample" "0: 12-bit input,1: 11-bit input,2: 10-bit input,3: 9-bit input,4: 8-bit input,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 27. "CCIR_REP,CCIR Replication" "0,1"
|
|
hexmask.long.byte 0x0 16.--23. 1. "SKIPCNT,Frame Skipping Counter"
|
|
newline
|
|
bitfld.long 0x0 13. "ROWEN,Row Cropping Enable" "0,1"
|
|
bitfld.long 0x0 12. "COLEN,Column Cropping Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CCIR10_8N,CCIR 10 bits or 8 bits" "0,1"
|
|
bitfld.long 0x0 10. "CCIR_CRC,CCIR656 CRC Decoder" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CCIR656,CCIR656 input mode" "0,1"
|
|
bitfld.long 0x0 8. "GATED,Gated input clock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CONT,Continuous Acquisition" "0,1"
|
|
bitfld.long 0x0 4.--6. "MODE,Parallel Front End Mode" "0: Video source is progressive.,1: Video source is interlaced two fields are..,2: Video source is interlaced two fields are..,3: Video source is interlaced two fields are..,4: Video source is interlaced one field is captured..,5: Video source is interlaced one field is captured..,6: Video source is interlaced one field is captured..,?"
|
|
newline
|
|
bitfld.long 0x0 3. "FPOL,Field Polarity" "0,1"
|
|
bitfld.long 0x0 2. "PPOL,Pixel Clock Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "VPOL,Vertical Synchronization Polarity" "0,1"
|
|
bitfld.long 0x0 0. "HPOL,Horizontal Synchronization Polarity" "0,1"
|
|
line.long 0x4 "PFE_CFG1,Parallel Front End Configuration 1 Register"
|
|
hexmask.long.word 0x4 16.--31. 1. "COLMAX,Column Maximum Limit"
|
|
hexmask.long.word 0x4 0.--15. 1. "COLMIN,Column Minimum Limit"
|
|
line.long 0x8 "PFE_CFG2,Parallel Front End Configuration 2 Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "ROWMAX,Row Maximum Limit"
|
|
hexmask.long.word 0x8 0.--15. 1. "ROWMIN,Row Minimum Limit"
|
|
wgroup.long 0x18++0x7
|
|
line.long 0x0 "CLKEN,Clock Enable Register"
|
|
bitfld.long 0x0 1. "MCEN,Master Clock Enable" "0,1"
|
|
bitfld.long 0x0 0. "ICEN,ISP Clock Enable" "0,1"
|
|
line.long 0x4 "CLKDIS,Clock Disable Register"
|
|
bitfld.long 0x4 9. "MCSWRST,Master Clock Software Reset" "0,1"
|
|
bitfld.long 0x4 8. "ICSWRST,ISP Clock Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MCDIS,Master Clock Disable" "0,1"
|
|
bitfld.long 0x4 0. "ICDIS,ISP Clock Disable" "0,1"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "CLKSR,Clock Status Register"
|
|
bitfld.long 0x0 31. "SIP,Synchronization In Progress" "0,1"
|
|
bitfld.long 0x0 1. "MCSR,Master Clock Status Register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ICSR,ISP Clock Status Register" "0,1"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "CLKCFG,Clock Configuration Register"
|
|
bitfld.long 0x0 24.--25. "MCSEL,Master Clock Reference Clock Selection" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--23. 1. "MCDIV,Master Clock Divider"
|
|
newline
|
|
bitfld.long 0x0 8. "ICSEL,ISP Clock Selection" "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ICDIV,ISP Clock Divider"
|
|
wgroup.long 0x28++0x7
|
|
line.long 0x0 "INTEN,Interrupt Enable Register"
|
|
bitfld.long 0x0 28. "CCIRERR,CCIR Decoder Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 27. "HDTO,Horizontal Synchronization Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "VDTO,Vertical Synchronization Timeout Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 25. "DAOV,Data Overflow Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "VFPOV,Vertical Front Porch Overflow Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 20. "RERR,Read Channel Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "WERR,Write Channel Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 13. "HISCLR,Histogram Clear Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "HISDONE,Histogram Completed Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 9. "LDONE,DMA List Done Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DDONE,DMA Done Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 5. "DIS,Disable Completed Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SWRST,Software Reset Completed Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "HD,Horizontal Synchronization Detection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "VD,Vertical Synchronization Detection Interrupt Enable" "0,1"
|
|
line.long 0x4 "INTDIS,Interrupt Disable Register"
|
|
bitfld.long 0x4 28. "CCIRERR,CCIR Decoder Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 27. "HDTO,Horizontal Synchronization Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "VDTO,Vertical Synchronization Timeout Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 25. "DAOV,Data Overflow Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "VFPOV,Vertical Front Porch Overflow Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 20. "RERR,Read Channel Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "WERR,Write Channel Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 13. "HISCLR,Histogram Clear Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "HISDONE,Histogram Completed Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 9. "LDONE,DMA List Done Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "DDONE,DMA Done Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 5. "DIS,Disable Completed Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SWRST,Software Reset Completed Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "HD,Horizontal Synchronization Detection Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "VD,Vertical Synchronization Detection Interrupt Disable" "0,1"
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "INTMASK,Interrupt Mask Register"
|
|
bitfld.long 0x0 28. "CCIRERR,CCIR Decoder Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 27. "HDTO,Horizontal Synchronization Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "VDTO,Vertical Synchronization Timeout Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 25. "DAOV,Data Overflow Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "VFPOV,Vertical Front Porch Overflow Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 20. "RERR,Read Channel Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "WERR,Write Channel Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 13. "HISCLR,Histogram Clear Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "HISDONE,Histogram Completed Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 9. "LDONE,DMA List Done Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DDONE,DMA Done Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "DIS,Disable Completed Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SWRST,Software Reset Completed Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 1. "HD,Horizontal Synchronization Detection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "VD,Vertical Synchronization Detection Interrupt Mask" "0,1"
|
|
line.long 0x4 "INTSR,Interrupt Status Register"
|
|
bitfld.long 0x4 28. "CCIRERR,CCIR Decoder Error Interrupt" "0,1"
|
|
bitfld.long 0x4 27. "HDTO,Horizontal Synchronization Timeout Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "VDTO,Vertical Synchronization Timeout Interrupt" "0,1"
|
|
bitfld.long 0x4 25. "DAOV,Data Overflow Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "VFPOV,Vertical Front Porch Overflow Interrupt" "0,1"
|
|
bitfld.long 0x4 20. "RERR,Read Channel Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17.--18. "WERRID,Write Channel Error Identifier" "0: An error occurred for Channel 0 (RAW/RGB/Y),1: An error occurred for Channel 1 (CbCr/Cb),2: An error occurred for Channel 2 (Cr),3: Write back channel error"
|
|
bitfld.long 0x4 16. "WERR,Write Channel Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "HISCLR,Histogram Clear Interrupt" "0,1"
|
|
bitfld.long 0x4 12. "HISDONE,Histogram Completed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "LDONE,DMA List Done Interrupt" "0,1"
|
|
bitfld.long 0x4 8. "DDONE,DMA Done Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DIS,Disable Completed Interrupt" "0,1"
|
|
bitfld.long 0x4 4. "SWRST,Software Reset Completed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "HD,Horizontal Synchronization Detected Interrupt" "0,1"
|
|
bitfld.long 0x4 0. "VD,Vertical Synchronization Detected Interrupt" "0,1"
|
|
group.long 0x58++0x3F
|
|
line.long 0x0 "WB_CTRL,White Balance Control Register"
|
|
bitfld.long 0x0 0. "ENABLE,White Balance Enable" "0,1"
|
|
line.long 0x4 "WB_CFG,White Balance Configuration Register"
|
|
bitfld.long 0x4 0.--1. "BAYCFG,White Balance Bayer Configuration (Pixel Color Pattern)" "0: Starting Row configuration is G R G R (Red Row),1: Starting Row configuration is R G R G (Red Row),2: Starting Row configuration is G B G B (Blue Row),3: Starting Row configuration is B G B G (Blue Row)"
|
|
line.long 0x8 "WB_O_RGR,White Balance Offset for R. GR Register"
|
|
hexmask.long.word 0x8 16.--28. 1. "GROFST,Offset Green Component for Red Row (signed 13 bits 1:12:0)"
|
|
hexmask.long.word 0x8 0.--12. 1. "ROFST,Offset Red Component (signed 13 bits 1:12:0)"
|
|
line.long 0xC "WB_O_BGB,White Balance Offset for B. GB Register"
|
|
hexmask.long.word 0xC 16.--28. 1. "GBOFST,Offset Green Component for Blue Row (signed 13 bits 1:12:0)"
|
|
hexmask.long.word 0xC 0.--12. 1. "BOFST,Offset Blue Component (signed 13 bits 1:12:0)"
|
|
line.long 0x10 "WB_G_RGR,White Balance Gain for R. GR Register"
|
|
hexmask.long.word 0x10 16.--28. 1. "GRGAIN,Green Component (Red row) Gain (unsigned 13 bits 0:4:9)"
|
|
hexmask.long.word 0x10 0.--12. 1. "RGAIN,Red Component Gain (unsigned 13 bits 0:4:9)"
|
|
line.long 0x14 "WB_G_BGB,White Balance Gain for B. GB Register"
|
|
hexmask.long.word 0x14 16.--28. 1. "GBGAIN,Green Component (Blue row) Gain (unsigned 13 bits 0:4:9)"
|
|
hexmask.long.word 0x14 0.--12. 1. "BGAIN,Blue Component Gain (unsigned 13 bits 0:4:9)"
|
|
line.long 0x18 "CFA_CTRL,Color Filter Array Control Register"
|
|
bitfld.long 0x18 0. "ENABLE,Color Filter Array Interpolation Enable" "0,1"
|
|
line.long 0x1C "CFA_CFG,Color Filter Array Configuration Register"
|
|
bitfld.long 0x1C 4. "EITPOL,Edge Interpolation" "0,1"
|
|
bitfld.long 0x1C 0.--1. "BAYCFG,Color Filter Array Pattern" "0: Starting row configuration is G R G R (red row),1: Starting row configuration is R G R G (red row,2: Starting row configuration is G B G B (blue row),3: Starting row configuration is B G B G (blue row)"
|
|
line.long 0x20 "CC_CTRL,Color Correction Control Register"
|
|
bitfld.long 0x20 0. "ENABLE,Color Correction Enable" "0,1"
|
|
line.long 0x24 "CC_RR_RG,Color Correction RR RG Register"
|
|
hexmask.long.word 0x24 16.--27. 1. "RGGAIN,Green Gain for Red Component (signed 12 bits 1:3:8)"
|
|
hexmask.long.word 0x24 0.--11. 1. "RRGAIN,Red Gain for Red Component (signed 12 bits 1:3:8)"
|
|
line.long 0x28 "CC_RB_OR,Color Correction RB OR Register"
|
|
hexmask.long.word 0x28 16.--28. 1. "ROFST,Red Component Offset (signed 13 bits 1:12:0)"
|
|
hexmask.long.word 0x28 0.--11. 1. "RBGAIN,Blue Gain for Red Component (signed 12 bits 1:3:8)"
|
|
line.long 0x2C "CC_GR_GG,Color Correction GR GG Register"
|
|
hexmask.long.word 0x2C 16.--27. 1. "GGGAIN,Green Gain for Green Component (signed 12 bits 1:3:8)"
|
|
hexmask.long.word 0x2C 0.--11. 1. "GRGAIN,Red Gain for Green Component (signed 12 bits 1:3:8)"
|
|
line.long 0x30 "CC_GB_OG,Color Correction GB OG Register"
|
|
hexmask.long.word 0x30 16.--28. 1. "ROFST,Green Component Offset (signed 13 bits 1:12:0)"
|
|
hexmask.long.word 0x30 0.--11. 1. "GBGAIN,Blue Gain for Green Component (signed 12 bits 1:3:8)"
|
|
line.long 0x34 "CC_BR_BG,Color Correction BR BG Register"
|
|
hexmask.long.word 0x34 16.--27. 1. "BGGAIN,Green Gain for Blue Component (signed 12 bits 1:3:8)"
|
|
hexmask.long.word 0x34 0.--11. 1. "BRGAIN,Red Gain for Blue Component (signed 12 bits 1:3:8)"
|
|
line.long 0x38 "CC_BB_OB,Color Correction BB OB Register"
|
|
hexmask.long.word 0x38 16.--28. 1. "BOFST,Blue Component Offset (signed 13 bits 1:12:0)"
|
|
hexmask.long.word 0x38 0.--11. 1. "BBGAIN,Blue Gain for Blue Component (signed 12 bits 1:3:8)"
|
|
line.long 0x3C "GAM_CTRL,Gamma Correction Control Register"
|
|
bitfld.long 0x3C 3. "RENABLE,Gamma Correction Enable for R Channel" "0,1"
|
|
bitfld.long 0x3C 2. "GENABLE,Gamma Correction Enable for G Channel" "0,1"
|
|
newline
|
|
bitfld.long 0x3C 1. "BENABLE,Gamma Correction Enable for B Channel" "0,1"
|
|
bitfld.long 0x3C 0. "ENABLE,Gamma Correction Enable" "0,1"
|
|
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x98)++0x3
|
|
line.long 0x0 "GAM_BENTRY[$1],Gamma Correction Blue Entry"
|
|
hexmask.long.word 0x0 16.--25. 1. "BCONSTANT,Blue Color Constant for Piecewise Interpolation (unsigned 10 bits 0:10:0)"
|
|
hexmask.long.word 0x0 0.--9. 1. "BSLOPE,Blue Color Slope for Piecewise Interpolation (signed 10 bits 1:3:6)"
|
|
repeat.end
|
|
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x198)++0x3
|
|
line.long 0x0 "GAM_GENTRY[$1],Gamma Correction Green Entry"
|
|
hexmask.long.word 0x0 16.--25. 1. "GCONSTANT,Green Color Constant for Piecewise Interpolation (unsigned 10 bits 0:10:0)"
|
|
hexmask.long.word 0x0 0.--9. 1. "GSLOPE,Green Color Slope for Piecewise Interpolation (signed 10 bits 1:3:6)"
|
|
repeat.end
|
|
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x298)++0x3
|
|
line.long 0x0 "GAM_RENTRY[$1],Gamma Correction Red Entry"
|
|
hexmask.long.word 0x0 16.--25. 1. "RCONSTANT,Red Color Constant for Piecewise Interpolation (unsigned 10 bits 0:10:0)"
|
|
hexmask.long.word 0x0 0.--9. 1. "RSLOPE,Red Color Slope for Piecewise Interpolation (signed 10 bits 1:3:6)"
|
|
repeat.end
|
|
group.long 0x398++0x43
|
|
line.long 0x0 "CSC_CTRL,Color Space Conversion Control Register"
|
|
bitfld.long 0x0 0. "ENABLE,RGB to YCbCr Color Space Conversion Enable" "0,1"
|
|
line.long 0x4 "CSC_YR_YG,Color Space Conversion YR. YG Register"
|
|
hexmask.long.word 0x4 16.--27. 1. "YGGAIN,Green Gain for Luminance (signed 12 bits 1:3:8)"
|
|
hexmask.long.word 0x4 0.--11. 1. "YRGAIN,Reg Gain for Luminance (signed 12 bits 1:3:8)"
|
|
line.long 0x8 "CSC_YB_OY,Color Space Conversion YB. OY Register"
|
|
hexmask.long.word 0x8 16.--26. 1. "YOFST,Luminance Offset (11 bits signed 1:10:0)"
|
|
hexmask.long.word 0x8 0.--11. 1. "YBGAIN,Blue Gain for Luminance Component (12 bits signed 1:3:8)"
|
|
line.long 0xC "CSC_CBR_CBG,Color Space Conversion CBR CBG Register"
|
|
hexmask.long.word 0xC 16.--27. 1. "CBGGAIN,Green Gain for Blue Chrominance (signed 12 bits 1:3:8)"
|
|
hexmask.long.word 0xC 0.--11. 1. "CBRGAIN,Red Gain for Blue Chrominance (signed 12 bits 1:3:8)"
|
|
line.long 0x10 "CSC_CBB_OCB,Color Space Conversion CBB OCB Register"
|
|
hexmask.long.word 0x10 16.--26. 1. "CBOFST,Blue Chrominance Offset (signed 11 bits 1:10:0)"
|
|
hexmask.long.word 0x10 0.--11. 1. "CBBGAIN,Blue Gain for Blue Chrominance (signed 12 bits 1:3:8)"
|
|
line.long 0x14 "CSC_CRR_CRG,Color Space Conversion CRR CRG Register"
|
|
hexmask.long.word 0x14 16.--27. 1. "CRGGAIN,Green Gain for Red Chrominance (signed 12 bits 1:3:8)"
|
|
hexmask.long.word 0x14 0.--11. 1. "CRRGAIN,Red Gain for Red Chrominance (signed 12 bits 1:3:8)"
|
|
line.long 0x18 "CSC_CRB_OCR,Color Space Conversion CRB OCR Register"
|
|
hexmask.long.word 0x18 16.--26. 1. "CROFST,Red Chrominance Offset (signed 11 bits 1:10:0)"
|
|
hexmask.long.word 0x18 0.--11. 1. "CRBGAIN,Blue Gain for Red Chrominance (signed 12 bits 1:3:8)"
|
|
line.long 0x1C "CBC_CTRL,Contrast and Brightness Control Register"
|
|
bitfld.long 0x1C 0. "ENABLE,Contrast and Brightness Control Enable" "0,1"
|
|
line.long 0x20 "CBC_CFG,Contrast and Brightness Configuration Register"
|
|
bitfld.long 0x20 1.--2. "CCIRMODE,CCIR656 Byte Ordering" "0: Byte ordering Cb0 Y0 Cr0 Y1,1: Byte ordering Cr0 Y0 Cb0 Y1,2: Byte ordering Y0 Cb0 Y1 Cr0,3: Byte ordering Y0 Cr0 Y1 Cb0"
|
|
bitfld.long 0x20 0. "CCIR,CCIR656 Stream Enable" "0,1"
|
|
line.long 0x24 "CBC_BRIGHT,Contrast and Brightness. Brightness Register"
|
|
hexmask.long.word 0x24 0.--10. 1. "BRIGHT,Brightness Control (signed 11 bits 1:10:0)"
|
|
line.long 0x28 "CBC_CONTRAST,Contrast and Brightness. Contrast Register"
|
|
hexmask.long.word 0x28 0.--11. 1. "CONTRAST,Contrast (unsigned 12 bits 0:4:8)"
|
|
line.long 0x2C "SUB422_CTRL,Subsampling 4:4:4 to 4:2:2 Control Register"
|
|
bitfld.long 0x2C 0. "ENABLE,4:4:4 to 4:2:2 Chrominance Horizontal Subsampling Filter Enable" "0,1"
|
|
line.long 0x30 "SUB422_CFG,Subsampling 4:4:4 to 4:2:2 Configuration Register"
|
|
bitfld.long 0x30 4.--5. "FILTER,Low Pass Filter Selection" "0: Cosited {1},1: Centered {1 1},2: Cosited {1 2 1},3: Centered {1 3 3 1}"
|
|
bitfld.long 0x30 1.--2. "CCIRMODE,CCIR656 Byte Ordering" "0: Byte ordering Cb0 Y0 Cr0 Y1,1: Byte ordering Cr0 Y0 Cb0 Y1,2: Byte ordering Y0 Cb0 Y1 Cr0,3: Byte ordering Y0 Cr0 Y1 Cb0"
|
|
newline
|
|
bitfld.long 0x30 0. "CCIR,CCIR656 Input Stream" "0,1"
|
|
line.long 0x34 "SUB420_CTRL,Subsampling 4:2:2 to 4:2:0 Control Register"
|
|
bitfld.long 0x34 4. "FILTER,Interlaced or Progressive Chrominance Filter" "0,1"
|
|
bitfld.long 0x34 0. "ENABLE,4:2:2 to 4:2:0 Vertical Subsampling Filter Enable (Center Aligned)" "0,1"
|
|
line.long 0x38 "RLP_CFG,Rounding. Limiting and Packing Configuration Register"
|
|
hexmask.long.byte 0x38 8.--15. 1. "ALPHA,Alpha Value for Alpha-enabled RGB Mode"
|
|
hexmask.long.byte 0x38 0.--3. 1. "MODE,Rounding Limiting and Packing Mode"
|
|
line.long 0x3C "HIS_CTRL,Histogram Control Register"
|
|
bitfld.long 0x3C 0. "ENABLE,Histogram Sub Module Enable" "0,1"
|
|
line.long 0x40 "HIS_CFG,Histogram Configuration Register"
|
|
bitfld.long 0x40 8. "RAR,Histogram Reset After Read" "0,1"
|
|
bitfld.long 0x40 4.--5. "BAYSEL,Bayer Color Component Selection" "0: Starting row configuration is G R G R (red row),1: Starting row configuration is R G R G (red row),2: Starting row configuration is G B G B (blue row,3: Starting row configuration is B G B G (blue row)"
|
|
newline
|
|
bitfld.long 0x40 0.--2. "MODE,Histogram Operating Mode" "0: Gr sampling,1: R sampling,2: Gb sampling,3: B sampling,4: Luminance-only mode,5: Raw sampling,6: Luminance only with CCIR656 10-bit or 8-bit mode,?"
|
|
group.long 0x3E0++0xB
|
|
line.long 0x0 "DCFG,DMA Configuration Register"
|
|
bitfld.long 0x0 8.--9. "CMBSIZE,DMA Memory Burst Size C channel" "0: DMA single access,1: 4-beat burst access,2: 8-beat burst access,3: 16-beat burst access"
|
|
bitfld.long 0x0 4.--5. "YMBSIZE,DMA Memory Burst Size Y channel" "0: DMA single access,1: 4-beat burst access,2: 8-beat burst access,3: 16-beat burst access"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "IMODE,DMA Input Mode Selection" "0: 8 bits single channel packed,1: 16 bits single channel packed,2: 32 bits single channel packed,3: 32 bits dual channel,4: 32 bits triple channel,5: 32 bits dual channel,6: 32 bits triple channel,?"
|
|
line.long 0x4 "DCTRL,DMA Control Register"
|
|
bitfld.long 0x4 7. "DONE,Descriptor Processing Status(2)" "0,1"
|
|
bitfld.long 0x4 6. "FIELD,Value of Captured Frame Field Signal(1)(2)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "WB,Write Back Operation Enable" "0,1"
|
|
bitfld.long 0x4 4. "IE,Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1.--2. "DVIEW,Descriptor View" "0: Address {0} Stride {0} are updated,1: Address {0 1} Stride {0 1} are updated,2: Address {0 1 2} Stride {0 1 2} are updated,?"
|
|
bitfld.long 0x4 0. "DE,Descriptor Enable" "0,1"
|
|
line.long 0x8 "DNDA,DMA Descriptor Address Register"
|
|
hexmask.long 0x8 2.--31. 1. "NDA,Next Descriptor Address Register"
|
|
repeat 3. (list 0x0 0x1 0x2)(list ad:0xF00083EC ad:0xF00083F4 ad:0xF00083FC)
|
|
tree "ISC_SUB0[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "DAD,DMA Address 0 Register"
|
|
hexmask.long 0x0 0.--31. 1. "AD0,Channel 0 Address"
|
|
line.long 0x4 "DST,DMA Stride 0 Register"
|
|
hexmask.long 0x4 0.--31. 1. "ST0,Channel 0 Stride"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0xF0008000
|
|
repeat 512. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x410)++0x3
|
|
line.long 0x0 "HIS_ENTRY[$1],Histogram Entry"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "COUNT,Entry Counter"
|
|
repeat.end
|
|
tree.end
|
|
tree "L2CC (L2 Cache Controller)"
|
|
base ad:0xA00000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "IDR,Cache ID Register"
|
|
hexmask.long 0x0 0.--31. 1. "ID,Cache Controller ID"
|
|
line.long 0x4 "TYPR,Cache Type Register"
|
|
bitfld.long 0x4 20.--22. "DL2WSIZE,Data L2 Cache Way Size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 18. "DL2ASS,Data L2 Cache Associativity" "0,1"
|
|
bitfld.long 0x4 8.--10. "IL2WSIZE,Instruction L2 Cache Way Size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 6. "IL2ASS,Instruction L2 Cache Associativity" "0,1"
|
|
group.long 0x100++0xF
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 0. "L2CEN,L2 Cache Enable" "0,1"
|
|
line.long 0x4 "ACR,Auxiliary Control Register"
|
|
bitfld.long 0x4 29. "IPEN,Instruction Prefetch Enable" "0,1"
|
|
bitfld.long 0x4 28. "DPEN,Data Prefetch Enable" "0,1"
|
|
bitfld.long 0x4 27. "NSIAC,Non-Secure Interrupt Access Control" "0,1"
|
|
bitfld.long 0x4 26. "NSLEN,Non-Secure Lockdown Enable" "0,1"
|
|
bitfld.long 0x4 25. "CRPOL,Cache Replacement Policy" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23.--24. "FWA,Force Write Allocate" "0,1,2,3"
|
|
bitfld.long 0x4 22. "SAOEN,Shared Attribute Override Enable" "0,1"
|
|
bitfld.long 0x4 21. "PEN,Parity Enable" "0,1"
|
|
bitfld.long 0x4 20. "EMBEN,Event Monitor Bus Enable" "0,1"
|
|
bitfld.long 0x4 17.--19. "WAYSIZE,Way Size" "?,1: 16-Kbyte way set associative,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x4 16. "ASS,Associativity" "0,1"
|
|
bitfld.long 0x4 13. "SAIE,Shared Attribute Invalidate Enable" "0,1"
|
|
bitfld.long 0x4 12. "EXCC,Exclusive Cache Configuration" "0,1"
|
|
bitfld.long 0x4 11. "SBDLE,Store Buffer Device Limitation Enable" "0,1"
|
|
bitfld.long 0x4 10. "HPSO,High Priority for SO and Dev Reads Enable" "0,1"
|
|
line.long 0x8 "TRCR,Tag RAM Control Register"
|
|
bitfld.long 0x8 8.--10. "TWRLAT,Write Access Latency" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 4.--6. "TRDLAT,Read Access Latency" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 0.--2. "TSETLAT,Setup Latency" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DRCR,Data RAM Control Register"
|
|
bitfld.long 0xC 8.--10. "DWRLAT,Write Access Latency" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 4.--6. "DRDLAT,Read Access Latency" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 0.--2. "DSETLAT,Setup Latency" "0,1,2,3,4,5,6,7"
|
|
group.long 0x200++0x17
|
|
line.long 0x0 "ECR,Event Counter Control Register"
|
|
bitfld.long 0x0 2. "EVC1RST,Event Counter 1 Reset" "0,1"
|
|
bitfld.long 0x0 1. "EVC0RST,Event Counter 0 Reset" "0,1"
|
|
bitfld.long 0x0 0. "EVCEN,Event Counter Enable" "0,1"
|
|
line.long 0x4 "ECFGR1,Event Counter 1 Configuration Register"
|
|
hexmask.long.byte 0x4 2.--5. 1. "ESRC,Event Counter Source"
|
|
bitfld.long 0x4 0.--1. "EIGEN,Event Counter Interrupt Generation" "0: Disables (default),1: Enables with Increment condition,2: Enables with Overflow condition,3: Disables Interrupt generation"
|
|
line.long 0x8 "ECFGR0,Event Counter 0 Configuration Register"
|
|
hexmask.long.byte 0x8 2.--5. 1. "ESRC,Event Counter Source"
|
|
bitfld.long 0x8 0.--1. "EIGEN,Event Counter Interrupt Generation" "0: Disables (default),1: Enables with Increment condition,2: Enables with Overflow condition,3: Disables Interrupt generation"
|
|
line.long 0xC "EVR1,Event Counter 1 Value Register"
|
|
hexmask.long 0xC 0.--31. 1. "VALUE,Event Counter Value"
|
|
line.long 0x10 "EVR0,Event Counter 0 Value Register"
|
|
hexmask.long 0x10 0.--31. 1. "VALUE,Event Counter Value"
|
|
line.long 0x14 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x14 8. "DECERR,DECERR from L3 Memory" "0,1"
|
|
bitfld.long 0x14 7. "SLVERR,SLVERR from L3 Memory" "0,1"
|
|
bitfld.long 0x14 6. "ERRRD,Error on L2 Data RAM Read" "0,1"
|
|
bitfld.long 0x14 5. "ERRRT,Error on L2 Tag RAM Read" "0,1"
|
|
bitfld.long 0x14 4. "ERRWD,Error on L2 Data RAM Write" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. "ERRWT,Error on L2 Tag RAM Write" "0,1"
|
|
bitfld.long 0x14 2. "PARRD,Parity Error on L2 Data RAM Read" "0,1"
|
|
bitfld.long 0x14 1. "PARRT,Parity Error on L2 Tag RAM Read" "0,1"
|
|
bitfld.long 0x14 0. "ECNTR,Event Counter 1/0 Overflow Increment" "0,1"
|
|
rgroup.long 0x218++0x7
|
|
line.long 0x0 "MISR,Masked Interrupt Status Register"
|
|
bitfld.long 0x0 8. "DECERR,DECERR from L3 memory" "0,1"
|
|
bitfld.long 0x0 7. "SLVERR,SLVERR from L3 memory" "0,1"
|
|
bitfld.long 0x0 6. "ERRRD,Error on L2 Data RAM Read" "0,1"
|
|
bitfld.long 0x0 5. "ERRRT,Error on L2 Tag RAM Read" "0,1"
|
|
bitfld.long 0x0 4. "ERRWD,Error on L2 Data RAM Write" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ERRWT,Error on L2 Tag RAM Write" "0,1"
|
|
bitfld.long 0x0 2. "PARRD,Parity Error on L2 Data RAM Read" "0,1"
|
|
bitfld.long 0x0 1. "PARRT,Parity Error on L2 Tag RAM Read" "0,1"
|
|
bitfld.long 0x0 0. "ECNTR,Event Counter 1/0 Overflow Increment" "0,1"
|
|
line.long 0x4 "RISR,Raw Interrupt Status Register"
|
|
bitfld.long 0x4 8. "DECERR,DECERR from L3 memory" "0,1"
|
|
bitfld.long 0x4 7. "SLVERR,SLVERR from L3 memory" "0,1"
|
|
bitfld.long 0x4 6. "ERRRD,Error on L2 Data RAM Read" "0,1"
|
|
bitfld.long 0x4 5. "ERRRT,Error on L2 Tag RAM Read" "0,1"
|
|
bitfld.long 0x4 4. "ERRWD,Error on L2 Data RAM Write" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ERRWT,Error on L2 Tag RAM Write" "0,1"
|
|
bitfld.long 0x4 2. "PARRD,Parity Error on L2 Data RAM Read" "0,1"
|
|
bitfld.long 0x4 1. "PARRT,Parity Error on L2 Tag RAM Read" "0,1"
|
|
bitfld.long 0x4 0. "ECNTR,Event Counter 1/0 Overflow Increment" "0,1"
|
|
group.long 0x220++0x3
|
|
line.long 0x0 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x0 8. "DECERR,DECERR from L3 memory" "0,1"
|
|
bitfld.long 0x0 7. "SLVERR,SLVERR from L3 memory" "0,1"
|
|
bitfld.long 0x0 6. "ERRRD,Error on L2 Data RAM Read" "0,1"
|
|
bitfld.long 0x0 5. "ERRRT,Error on L2 Tag RAM Read" "0,1"
|
|
bitfld.long 0x0 4. "ERRWD,Error on L2 Data RAM Write" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ERRWT,Error on L2 Tag RAM Write" "0,1"
|
|
bitfld.long 0x0 2. "PARRD,Parity Error on L2 Data RAM Read" "0,1"
|
|
bitfld.long 0x0 1. "PARRT,Parity Error on L2 Tag RAM Read" "0,1"
|
|
bitfld.long 0x0 0. "ECNTR,Event Counter 1/0 Overflow Increment" "0,1"
|
|
group.long 0x730++0x3
|
|
line.long 0x0 "CSR,Cache Synchronization Register"
|
|
bitfld.long 0x0 0. "C,Cache Synchronization Status" "0,1"
|
|
group.long 0x770++0x3
|
|
line.long 0x0 "IPALR,Invalidate Physical Address Line Register"
|
|
hexmask.long.tbyte 0x0 14.--31. 1. "TAG,Tag Number"
|
|
hexmask.long.word 0x0 5.--13. 1. "IDX,Index Number"
|
|
bitfld.long 0x0 0. "C,Cache Synchronization Status" "0,1"
|
|
group.long 0x77C++0x3
|
|
line.long 0x0 "IWR,Invalidate Way Register"
|
|
bitfld.long 0x0 7. "WAY7,Invalidate Way Number 7" "0,1"
|
|
bitfld.long 0x0 6. "WAY6,Invalidate Way Number 6" "0,1"
|
|
bitfld.long 0x0 5. "WAY5,Invalidate Way Number 5" "0,1"
|
|
bitfld.long 0x0 4. "WAY4,Invalidate Way Number 4" "0,1"
|
|
bitfld.long 0x0 3. "WAY3,Invalidate Way Number 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "WAY2,Invalidate Way Number 2" "0,1"
|
|
bitfld.long 0x0 1. "WAY1,Invalidate Way Number 1" "0,1"
|
|
bitfld.long 0x0 0. "WAY0,Invalidate Way Number 0" "0,1"
|
|
group.long 0x7B0++0x3
|
|
line.long 0x0 "CPALR,Clean Physical Address Line Register"
|
|
hexmask.long.tbyte 0x0 14.--31. 1. "TAG,Tag number"
|
|
hexmask.long.word 0x0 5.--13. 1. "IDX,Index number"
|
|
bitfld.long 0x0 0. "C,Cache Synchronization Status" "0,1"
|
|
group.long 0x7B8++0x7
|
|
line.long 0x0 "CIR,Clean Index Register"
|
|
bitfld.long 0x0 28.--30. "WAY,Way number" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 5.--13. 1. "IDX,Index number"
|
|
bitfld.long 0x0 0. "C,Cache Synchronization Status" "0,1"
|
|
line.long 0x4 "CWR,Clean Way Register"
|
|
bitfld.long 0x4 7. "WAY7,Clean Way Number 7" "0,1"
|
|
bitfld.long 0x4 6. "WAY6,Clean Way Number 6" "0,1"
|
|
bitfld.long 0x4 5. "WAY5,Clean Way Number 5" "0,1"
|
|
bitfld.long 0x4 4. "WAY4,Clean Way Number 4" "0,1"
|
|
bitfld.long 0x4 3. "WAY3,Clean Way Number 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "WAY2,Clean Way Number 2" "0,1"
|
|
bitfld.long 0x4 1. "WAY1,Clean Way Number 1" "0,1"
|
|
bitfld.long 0x4 0. "WAY0,Clean Way Number 0" "0,1"
|
|
group.long 0x7F0++0x3
|
|
line.long 0x0 "CIPALR,Clean Invalidate Physical Address Line Register"
|
|
hexmask.long.tbyte 0x0 14.--31. 1. "TAG,Tag Number"
|
|
hexmask.long.word 0x0 5.--13. 1. "IDX,Index Number"
|
|
bitfld.long 0x0 0. "C,Cache Synchronization Status" "0,1"
|
|
group.long 0x7F8++0x7
|
|
line.long 0x0 "CIIR,Clean Invalidate Index Register"
|
|
bitfld.long 0x0 28.--30. "WAY,Way Number" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 5.--13. 1. "IDX,Index Number"
|
|
bitfld.long 0x0 0. "C,Cache Synchronization Status" "0,1"
|
|
line.long 0x4 "CIWR,Clean Invalidate Way Register"
|
|
bitfld.long 0x4 7. "WAY7,Clean Invalidate Way Number 7" "0,1"
|
|
bitfld.long 0x4 6. "WAY6,Clean Invalidate Way Number 6" "0,1"
|
|
bitfld.long 0x4 5. "WAY5,Clean Invalidate Way Number 5" "0,1"
|
|
bitfld.long 0x4 4. "WAY4,Clean Invalidate Way Number 4" "0,1"
|
|
bitfld.long 0x4 3. "WAY3,Clean Invalidate Way Number 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "WAY2,Clean Invalidate Way Number 2" "0,1"
|
|
bitfld.long 0x4 1. "WAY1,Clean Invalidate Way Number 1" "0,1"
|
|
bitfld.long 0x4 0. "WAY0,Clean Invalidate Way Number 0" "0,1"
|
|
group.long 0x900++0x7
|
|
line.long 0x0 "DLKR,Data Lockdown Register"
|
|
bitfld.long 0x0 7. "DLK7,Data Lockdown in Way Number 7" "0,1"
|
|
bitfld.long 0x0 6. "DLK6,Data Lockdown in Way Number 6" "0,1"
|
|
bitfld.long 0x0 5. "DLK5,Data Lockdown in Way Number 5" "0,1"
|
|
bitfld.long 0x0 4. "DLK4,Data Lockdown in Way Number 4" "0,1"
|
|
bitfld.long 0x0 3. "DLK3,Data Lockdown in Way Number 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DLK2,Data Lockdown in Way Number 2" "0,1"
|
|
bitfld.long 0x0 1. "DLK1,Data Lockdown in Way Number 1" "0,1"
|
|
bitfld.long 0x0 0. "DLK0,Data Lockdown in Way Number 0" "0,1"
|
|
line.long 0x4 "ILKR,Instruction Lockdown Register"
|
|
bitfld.long 0x4 7. "ILK7,Instruction Lockdown in Way Number 7" "0,1"
|
|
bitfld.long 0x4 6. "ILK6,Instruction Lockdown in Way Number 6" "0,1"
|
|
bitfld.long 0x4 5. "ILK5,Instruction Lockdown in Way Number 5" "0,1"
|
|
bitfld.long 0x4 4. "ILK4,Instruction Lockdown in Way Number 4" "0,1"
|
|
bitfld.long 0x4 3. "ILK3,Instruction Lockdown in Way Number 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "ILK2,Instruction Lockdown in Way Number 2" "0,1"
|
|
bitfld.long 0x4 1. "ILK1,Instruction Lockdown in Way Number 1" "0,1"
|
|
bitfld.long 0x4 0. "ILK0,Instruction Lockdown in Way Number 0" "0,1"
|
|
group.long 0xF40++0x3
|
|
line.long 0x0 "DCR,Debug Control Register"
|
|
bitfld.long 0x0 2. "SPNIDEN,SPNIDEN Value" "0,1"
|
|
bitfld.long 0x0 1. "DWB,Disable Write-back Force Write-through" "0,1"
|
|
bitfld.long 0x0 0. "DCL,Disable Cache Linefill" "0,1"
|
|
group.long 0xF60++0x3
|
|
line.long 0x0 "PCR,Prefetch Control Register"
|
|
bitfld.long 0x0 30. "DLEN,Double Linefill Enable" "0,1"
|
|
bitfld.long 0x0 29. "INSPEN,Instruction Prefetch Enable" "0,1"
|
|
bitfld.long 0x0 28. "DATPEN,Data Prefetch Enable" "0,1"
|
|
bitfld.long 0x0 27. "DLFWRDIS,Double Linefill on WRAP Read Disable" "0,1"
|
|
bitfld.long 0x0 24. "PDEN,Prefetch Drop Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "IDLEN,INCR Double Linefill Enable" "0,1"
|
|
bitfld.long 0x0 21. "NSIDEN,Not Same ID on Exclusive Sequence Enable" "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "OFFSET,Prefetch Offset"
|
|
group.long 0xF80++0x3
|
|
line.long 0x0 "POWCR,Power Control Register"
|
|
bitfld.long 0x0 1. "DCKGATEN,Dynamic Clock Gating Enable" "0,1"
|
|
bitfld.long 0x0 0. "STBYEN,Standby Mode Enable" "0,1"
|
|
tree.end
|
|
tree "LCDC (LCD Controller)"
|
|
base ad:0xF0000000
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "LCDCFG0,LCD Controller Configuration Register 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CLKDIV,LCD Controller Clock Divider"
|
|
bitfld.long 0x0 13. "CGDISPP,Clock Gating Disable Control for the Post Processing Layer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CGDISHEO,Clock Gating Disable Control for the High-End Overlay" "0,1"
|
|
bitfld.long 0x0 10. "CGDISOVR2,Clock Gating Disable Control for the Overlay 2 Layer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CGDISOVR1,Clock Gating Disable Control for the Overlay 1 Layer" "0,1"
|
|
bitfld.long 0x0 8. "CGDISBASE,Clock Gating Disable Control for the Base Layer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CLKPWMSEL,LCD Controller PWM Clock Source Selection" "0,1"
|
|
bitfld.long 0x0 2. "CLKSEL,LCD Controller Clock Source Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CLKPOL,LCD Controller Clock Polarity" "0,1"
|
|
line.long 0x4 "LCDCFG1,LCD Controller Configuration Register 1"
|
|
hexmask.long.word 0x4 16.--25. 1. "VSPW,Vertical Synchronization Pulse Width"
|
|
hexmask.long.word 0x4 0.--9. 1. "HSPW,Horizontal Synchronization Pulse Width"
|
|
line.long 0x8 "LCDCFG2,LCD Controller Configuration Register 2"
|
|
hexmask.long.word 0x8 16.--25. 1. "VBPW,Vertical Back Porch Width"
|
|
hexmask.long.word 0x8 0.--9. 1. "VFPW,Vertical Front Porch Width"
|
|
line.long 0xC "LCDCFG3,LCD Controller Configuration Register 3"
|
|
hexmask.long.word 0xC 16.--25. 1. "HBPW,Horizontal Back Porch Width"
|
|
hexmask.long.word 0xC 0.--9. 1. "HFPW,Horizontal Front Porch Width"
|
|
line.long 0x10 "LCDCFG4,LCD Controller Configuration Register 4"
|
|
hexmask.long.word 0x10 16.--26. 1. "RPF,Number of Active Row Per Frame"
|
|
hexmask.long.word 0x10 0.--10. 1. "PPL,Number of Pixels Per Line"
|
|
line.long 0x14 "LCDCFG5,LCD Controller Configuration Register 5"
|
|
hexmask.long.byte 0x14 16.--23. 1. "GUARDTIME,LCD DISPLAY Guard Time"
|
|
bitfld.long 0x14 13. "VSPHO,LCD Controller Vertical synchronization Pulse Hold Configuration" "0,1"
|
|
newline
|
|
bitfld.long 0x14 12. "VSPSU,LCD Controller Vertical synchronization Pulse Setup Configuration" "0,1"
|
|
bitfld.long 0x14 10. "PP,Post Processing Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x14 8.--9. "MODE,LCD Controller Output Mode" "0: LCD Output mode is set to 12 bits per pixel,1: LCD Output mode is set to 16 bits per pixel,2: LCD Output mode is set to 18 bits per pixel,3: LCD Output mode is set to 24 bits per pixel"
|
|
bitfld.long 0x14 7. "DISPDLY,LCD Controller Display Power Signal Synchronization" "0,1"
|
|
newline
|
|
bitfld.long 0x14 6. "DITHER,LCD Controller Dithering" "0,1"
|
|
bitfld.long 0x14 4. "DISPPOL,Display Signal Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. "VSPDLYE,Vertical Synchronization Pulse End" "0,1"
|
|
bitfld.long 0x14 2. "VSPDLYS,Vertical Synchronization Pulse Start" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "VSPOL,Vertical Synchronization Pulse Polarity" "0,1"
|
|
bitfld.long 0x14 0. "HSPOL,Horizontal Synchronization Pulse Polarity" "0,1"
|
|
line.long 0x18 "LCDCFG6,LCD Controller Configuration Register 6"
|
|
hexmask.long.byte 0x18 8.--15. 1. "PWMCVAL,LCD Controller PWM Compare Value"
|
|
bitfld.long 0x18 4. "PWMPOL,LCD Controller PWM Signal Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0.--2. "PWMPS,PWM Clock Prescaler" "0: The counter advances at a rate of fCOUNTER =..,1: The counter advances at a rate of fCOUNTER =..,2: The counter advances at a rate of fCOUNTER =..,3: The counter advances at a rate of fCOUNTER =..,4: The counter advances at a rate of fCOUNTER =..,5: The counter advances at a of rate fCOUNTER =..,6: The counter advances at a of rate fCOUNTER =..,?"
|
|
wgroup.long 0x20++0x7
|
|
line.long 0x0 "LCDEN,LCD Controller Enable Register"
|
|
bitfld.long 0x0 3. "PWMEN,LCD Controller Pulse Width Modulation Enable" "0,1"
|
|
bitfld.long 0x0 2. "DISPEN,LCD Controller DISP Signal Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SYNCEN,LCD Controller Horizontal and Vertical Synchronization Enable" "0,1"
|
|
bitfld.long 0x0 0. "CLKEN,LCD Controller Pixel Clock Enable" "0,1"
|
|
line.long 0x4 "LCDDIS,LCD Controller Disable Register"
|
|
bitfld.long 0x4 11. "PWMRST,LCD Controller PWM Reset" "0,1"
|
|
bitfld.long 0x4 10. "DISPRST,LCD Controller DISP Signal Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SYNCRST,LCD Controller Horizontal and Vertical Synchronization Reset" "0,1"
|
|
bitfld.long 0x4 8. "CLKRST,LCD Controller Clock Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PWMDIS,LCD Controller Pulse Width Modulation Disable" "0,1"
|
|
bitfld.long 0x4 2. "DISPDIS,LCD Controller DISP Signal Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "SYNCDIS,LCD Controller Horizontal and Vertical Synchronization Disable" "0,1"
|
|
bitfld.long 0x4 0. "CLKDIS,LCD Controller Pixel Clock Disable" "0,1"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x0 "LCDSR,LCD Controller Status Register"
|
|
bitfld.long 0x0 4. "SIPSTS,Synchronization In Progress" "0,1"
|
|
bitfld.long 0x0 3. "PWMSTS,LCD Controller PWM Signal Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DISPSTS,LCD Controller DISP Signal Status" "0,1"
|
|
bitfld.long 0x0 1. "LCDSTS,LCD Controller Synchronization status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CLKSTS,Clock Status" "0,1"
|
|
wgroup.long 0x2C++0x7
|
|
line.long 0x0 "LCDIER,LCD Controller Interrupt Enable Register"
|
|
bitfld.long 0x0 13. "PPIE,Post Processing Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 11. "HEOIE,High-End Overlay Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "OVR2IE,Overlay 2 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 9. "OVR1IE,Overlay 1 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "BASEIE,Base Layer Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "FIFOERRIE,Output FIFO Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DISPIE,Powerup/Powerdown Sequence Terminated Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "DISIE,LCD Disable Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SOFIE,Start of Frame Interrupt Enable" "0,1"
|
|
line.long 0x4 "LCDIDR,LCD Controller Interrupt Disable Register"
|
|
bitfld.long 0x4 13. "PPID,Post Processing Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 11. "HEOID,High-End Overlay Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "OVR2ID,Overlay 2 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 9. "OVR1ID,Overlay 1 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "BASEID,Base Layer Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "FIFOERRID,Output FIFO Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DISPID,Powerup/Powerdown Sequence Terminated Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "DISID,LCD Disable Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "SOFID,Start of Frame Interrupt Disable" "0,1"
|
|
rgroup.long 0x34++0x7
|
|
line.long 0x0 "LCDIMR,LCD Controller Interrupt Mask Register"
|
|
bitfld.long 0x0 13. "PPIM,Post Processing Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 11. "HEOIM,High-End Overlay Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "OVR2IM,Overlay 2 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 9. "OVR1IM,Overlay 1 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "BASEIM,Base Layer Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "FIFOERRIM,Output FIFO Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DISPIM,Powerup/Powerdown Sequence Terminated Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 1. "DISIM,LCD Disable Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SOFIM,Start of Frame Interrupt Mask" "0,1"
|
|
line.long 0x4 "LCDISR,LCD Controller Interrupt Status Register"
|
|
bitfld.long 0x4 13. "PP,Post Processing Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x4 11. "HEO,High-End Overlay Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "OVR2,Overlay 2 Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x4 9. "OVR1,Overlay 1 Raw Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "BASE,Base Layer Raw Interrupt Status" "0,1"
|
|
bitfld.long 0x4 4. "FIFOERR,Output FIFO Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DISP,Powerup/Powerdown Sequence Terminated Interrupt Status" "0,1"
|
|
bitfld.long 0x4 1. "DIS,LCD Disable Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "SOF,Start of Frame Interrupt Status" "0,1"
|
|
wgroup.long 0x3C++0xB
|
|
line.long 0x0 "ATTR,LCD Controller Attribute Register"
|
|
bitfld.long 0x0 13. "PPA2Q,Post-Processing Update Add To Queue" "0,1"
|
|
bitfld.long 0x0 11. "HEOA2Q,High-End Overlay Update Add To Queue" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "OVR2A2Q,Overlay 2 Update Add to Queue" "0,1"
|
|
bitfld.long 0x0 9. "OVR1A2Q,Overlay 1 Update Add To Queue" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "BASEA2Q,Base Layer Update Add To Queue" "0,1"
|
|
bitfld.long 0x0 5. "PP,Post-Processing Update Attribute" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "HEO,High-End Overlay Update Attribute" "0,1"
|
|
bitfld.long 0x0 2. "OVR2,Overlay 2 Update Attribute" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OVR1,Overlay 1 Update Attribute" "0,1"
|
|
bitfld.long 0x0 0. "BASE,Base Layer Update Attribute" "0,1"
|
|
line.long 0x4 "BASECHER,Base Layer Channel Enable Register"
|
|
bitfld.long 0x4 2. "A2QEN,Add To Queue Enable" "0,1"
|
|
bitfld.long 0x4 1. "UPDATEEN,Update Overlay Attributes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CHEN,Channel Enable" "0,1"
|
|
line.long 0x8 "BASECHDR,Base Layer Channel Disable Register"
|
|
bitfld.long 0x8 8. "CHRST,Channel Reset" "0,1"
|
|
bitfld.long 0x8 0. "CHDIS,Channel Disable" "0,1"
|
|
rgroup.long 0x48++0x3
|
|
line.long 0x0 "BASECHSR,Base Layer Channel Status Register"
|
|
bitfld.long 0x0 2. "A2QSR,Add To Queue Status" "0,1"
|
|
bitfld.long 0x0 1. "UPDATESR,Update Overlay Attributes In Progress Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CHSR,Channel Status" "0,1"
|
|
wgroup.long 0x4C++0x7
|
|
line.long 0x0 "BASEIER,Base Layer Interrupt Enable Register"
|
|
bitfld.long 0x0 6. "OVR,Overflow Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 5. "DONE,End of List Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ADD,Head Descriptor Loaded Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "DSCR,Descriptor Loaded Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DMA,End of DMA Transfer Interrupt Enable" "0,1"
|
|
line.long 0x4 "BASEIDR,Base Layer Interrupt Disabled Register"
|
|
bitfld.long 0x4 6. "OVR,Overflow Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 5. "DONE,End of List Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ADD,Head Descriptor Loaded Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 3. "DSCR,Descriptor Loaded Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DMA,End of DMA Transfer Interrupt Disable" "0,1"
|
|
rgroup.long 0x54++0x7
|
|
line.long 0x0 "BASEIMR,Base Layer Interrupt Mask Register"
|
|
bitfld.long 0x0 6. "OVR,Overflow Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "DONE,End of List Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ADD,Head Descriptor Loaded Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 3. "DSCR,Descriptor Loaded Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DMA,End of DMA Transfer Interrupt Mask" "0,1"
|
|
line.long 0x4 "BASEISR,Base Layer Interrupt Status Register"
|
|
bitfld.long 0x4 6. "OVR,Overflow Detected" "0,1"
|
|
bitfld.long 0x4 5. "DONE,End of List Detected" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ADD,Head Descriptor Loaded" "0,1"
|
|
bitfld.long 0x4 3. "DSCR,DMA Descriptor Loaded" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DMA,End of DMA Transfer" "0,1"
|
|
group.long 0x5C++0x2B
|
|
line.long 0x0 "BASEHEAD,Base DMA Head Register"
|
|
hexmask.long 0x0 2.--31. 1. "HEAD,DMA Head Pointer"
|
|
line.long 0x4 "BASEADDR,Base DMA Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,DMA Transfer Start Address"
|
|
line.long 0x8 "BASECTRL,Base DMA Control Register"
|
|
bitfld.long 0x8 5. "DONEIEN,End of List Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 4. "ADDIEN,Add Head Descriptor to Queue Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "DSCRIEN,Descriptor Loaded Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 2. "DMAIEN,End of DMA Transfer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "LFETCH,Lookup Table Fetch Enable" "0,1"
|
|
bitfld.long 0x8 0. "DFETCH,Transfer Descriptor Fetch Enable" "0,1"
|
|
line.long 0xC "BASENEXT,Base DMA Next Register"
|
|
hexmask.long 0xC 0.--31. 1. "NEXT,DMA Descriptor Next Address"
|
|
line.long 0x10 "BASECFG0,Base Layer Configuration Register 0"
|
|
bitfld.long 0x10 8. "DLBO,Defined Length Burst Only For Channel Bus Transaction" "0,1"
|
|
bitfld.long 0x10 4.--5. "BLEN,AHB Burst Length" "0: AHB Access is started as soon as there is enough..,1: AHB Access is started as soon as there is enough..,2: AHB Access is started as soon as there is enough..,3: AHB Access is started as soon as there is enough.."
|
|
newline
|
|
bitfld.long 0x10 0. "SIF,Source Interface" "0,1"
|
|
line.long 0x14 "BASECFG1,Base Layer Configuration Register 1"
|
|
bitfld.long 0x14 8.--9. "CLUTMODE,Color Lookup Table Mode Input Selection" "0: Color Lookup Table mode set to 1 bit per pixel,1: Color Lookup Table mode set to 2 bits per pixel,2: Color Lookup Table mode set to 4 bits per pixel,3: Color Lookup Table mode set to 8 bits per pixel"
|
|
hexmask.long.byte 0x14 4.--7. 1. "RGBMODE,RGB Mode Input Selection"
|
|
newline
|
|
bitfld.long 0x14 0. "CLUTEN,Color Lookup Table Mode Enable" "0,1"
|
|
line.long 0x18 "BASECFG2,Base Layer Configuration Register 2"
|
|
hexmask.long 0x18 0.--31. 1. "XSTRIDE,Horizontal Stride"
|
|
line.long 0x1C "BASECFG3,Base Layer Configuration Register 3"
|
|
hexmask.long.byte 0x1C 16.--23. 1. "RDEF,Red Default"
|
|
hexmask.long.byte 0x1C 8.--15. 1. "GDEF,Green Default"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--7. 1. "BDEF,Blue Default"
|
|
line.long 0x20 "BASECFG4,Base Layer Configuration Register 4"
|
|
bitfld.long 0x20 11. "DISCEN,Discard Area Enable" "0,1"
|
|
bitfld.long 0x20 9. "REP,Use Replication logic to expand RGB color to 24 bits" "0,1"
|
|
newline
|
|
bitfld.long 0x20 8. "DMA,Use DMA Data Path" "0,1"
|
|
line.long 0x24 "BASECFG5,Base Layer Configuration Register 5"
|
|
hexmask.long.word 0x24 16.--26. 1. "DISCYPOS,Discard Area Vertical Coordinate"
|
|
hexmask.long.word 0x24 0.--10. 1. "DISCXPOS,Discard Area Horizontal Coordinate"
|
|
line.long 0x28 "BASECFG6,Base Layer Configuration Register 6"
|
|
hexmask.long.word 0x28 16.--26. 1. "DISCYSIZE,Discard Area Vertical Size"
|
|
hexmask.long.word 0x28 0.--10. 1. "DISCXSIZE,Discard Area Horizontal Size"
|
|
wgroup.long 0x140++0x7
|
|
line.long 0x0 "OVR1CHER,Overlay 1 Channel Enable Register"
|
|
bitfld.long 0x0 2. "A2QEN,Add To Queue Enable" "0,1"
|
|
bitfld.long 0x0 1. "UPDATEEN,Update Overlay Attributes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CHEN,Channel Enable" "0,1"
|
|
line.long 0x4 "OVR1CHDR,Overlay 1 Channel Disable Register"
|
|
bitfld.long 0x4 8. "CHRST,Channel Reset" "0,1"
|
|
bitfld.long 0x4 0. "CHDIS,Channel Disable" "0,1"
|
|
rgroup.long 0x148++0x3
|
|
line.long 0x0 "OVR1CHSR,Overlay 1 Channel Status Register"
|
|
bitfld.long 0x0 2. "A2QSR,Add To Queue Status" "0,1"
|
|
bitfld.long 0x0 1. "UPDATESR,Update Overlay Attributes In Progress Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CHSR,Channel Status" "0,1"
|
|
wgroup.long 0x14C++0x7
|
|
line.long 0x0 "OVR1IER,Overlay 1 Interrupt Enable Register"
|
|
bitfld.long 0x0 6. "OVR,Overflow Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 5. "DONE,End of List Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ADD,Head Descriptor Loaded Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "DSCR,Descriptor Loaded Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DMA,End of DMA Transfer Interrupt Enable" "0,1"
|
|
line.long 0x4 "OVR1IDR,Overlay 1 Interrupt Disable Register"
|
|
bitfld.long 0x4 6. "OVR,Overflow Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 5. "DONE,End of List Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ADD,Head Descriptor Loaded Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 3. "DSCR,Descriptor Loaded Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DMA,End of DMA Transfer Interrupt Disable" "0,1"
|
|
rgroup.long 0x154++0x7
|
|
line.long 0x0 "OVR1IMR,Overlay 1 Interrupt Mask Register"
|
|
bitfld.long 0x0 6. "OVR,Overflow Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "DONE,End of List Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ADD,Head Descriptor Loaded Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 3. "DSCR,Descriptor Loaded Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DMA,End of DMA Transfer Interrupt Mask" "0,1"
|
|
line.long 0x4 "OVR1ISR,Overlay 1 Interrupt Status Register"
|
|
bitfld.long 0x4 6. "OVR,Overflow Detected" "0,1"
|
|
bitfld.long 0x4 5. "DONE,End of List Detected" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ADD,Head Descriptor Loaded" "0,1"
|
|
bitfld.long 0x4 3. "DSCR,DMA Descriptor Loaded" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DMA,End of DMA Transfer" "0,1"
|
|
group.long 0x15C++0x37
|
|
line.long 0x0 "OVR1HEAD,Overlay 1 DMA Head Register"
|
|
hexmask.long 0x0 2.--31. 1. "HEAD,DMA Head Pointer"
|
|
line.long 0x4 "OVR1ADDR,Overlay 1 DMA Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,DMA Transfer Overlay 1 Address"
|
|
line.long 0x8 "OVR1CTRL,Overlay 1 DMA Control Register"
|
|
bitfld.long 0x8 5. "DONEIEN,End of List Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 4. "ADDIEN,Add Head Descriptor to Queue Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "DSCRIEN,Descriptor Loaded Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 2. "DMAIEN,End of DMA Transfer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "LFETCH,Lookup Table Fetch Enable" "0,1"
|
|
bitfld.long 0x8 0. "DFETCH,Transfer Descriptor Fetch Enable" "0,1"
|
|
line.long 0xC "OVR1NEXT,Overlay 1 DMA Next Register"
|
|
hexmask.long 0xC 0.--31. 1. "NEXT,DMA Descriptor Next Address"
|
|
line.long 0x10 "OVR1CFG0,Overlay 1 Configuration Register 0"
|
|
bitfld.long 0x10 13. "LOCKDIS,Hardware Rotation Lock Disable" "0,1"
|
|
bitfld.long 0x10 12. "ROTDIS,Hardware Rotation Optimization Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "DLBO,Defined Length Burst Only for Channel Bus Transaction" "0,1"
|
|
bitfld.long 0x10 4.--5. "BLEN,AHB Burst Length" "0: AHB Access is started as soon as there is enough..,1: AHB Access is started as soon as there is enough..,2: AHB Access is started as soon as there is enough..,3: AHB Access is started as soon as there is enough.."
|
|
newline
|
|
bitfld.long 0x10 0. "SIF,Source Interface" "0,1"
|
|
line.long 0x14 "OVR1CFG1,Overlay 1 Configuration Register 1"
|
|
bitfld.long 0x14 8.--9. "CLUTMODE,Color Lookup Table Mode Input Selection" "0: Color Lookup Table mode set to 1 bit per pixel,1: Color Lookup Table mode set to 2 bits per pixel,2: Color Lookup Table mode set to 4 bits per pixel,3: Color Lookup Table mode set to 8 bits per pixel"
|
|
hexmask.long.byte 0x14 4.--7. 1. "RGBMODE,RGB Mode Input Selection"
|
|
newline
|
|
bitfld.long 0x14 0. "CLUTEN,Color Lookup Table Mode Enable" "0,1"
|
|
line.long 0x18 "OVR1CFG2,Overlay 1 Configuration Register 2"
|
|
hexmask.long.word 0x18 16.--26. 1. "YPOS,Vertical Window Position"
|
|
hexmask.long.word 0x18 0.--10. 1. "XPOS,Horizontal Window Position"
|
|
line.long 0x1C "OVR1CFG3,Overlay 1 Configuration Register 3"
|
|
hexmask.long.word 0x1C 16.--26. 1. "YSIZE,Vertical Window Size"
|
|
hexmask.long.word 0x1C 0.--10. 1. "XSIZE,Horizontal Window Size"
|
|
line.long 0x20 "OVR1CFG4,Overlay 1 Configuration Register 4"
|
|
hexmask.long 0x20 0.--31. 1. "XSTRIDE,Horizontal Stride"
|
|
line.long 0x24 "OVR1CFG5,Overlay 1 Configuration Register 5"
|
|
hexmask.long 0x24 0.--31. 1. "PSTRIDE,Pixel Stride"
|
|
line.long 0x28 "OVR1CFG6,Overlay 1 Configuration Register 6"
|
|
hexmask.long.byte 0x28 16.--23. 1. "RDEF,Red Default"
|
|
hexmask.long.byte 0x28 8.--15. 1. "GDEF,Green Default"
|
|
newline
|
|
hexmask.long.byte 0x28 0.--7. 1. "BDEF,Blue Default"
|
|
line.long 0x2C "OVR1CFG7,Overlay 1 Configuration Register 7"
|
|
hexmask.long.byte 0x2C 16.--23. 1. "RKEY,Red Color Component Chroma Key"
|
|
hexmask.long.byte 0x2C 8.--15. 1. "GKEY,Green Color Component Chroma Key"
|
|
newline
|
|
hexmask.long.byte 0x2C 0.--7. 1. "BKEY,Blue Color Component Chroma Key"
|
|
line.long 0x30 "OVR1CFG8,Overlay 1 Configuration Register 8"
|
|
hexmask.long.byte 0x30 16.--23. 1. "RMASK,Red Color Component Chroma Key Mask"
|
|
hexmask.long.byte 0x30 8.--15. 1. "GMASK,Green Color Component Chroma Key Mask"
|
|
newline
|
|
hexmask.long.byte 0x30 0.--7. 1. "BMASK,Blue Color Component Chroma Key Mask"
|
|
line.long 0x34 "OVR1CFG9,Overlay 1 Configuration Register 9"
|
|
hexmask.long.byte 0x34 16.--23. 1. "GA,Blender Global Alpha"
|
|
bitfld.long 0x34 10. "DSTKEY,Destination Chroma Keying" "0,1"
|
|
newline
|
|
bitfld.long 0x34 9. "REP,Use Replication logic to expand RGB color to 24 bits" "0,1"
|
|
bitfld.long 0x34 8. "DMA,Blender DMA Layer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x34 7. "OVR,Blender Overlay Layer Enable" "0,1"
|
|
bitfld.long 0x34 6. "LAEN,Blender Local Alpha Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x34 5. "GAEN,Blender Global Alpha Enable" "0,1"
|
|
bitfld.long 0x34 4. "REVALPHA,Blender Reverse Alpha" "0,1"
|
|
newline
|
|
bitfld.long 0x34 3. "ITER,Blender Use Iterated Color" "0,1"
|
|
bitfld.long 0x34 2. "ITER2BL,Blender Iterated Color Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x34 1. "INV,Blender Inverted Blender Output Enable" "0,1"
|
|
bitfld.long 0x34 0. "CRKEY,Blender Chroma Key Enable" "0,1"
|
|
wgroup.long 0x240++0x7
|
|
line.long 0x0 "OVR2CHER,Overlay 2 Channel Enable Register"
|
|
bitfld.long 0x0 2. "A2QEN,Add To Queue Enable" "0,1"
|
|
bitfld.long 0x0 1. "UPDATEEN,Update Overlay Attributes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CHEN,Channel Enable" "0,1"
|
|
line.long 0x4 "OVR2CHDR,Overlay 2 Channel Disable Register"
|
|
bitfld.long 0x4 8. "CHRST,Channel Reset" "0,1"
|
|
bitfld.long 0x4 0. "CHDIS,Channel Disable" "0,1"
|
|
rgroup.long 0x248++0x3
|
|
line.long 0x0 "OVR2CHSR,Overlay 2 Channel Status Register"
|
|
bitfld.long 0x0 2. "A2QSR,Add To Queue Status" "0,1"
|
|
bitfld.long 0x0 1. "UPDATESR,Update Overlay Attributes In Progress Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CHSR,Channel Status" "0,1"
|
|
wgroup.long 0x24C++0x7
|
|
line.long 0x0 "OVR2IER,Overlay 2 Interrupt Enable Register"
|
|
bitfld.long 0x0 6. "OVR,Overflow Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 5. "DONE,End of List Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ADD,Head Descriptor Loaded Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "DSCR,Descriptor Loaded Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DMA,End of DMA Transfer Interrupt Enable" "0,1"
|
|
line.long 0x4 "OVR2IDR,Overlay 2 Interrupt Disable Register"
|
|
bitfld.long 0x4 6. "OVR,Overflow Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 5. "DONE,End of List Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ADD,Head Descriptor Loaded Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 3. "DSCR,Descriptor Loaded Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DMA,End of DMA Transfer Interrupt Disable" "0,1"
|
|
rgroup.long 0x254++0x7
|
|
line.long 0x0 "OVR2IMR,Overlay 2 Interrupt Mask Register"
|
|
bitfld.long 0x0 6. "OVR,Overflow Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "DONE,End of List Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ADD,Head Descriptor Loaded Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 3. "DSCR,Descriptor Loaded Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DMA,End of DMA Transfer Interrupt Mask" "0,1"
|
|
line.long 0x4 "OVR2ISR,Overlay 2 Interrupt Status Register"
|
|
bitfld.long 0x4 6. "OVR,Overflow Detected" "0,1"
|
|
bitfld.long 0x4 5. "DONE,End of List Detected" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ADD,Head Descriptor Loaded" "0,1"
|
|
bitfld.long 0x4 3. "DSCR,DMA Descriptor Loaded" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DMA,End of DMA Transfer" "0,1"
|
|
group.long 0x25C++0x37
|
|
line.long 0x0 "OVR2HEAD,Overlay 2 DMA Head Register"
|
|
hexmask.long 0x0 2.--31. 1. "HEAD,DMA Head Pointer"
|
|
line.long 0x4 "OVR2ADDR,Overlay 2 DMA Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,DMA Transfer Overlay 2 Address"
|
|
line.long 0x8 "OVR2CTRL,Overlay 2 DMA Control Register"
|
|
bitfld.long 0x8 5. "DONEIEN,End of List Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 4. "ADDIEN,Add Head Descriptor to Queue Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "DSCRIEN,Descriptor Loaded Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 2. "DMAIEN,End of DMA Transfer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "LFETCH,Lookup Table Fetch Enable" "0,1"
|
|
bitfld.long 0x8 0. "DFETCH,Transfer Descriptor Fetch Enable" "0,1"
|
|
line.long 0xC "OVR2NEXT,Overlay 2 DMA Next Register"
|
|
hexmask.long 0xC 0.--31. 1. "NEXT,DMA Descriptor Next Address"
|
|
line.long 0x10 "OVR2CFG0,Overlay 2 Configuration Register 0"
|
|
bitfld.long 0x10 13. "LOCKDIS,Hardware Rotation Lock Disable" "0,1"
|
|
bitfld.long 0x10 12. "ROTDIS,Hardware Rotation Optimization Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "DLBO,Defined Length Burst Only For Channel Bus Transaction" "0,1"
|
|
bitfld.long 0x10 4.--5. "BLEN,AHB Burst Length" "0: AHB Access is started as soon as there is enough..,1: AHB Access is started as soon as there is enough..,2: AHB Access is started as soon as there is enough..,3: AHB Access is started as soon as there is enough.."
|
|
line.long 0x14 "OVR2CFG1,Overlay 2 Configuration Register 1"
|
|
bitfld.long 0x14 8.--9. "CLUTMODE,Color Lookup Table Mode Input Selection" "0: Color Lookup Table mode set to 1 bit per pixel,1: Color Lookup Table mode set to 2 bits per pixel,2: Color Lookup Table mode set to 4 bits per pixel,3: Color Lookup Table mode set to 8 bits per pixel"
|
|
hexmask.long.byte 0x14 4.--7. 1. "RGBMODE,RGB Mode Input Selection"
|
|
newline
|
|
bitfld.long 0x14 0. "CLUTEN,Color Lookup Table Mode Enable" "0,1"
|
|
line.long 0x18 "OVR2CFG2,Overlay 2 Configuration Register 2"
|
|
hexmask.long.word 0x18 16.--26. 1. "YPOS,Vertical Window Position"
|
|
hexmask.long.word 0x18 0.--10. 1. "XPOS,Horizontal Window Position"
|
|
line.long 0x1C "OVR2CFG3,Overlay 2 Configuration Register 3"
|
|
hexmask.long.word 0x1C 16.--26. 1. "YSIZE,Vertical Window Size"
|
|
hexmask.long.word 0x1C 0.--10. 1. "XSIZE,Horizontal Window Size"
|
|
line.long 0x20 "OVR2CFG4,Overlay 2 Configuration Register 4"
|
|
hexmask.long 0x20 0.--31. 1. "XSTRIDE,Horizontal Stride"
|
|
line.long 0x24 "OVR2CFG5,Overlay 2 Configuration Register 5"
|
|
hexmask.long 0x24 0.--31. 1. "PSTRIDE,Pixel Stride"
|
|
line.long 0x28 "OVR2CFG6,Overlay 2 Configuration Register 6"
|
|
hexmask.long.byte 0x28 16.--23. 1. "RDEF,Red Default"
|
|
hexmask.long.byte 0x28 8.--15. 1. "GDEF,Green Default"
|
|
newline
|
|
hexmask.long.byte 0x28 0.--7. 1. "BDEF,Blue Default"
|
|
line.long 0x2C "OVR2CFG7,Overlay 2 Configuration Register 7"
|
|
hexmask.long.byte 0x2C 16.--23. 1. "RKEY,Red Color Component Chroma Key"
|
|
hexmask.long.byte 0x2C 8.--15. 1. "GKEY,Green Color Component Chroma Key"
|
|
newline
|
|
hexmask.long.byte 0x2C 0.--7. 1. "BKEY,Blue Color Component Chroma Key"
|
|
line.long 0x30 "OVR2CFG8,Overlay 2 Configuration Register 8"
|
|
hexmask.long.byte 0x30 16.--23. 1. "RMASK,Red Color Component Chroma Key Mask"
|
|
hexmask.long.byte 0x30 8.--15. 1. "GMASK,Green Color Component Chroma Key Mask"
|
|
newline
|
|
hexmask.long.byte 0x30 0.--7. 1. "BMASK,Blue Color Component Chroma Key Mask"
|
|
line.long 0x34 "OVR2CFG9,Overlay 2 Configuration Register 9"
|
|
hexmask.long.byte 0x34 16.--23. 1. "GA,Blender Global Alpha"
|
|
bitfld.long 0x34 10. "DSTKEY,Destination Chroma Keying" "0,1"
|
|
newline
|
|
bitfld.long 0x34 9. "REP,Use Replication logic to expand RGB color to 24 bits" "0,1"
|
|
bitfld.long 0x34 8. "DMA,Blender DMA Layer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x34 7. "OVR,Blender Overlay Layer Enable" "0,1"
|
|
bitfld.long 0x34 6. "LAEN,Blender Local Alpha Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x34 5. "GAEN,Blender Global Alpha Enable" "0,1"
|
|
bitfld.long 0x34 4. "REVALPHA,Blender Reverse Alpha" "0,1"
|
|
newline
|
|
bitfld.long 0x34 3. "ITER,Blender Use Iterated Color" "0,1"
|
|
bitfld.long 0x34 2. "ITER2BL,Blender Iterated Color Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x34 1. "INV,Blender Inverted Blender Output Enable" "0,1"
|
|
bitfld.long 0x34 0. "CRKEY,Blender Chroma Key Enable" "0,1"
|
|
wgroup.long 0x340++0x7
|
|
line.long 0x0 "HEOCHER,High-End Overlay Channel Enable Register"
|
|
bitfld.long 0x0 2. "A2QEN,Add To Queue Enable" "0,1"
|
|
bitfld.long 0x0 1. "UPDATEEN,Update Overlay Attributes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CHEN,Channel Enable" "0,1"
|
|
line.long 0x4 "HEOCHDR,High-End Overlay Channel Disable Register"
|
|
bitfld.long 0x4 8. "CHRST,Channel Reset" "0,1"
|
|
bitfld.long 0x4 0. "CHDIS,Channel Disable" "0,1"
|
|
rgroup.long 0x348++0x3
|
|
line.long 0x0 "HEOCHSR,High-End Overlay Channel Status Register"
|
|
bitfld.long 0x0 2. "A2QSR,Add To Queue Status" "0,1"
|
|
bitfld.long 0x0 1. "UPDATESR,Update Overlay Attributes In Progress Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CHSR,Channel Status" "0,1"
|
|
wgroup.long 0x34C++0x7
|
|
line.long 0x0 "HEOIER,High-End Overlay Interrupt Enable Register"
|
|
bitfld.long 0x0 22. "VOVR,Overflow for V Chrominance Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 21. "VDONE,End of List for V Chrominance Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "VADD,Head Descriptor Loaded for V Chrominance Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 19. "VDSCR,Descriptor Loaded for V Chrominance Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "VDMA,End of DMA for V Chrominance Transfer Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 14. "UOVR,Overflow for U or UV Chrominance Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDONE,End of List for U or UV Chrominance Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 12. "UADD,Head Descriptor Loaded for U or UV Chrominance Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "UDSCR,Descriptor Loaded for U or UV Chrominance Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 10. "UDMA,End of DMA Transfer for U or UV Chrominance Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVR,Overflow Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 5. "DONE,End of List Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ADD,Head Descriptor Loaded Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "DSCR,Descriptor Loaded Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DMA,End of DMA Transfer Interrupt Enable" "0,1"
|
|
line.long 0x4 "HEOIDR,High-End Overlay Interrupt Disable Register"
|
|
bitfld.long 0x4 22. "VOVR,Overflow for V Chrominance Component Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 21. "VDONE,End of List for V Chrominance Component Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "VADD,Head Descriptor Loaded for V Chrominance Component Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 19. "VDSCR,Descriptor Loaded for V Chrominance Component Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "VDMA,End of DMA Transfer for V Chrominance Component Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 14. "UOVR,Overflow Interrupt for U or UV Chrominance Component Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "UDONE,End of List Interrupt for U or UV Chrominance Component Disable" "0,1"
|
|
bitfld.long 0x4 12. "UADD,Head Descriptor Loaded for U or UV Chrominance Component Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "UDSCR,Descriptor Loaded for U or UV Chrominance Component Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 10. "UDMA,End of DMA Transfer for U or UV Chrominance Component Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "OVR,Overflow Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 5. "DONE,End of List Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ADD,Head Descriptor Loaded Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 3. "DSCR,Descriptor Loaded Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DMA,End of DMA Transfer Interrupt Disable" "0,1"
|
|
rgroup.long 0x354++0x7
|
|
line.long 0x0 "HEOIMR,High-End Overlay Interrupt Mask Register"
|
|
bitfld.long 0x0 22. "VOVR,Overflow for V Chrominance Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 21. "VDONE,End of List for V Chrominance Component Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "VADD,Head Descriptor Loaded for V Chrominance Component Mask" "0,1"
|
|
bitfld.long 0x0 19. "VDSCR,Descriptor Loaded for V Chrominance Component Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "VDMA,End of DMA Transfer for V Chrominance Component Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 14. "UOVR,Overflow for U Chrominance Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDONE,End of List for U or UV Chrominance Component Mask" "0,1"
|
|
bitfld.long 0x0 12. "UADD,Head Descriptor Loaded for U or UV Chrominance Component Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "UDSCR,Descriptor Loaded for U or UV Chrominance Component Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "UDMA,End of DMA Transfer for U or UV Chrominance Component Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVR,Overflow Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "DONE,End of List Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ADD,Head Descriptor Loaded Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 3. "DSCR,Descriptor Loaded Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DMA,End of DMA Transfer Interrupt Mask" "0,1"
|
|
line.long 0x4 "HEOISR,High-End Overlay Interrupt Status Register"
|
|
bitfld.long 0x4 22. "VOVR,Overflow Detected for V Component" "0,1"
|
|
bitfld.long 0x4 21. "VDONE,End of List Detected for V Component" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "VADD,Head Descriptor Loaded for V Component" "0,1"
|
|
bitfld.long 0x4 19. "VDSCR,DMA Descriptor Loaded for V Component" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "VDMA,End of DMA Transfer for V Component" "0,1"
|
|
bitfld.long 0x4 14. "UOVR,Overflow Detected for U Component" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "UDONE,End of List Detected for U Component" "0,1"
|
|
bitfld.long 0x4 12. "UADD,Head Descriptor Loaded for U Component" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "UDSCR,DMA Descriptor Loaded for U Component" "0,1"
|
|
bitfld.long 0x4 10. "UDMA,End of DMA Transfer for U Component" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "OVR,Overflow Detected" "0,1"
|
|
bitfld.long 0x4 5. "DONE,End of List Detected" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ADD,Head Descriptor Loaded" "0,1"
|
|
bitfld.long 0x4 3. "DSCR,DMA Descriptor Loaded" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DMA,End of DMA Transfer" "0,1"
|
|
group.long 0x35C++0xD7
|
|
line.long 0x0 "HEOHEAD,High-End Overlay DMA Head Register"
|
|
hexmask.long 0x0 2.--31. 1. "HEAD,DMA Head Pointer"
|
|
line.long 0x4 "HEOADDR,High-End Overlay DMA Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,DMA Transfer Start Address"
|
|
line.long 0x8 "HEOCTRL,High-End Overlay DMA Control Register"
|
|
bitfld.long 0x8 5. "DONEIEN,End of List Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 4. "ADDIEN,Add Head Descriptor to Queue Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "DSCRIEN,Descriptor Loaded Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 2. "DMAIEN,End of DMA Transfer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "LFETCH,Lookup Table Fetch Enable" "0,1"
|
|
bitfld.long 0x8 0. "DFETCH,Transfer Descriptor Fetch Enable" "0,1"
|
|
line.long 0xC "HEONEXT,High-End Overlay DMA Next Register"
|
|
hexmask.long 0xC 0.--31. 1. "NEXT,DMA Descriptor Next Address"
|
|
line.long 0x10 "HEOUHEAD,High-End Overlay U-UV DMA Head Register"
|
|
hexmask.long 0x10 0.--31. 1. "UHEAD,DMA Head Pointer"
|
|
line.long 0x14 "HEOUADDR,High-End Overlay U-UV DMA Address Register"
|
|
hexmask.long 0x14 0.--31. 1. "UADDR,DMA Transfer Start Address for U or UV Chrominance"
|
|
line.long 0x18 "HEOUCTRL,High-End Overlay U-UV DMA Control Register"
|
|
bitfld.long 0x18 5. "UDONEIEN,End of List Interrupt Enable" "0,1"
|
|
bitfld.long 0x18 4. "UADDIEN,Add Head Descriptor to Queue Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 3. "UDSCRIEN,Descriptor Loaded Interrupt Enable" "0,1"
|
|
bitfld.long 0x18 2. "UDMAIEN,End of DMA Transfer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "UDFETCH,Transfer Descriptor Fetch Enable" "0,1"
|
|
line.long 0x1C "HEOUNEXT,High-End Overlay U-UV DMA Next Register"
|
|
hexmask.long 0x1C 0.--31. 1. "UNEXT,DMA Descriptor Next Address"
|
|
line.long 0x20 "HEOVHEAD,High-End Overlay V DMA Head Register"
|
|
hexmask.long 0x20 0.--31. 1. "VHEAD,DMA Head Pointer"
|
|
line.long 0x24 "HEOVADDR,High-End Overlay V DMA Address Register"
|
|
hexmask.long 0x24 0.--31. 1. "VADDR,DMA Transfer Start Address for V Chrominance"
|
|
line.long 0x28 "HEOVCTRL,High-End Overlay V DMA Control Register"
|
|
bitfld.long 0x28 5. "VDONEIEN,End of List Interrupt Enable" "0,1"
|
|
bitfld.long 0x28 4. "VADDIEN,Add Head Descriptor to Queue Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x28 3. "VDSCRIEN,Descriptor Loaded Interrupt Enable" "0,1"
|
|
bitfld.long 0x28 2. "VDMAIEN,End of DMA Transfer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x28 0. "VDFETCH,Transfer Descriptor Fetch Enable" "0,1"
|
|
line.long 0x2C "HEOVNEXT,High-End Overlay V DMA Next Register"
|
|
hexmask.long 0x2C 0.--31. 1. "VNEXT,DMA Descriptor Next Address"
|
|
line.long 0x30 "HEOCFG0,High-End Overlay Configuration Register 0"
|
|
bitfld.long 0x30 13. "LOCKDIS,Hardware Rotation Lock Disable" "0,1"
|
|
bitfld.long 0x30 12. "ROTDIS,Hardware Rotation Optimization Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x30 8. "DLBO,Defined Length Burst Only For Channel Bus Transaction" "0,1"
|
|
bitfld.long 0x30 6.--7. "BLENUV,AHB Burst Length for U-V Channel" "0: AHB Access is started as soon as there is enough..,1: AHB Access is started as soon as there is enough..,2: AHB Access is started as soon as there is enough..,3: AHB Access is started as soon as there is enough.."
|
|
newline
|
|
bitfld.long 0x30 4.--5. "BLEN,AHB Burst Length" "0: AHB Access is started as soon as there is enough..,1: AHB Access is started as soon as there is enough..,2: AHB Access is started as soon as there is enough..,3: AHB Access is started as soon as there is enough.."
|
|
bitfld.long 0x30 0. "SIF,Source Interface" "0,1"
|
|
line.long 0x34 "HEOCFG1,High-End Overlay Configuration Register 1"
|
|
bitfld.long 0x34 20. "DSCALEOPT,Down Scaling Bandwidth Optimization" "0,1"
|
|
bitfld.long 0x34 17. "YUV422SWP,YUV 4:2:2 Swap" "0,1"
|
|
newline
|
|
bitfld.long 0x34 16. "YUV422ROT,YUV 4:2:2 Rotation" "0,1"
|
|
hexmask.long.byte 0x34 12.--15. 1. "YUVMODE,YUV Mode Input Selection"
|
|
newline
|
|
bitfld.long 0x34 8.--9. "CLUTMODE,Color Lookup Table Mode Input Selection" "0: Color Lookup Table mode set to 1 bit per pixel,1: Color Lookup Table mode set to 2 bits per pixel,2: Color Lookup Table mode set to 4 bits per pixel,3: Color Lookup Table mode set to 8 bits per pixel"
|
|
hexmask.long.byte 0x34 4.--7. 1. "RGBMODE,RGB Mode Input Selection"
|
|
newline
|
|
bitfld.long 0x34 1. "YUVEN,YUV Color Space Enable" "0,1"
|
|
bitfld.long 0x34 0. "CLUTEN,Color Lookup Table Mode Enable" "0,1"
|
|
line.long 0x38 "HEOCFG2,High-End Overlay Configuration Register 2"
|
|
hexmask.long.word 0x38 16.--26. 1. "YPOS,Vertical Window Position"
|
|
hexmask.long.word 0x38 0.--10. 1. "XPOS,Horizontal Window Position"
|
|
line.long 0x3C "HEOCFG3,High-End Overlay Configuration Register 3"
|
|
hexmask.long.word 0x3C 16.--26. 1. "YSIZE,Vertical Window Size"
|
|
hexmask.long.word 0x3C 0.--10. 1. "XSIZE,Horizontal Window Size"
|
|
line.long 0x40 "HEOCFG4,High-End Overlay Configuration Register 4"
|
|
hexmask.long.word 0x40 16.--26. 1. "YMEMSIZE,Vertical image Size in Memory"
|
|
hexmask.long.word 0x40 0.--10. 1. "XMEMSIZE,Horizontal image Size in Memory"
|
|
line.long 0x44 "HEOCFG5,High-End Overlay Configuration Register 5"
|
|
hexmask.long 0x44 0.--31. 1. "XSTRIDE,Horizontal Stride"
|
|
line.long 0x48 "HEOCFG6,High-End Overlay Configuration Register 6"
|
|
hexmask.long 0x48 0.--31. 1. "PSTRIDE,Pixel Stride"
|
|
line.long 0x4C "HEOCFG7,High-End Overlay Configuration Register 7"
|
|
hexmask.long 0x4C 0.--31. 1. "UVXSTRIDE,UV Horizontal Stride"
|
|
line.long 0x50 "HEOCFG8,High-End Overlay Configuration Register 8"
|
|
hexmask.long 0x50 0.--31. 1. "UVPSTRIDE,UV Pixel Stride"
|
|
line.long 0x54 "HEOCFG9,High-End Overlay Configuration Register 9"
|
|
hexmask.long.byte 0x54 16.--23. 1. "RDEF,Red Default"
|
|
hexmask.long.byte 0x54 8.--15. 1. "GDEF,Green Default"
|
|
newline
|
|
hexmask.long.byte 0x54 0.--7. 1. "BDEF,Blue Default"
|
|
line.long 0x58 "HEOCFG10,High-End Overlay Configuration Register 10"
|
|
hexmask.long.byte 0x58 16.--23. 1. "RKEY,Red Color Component Chroma Key"
|
|
hexmask.long.byte 0x58 8.--15. 1. "GKEY,Green Color Component Chroma Key"
|
|
newline
|
|
hexmask.long.byte 0x58 0.--7. 1. "BKEY,Blue Color Component Chroma Key"
|
|
line.long 0x5C "HEOCFG11,High-End Overlay Configuration Register 11"
|
|
hexmask.long.byte 0x5C 16.--23. 1. "RMASK,Red Color Component Chroma Key Mask"
|
|
hexmask.long.byte 0x5C 8.--15. 1. "GMASK,Green Color Component Chroma Key Mask"
|
|
newline
|
|
hexmask.long.byte 0x5C 0.--7. 1. "BMASK,Blue Color Component Chroma Key Mask"
|
|
line.long 0x60 "HEOCFG12,High-End Overlay Configuration Register 12"
|
|
hexmask.long.byte 0x60 16.--23. 1. "GA,Blender Global Alpha"
|
|
bitfld.long 0x60 12. "VIDPRI,Video Priority" "0,1"
|
|
newline
|
|
bitfld.long 0x60 10. "DSTKEY,Destination Chroma Keying" "0,1"
|
|
bitfld.long 0x60 9. "REP,Use Replication logic to expand RGB color to 24 bits" "0,1"
|
|
newline
|
|
bitfld.long 0x60 8. "DMA,Blender DMA Layer Enable" "0,1"
|
|
bitfld.long 0x60 7. "OVR,Blender Overlay Layer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x60 6. "LAEN,Blender Local Alpha Enable" "0,1"
|
|
bitfld.long 0x60 5. "GAEN,Blender Global Alpha Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x60 4. "REVALPHA,Blender Reverse Alpha" "0,1"
|
|
bitfld.long 0x60 3. "ITER,Blender Use Iterated Color" "0,1"
|
|
newline
|
|
bitfld.long 0x60 2. "ITER2BL,Blender Iterated Color Enable" "0,1"
|
|
bitfld.long 0x60 1. "INV,Blender Inverted Blender Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x60 0. "CRKEY,Blender Chroma Key Enable" "0,1"
|
|
line.long 0x64 "HEOCFG13,High-End Overlay Configuration Register 13"
|
|
bitfld.long 0x64 31. "SCALEN,Hardware Scaler Enable" "0,1"
|
|
hexmask.long.word 0x64 16.--29. 1. "YFACTOR,Vertical Scaling Factor"
|
|
newline
|
|
hexmask.long.word 0x64 0.--13. 1. "XFACTOR,Horizontal Scaling Factor"
|
|
line.long 0x68 "HEOCFG14,High-End Overlay Configuration Register 14"
|
|
bitfld.long 0x68 30. "CSCYOFF,Color Space Conversion Offset" "0,1"
|
|
hexmask.long.word 0x68 20.--29. 1. "CSCRV,Color Space Conversion V coefficient for Red Component 1:2:7 format"
|
|
newline
|
|
hexmask.long.word 0x68 10.--19. 1. "CSCRU,Color Space Conversion U coefficient for Red Component 1:2:7 format"
|
|
hexmask.long.word 0x68 0.--9. 1. "CSCRY,Color Space Conversion Y coefficient for Red Component 1:2:7 format"
|
|
line.long 0x6C "HEOCFG15,High-End Overlay Configuration Register 15"
|
|
bitfld.long 0x6C 30. "CSCUOFF,Color Space Conversion Offset" "0,1"
|
|
hexmask.long.word 0x6C 20.--29. 1. "CSCGV,Color Space Conversion V coefficient for Green Component 1:2:7 format"
|
|
newline
|
|
hexmask.long.word 0x6C 10.--19. 1. "CSCGU,Color Space Conversion U coefficient for Green Component 1:2:7 format"
|
|
hexmask.long.word 0x6C 0.--9. 1. "CSCGY,Color Space Conversion Y coefficient for Green Component 1:2:7 format"
|
|
line.long 0x70 "HEOCFG16,High-End Overlay Configuration Register 16"
|
|
bitfld.long 0x70 30. "CSCVOFF,Color Space Conversion Offset" "0,1"
|
|
hexmask.long.word 0x70 20.--29. 1. "CSCBV,Color Space Conversion V coefficient for Blue Component 1:2:7 format"
|
|
newline
|
|
hexmask.long.word 0x70 10.--19. 1. "CSCBU,Color Space Conversion U coefficient for Blue Component 1:2:7 format"
|
|
hexmask.long.word 0x70 0.--9. 1. "CSCBY,Color Space Conversion Y coefficient for Blue Component 1:2:7 format"
|
|
line.long 0x74 "HEOCFG17,High-End Overlay Configuration Register 17"
|
|
hexmask.long.byte 0x74 24.--31. 1. "XPHI0COEFF3,Horizontal Coefficient for phase 0 tap 3"
|
|
hexmask.long.byte 0x74 16.--23. 1. "XPHI0COEFF2,Horizontal Coefficient for phase 0 tap 2"
|
|
newline
|
|
hexmask.long.byte 0x74 8.--15. 1. "XPHI0COEFF1,Horizontal Coefficient for phase 0 tap 1"
|
|
hexmask.long.byte 0x74 0.--7. 1. "XPHI0COEFF0,Horizontal Coefficient for phase 0 tap 0"
|
|
line.long 0x78 "HEOCFG18,High-End Overlay Configuration Register 18"
|
|
hexmask.long.byte 0x78 0.--7. 1. "XPHI0COEFF4,Horizontal Coefficient for phase 0 tap 4"
|
|
line.long 0x7C "HEOCFG19,High-End Overlay Configuration Register 19"
|
|
hexmask.long.byte 0x7C 24.--31. 1. "XPHI1COEFF3,Horizontal Coefficient for phase 1 tap 3"
|
|
hexmask.long.byte 0x7C 16.--23. 1. "XPHI1COEFF2,Horizontal Coefficient for phase 1 tap 2"
|
|
newline
|
|
hexmask.long.byte 0x7C 8.--15. 1. "XPHI1COEFF1,Horizontal Coefficient for phase 1 tap 1"
|
|
hexmask.long.byte 0x7C 0.--7. 1. "XPHI1COEFF0,Horizontal Coefficient for phase 1 tap 0"
|
|
line.long 0x80 "HEOCFG20,High-End Overlay Configuration Register 20"
|
|
hexmask.long.byte 0x80 0.--7. 1. "XPHI1COEFF4,Horizontal Coefficient for phase 1 tap 4"
|
|
line.long 0x84 "HEOCFG21,High-End Overlay Configuration Register 21"
|
|
hexmask.long.byte 0x84 24.--31. 1. "XPHI2COEFF3,Horizontal Coefficient for phase 2 tap 3"
|
|
hexmask.long.byte 0x84 16.--23. 1. "XPHI2COEFF2,Horizontal Coefficient for phase 2 tap 2"
|
|
newline
|
|
hexmask.long.byte 0x84 8.--15. 1. "XPHI2COEFF1,Horizontal Coefficient for phase 2 tap 1"
|
|
hexmask.long.byte 0x84 0.--7. 1. "XPHI2COEFF0,Horizontal Coefficient for phase 2 tap 0"
|
|
line.long 0x88 "HEOCFG22,High-End Overlay Configuration Register 22"
|
|
hexmask.long.byte 0x88 0.--7. 1. "XPHI2COEFF4,Horizontal Coefficient for phase 2 tap 4"
|
|
line.long 0x8C "HEOCFG23,High-End Overlay Configuration Register 23"
|
|
hexmask.long.byte 0x8C 24.--31. 1. "XPHI3COEFF3,Horizontal Coefficient for phase 3 tap 3"
|
|
hexmask.long.byte 0x8C 16.--23. 1. "XPHI3COEFF2,Horizontal Coefficient for phase 3 tap 2"
|
|
newline
|
|
hexmask.long.byte 0x8C 8.--15. 1. "XPHI3COEFF1,Horizontal Coefficient for phase 3 tap 1"
|
|
hexmask.long.byte 0x8C 0.--7. 1. "XPHI3COEFF0,Horizontal Coefficient for phase 3 tap 0"
|
|
line.long 0x90 "HEOCFG24,High-End Overlay Configuration Register 24"
|
|
hexmask.long.byte 0x90 0.--7. 1. "XPHI3COEFF4,Horizontal Coefficient for phase 3 tap 4"
|
|
line.long 0x94 "HEOCFG25,High-End Overlay Configuration Register 25"
|
|
hexmask.long.byte 0x94 24.--31. 1. "XPHI4COEFF3,Horizontal Coefficient for phase 4 tap 3"
|
|
hexmask.long.byte 0x94 16.--23. 1. "XPHI4COEFF2,Horizontal Coefficient for phase 4 tap 2"
|
|
newline
|
|
hexmask.long.byte 0x94 8.--15. 1. "XPHI4COEFF1,Horizontal Coefficient for phase 4 tap 1"
|
|
hexmask.long.byte 0x94 0.--7. 1. "XPHI4COEFF0,Horizontal Coefficient for phase 4 tap 0"
|
|
line.long 0x98 "HEOCFG26,High-End Overlay Configuration Register 26"
|
|
hexmask.long.byte 0x98 0.--7. 1. "XPHI4COEFF4,Horizontal Coefficient for phase 4 tap 4"
|
|
line.long 0x9C "HEOCFG27,High-End Overlay Configuration Register 27"
|
|
hexmask.long.byte 0x9C 24.--31. 1. "XPHI5COEFF3,Horizontal Coefficient for phase 5 tap 3"
|
|
hexmask.long.byte 0x9C 16.--23. 1. "XPHI5COEFF2,Horizontal Coefficient for phase 5 tap 2"
|
|
newline
|
|
hexmask.long.byte 0x9C 8.--15. 1. "XPHI5COEFF1,Horizontal Coefficient for phase 5 tap 1"
|
|
hexmask.long.byte 0x9C 0.--7. 1. "XPHI5COEFF0,Horizontal Coefficient for phase 5 tap 0"
|
|
line.long 0xA0 "HEOCFG28,High-End Overlay Configuration Register 28"
|
|
hexmask.long.byte 0xA0 0.--7. 1. "XPHI5COEFF4,Horizontal Coefficient for phase 5 tap 4"
|
|
line.long 0xA4 "HEOCFG29,High-End Overlay Configuration Register 29"
|
|
hexmask.long.byte 0xA4 24.--31. 1. "XPHI6COEFF3,Horizontal Coefficient for phase 6 tap 3"
|
|
hexmask.long.byte 0xA4 16.--23. 1. "XPHI6COEFF2,Horizontal Coefficient for phase 6 tap 2"
|
|
newline
|
|
hexmask.long.byte 0xA4 8.--15. 1. "XPHI6COEFF1,Horizontal Coefficient for phase 6 tap 1"
|
|
hexmask.long.byte 0xA4 0.--7. 1. "XPHI6COEFF0,Horizontal Coefficient for phase 6 tap 0"
|
|
line.long 0xA8 "HEOCFG30,High-End Overlay Configuration Register 30"
|
|
hexmask.long.byte 0xA8 0.--7. 1. "XPHI6COEFF4,Horizontal Coefficient for phase 6 tap 4"
|
|
line.long 0xAC "HEOCFG31,High-End Overlay Configuration Register 31"
|
|
hexmask.long.byte 0xAC 24.--31. 1. "XPHI7COEFF3,Horizontal Coefficient for phase 7 tap 3"
|
|
hexmask.long.byte 0xAC 16.--23. 1. "XPHI7COEFF2,Horizontal Coefficient for phase 7 tap 2"
|
|
newline
|
|
hexmask.long.byte 0xAC 8.--15. 1. "XPHI7COEFF1,Horizontal Coefficient for phase 7 tap 1"
|
|
hexmask.long.byte 0xAC 0.--7. 1. "XPHI7COEFF0,Horizontal Coefficient for phase 7 tap 0"
|
|
line.long 0xB0 "HEOCFG32,High-End Overlay Configuration Register 32"
|
|
hexmask.long.byte 0xB0 0.--7. 1. "XPHI7COEFF4,Horizontal Coefficient for phase 7 tap 4"
|
|
line.long 0xB4 "HEOCFG33,High-End Overlay Configuration Register 33"
|
|
hexmask.long.byte 0xB4 16.--23. 1. "YPHI0COEFF2,Vertical Coefficient for phase 0 tap 2"
|
|
hexmask.long.byte 0xB4 8.--15. 1. "YPHI0COEFF1,Vertical Coefficient for phase 0 tap 1"
|
|
newline
|
|
hexmask.long.byte 0xB4 0.--7. 1. "YPHI0COEFF0,Vertical Coefficient for phase 0 tap 0"
|
|
line.long 0xB8 "HEOCFG34,High-End Overlay Configuration Register 34"
|
|
hexmask.long.byte 0xB8 16.--23. 1. "YPHI1COEFF2,Vertical Coefficient for phase 1 tap 2"
|
|
hexmask.long.byte 0xB8 8.--15. 1. "YPHI1COEFF1,Vertical Coefficient for phase 1 tap 1"
|
|
newline
|
|
hexmask.long.byte 0xB8 0.--7. 1. "YPHI1COEFF0,Vertical Coefficient for phase 1 tap 0"
|
|
line.long 0xBC "HEOCFG35,High-End Overlay Configuration Register 35"
|
|
hexmask.long.byte 0xBC 16.--23. 1. "YPHI2COEFF2,Vertical Coefficient for phase 2 tap 2"
|
|
hexmask.long.byte 0xBC 8.--15. 1. "YPHI2COEFF1,Vertical Coefficient for phase 2 tap 1"
|
|
newline
|
|
hexmask.long.byte 0xBC 0.--7. 1. "YPHI2COEFF0,Vertical Coefficient for phase 2 tap 0"
|
|
line.long 0xC0 "HEOCFG36,High-End Overlay Configuration Register 36"
|
|
hexmask.long.byte 0xC0 16.--23. 1. "YPHI3COEFF2,Vertical Coefficient for phase 3 tap 2"
|
|
hexmask.long.byte 0xC0 8.--15. 1. "YPHI3COEFF1,Vertical Coefficient for phase 3 tap 1"
|
|
newline
|
|
hexmask.long.byte 0xC0 0.--7. 1. "YPHI3COEFF0,Vertical Coefficient for phase 3 tap 0"
|
|
line.long 0xC4 "HEOCFG37,High-End Overlay Configuration Register 37"
|
|
hexmask.long.byte 0xC4 16.--23. 1. "YPHI4COEFF2,Vertical Coefficient for phase 4 tap 2"
|
|
hexmask.long.byte 0xC4 8.--15. 1. "YPHI4COEFF1,Vertical Coefficient for phase 4 tap 1"
|
|
newline
|
|
hexmask.long.byte 0xC4 0.--7. 1. "YPHI4COEFF0,Vertical Coefficient for phase 4 tap 0"
|
|
line.long 0xC8 "HEOCFG38,High-End Overlay Configuration Register 38"
|
|
hexmask.long.byte 0xC8 16.--23. 1. "YPHI5COEFF2,Vertical Coefficient for phase 5 tap 2"
|
|
hexmask.long.byte 0xC8 8.--15. 1. "YPHI5COEFF1,Vertical Coefficient for phase 5 tap 1"
|
|
newline
|
|
hexmask.long.byte 0xC8 0.--7. 1. "YPHI5COEFF0,Vertical Coefficient for phase 5 tap 0"
|
|
line.long 0xCC "HEOCFG39,High-End Overlay Configuration Register 39"
|
|
hexmask.long.byte 0xCC 16.--23. 1. "YPHI6COEFF2,Vertical Coefficient for phase 6 tap 2"
|
|
hexmask.long.byte 0xCC 8.--15. 1. "YPHI6COEFF1,Vertical Coefficient for phase 6 tap 1"
|
|
newline
|
|
hexmask.long.byte 0xCC 0.--7. 1. "YPHI6COEFF0,Vertical Coefficient for phase 6 tap 0"
|
|
line.long 0xD0 "HEOCFG40,High-End Overlay Configuration Register 40"
|
|
hexmask.long.byte 0xD0 16.--23. 1. "YPHI7COEFF2,Vertical Coefficient for phase 7 tap 2"
|
|
hexmask.long.byte 0xD0 8.--15. 1. "YPHI7COEFF1,Vertical Coefficient for phase 7 tap 1"
|
|
newline
|
|
hexmask.long.byte 0xD0 0.--7. 1. "YPHI7COEFF0,Vertical Coefficient for phase 7 tap 0"
|
|
line.long 0xD4 "HEOCFG41,High-End Overlay Configuration Register 41"
|
|
bitfld.long 0xD4 16.--18. "YPHIDEF,Vertical Filter Phase Offset" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xD4 0.--2. "XPHIDEF,Horizontal Filter Phase Offset" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x540++0x7
|
|
line.long 0x0 "PPCHER,Post Processing Channel Enable Register"
|
|
bitfld.long 0x0 2. "A2QEN,Add To Queue Enable" "0,1"
|
|
bitfld.long 0x0 1. "UPDATEEN,Update Overlay Attributes Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CHEN,Channel Enable" "0,1"
|
|
line.long 0x4 "PPCHDR,Post Processing Channel Disable Register"
|
|
bitfld.long 0x4 8. "CHRST,Channel Reset" "0,1"
|
|
bitfld.long 0x4 0. "CHDIS,Channel Disable" "0,1"
|
|
rgroup.long 0x548++0x3
|
|
line.long 0x0 "PPCHSR,Post Processing Channel Status Register"
|
|
bitfld.long 0x0 2. "A2QSR,Add To Queue Status" "0,1"
|
|
bitfld.long 0x0 1. "UPDATESR,Update Overlay Attributes In Progress Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CHSR,Channel Status" "0,1"
|
|
wgroup.long 0x54C++0x7
|
|
line.long 0x0 "PPIER,Post Processing Interrupt Enable Register"
|
|
bitfld.long 0x0 5. "DONE,End of List Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "ADD,Head Descriptor Loaded Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DSCR,Descriptor Loaded Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "DMA,End of DMA Transfer Interrupt Enable" "0,1"
|
|
line.long 0x4 "PPIDR,Post Processing Interrupt Disable Register"
|
|
bitfld.long 0x4 5. "DONE,End of List Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "ADD,Head Descriptor Loaded Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "DSCR,Descriptor Loaded Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "DMA,End of DMA Transfer Interrupt Disable" "0,1"
|
|
rgroup.long 0x554++0x7
|
|
line.long 0x0 "PPIMR,Post Processing Interrupt Mask Register"
|
|
bitfld.long 0x0 5. "DONE,End of List Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "ADD,Head Descriptor Loaded Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DSCR,Descriptor Loaded Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "DMA,End of DMA Transfer Interrupt Mask" "0,1"
|
|
line.long 0x4 "PPISR,Post Processing Interrupt Status Register"
|
|
bitfld.long 0x4 5. "DONE,End of List Detected" "0,1"
|
|
bitfld.long 0x4 4. "ADD,Head Descriptor Loaded" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "DSCR,DMA Descriptor Loaded" "0,1"
|
|
bitfld.long 0x4 2. "DMA,End of DMA Transfer" "0,1"
|
|
group.long 0x55C++0x27
|
|
line.long 0x0 "PPHEAD,Post Processing Head Register"
|
|
hexmask.long 0x0 2.--31. 1. "HEAD,DMA Head Pointer"
|
|
line.long 0x4 "PPADDR,Post Processing Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,DMA Transfer Start Address"
|
|
line.long 0x8 "PPCTRL,Post Processing Control Register"
|
|
bitfld.long 0x8 5. "DONEIEN,End of List Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 4. "ADDIEN,Add Head Descriptor to Queue Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "DSCRIEN,Descriptor Loaded Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 2. "DMAIEN,End of DMA Transfer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "DFETCH,Transfer Descriptor Fetch Enable" "0,1"
|
|
line.long 0xC "PPNEXT,Post Processing Next Register"
|
|
hexmask.long 0xC 0.--31. 1. "NEXT,DMA Descriptor Next Address"
|
|
line.long 0x10 "PPCFG0,Post Processing Configuration Register 0"
|
|
bitfld.long 0x10 8. "DLBO,Defined Length Burst Only For Channel Bus Transaction" "0,1"
|
|
bitfld.long 0x10 4.--5. "BLEN,AHB Burst Length" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 0. "SIF,Source Interface" "0,1"
|
|
line.long 0x14 "PPCFG1,Post Processing Configuration Register 1"
|
|
bitfld.long 0x14 4. "ITUBT601,Color Space Conversion Luminance" "0,1"
|
|
bitfld.long 0x14 0.--2. "PPMODE,Post Processing Output Format Selection" "0: RGB 16 bpp,1: RGB 24 bpp PACKED,2: RGB 24 bpp UNPACKED,3: YCbCr 422 16 bpp (Mode 0),4: YCbCr 422 16 bpp (Mode 1),5: YCbCr 422 16 bpp (Mode 2),6: YCbCr 422 16 bpp (Mode 3),?"
|
|
line.long 0x18 "PPCFG2,Post Processing Configuration Register 2"
|
|
hexmask.long 0x18 0.--31. 1. "XSTRIDE,Horizontal Stride"
|
|
line.long 0x1C "PPCFG3,Post Processing Configuration Register 3"
|
|
bitfld.long 0x1C 30. "CSCYOFF,Color Space Conversion Luminance Offset" "0,1"
|
|
hexmask.long.word 0x1C 20.--29. 1. "CSCYB,Color Space Conversion B coefficient for Luminance component signed format step set to 1/1024"
|
|
newline
|
|
hexmask.long.word 0x1C 10.--19. 1. "CSCYG,Color Space Conversion G coefficient for Luminance component signed format step set to 1/512"
|
|
hexmask.long.word 0x1C 0.--9. 1. "CSCYR,Color Space Conversion R coefficient for Luminance component signed format step set to 1/1024"
|
|
line.long 0x20 "PPCFG4,Post Processing Configuration Register 4"
|
|
bitfld.long 0x20 30. "CSCUOFF,Color Space Conversion Chrominance B Offset" "0,1"
|
|
hexmask.long.word 0x20 20.--29. 1. "CSCUB,Color Space Conversion B coefficient for Chrominance B component signed format. (step 1/512)"
|
|
newline
|
|
hexmask.long.word 0x20 10.--19. 1. "CSCUG,Color Space Conversion G coefficient for Chrominance B component signed format. (step 1/512)"
|
|
hexmask.long.word 0x20 0.--9. 1. "CSCUR,Color Space Conversion R coefficient for Chrominance B component signed format. (step 1/1024)"
|
|
line.long 0x24 "PPCFG5,Post Processing Configuration Register 5"
|
|
bitfld.long 0x24 30. "CSCVOFF,Color Space Conversion Chrominance R Offset" "0,1"
|
|
hexmask.long.word 0x24 20.--29. 1. "CSCVB,Color Space Conversion B coefficient for Chrominance R component signed format. (step 1/1024)"
|
|
newline
|
|
hexmask.long.word 0x24 10.--19. 1. "CSCVG,Color Space Conversion G coefficient for Chrominance R component signed format. (step 1/512)"
|
|
hexmask.long.word 0x24 0.--9. 1. "CSCVR,Color Space Conversion R coefficient for Chrominance R component signed format. (step 1/1024)"
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x600)++0x3
|
|
line.long 0x0 "BASECLUT[$1],Base CLUT Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RCLUT,Red Color Entry"
|
|
hexmask.long.byte 0x0 8.--15. 1. "GCLUT,Green Color Entry"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "BCLUT,Blue Color Entry"
|
|
repeat.end
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xA00)++0x3
|
|
line.long 0x0 "OVR1CLUT[$1],Overlay 1 CLUT Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ACLUT,Alpha Color Entry"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RCLUT,Red Color Entry"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "GCLUT,Green Color Entry"
|
|
hexmask.long.byte 0x0 0.--7. 1. "BCLUT,Blue Color Entry"
|
|
repeat.end
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xE00)++0x3
|
|
line.long 0x0 "OVR2CLUT[$1],Overlay 2 CLUT Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ACLUT,Alpha Color Entry"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RCLUT,Red Color Entry"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "GCLUT,Green Color Entry"
|
|
hexmask.long.byte 0x0 0.--7. 1. "BCLUT,Blue Color Entry"
|
|
repeat.end
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1200)++0x3
|
|
line.long 0x0 "HEOCLUT[$1],High-End Overlay CLUT Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ACLUT,Alpha Color Entry"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RCLUT,Red Color Entry"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "GCLUT,Green Color Entry"
|
|
hexmask.long.byte 0x0 0.--7. 1. "BCLUT,Blue Color Entry"
|
|
repeat.end
|
|
tree.end
|
|
tree "MATRIX (AHB Bus Matrix)"
|
|
base ad:0x0
|
|
tree "MATRIX0"
|
|
base ad:0xF0018000
|
|
repeat 12. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "MCFG[$1],Master Configuration Register"
|
|
bitfld.long 0x0 0.--2. "ULBT,Undefined Length Burst Type" "0: Unlimited Length Burst-No predicted end of burst..,1: Single Access-The undefined length burst is..,2: 4-beat Burst-The undefined length burst or..,3: 8-beat Burst-The undefined length burst or..,4: 16-beat Burst-The undefined length burst or..,5: 32-beat Burst-The undefined length burst or..,6: 64-beat Burst-The undefined length burst or..,7: 128-beat Burst-The undefined length burst or.."
|
|
repeat.end
|
|
repeat 15. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "SCFG[$1],Slave Configuration Register"
|
|
hexmask.long.byte 0x0 18.--21. 1. "FIXED_DEFMSTR,Fixed Default Master"
|
|
bitfld.long 0x0 16.--17. "DEFMSTR_TYPE,Default Master Type" "0: No Default Master-At the end of the current..,1: Last Default Master-At the end of the current..,2: Fixed Default Master-At the end of the current..,?"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "SLOT_CYCLE,Maximum Bus Grant Duration for Masters"
|
|
repeat.end
|
|
repeat 15. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE)(list ad:0xF0018080 ad:0xF0018088 ad:0xF0018090 ad:0xF0018098 ad:0xF00180A0 ad:0xF00180A8 ad:0xF00180B0 ad:0xF00180B8 ad:0xF00180C0 ad:0xF00180C8 ad:0xF00180D0 ad:0xF00180D8 ad:0xF00180E0 ad:0xF00180E8 ad:0xF00180F0)
|
|
tree "MATRIX_PR[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "PRAS,Priority Register A for Slave 0"
|
|
bitfld.long 0x0 28.--29. "M7PR,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "M6PR,Master 6 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "M5PR,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "M4PR,Master 4 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "M3PR,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "M2PR,Master 2 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "M1PR,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "M0PR,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x4 "PRBS,Priority Register B for Slave 0"
|
|
bitfld.long 0x4 12.--13. "M11PR,Master 11 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "M10PR,Master 10 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "M9PR,Master 9 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "M8PR,Master 8 Priority" "0,1,2,3"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0xF0018000
|
|
wgroup.long 0x150++0x7
|
|
line.long 0x0 "MEIER,Master Error Interrupt Enable Register"
|
|
bitfld.long 0x0 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x0 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x0 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x0 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x0 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x0 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x0 0. "MERR0,Master 0 Access Error" "0,1"
|
|
line.long 0x4 "MEIDR,Master Error Interrupt Disable Register"
|
|
bitfld.long 0x4 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x4 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x4 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x4 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x4 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x4 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x4 0. "MERR0,Master 0 Access Error" "0,1"
|
|
rgroup.long 0x158++0x7
|
|
line.long 0x0 "MEIMR,Master Error Interrupt Mask Register"
|
|
bitfld.long 0x0 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x0 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x0 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x0 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x0 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x0 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x0 0. "MERR0,Master 0 Access Error" "0,1"
|
|
line.long 0x4 "MESR,Master Error Status Register"
|
|
bitfld.long 0x4 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x4 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x4 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x4 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x4 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x4 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x4 0. "MERR0,Master 0 Access Error" "0,1"
|
|
repeat 12. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x160)++0x3
|
|
line.long 0x0 "MEAR[$1],Master 0 Error Address Register"
|
|
hexmask.long 0x0 0.--31. 1. "ERRADD,Master Error Address"
|
|
repeat.end
|
|
group.long 0x1E4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key (Write-only)"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x1E8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
repeat 15. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x200)++0x3
|
|
line.long 0x0 "SSR[$1],Security Slave 0 Register"
|
|
bitfld.long 0x0 23. "WRNSECH7,Write Non-secured for HSELx Security Region" "0,1"
|
|
bitfld.long 0x0 22. "WRNSECH6,Write Non-secured for HSELx Security Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "WRNSECH5,Write Non-secured for HSELx Security Region" "0,1"
|
|
bitfld.long 0x0 20. "WRNSECH4,Write Non-secured for HSELx Security Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "WRNSECH3,Write Non-secured for HSELx Security Region" "0,1"
|
|
bitfld.long 0x0 18. "WRNSECH2,Write Non-secured for HSELx Security Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "WRNSECH1,Write Non-secured for HSELx Security Region" "0,1"
|
|
bitfld.long 0x0 16. "WRNSECH0,Write Non-secured for HSELx Security Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RDNSECH7,Read Non-secured for HSELx Security Region" "0,1"
|
|
bitfld.long 0x0 14. "RDNSECH6,Read Non-secured for HSELx Security Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RDNSECH5,Read Non-secured for HSELx Security Region" "0,1"
|
|
bitfld.long 0x0 12. "RDNSECH4,Read Non-secured for HSELx Security Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RDNSECH3,Read Non-secured for HSELx Security Region" "0,1"
|
|
bitfld.long 0x0 10. "RDNSECH2,Read Non-secured for HSELx Security Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RDNSECH1,Read Non-secured for HSELx Security Region" "0,1"
|
|
bitfld.long 0x0 8. "RDNSECH0,Read Non-secured for HSELx Security Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LANSECH7,Low Area Non-secured in HSELx Security Region" "0,1"
|
|
bitfld.long 0x0 6. "LANSECH6,Low Area Non-secured in HSELx Security Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LANSECH5,Low Area Non-secured in HSELx Security Region" "0,1"
|
|
bitfld.long 0x0 4. "LANSECH4,Low Area Non-secured in HSELx Security Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "LANSECH3,Low Area Non-secured in HSELx Security Region" "0,1"
|
|
bitfld.long 0x0 2. "LANSECH2,Low Area Non-secured in HSELx Security Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LANSECH1,Low Area Non-secured in HSELx Security Region" "0,1"
|
|
bitfld.long 0x0 0. "LANSECH0,Low Area Non-secured in HSELx Security Region" "0,1"
|
|
repeat.end
|
|
repeat 15. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x240)++0x3
|
|
line.long 0x0 "SASSR[$1],Security Areas Split Slave 0 Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "SASPLIT7,Security Areas Split for HSELx Security Region"
|
|
hexmask.long.byte 0x0 24.--27. 1. "SASPLIT6,Security Areas Split for HSELx Security Region"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SASPLIT5,Security Areas Split for HSELx Security Region"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SASPLIT4,Security Areas Split for HSELx Security Region"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "SASPLIT3,Security Areas Split for HSELx Security Region"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SASPLIT2,Security Areas Split for HSELx Security Region"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "SASPLIT1,Security Areas Split for HSELx Security Region"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SASPLIT0,Security Areas Split for HSELx Security Region"
|
|
repeat.end
|
|
repeat 14. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x284)++0x3
|
|
line.long 0x0 "SRTSR[$1],Security Region Top Slave 1 Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "SRTOP7,HSELx Security Region Top"
|
|
hexmask.long.byte 0x0 24.--27. 1. "SRTOP6,HSELx Security Region Top"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SRTOP5,HSELx Security Region Top"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SRTOP4,HSELx Security Region Top"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "SRTOP3,HSELx Security Region Top"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SRTOP2,HSELx Security Region Top"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "SRTOP1,HSELx Security Region Top"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SRTOP0,HSELx Security Region Top"
|
|
repeat.end
|
|
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x2C0)++0x3
|
|
line.long 0x0 "SPSELR[$1],Security Peripheral Select 1 Register"
|
|
bitfld.long 0x0 31. "NSECP31,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 30. "NSECP30,Non-secured Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "NSECP29,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 28. "NSECP28,Non-secured Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "NSECP27,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 26. "NSECP26,Non-secured Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "NSECP25,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 24. "NSECP24,Non-secured Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "NSECP23,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 22. "NSECP22,Non-secured Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "NSECP21,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 20. "NSECP20,Non-secured Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "NSECP19,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 18. "NSECP18,Non-secured Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "NSECP17,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 16. "NSECP16,Non-secured Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "NSECP15,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 14. "NSECP14,Non-secured Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NSECP13,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 12. "NSECP12,Non-secured Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "NSECP11,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 10. "NSECP10,Non-secured Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "NSECP9,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 8. "NSECP8,Non-secured Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "NSECP7,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 6. "NSECP6,Non-secured Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "NSECP5,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 4. "NSECP4,Non-secured Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "NSECP3,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 2. "NSECP2,Non-secured Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NSECP1,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 0. "NSECP0,Non-secured Peripheral" "0,1"
|
|
repeat.end
|
|
tree.end
|
|
tree "MATRIX1"
|
|
base ad:0xFC03C000
|
|
repeat 12. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "MCFG[$1],Master Configuration Register"
|
|
bitfld.long 0x0 0.--2. "ULBT,Undefined Length Burst Type" "0: Unlimited Length Burst-No predicted end of burst..,1: Single Access-The undefined length burst is..,2: 4-beat Burst-The undefined length burst or..,3: 8-beat Burst-The undefined length burst or..,4: 16-beat Burst-The undefined length burst or..,5: 32-beat Burst-The undefined length burst or..,6: 64-beat Burst-The undefined length burst or..,7: 128-beat Burst-The undefined length burst or.."
|
|
repeat.end
|
|
repeat 15. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "SCFG[$1],Slave Configuration Register"
|
|
hexmask.long.byte 0x0 18.--21. 1. "FIXED_DEFMSTR,Fixed Default Master"
|
|
bitfld.long 0x0 16.--17. "DEFMSTR_TYPE,Default Master Type" "0: No Default Master-At the end of the current..,1: Last Default Master-At the end of the current..,2: Fixed Default Master-At the end of the current..,?"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "SLOT_CYCLE,Maximum Bus Grant Duration for Masters"
|
|
repeat.end
|
|
repeat 15. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE)(list ad:0xFC03C080 ad:0xFC03C088 ad:0xFC03C090 ad:0xFC03C098 ad:0xFC03C0A0 ad:0xFC03C0A8 ad:0xFC03C0B0 ad:0xFC03C0B8 ad:0xFC03C0C0 ad:0xFC03C0C8 ad:0xFC03C0D0 ad:0xFC03C0D8 ad:0xFC03C0E0 ad:0xFC03C0E8 ad:0xFC03C0F0)
|
|
tree "MATRIX_PR[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "PRAS,Priority Register A for Slave 0"
|
|
bitfld.long 0x0 28.--29. "M7PR,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "M6PR,Master 6 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "M5PR,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "M4PR,Master 4 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "M3PR,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "M2PR,Master 2 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "M1PR,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "M0PR,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x4 "PRBS,Priority Register B for Slave 0"
|
|
bitfld.long 0x4 12.--13. "M11PR,Master 11 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "M10PR,Master 10 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "M9PR,Master 9 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "M8PR,Master 8 Priority" "0,1,2,3"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0xFC03C000
|
|
wgroup.long 0x150++0x7
|
|
line.long 0x0 "MEIER,Master Error Interrupt Enable Register"
|
|
bitfld.long 0x0 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x0 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x0 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x0 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x0 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x0 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x0 0. "MERR0,Master 0 Access Error" "0,1"
|
|
line.long 0x4 "MEIDR,Master Error Interrupt Disable Register"
|
|
bitfld.long 0x4 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x4 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x4 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x4 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x4 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x4 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x4 0. "MERR0,Master 0 Access Error" "0,1"
|
|
rgroup.long 0x158++0x7
|
|
line.long 0x0 "MEIMR,Master Error Interrupt Mask Register"
|
|
bitfld.long 0x0 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x0 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x0 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x0 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x0 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x0 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x0 0. "MERR0,Master 0 Access Error" "0,1"
|
|
line.long 0x4 "MESR,Master Error Status Register"
|
|
bitfld.long 0x4 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x4 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x4 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x4 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x4 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x4 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x4 0. "MERR0,Master 0 Access Error" "0,1"
|
|
repeat 12. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x160)++0x3
|
|
line.long 0x0 "MEAR[$1],Master 0 Error Address Register"
|
|
hexmask.long 0x0 0.--31. 1. "ERRADD,Master Error Address"
|
|
repeat.end
|
|
group.long 0x1E4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key (Write-only)"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x1E8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
repeat 15. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x200)++0x3
|
|
line.long 0x0 "SSR[$1],Security Slave 0 Register"
|
|
bitfld.long 0x0 23. "WRNSECH7,Write Non-secured for HSELx Security Region" "0,1"
|
|
bitfld.long 0x0 22. "WRNSECH6,Write Non-secured for HSELx Security Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "WRNSECH5,Write Non-secured for HSELx Security Region" "0,1"
|
|
bitfld.long 0x0 20. "WRNSECH4,Write Non-secured for HSELx Security Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "WRNSECH3,Write Non-secured for HSELx Security Region" "0,1"
|
|
bitfld.long 0x0 18. "WRNSECH2,Write Non-secured for HSELx Security Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "WRNSECH1,Write Non-secured for HSELx Security Region" "0,1"
|
|
bitfld.long 0x0 16. "WRNSECH0,Write Non-secured for HSELx Security Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RDNSECH7,Read Non-secured for HSELx Security Region" "0,1"
|
|
bitfld.long 0x0 14. "RDNSECH6,Read Non-secured for HSELx Security Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RDNSECH5,Read Non-secured for HSELx Security Region" "0,1"
|
|
bitfld.long 0x0 12. "RDNSECH4,Read Non-secured for HSELx Security Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RDNSECH3,Read Non-secured for HSELx Security Region" "0,1"
|
|
bitfld.long 0x0 10. "RDNSECH2,Read Non-secured for HSELx Security Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RDNSECH1,Read Non-secured for HSELx Security Region" "0,1"
|
|
bitfld.long 0x0 8. "RDNSECH0,Read Non-secured for HSELx Security Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LANSECH7,Low Area Non-secured in HSELx Security Region" "0,1"
|
|
bitfld.long 0x0 6. "LANSECH6,Low Area Non-secured in HSELx Security Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LANSECH5,Low Area Non-secured in HSELx Security Region" "0,1"
|
|
bitfld.long 0x0 4. "LANSECH4,Low Area Non-secured in HSELx Security Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "LANSECH3,Low Area Non-secured in HSELx Security Region" "0,1"
|
|
bitfld.long 0x0 2. "LANSECH2,Low Area Non-secured in HSELx Security Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LANSECH1,Low Area Non-secured in HSELx Security Region" "0,1"
|
|
bitfld.long 0x0 0. "LANSECH0,Low Area Non-secured in HSELx Security Region" "0,1"
|
|
repeat.end
|
|
repeat 15. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x240)++0x3
|
|
line.long 0x0 "SASSR[$1],Security Areas Split Slave 0 Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "SASPLIT7,Security Areas Split for HSELx Security Region"
|
|
hexmask.long.byte 0x0 24.--27. 1. "SASPLIT6,Security Areas Split for HSELx Security Region"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SASPLIT5,Security Areas Split for HSELx Security Region"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SASPLIT4,Security Areas Split for HSELx Security Region"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "SASPLIT3,Security Areas Split for HSELx Security Region"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SASPLIT2,Security Areas Split for HSELx Security Region"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "SASPLIT1,Security Areas Split for HSELx Security Region"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SASPLIT0,Security Areas Split for HSELx Security Region"
|
|
repeat.end
|
|
repeat 14. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x284)++0x3
|
|
line.long 0x0 "SRTSR[$1],Security Region Top Slave 1 Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "SRTOP7,HSELx Security Region Top"
|
|
hexmask.long.byte 0x0 24.--27. 1. "SRTOP6,HSELx Security Region Top"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SRTOP5,HSELx Security Region Top"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SRTOP4,HSELx Security Region Top"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "SRTOP3,HSELx Security Region Top"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SRTOP2,HSELx Security Region Top"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "SRTOP1,HSELx Security Region Top"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SRTOP0,HSELx Security Region Top"
|
|
repeat.end
|
|
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x2C0)++0x3
|
|
line.long 0x0 "SPSELR[$1],Security Peripheral Select 1 Register"
|
|
bitfld.long 0x0 31. "NSECP31,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 30. "NSECP30,Non-secured Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "NSECP29,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 28. "NSECP28,Non-secured Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "NSECP27,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 26. "NSECP26,Non-secured Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "NSECP25,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 24. "NSECP24,Non-secured Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "NSECP23,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 22. "NSECP22,Non-secured Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "NSECP21,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 20. "NSECP20,Non-secured Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "NSECP19,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 18. "NSECP18,Non-secured Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "NSECP17,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 16. "NSECP16,Non-secured Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "NSECP15,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 14. "NSECP14,Non-secured Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NSECP13,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 12. "NSECP12,Non-secured Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "NSECP11,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 10. "NSECP10,Non-secured Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "NSECP9,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 8. "NSECP8,Non-secured Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "NSECP7,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 6. "NSECP6,Non-secured Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "NSECP5,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 4. "NSECP4,Non-secured Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "NSECP3,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 2. "NSECP2,Non-secured Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NSECP1,Non-secured Peripheral" "0,1"
|
|
bitfld.long 0x0 0. "NSECP0,Non-secured Peripheral" "0,1"
|
|
repeat.end
|
|
tree.end
|
|
tree.end
|
|
tree "MCAN (Controller Area Network)"
|
|
base ad:0x0
|
|
tree "MCAN0"
|
|
base ad:0xF8054000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "CREL,Core Release Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp Year"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp Month"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp Day"
|
|
line.long 0x4 "ENDN,Endian Register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value"
|
|
group.long 0x8++0x27
|
|
line.long 0x0 "CUST,Customer Register"
|
|
hexmask.long 0x0 0.--31. 1. "CSV,Customer-specific Value"
|
|
line.long 0x4 "DBTP,Data Bit Timing and Prescaler Register"
|
|
bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0: Transmitter Delay Compensation disabled.,1: Transmitter Delay Compensation enabled."
|
|
hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Bit Rate Prescaler"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data Time Segment Before Sample Point"
|
|
hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data Time Segment After Sample Point"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "DSJW,Data (Re) Synchronization Jump Width" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "TEST,Test Register"
|
|
bitfld.long 0x8 7. "RX,Receive Pin (read-only)" "0,1"
|
|
bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin (read/write)" "0: Reset value CANTX controlled by the CAN Core..,1: Sample Point can be monitored at pin CANTX.,2: Dominant ('0') level at pin CANTX.,3: Recessive ('1') at pin CANTX."
|
|
newline
|
|
bitfld.long 0x8 4. "LBCK,Loop Back Mode (read/write)" "0: Reset value. Loop Back mode is disabled.,1: Loop Back mode is enabled (see Section 6.1.9)."
|
|
line.long 0xC "RWD,RAM Watchdog Register"
|
|
hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value (read-only)"
|
|
hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Configuration (read/write)"
|
|
line.long 0x10 "CCCR,CC Control Register"
|
|
bitfld.long 0x10 14. "TXP,Transmit Pause (read/write write protection)" "0,1"
|
|
bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration (read/write write protection)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "PXHD,Protocol Exception Event Handling (read/write write protection)" "0,1"
|
|
bitfld.long 0x10 9. "BRSE,Bit Rate Switching Enable (read/write write protection)" "0: Bit rate switching for transmissions disabled.,1: Bit rate switching for transmissions enabled."
|
|
newline
|
|
bitfld.long 0x10 8. "FDOE,CAN FD Operation Enable (read/write write protection)" "0: FD operation disabled.,1: FD operation enabled."
|
|
bitfld.long 0x10 7. "TEST,Test Mode Enable (read/write write protection against '1')" "0: Normal operation MCAN_TEST register holds reset..,1: Test mode write access to MCAN_TEST register.."
|
|
newline
|
|
bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission (read/write write protection)" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled."
|
|
bitfld.long 0x10 5. "MON,Bus Monitoring Mode (read/write write protection against '1')" "0: Bus Monitoring mode is disabled.,1: Bus Monitoring mode is enabled."
|
|
newline
|
|
bitfld.long 0x10 4. "CSR,Clock Stop Request (read/write)" "0: No clock stop is requested.,1: Clock stop requested. When clock stop is.."
|
|
bitfld.long 0x10 3. "CSA,Clock Stop Acknowledge (read-only)" "0,1"
|
|
newline
|
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bitfld.long 0x10 2. "ASM,Restricted Operation Mode (read/write write protection against '1')" "0: Normal CAN operation.,1: Restricted Operation mode active."
|
|
bitfld.long 0x10 1. "CCE,Configuration Change Enable (read/write write protection)" "0: The processor has no write access to the..,1: The processor has write access to the protected.."
|
|
newline
|
|
bitfld.long 0x10 0. "INIT,Initialization (read/write)" "0: Normal operation.,1: Initialization is started."
|
|
line.long 0x14 "NBTP,Nominal Bit Timing and Prescaler Register"
|
|
hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal (Re) Synchronization Jump Width"
|
|
hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time Segment Before Sample Point"
|
|
hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time Segment After Sample Point"
|
|
line.long 0x18 "TSCC,Timestamp Counter Configuration Register"
|
|
hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler"
|
|
bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter value used,?"
|
|
line.long 0x1C "TSCV,Timestamp Counter Value Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter (cleared on write)"
|
|
line.long 0x20 "TOCC,Timeout Counter Configuration Register"
|
|
hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period"
|
|
bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Receive FIFO 0,3: Timeout controlled by Receive FIFO 1"
|
|
newline
|
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bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled.,1: Timeout Counter enabled."
|
|
line.long 0x24 "TOCV,Timeout Counter Value Register"
|
|
hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter (cleared on write)"
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x0 "ECR,Error Counter Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging (cleared on read)"
|
|
bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1"
|
|
newline
|
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hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter"
|
|
line.long 0x4 "PSR,Protocol Status Register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
|
|
bitfld.long 0x4 14. "PXE,Protocol Exception Event (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "RFDF,Received a CAN FD Message (cleared on read)" "0,1"
|
|
bitfld.long 0x4 12. "RBRS,BRS Flag of Last Received CAN FD Message (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "RESI,ESI Flag of Last Received CAN FD Message (cleared on read)" "0,1"
|
|
bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code (set to 111 on read)" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x4 7. "BO,Bus_Off Status" "0,1"
|
|
bitfld.long 0x4 6. "EW,Warning Status" "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "EP,Error Passive" "0,1"
|
|
bitfld.long 0x4 3.--4. "ACT,Activity" "0: Node is synchronizing on CAN communication,1: Node is neither receiver nor transmitter,2: Node is operating as receiver,3: Node is operating as transmitter"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "LEC,Last Error Code (set to 111 on read)" "0: No error occurred since LEC has been reset by..,1: More than 5 equal bits in a sequence have..,2: A fixed format part of a received frame has the..,3: The message transmitted by the MCAN was not..,4: During transmission of a message (with the..,5: During transmission of a message (or acknowledge..,6: The CRC check sum of a received message was..,7: Any read access to the Protocol Status Register.."
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "TDCR,Transmit Delay Compensation Register"
|
|
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
|
|
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "IR,Interrupt Register"
|
|
bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0,1"
|
|
bitfld.long 0x0 28. "PED,Protocol Error in Data Phase" "0,1"
|
|
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|
|
bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0,1"
|
|
bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0,1"
|
|
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|
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bitfld.long 0x0 25. "BO,Bus_Off Status" "0,1"
|
|
bitfld.long 0x0 24. "EW,Warning Status" "0,1"
|
|
newline
|
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bitfld.long 0x0 23. "EP,Error Passive" "0,1"
|
|
bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0,1"
|
|
newline
|
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bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0,1"
|
|
bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0,1"
|
|
newline
|
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bitfld.long 0x0 19. "DRX,Message stored to Dedicated Receive Buffer" "0,1"
|
|
bitfld.long 0x0 18. "TOO,Timeout Occurred" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0,1"
|
|
bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0,1"
|
|
newline
|
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bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0,1"
|
|
bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1"
|
|
newline
|
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bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1"
|
|
bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0,1"
|
|
newline
|
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bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0,1"
|
|
bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "TC,Transmission Completed" "0,1"
|
|
bitfld.long 0x0 8. "HPM,High Priority Message" "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "RF1L,Receive FIFO 1 Message Lost" "0,1"
|
|
bitfld.long 0x0 6. "RF1F,Receive FIFO 1 Full" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "RF1W,Receive FIFO 1 Watermark Reached" "0,1"
|
|
bitfld.long 0x0 4. "RF1N,Receive FIFO 1 New Message" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "RF0L,Receive FIFO 0 Message Lost" "0,1"
|
|
bitfld.long 0x0 2. "RF0F,Receive FIFO 0 Full" "0,1"
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newline
|
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bitfld.long 0x0 1. "RF0W,Receive FIFO 0 Watermark Reached" "0,1"
|
|
bitfld.long 0x0 0. "RF0N,Receive FIFO 0 New Message" "0,1"
|
|
line.long 0x4 "IE,Interrupt Enable Register"
|
|
bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0,1"
|
|
bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0,1"
|
|
newline
|
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bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0,1"
|
|
bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Receive Buffer Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "RF1LE,Receive FIFO 1 Message Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 6. "RF1FE,Receive FIFO 1 Full Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "RF1WE,Receive FIFO 1 Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 4. "RF1NE,Receive FIFO 1 New Message Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x4 3. "RF0LE,Receive FIFO 0 Message Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 2. "RF0FE,Receive FIFO 0 Full Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x4 1. "RF0WE,Receive FIFO 0 Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "RF0NE,Receive FIFO 0 New Message Interrupt Enable" "0,1"
|
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line.long 0x8 "ILS,Interrupt Line Select Register"
|
|
bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0,1"
|
|
bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0,1"
|
|
bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
|
|
bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0,1"
|
|
bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1"
|
|
bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Receive Buffer Interrupt Line" "0,1"
|
|
bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
|
|
bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
|
|
bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0,1"
|
|
bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 7. "RF1LL,Receive FIFO 1 Message Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 6. "RF1FL,Receive FIFO 1 Full Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 5. "RF1WL,Receive FIFO 1 Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 4. "RF1NL,Receive FIFO 1 New Message Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 3. "RF0LL,Receive FIFO 0 Message Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 2. "RF0FL,Receive FIFO 0 Full Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 1. "RF0WL,Receive FIFO 0 Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 0. "RF0NL,Receive FIFO 0 New Message Interrupt Line" "0,1"
|
|
line.long 0xC "ILE,Interrupt Line Enable Register"
|
|
bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0,1"
|
|
bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0,1"
|
|
group.long 0x80++0xB
|
|
line.long 0x0 "GFC,Global Filter Configuration Register"
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
|
|
newline
|
|
bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs.,1: Reject all remote frames with 11-bit standard IDs."
|
|
bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs.,1: Reject all remote frames with 29-bit extended IDs."
|
|
line.long 0x4 "SIDFC,Standard ID Filter Configuration Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard"
|
|
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address"
|
|
line.long 0x8 "XIDFC,Extended ID Filter Configuration Register"
|
|
hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended"
|
|
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "XIDAM,Extended ID AND Mask Register"
|
|
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask"
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x0 "HPMS,High Priority Message Status Register"
|
|
bitfld.long 0x0 15. "FLST,Filter List" "0,1"
|
|
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected.,1: FIFO message lost.,2: Message stored in FIFO 0.,3: Message stored in FIFO 1."
|
|
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index"
|
|
group.long 0x98++0xB
|
|
line.long 0x0 "NDAT1,New Data 1 Register"
|
|
bitfld.long 0x0 31. "ND31,New Data" "0,1"
|
|
bitfld.long 0x0 30. "ND30,New Data" "0,1"
|
|
newline
|
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bitfld.long 0x0 29. "ND29,New Data" "0,1"
|
|
bitfld.long 0x0 28. "ND28,New Data" "0,1"
|
|
newline
|
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bitfld.long 0x0 27. "ND27,New Data" "0,1"
|
|
bitfld.long 0x0 26. "ND26,New Data" "0,1"
|
|
newline
|
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bitfld.long 0x0 25. "ND25,New Data" "0,1"
|
|
bitfld.long 0x0 24. "ND24,New Data" "0,1"
|
|
newline
|
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bitfld.long 0x0 23. "ND23,New Data" "0,1"
|
|
bitfld.long 0x0 22. "ND22,New Data" "0,1"
|
|
newline
|
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bitfld.long 0x0 21. "ND21,New Data" "0,1"
|
|
bitfld.long 0x0 20. "ND20,New Data" "0,1"
|
|
newline
|
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bitfld.long 0x0 19. "ND19,New Data" "0,1"
|
|
bitfld.long 0x0 18. "ND18,New Data" "0,1"
|
|
newline
|
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bitfld.long 0x0 17. "ND17,New Data" "0,1"
|
|
bitfld.long 0x0 16. "ND16,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "ND15,New Data" "0,1"
|
|
bitfld.long 0x0 14. "ND14,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ND13,New Data" "0,1"
|
|
bitfld.long 0x0 12. "ND12,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ND11,New Data" "0,1"
|
|
bitfld.long 0x0 10. "ND10,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ND9,New Data" "0,1"
|
|
bitfld.long 0x0 8. "ND8,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ND7,New Data" "0,1"
|
|
bitfld.long 0x0 6. "ND6,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ND5,New Data" "0,1"
|
|
bitfld.long 0x0 4. "ND4,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ND3,New Data" "0,1"
|
|
bitfld.long 0x0 2. "ND2,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ND1,New Data" "0,1"
|
|
bitfld.long 0x0 0. "ND0,New Data" "0,1"
|
|
line.long 0x4 "NDAT2,New Data 2 Register"
|
|
bitfld.long 0x4 31. "ND63,New Data" "0,1"
|
|
bitfld.long 0x4 30. "ND62,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "ND61,New Data" "0,1"
|
|
bitfld.long 0x4 28. "ND60,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "ND59,New Data" "0,1"
|
|
bitfld.long 0x4 26. "ND58,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "ND57,New Data" "0,1"
|
|
bitfld.long 0x4 24. "ND56,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "ND55,New Data" "0,1"
|
|
bitfld.long 0x4 22. "ND54,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "ND53,New Data" "0,1"
|
|
bitfld.long 0x4 20. "ND52,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "ND51,New Data" "0,1"
|
|
bitfld.long 0x4 18. "ND50,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "ND49,New Data" "0,1"
|
|
bitfld.long 0x4 16. "ND48,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "ND47,New Data" "0,1"
|
|
bitfld.long 0x4 14. "ND46,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ND45,New Data" "0,1"
|
|
bitfld.long 0x4 12. "ND44,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "ND43,New Data" "0,1"
|
|
bitfld.long 0x4 10. "ND42,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "ND41,New Data" "0,1"
|
|
bitfld.long 0x4 8. "ND40,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "ND39,New Data" "0,1"
|
|
bitfld.long 0x4 6. "ND38,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "ND37,New Data" "0,1"
|
|
bitfld.long 0x4 4. "ND36,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ND35,New Data" "0,1"
|
|
bitfld.long 0x4 2. "ND34,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ND33,New Data" "0,1"
|
|
bitfld.long 0x4 0. "ND32,New Data" "0,1"
|
|
line.long 0x8 "RXF0C,Receive FIFO 0 Configuration Register"
|
|
bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0,1"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Receive FIFO 0 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F0S,Receive FIFO 0 Start Address"
|
|
hexmask.long.word 0x8 2.--15. 1. "F0SA,Receive FIFO 0 Start Address"
|
|
rgroup.long 0xA4++0x3
|
|
line.long 0x0 "RXF0S,Receive FIFO 0 Status Register"
|
|
bitfld.long 0x0 25. "RF0L,Receive FIFO 0 Message Lost" "0,1"
|
|
bitfld.long 0x0 24. "F0F,Receive FIFO 0 Fill Level" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "F0PI,Receive FIFO 0 Put Index"
|
|
hexmask.long.byte 0x0 8.--13. 1. "F0GI,Receive FIFO 0 Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "F0FL,Receive FIFO 0 Fill Level"
|
|
group.long 0xA8++0xB
|
|
line.long 0x0 "RXF0A,Receive FIFO 0 Acknowledge Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F0AI,Receive FIFO 0 Acknowledge Index"
|
|
line.long 0x4 "RXBC,Receive Rx Buffer Configuration Register"
|
|
hexmask.long.word 0x4 2.--15. 1. "RBSA,Receive Buffer Start Address"
|
|
line.long 0x8 "RXF1C,Receive FIFO 1 Configuration Register"
|
|
bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0,1"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F1WM,Receive FIFO 1 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F1S,Receive FIFO 1 Start Address"
|
|
hexmask.long.word 0x8 2.--15. 1. "F1SA,Receive FIFO 1 Start Address"
|
|
rgroup.long 0xB4++0x3
|
|
line.long 0x0 "RXF1S,Receive FIFO 1 Status Register"
|
|
bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages..,1: Debug message A received.,2: Debug messages A B received.,3: Debug messages A B C received DMA request is set."
|
|
bitfld.long 0x0 25. "RF1L,Receive FIFO 1 Message Lost" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "F1F,Receive FIFO 1 Fill Level" "0,1"
|
|
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Receive FIFO 1 Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Receive FIFO 1 Get Index"
|
|
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Receive FIFO 1 Fill Level"
|
|
group.long 0xB8++0xB
|
|
line.long 0x0 "RXF1A,Receive FIFO 1 Acknowledge Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Receive FIFO 1 Acknowledge Index"
|
|
line.long 0x4 "RXESC,Receive Buffer / FIFO Element Size Configuration Register"
|
|
bitfld.long 0x4 8.--10. "RBDS,Receive Buffer Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field"
|
|
bitfld.long 0x4 4.--6. "F1DS,Receive FIFO 1 Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "F0DS,Receive FIFO 0 Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field"
|
|
line.long 0x8 "TXBC,Transmit Buffer Configuration Register"
|
|
bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1"
|
|
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
|
|
hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address"
|
|
rgroup.long 0xC4++0x3
|
|
line.long 0x0 "TXFQS,Transmit FIFO/Queue Status Register"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index"
|
|
hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level"
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "TXESC,Transmit Buffer Element Size Configuration Register"
|
|
bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48- byte data field,7: 64-byte data field"
|
|
rgroup.long 0xCC++0x3
|
|
line.long 0x0 "TXBRP,Transmit Buffer Request Pending Register"
|
|
bitfld.long 0x0 31. "TRP31,Transmission Request Pending for Buffer 31" "0,1"
|
|
bitfld.long 0x0 30. "TRP30,Transmission Request Pending for Buffer 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TRP29,Transmission Request Pending for Buffer 29" "0,1"
|
|
bitfld.long 0x0 28. "TRP28,Transmission Request Pending for Buffer 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "TRP27,Transmission Request Pending for Buffer 27" "0,1"
|
|
bitfld.long 0x0 26. "TRP26,Transmission Request Pending for Buffer 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TRP25,Transmission Request Pending for Buffer 25" "0,1"
|
|
bitfld.long 0x0 24. "TRP24,Transmission Request Pending for Buffer 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TRP23,Transmission Request Pending for Buffer 23" "0,1"
|
|
bitfld.long 0x0 22. "TRP22,Transmission Request Pending for Buffer 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TRP21,Transmission Request Pending for Buffer 21" "0,1"
|
|
bitfld.long 0x0 20. "TRP20,Transmission Request Pending for Buffer 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TRP19,Transmission Request Pending for Buffer 19" "0,1"
|
|
bitfld.long 0x0 18. "TRP18,Transmission Request Pending for Buffer 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TRP17,Transmission Request Pending for Buffer 17" "0,1"
|
|
bitfld.long 0x0 16. "TRP16,Transmission Request Pending for Buffer 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TRP15,Transmission Request Pending for Buffer 15" "0,1"
|
|
bitfld.long 0x0 14. "TRP14,Transmission Request Pending for Buffer 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TRP13,Transmission Request Pending for Buffer 13" "0,1"
|
|
bitfld.long 0x0 12. "TRP12,Transmission Request Pending for Buffer 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TRP11,Transmission Request Pending for Buffer 11" "0,1"
|
|
bitfld.long 0x0 10. "TRP10,Transmission Request Pending for Buffer 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TRP9,Transmission Request Pending for Buffer 9" "0,1"
|
|
bitfld.long 0x0 8. "TRP8,Transmission Request Pending for Buffer 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TRP7,Transmission Request Pending for Buffer 7" "0,1"
|
|
bitfld.long 0x0 6. "TRP6,Transmission Request Pending for Buffer 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TRP5,Transmission Request Pending for Buffer 5" "0,1"
|
|
bitfld.long 0x0 4. "TRP4,Transmission Request Pending for Buffer 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TRP3,Transmission Request Pending for Buffer 3" "0,1"
|
|
bitfld.long 0x0 2. "TRP2,Transmission Request Pending for Buffer 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TRP1,Transmission Request Pending for Buffer 1" "0,1"
|
|
bitfld.long 0x0 0. "TRP0,Transmission Request Pending for Buffer 0" "0,1"
|
|
group.long 0xD0++0x7
|
|
line.long 0x0 "TXBAR,Transmit Buffer Add Request Register"
|
|
bitfld.long 0x0 31. "AR31,Add Request for Transmit Buffer 31" "0,1"
|
|
bitfld.long 0x0 30. "AR30,Add Request for Transmit Buffer 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "AR29,Add Request for Transmit Buffer 29" "0,1"
|
|
bitfld.long 0x0 28. "AR28,Add Request for Transmit Buffer 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "AR27,Add Request for Transmit Buffer 27" "0,1"
|
|
bitfld.long 0x0 26. "AR26,Add Request for Transmit Buffer 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "AR25,Add Request for Transmit Buffer 25" "0,1"
|
|
bitfld.long 0x0 24. "AR24,Add Request for Transmit Buffer 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "AR23,Add Request for Transmit Buffer 23" "0,1"
|
|
bitfld.long 0x0 22. "AR22,Add Request for Transmit Buffer 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "AR21,Add Request for Transmit Buffer 21" "0,1"
|
|
bitfld.long 0x0 20. "AR20,Add Request for Transmit Buffer 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "AR19,Add Request for Transmit Buffer 19" "0,1"
|
|
bitfld.long 0x0 18. "AR18,Add Request for Transmit Buffer 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "AR17,Add Request for Transmit Buffer 17" "0,1"
|
|
bitfld.long 0x0 16. "AR16,Add Request for Transmit Buffer 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "AR15,Add Request for Transmit Buffer 15" "0,1"
|
|
bitfld.long 0x0 14. "AR14,Add Request for Transmit Buffer 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "AR13,Add Request for Transmit Buffer 13" "0,1"
|
|
bitfld.long 0x0 12. "AR12,Add Request for Transmit Buffer 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "AR11,Add Request for Transmit Buffer 11" "0,1"
|
|
bitfld.long 0x0 10. "AR10,Add Request for Transmit Buffer 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "AR9,Add Request for Transmit Buffer 9" "0,1"
|
|
bitfld.long 0x0 8. "AR8,Add Request for Transmit Buffer 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "AR7,Add Request for Transmit Buffer 7" "0,1"
|
|
bitfld.long 0x0 6. "AR6,Add Request for Transmit Buffer 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "AR5,Add Request for Transmit Buffer 5" "0,1"
|
|
bitfld.long 0x0 4. "AR4,Add Request for Transmit Buffer 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "AR3,Add Request for Transmit Buffer 3" "0,1"
|
|
bitfld.long 0x0 2. "AR2,Add Request for Transmit Buffer 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "AR1,Add Request for Transmit Buffer 1" "0,1"
|
|
bitfld.long 0x0 0. "AR0,Add Request for Transmit Buffer 0" "0,1"
|
|
line.long 0x4 "TXBCR,Transmit Buffer Cancellation Request Register"
|
|
bitfld.long 0x4 31. "CR31,Cancellation Request for Transmit Buffer 31" "0,1"
|
|
bitfld.long 0x4 30. "CR30,Cancellation Request for Transmit Buffer 30" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "CR29,Cancellation Request for Transmit Buffer 29" "0,1"
|
|
bitfld.long 0x4 28. "CR28,Cancellation Request for Transmit Buffer 28" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "CR27,Cancellation Request for Transmit Buffer 27" "0,1"
|
|
bitfld.long 0x4 26. "CR26,Cancellation Request for Transmit Buffer 26" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "CR25,Cancellation Request for Transmit Buffer 25" "0,1"
|
|
bitfld.long 0x4 24. "CR24,Cancellation Request for Transmit Buffer 24" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CR23,Cancellation Request for Transmit Buffer 23" "0,1"
|
|
bitfld.long 0x4 22. "CR22,Cancellation Request for Transmit Buffer 22" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "CR21,Cancellation Request for Transmit Buffer 21" "0,1"
|
|
bitfld.long 0x4 20. "CR20,Cancellation Request for Transmit Buffer 20" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CR19,Cancellation Request for Transmit Buffer 19" "0,1"
|
|
bitfld.long 0x4 18. "CR18,Cancellation Request for Transmit Buffer 18" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CR17,Cancellation Request for Transmit Buffer 17" "0,1"
|
|
bitfld.long 0x4 16. "CR16,Cancellation Request for Transmit Buffer 16" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CR15,Cancellation Request for Transmit Buffer 15" "0,1"
|
|
bitfld.long 0x4 14. "CR14,Cancellation Request for Transmit Buffer 14" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CR13,Cancellation Request for Transmit Buffer 13" "0,1"
|
|
bitfld.long 0x4 12. "CR12,Cancellation Request for Transmit Buffer 12" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CR11,Cancellation Request for Transmit Buffer 11" "0,1"
|
|
bitfld.long 0x4 10. "CR10,Cancellation Request for Transmit Buffer 10" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CR9,Cancellation Request for Transmit Buffer 9" "0,1"
|
|
bitfld.long 0x4 8. "CR8,Cancellation Request for Transmit Buffer 8" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CR7,Cancellation Request for Transmit Buffer 7" "0,1"
|
|
bitfld.long 0x4 6. "CR6,Cancellation Request for Transmit Buffer 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CR5,Cancellation Request for Transmit Buffer 5" "0,1"
|
|
bitfld.long 0x4 4. "CR4,Cancellation Request for Transmit Buffer 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CR3,Cancellation Request for Transmit Buffer 3" "0,1"
|
|
bitfld.long 0x4 2. "CR2,Cancellation Request for Transmit Buffer 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CR1,Cancellation Request for Transmit Buffer 1" "0,1"
|
|
bitfld.long 0x4 0. "CR0,Cancellation Request for Transmit Buffer 0" "0,1"
|
|
rgroup.long 0xD8++0x7
|
|
line.long 0x0 "TXBTO,Transmit Buffer Transmission Occurred Register"
|
|
bitfld.long 0x0 31. "TO31,Transmission Occurred for Buffer 31" "0,1"
|
|
bitfld.long 0x0 30. "TO30,Transmission Occurred for Buffer 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TO29,Transmission Occurred for Buffer 29" "0,1"
|
|
bitfld.long 0x0 28. "TO28,Transmission Occurred for Buffer 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "TO27,Transmission Occurred for Buffer 27" "0,1"
|
|
bitfld.long 0x0 26. "TO26,Transmission Occurred for Buffer 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TO25,Transmission Occurred for Buffer 25" "0,1"
|
|
bitfld.long 0x0 24. "TO24,Transmission Occurred for Buffer 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TO23,Transmission Occurred for Buffer 23" "0,1"
|
|
bitfld.long 0x0 22. "TO22,Transmission Occurred for Buffer 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TO21,Transmission Occurred for Buffer 21" "0,1"
|
|
bitfld.long 0x0 20. "TO20,Transmission Occurred for Buffer 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TO19,Transmission Occurred for Buffer 19" "0,1"
|
|
bitfld.long 0x0 18. "TO18,Transmission Occurred for Buffer 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TO17,Transmission Occurred for Buffer 17" "0,1"
|
|
bitfld.long 0x0 16. "TO16,Transmission Occurred for Buffer 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TO15,Transmission Occurred for Buffer 15" "0,1"
|
|
bitfld.long 0x0 14. "TO14,Transmission Occurred for Buffer 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TO13,Transmission Occurred for Buffer 13" "0,1"
|
|
bitfld.long 0x0 12. "TO12,Transmission Occurred for Buffer 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TO11,Transmission Occurred for Buffer 11" "0,1"
|
|
bitfld.long 0x0 10. "TO10,Transmission Occurred for Buffer 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TO9,Transmission Occurred for Buffer 9" "0,1"
|
|
bitfld.long 0x0 8. "TO8,Transmission Occurred for Buffer 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TO7,Transmission Occurred for Buffer 7" "0,1"
|
|
bitfld.long 0x0 6. "TO6,Transmission Occurred for Buffer 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TO5,Transmission Occurred for Buffer 5" "0,1"
|
|
bitfld.long 0x0 4. "TO4,Transmission Occurred for Buffer 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TO3,Transmission Occurred for Buffer 3" "0,1"
|
|
bitfld.long 0x0 2. "TO2,Transmission Occurred for Buffer 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TO1,Transmission Occurred for Buffer 1" "0,1"
|
|
bitfld.long 0x0 0. "TO0,Transmission Occurred for Buffer 0" "0,1"
|
|
line.long 0x4 "TXBCF,Transmit Buffer Cancellation Finished Register"
|
|
bitfld.long 0x4 31. "CF31,Cancellation Finished for Transmit Buffer 31" "0,1"
|
|
bitfld.long 0x4 30. "CF30,Cancellation Finished for Transmit Buffer 30" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "CF29,Cancellation Finished for Transmit Buffer 29" "0,1"
|
|
bitfld.long 0x4 28. "CF28,Cancellation Finished for Transmit Buffer 28" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "CF27,Cancellation Finished for Transmit Buffer 27" "0,1"
|
|
bitfld.long 0x4 26. "CF26,Cancellation Finished for Transmit Buffer 26" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "CF25,Cancellation Finished for Transmit Buffer 25" "0,1"
|
|
bitfld.long 0x4 24. "CF24,Cancellation Finished for Transmit Buffer 24" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CF23,Cancellation Finished for Transmit Buffer 23" "0,1"
|
|
bitfld.long 0x4 22. "CF22,Cancellation Finished for Transmit Buffer 22" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "CF21,Cancellation Finished for Transmit Buffer 21" "0,1"
|
|
bitfld.long 0x4 20. "CF20,Cancellation Finished for Transmit Buffer 20" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CF19,Cancellation Finished for Transmit Buffer 19" "0,1"
|
|
bitfld.long 0x4 18. "CF18,Cancellation Finished for Transmit Buffer 18" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CF17,Cancellation Finished for Transmit Buffer 17" "0,1"
|
|
bitfld.long 0x4 16. "CF16,Cancellation Finished for Transmit Buffer 16" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CF15,Cancellation Finished for Transmit Buffer 15" "0,1"
|
|
bitfld.long 0x4 14. "CF14,Cancellation Finished for Transmit Buffer 14" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CF13,Cancellation Finished for Transmit Buffer 13" "0,1"
|
|
bitfld.long 0x4 12. "CF12,Cancellation Finished for Transmit Buffer 12" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CF11,Cancellation Finished for Transmit Buffer 11" "0,1"
|
|
bitfld.long 0x4 10. "CF10,Cancellation Finished for Transmit Buffer 10" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CF9,Cancellation Finished for Transmit Buffer 9" "0,1"
|
|
bitfld.long 0x4 8. "CF8,Cancellation Finished for Transmit Buffer 8" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CF7,Cancellation Finished for Transmit Buffer 7" "0,1"
|
|
bitfld.long 0x4 6. "CF6,Cancellation Finished for Transmit Buffer 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CF5,Cancellation Finished for Transmit Buffer 5" "0,1"
|
|
bitfld.long 0x4 4. "CF4,Cancellation Finished for Transmit Buffer 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CF3,Cancellation Finished for Transmit Buffer 3" "0,1"
|
|
bitfld.long 0x4 2. "CF2,Cancellation Finished for Transmit Buffer 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CF1,Cancellation Finished for Transmit Buffer 1" "0,1"
|
|
bitfld.long 0x4 0. "CF0,Cancellation Finished for Transmit Buffer 0" "0,1"
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "TXBTIE,Transmit Buffer Transmission Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable for Buffer 31" "0,1"
|
|
bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable for Buffer 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable for Buffer 29" "0,1"
|
|
bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable for Buffer 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable for Buffer 27" "0,1"
|
|
bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable for Buffer 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable for Buffer 25" "0,1"
|
|
bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable for Buffer 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable for Buffer 23" "0,1"
|
|
bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable for Buffer 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable for Buffer 21" "0,1"
|
|
bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable for Buffer 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable for Buffer 19" "0,1"
|
|
bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable for Buffer 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable for Buffer 17" "0,1"
|
|
bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable for Buffer 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable for Buffer 15" "0,1"
|
|
bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable for Buffer 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable for Buffer 13" "0,1"
|
|
bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable for Buffer 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable for Buffer 11" "0,1"
|
|
bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable for Buffer 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable for Buffer 9" "0,1"
|
|
bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable for Buffer 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable for Buffer 7" "0,1"
|
|
bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable for Buffer 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable for Buffer 5" "0,1"
|
|
bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable for Buffer 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable for Buffer 3" "0,1"
|
|
bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable for Buffer 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable for Buffer 1" "0,1"
|
|
bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable for Buffer 0" "0,1"
|
|
line.long 0x4 "TXBCIE,Transmit Buffer Cancellation Finished Interrupt Enable Register"
|
|
bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable for Transmit Buffer 31" "0,1"
|
|
bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable for Transmit Buffer 30" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable for Transmit Buffer 29" "0,1"
|
|
bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable for Transmit Buffer 28" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable for Transmit Buffer 27" "0,1"
|
|
bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable for Transmit Buffer 26" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable for Transmit Buffer 25" "0,1"
|
|
bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable for Transmit Buffer 24" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable for Transmit Buffer 23" "0,1"
|
|
bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable for Transmit Buffer 22" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable for Transmit Buffer 21" "0,1"
|
|
bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable for Transmit Buffer 20" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable for Transmit Buffer 19" "0,1"
|
|
bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable for Transmit Buffer 18" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable for Transmit Buffer 17" "0,1"
|
|
bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable for Transmit Buffer 16" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable for Transmit Buffer 15" "0,1"
|
|
bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable for Transmit Buffer 14" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable for Transmit Buffer 13" "0,1"
|
|
bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable for Transmit Buffer 12" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable for Transmit Buffer 11" "0,1"
|
|
bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable for Transmit Buffer 10" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable for Transmit Buffer 9" "0,1"
|
|
bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable for Transmit Buffer 8" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable for Transmit Buffer 7" "0,1"
|
|
bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable for Transmit Buffer 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable for Transmit Buffer 5" "0,1"
|
|
bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable for Transmit Buffer 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable for Transmit Buffer 3" "0,1"
|
|
bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable for Transmit Buffer 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable for Transmit Buffer 1" "0,1"
|
|
bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable for Transmit Buffer 0" "0,1"
|
|
group.long 0xF0++0x3
|
|
line.long 0x0 "TXEFC,Transmit Event FIFO Configuration Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark"
|
|
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address"
|
|
rgroup.long 0xF4++0x3
|
|
line.long 0x0 "TXEFS,Transmit Event FIFO Status Register"
|
|
bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index"
|
|
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level"
|
|
group.long 0xF8++0x3
|
|
line.long 0x0 "TXEFA,Transmit Event FIFO Acknowledge Register"
|
|
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index"
|
|
tree.end
|
|
tree "MCAN1"
|
|
base ad:0xFC050000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "CREL,Core Release Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp Year"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp Month"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp Day"
|
|
line.long 0x4 "ENDN,Endian Register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value"
|
|
group.long 0x8++0x27
|
|
line.long 0x0 "CUST,Customer Register"
|
|
hexmask.long 0x0 0.--31. 1. "CSV,Customer-specific Value"
|
|
line.long 0x4 "DBTP,Data Bit Timing and Prescaler Register"
|
|
bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0: Transmitter Delay Compensation disabled.,1: Transmitter Delay Compensation enabled."
|
|
hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Bit Rate Prescaler"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data Time Segment Before Sample Point"
|
|
hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data Time Segment After Sample Point"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "DSJW,Data (Re) Synchronization Jump Width" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "TEST,Test Register"
|
|
bitfld.long 0x8 7. "RX,Receive Pin (read-only)" "0,1"
|
|
bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin (read/write)" "0: Reset value CANTX controlled by the CAN Core..,1: Sample Point can be monitored at pin CANTX.,2: Dominant ('0') level at pin CANTX.,3: Recessive ('1') at pin CANTX."
|
|
newline
|
|
bitfld.long 0x8 4. "LBCK,Loop Back Mode (read/write)" "0: Reset value. Loop Back mode is disabled.,1: Loop Back mode is enabled (see Section 6.1.9)."
|
|
line.long 0xC "RWD,RAM Watchdog Register"
|
|
hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value (read-only)"
|
|
hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Configuration (read/write)"
|
|
line.long 0x10 "CCCR,CC Control Register"
|
|
bitfld.long 0x10 14. "TXP,Transmit Pause (read/write write protection)" "0,1"
|
|
bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration (read/write write protection)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "PXHD,Protocol Exception Event Handling (read/write write protection)" "0,1"
|
|
bitfld.long 0x10 9. "BRSE,Bit Rate Switching Enable (read/write write protection)" "0: Bit rate switching for transmissions disabled.,1: Bit rate switching for transmissions enabled."
|
|
newline
|
|
bitfld.long 0x10 8. "FDOE,CAN FD Operation Enable (read/write write protection)" "0: FD operation disabled.,1: FD operation enabled."
|
|
bitfld.long 0x10 7. "TEST,Test Mode Enable (read/write write protection against '1')" "0: Normal operation MCAN_TEST register holds reset..,1: Test mode write access to MCAN_TEST register.."
|
|
newline
|
|
bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission (read/write write protection)" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled."
|
|
bitfld.long 0x10 5. "MON,Bus Monitoring Mode (read/write write protection against '1')" "0: Bus Monitoring mode is disabled.,1: Bus Monitoring mode is enabled."
|
|
newline
|
|
bitfld.long 0x10 4. "CSR,Clock Stop Request (read/write)" "0: No clock stop is requested.,1: Clock stop requested. When clock stop is.."
|
|
bitfld.long 0x10 3. "CSA,Clock Stop Acknowledge (read-only)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "ASM,Restricted Operation Mode (read/write write protection against '1')" "0: Normal CAN operation.,1: Restricted Operation mode active."
|
|
bitfld.long 0x10 1. "CCE,Configuration Change Enable (read/write write protection)" "0: The processor has no write access to the..,1: The processor has write access to the protected.."
|
|
newline
|
|
bitfld.long 0x10 0. "INIT,Initialization (read/write)" "0: Normal operation.,1: Initialization is started."
|
|
line.long 0x14 "NBTP,Nominal Bit Timing and Prescaler Register"
|
|
hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal (Re) Synchronization Jump Width"
|
|
hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time Segment Before Sample Point"
|
|
hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time Segment After Sample Point"
|
|
line.long 0x18 "TSCC,Timestamp Counter Configuration Register"
|
|
hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler"
|
|
bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter value used,?"
|
|
line.long 0x1C "TSCV,Timestamp Counter Value Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter (cleared on write)"
|
|
line.long 0x20 "TOCC,Timeout Counter Configuration Register"
|
|
hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period"
|
|
bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Receive FIFO 0,3: Timeout controlled by Receive FIFO 1"
|
|
newline
|
|
bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled.,1: Timeout Counter enabled."
|
|
line.long 0x24 "TOCV,Timeout Counter Value Register"
|
|
hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter (cleared on write)"
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x0 "ECR,Error Counter Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging (cleared on read)"
|
|
bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter"
|
|
line.long 0x4 "PSR,Protocol Status Register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
|
|
bitfld.long 0x4 14. "PXE,Protocol Exception Event (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "RFDF,Received a CAN FD Message (cleared on read)" "0,1"
|
|
bitfld.long 0x4 12. "RBRS,BRS Flag of Last Received CAN FD Message (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "RESI,ESI Flag of Last Received CAN FD Message (cleared on read)" "0,1"
|
|
bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code (set to 111 on read)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 7. "BO,Bus_Off Status" "0,1"
|
|
bitfld.long 0x4 6. "EW,Warning Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "EP,Error Passive" "0,1"
|
|
bitfld.long 0x4 3.--4. "ACT,Activity" "0: Node is synchronizing on CAN communication,1: Node is neither receiver nor transmitter,2: Node is operating as receiver,3: Node is operating as transmitter"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "LEC,Last Error Code (set to 111 on read)" "0: No error occurred since LEC has been reset by..,1: More than 5 equal bits in a sequence have..,2: A fixed format part of a received frame has the..,3: The message transmitted by the MCAN was not..,4: During transmission of a message (with the..,5: During transmission of a message (or acknowledge..,6: The CRC check sum of a received message was..,7: Any read access to the Protocol Status Register.."
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "TDCR,Transmit Delay Compensation Register"
|
|
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
|
|
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "IR,Interrupt Register"
|
|
bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0,1"
|
|
bitfld.long 0x0 28. "PED,Protocol Error in Data Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0,1"
|
|
bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "BO,Bus_Off Status" "0,1"
|
|
bitfld.long 0x0 24. "EW,Warning Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "EP,Error Passive" "0,1"
|
|
bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0,1"
|
|
bitfld.long 0x0 20. "BEC,Bit Error Corrected" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "DRX,Message stored to Dedicated Receive Buffer" "0,1"
|
|
bitfld.long 0x0 18. "TOO,Timeout Occurred" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0,1"
|
|
bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0,1"
|
|
bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1"
|
|
bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0,1"
|
|
bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TC,Transmission Completed" "0,1"
|
|
bitfld.long 0x0 8. "HPM,High Priority Message" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RF1L,Receive FIFO 1 Message Lost" "0,1"
|
|
bitfld.long 0x0 6. "RF1F,Receive FIFO 1 Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RF1W,Receive FIFO 1 Watermark Reached" "0,1"
|
|
bitfld.long 0x0 4. "RF1N,Receive FIFO 1 New Message" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RF0L,Receive FIFO 0 Message Lost" "0,1"
|
|
bitfld.long 0x0 2. "RF0F,Receive FIFO 0 Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RF0W,Receive FIFO 0 Watermark Reached" "0,1"
|
|
bitfld.long 0x0 0. "RF0N,Receive FIFO 0 New Message" "0,1"
|
|
line.long 0x4 "IE,Interrupt Enable Register"
|
|
bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0,1"
|
|
bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0,1"
|
|
bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Receive Buffer Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RF1LE,Receive FIFO 1 Message Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 6. "RF1FE,Receive FIFO 1 Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RF1WE,Receive FIFO 1 Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 4. "RF1NE,Receive FIFO 1 New Message Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RF0LE,Receive FIFO 0 Message Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 2. "RF0FE,Receive FIFO 0 Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RF0WE,Receive FIFO 0 Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "RF0NE,Receive FIFO 0 New Message Interrupt Enable" "0,1"
|
|
line.long 0x8 "ILS,Interrupt Line Select Register"
|
|
bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0,1"
|
|
bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0,1"
|
|
bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
|
|
bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0,1"
|
|
bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1"
|
|
bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Receive Buffer Interrupt Line" "0,1"
|
|
bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
|
|
bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
|
|
bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0,1"
|
|
bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "RF1LL,Receive FIFO 1 Message Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 6. "RF1FL,Receive FIFO 1 Full Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "RF1WL,Receive FIFO 1 Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 4. "RF1NL,Receive FIFO 1 New Message Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "RF0LL,Receive FIFO 0 Message Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 2. "RF0FL,Receive FIFO 0 Full Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "RF0WL,Receive FIFO 0 Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 0. "RF0NL,Receive FIFO 0 New Message Interrupt Line" "0,1"
|
|
line.long 0xC "ILE,Interrupt Line Enable Register"
|
|
bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0,1"
|
|
bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0,1"
|
|
group.long 0x80++0xB
|
|
line.long 0x0 "GFC,Global Filter Configuration Register"
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
|
|
newline
|
|
bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs.,1: Reject all remote frames with 11-bit standard IDs."
|
|
bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs.,1: Reject all remote frames with 29-bit extended IDs."
|
|
line.long 0x4 "SIDFC,Standard ID Filter Configuration Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard"
|
|
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address"
|
|
line.long 0x8 "XIDFC,Extended ID Filter Configuration Register"
|
|
hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended"
|
|
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "XIDAM,Extended ID AND Mask Register"
|
|
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask"
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x0 "HPMS,High Priority Message Status Register"
|
|
bitfld.long 0x0 15. "FLST,Filter List" "0,1"
|
|
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected.,1: FIFO message lost.,2: Message stored in FIFO 0.,3: Message stored in FIFO 1."
|
|
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index"
|
|
group.long 0x98++0xB
|
|
line.long 0x0 "NDAT1,New Data 1 Register"
|
|
bitfld.long 0x0 31. "ND31,New Data" "0,1"
|
|
bitfld.long 0x0 30. "ND30,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ND29,New Data" "0,1"
|
|
bitfld.long 0x0 28. "ND28,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "ND27,New Data" "0,1"
|
|
bitfld.long 0x0 26. "ND26,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "ND25,New Data" "0,1"
|
|
bitfld.long 0x0 24. "ND24,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "ND23,New Data" "0,1"
|
|
bitfld.long 0x0 22. "ND22,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "ND21,New Data" "0,1"
|
|
bitfld.long 0x0 20. "ND20,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "ND19,New Data" "0,1"
|
|
bitfld.long 0x0 18. "ND18,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ND17,New Data" "0,1"
|
|
bitfld.long 0x0 16. "ND16,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "ND15,New Data" "0,1"
|
|
bitfld.long 0x0 14. "ND14,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ND13,New Data" "0,1"
|
|
bitfld.long 0x0 12. "ND12,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ND11,New Data" "0,1"
|
|
bitfld.long 0x0 10. "ND10,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ND9,New Data" "0,1"
|
|
bitfld.long 0x0 8. "ND8,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ND7,New Data" "0,1"
|
|
bitfld.long 0x0 6. "ND6,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ND5,New Data" "0,1"
|
|
bitfld.long 0x0 4. "ND4,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ND3,New Data" "0,1"
|
|
bitfld.long 0x0 2. "ND2,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ND1,New Data" "0,1"
|
|
bitfld.long 0x0 0. "ND0,New Data" "0,1"
|
|
line.long 0x4 "NDAT2,New Data 2 Register"
|
|
bitfld.long 0x4 31. "ND63,New Data" "0,1"
|
|
bitfld.long 0x4 30. "ND62,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "ND61,New Data" "0,1"
|
|
bitfld.long 0x4 28. "ND60,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "ND59,New Data" "0,1"
|
|
bitfld.long 0x4 26. "ND58,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "ND57,New Data" "0,1"
|
|
bitfld.long 0x4 24. "ND56,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "ND55,New Data" "0,1"
|
|
bitfld.long 0x4 22. "ND54,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "ND53,New Data" "0,1"
|
|
bitfld.long 0x4 20. "ND52,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "ND51,New Data" "0,1"
|
|
bitfld.long 0x4 18. "ND50,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "ND49,New Data" "0,1"
|
|
bitfld.long 0x4 16. "ND48,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "ND47,New Data" "0,1"
|
|
bitfld.long 0x4 14. "ND46,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ND45,New Data" "0,1"
|
|
bitfld.long 0x4 12. "ND44,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "ND43,New Data" "0,1"
|
|
bitfld.long 0x4 10. "ND42,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "ND41,New Data" "0,1"
|
|
bitfld.long 0x4 8. "ND40,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "ND39,New Data" "0,1"
|
|
bitfld.long 0x4 6. "ND38,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "ND37,New Data" "0,1"
|
|
bitfld.long 0x4 4. "ND36,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ND35,New Data" "0,1"
|
|
bitfld.long 0x4 2. "ND34,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ND33,New Data" "0,1"
|
|
bitfld.long 0x4 0. "ND32,New Data" "0,1"
|
|
line.long 0x8 "RXF0C,Receive FIFO 0 Configuration Register"
|
|
bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0,1"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Receive FIFO 0 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F0S,Receive FIFO 0 Start Address"
|
|
hexmask.long.word 0x8 2.--15. 1. "F0SA,Receive FIFO 0 Start Address"
|
|
rgroup.long 0xA4++0x3
|
|
line.long 0x0 "RXF0S,Receive FIFO 0 Status Register"
|
|
bitfld.long 0x0 25. "RF0L,Receive FIFO 0 Message Lost" "0,1"
|
|
bitfld.long 0x0 24. "F0F,Receive FIFO 0 Fill Level" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "F0PI,Receive FIFO 0 Put Index"
|
|
hexmask.long.byte 0x0 8.--13. 1. "F0GI,Receive FIFO 0 Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "F0FL,Receive FIFO 0 Fill Level"
|
|
group.long 0xA8++0xB
|
|
line.long 0x0 "RXF0A,Receive FIFO 0 Acknowledge Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F0AI,Receive FIFO 0 Acknowledge Index"
|
|
line.long 0x4 "RXBC,Receive Rx Buffer Configuration Register"
|
|
hexmask.long.word 0x4 2.--15. 1. "RBSA,Receive Buffer Start Address"
|
|
line.long 0x8 "RXF1C,Receive FIFO 1 Configuration Register"
|
|
bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0,1"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F1WM,Receive FIFO 1 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F1S,Receive FIFO 1 Start Address"
|
|
hexmask.long.word 0x8 2.--15. 1. "F1SA,Receive FIFO 1 Start Address"
|
|
rgroup.long 0xB4++0x3
|
|
line.long 0x0 "RXF1S,Receive FIFO 1 Status Register"
|
|
bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages..,1: Debug message A received.,2: Debug messages A B received.,3: Debug messages A B C received DMA request is set."
|
|
bitfld.long 0x0 25. "RF1L,Receive FIFO 1 Message Lost" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "F1F,Receive FIFO 1 Fill Level" "0,1"
|
|
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Receive FIFO 1 Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Receive FIFO 1 Get Index"
|
|
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Receive FIFO 1 Fill Level"
|
|
group.long 0xB8++0xB
|
|
line.long 0x0 "RXF1A,Receive FIFO 1 Acknowledge Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Receive FIFO 1 Acknowledge Index"
|
|
line.long 0x4 "RXESC,Receive Buffer / FIFO Element Size Configuration Register"
|
|
bitfld.long 0x4 8.--10. "RBDS,Receive Buffer Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field"
|
|
bitfld.long 0x4 4.--6. "F1DS,Receive FIFO 1 Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "F0DS,Receive FIFO 0 Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field"
|
|
line.long 0x8 "TXBC,Transmit Buffer Configuration Register"
|
|
bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1"
|
|
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
|
|
hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address"
|
|
rgroup.long 0xC4++0x3
|
|
line.long 0x0 "TXFQS,Transmit FIFO/Queue Status Register"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index"
|
|
hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level"
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "TXESC,Transmit Buffer Element Size Configuration Register"
|
|
bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48- byte data field,7: 64-byte data field"
|
|
rgroup.long 0xCC++0x3
|
|
line.long 0x0 "TXBRP,Transmit Buffer Request Pending Register"
|
|
bitfld.long 0x0 31. "TRP31,Transmission Request Pending for Buffer 31" "0,1"
|
|
bitfld.long 0x0 30. "TRP30,Transmission Request Pending for Buffer 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TRP29,Transmission Request Pending for Buffer 29" "0,1"
|
|
bitfld.long 0x0 28. "TRP28,Transmission Request Pending for Buffer 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "TRP27,Transmission Request Pending for Buffer 27" "0,1"
|
|
bitfld.long 0x0 26. "TRP26,Transmission Request Pending for Buffer 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TRP25,Transmission Request Pending for Buffer 25" "0,1"
|
|
bitfld.long 0x0 24. "TRP24,Transmission Request Pending for Buffer 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TRP23,Transmission Request Pending for Buffer 23" "0,1"
|
|
bitfld.long 0x0 22. "TRP22,Transmission Request Pending for Buffer 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TRP21,Transmission Request Pending for Buffer 21" "0,1"
|
|
bitfld.long 0x0 20. "TRP20,Transmission Request Pending for Buffer 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TRP19,Transmission Request Pending for Buffer 19" "0,1"
|
|
bitfld.long 0x0 18. "TRP18,Transmission Request Pending for Buffer 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TRP17,Transmission Request Pending for Buffer 17" "0,1"
|
|
bitfld.long 0x0 16. "TRP16,Transmission Request Pending for Buffer 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TRP15,Transmission Request Pending for Buffer 15" "0,1"
|
|
bitfld.long 0x0 14. "TRP14,Transmission Request Pending for Buffer 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TRP13,Transmission Request Pending for Buffer 13" "0,1"
|
|
bitfld.long 0x0 12. "TRP12,Transmission Request Pending for Buffer 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TRP11,Transmission Request Pending for Buffer 11" "0,1"
|
|
bitfld.long 0x0 10. "TRP10,Transmission Request Pending for Buffer 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TRP9,Transmission Request Pending for Buffer 9" "0,1"
|
|
bitfld.long 0x0 8. "TRP8,Transmission Request Pending for Buffer 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TRP7,Transmission Request Pending for Buffer 7" "0,1"
|
|
bitfld.long 0x0 6. "TRP6,Transmission Request Pending for Buffer 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TRP5,Transmission Request Pending for Buffer 5" "0,1"
|
|
bitfld.long 0x0 4. "TRP4,Transmission Request Pending for Buffer 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TRP3,Transmission Request Pending for Buffer 3" "0,1"
|
|
bitfld.long 0x0 2. "TRP2,Transmission Request Pending for Buffer 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TRP1,Transmission Request Pending for Buffer 1" "0,1"
|
|
bitfld.long 0x0 0. "TRP0,Transmission Request Pending for Buffer 0" "0,1"
|
|
group.long 0xD0++0x7
|
|
line.long 0x0 "TXBAR,Transmit Buffer Add Request Register"
|
|
bitfld.long 0x0 31. "AR31,Add Request for Transmit Buffer 31" "0,1"
|
|
bitfld.long 0x0 30. "AR30,Add Request for Transmit Buffer 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "AR29,Add Request for Transmit Buffer 29" "0,1"
|
|
bitfld.long 0x0 28. "AR28,Add Request for Transmit Buffer 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "AR27,Add Request for Transmit Buffer 27" "0,1"
|
|
bitfld.long 0x0 26. "AR26,Add Request for Transmit Buffer 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "AR25,Add Request for Transmit Buffer 25" "0,1"
|
|
bitfld.long 0x0 24. "AR24,Add Request for Transmit Buffer 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "AR23,Add Request for Transmit Buffer 23" "0,1"
|
|
bitfld.long 0x0 22. "AR22,Add Request for Transmit Buffer 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "AR21,Add Request for Transmit Buffer 21" "0,1"
|
|
bitfld.long 0x0 20. "AR20,Add Request for Transmit Buffer 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "AR19,Add Request for Transmit Buffer 19" "0,1"
|
|
bitfld.long 0x0 18. "AR18,Add Request for Transmit Buffer 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "AR17,Add Request for Transmit Buffer 17" "0,1"
|
|
bitfld.long 0x0 16. "AR16,Add Request for Transmit Buffer 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "AR15,Add Request for Transmit Buffer 15" "0,1"
|
|
bitfld.long 0x0 14. "AR14,Add Request for Transmit Buffer 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "AR13,Add Request for Transmit Buffer 13" "0,1"
|
|
bitfld.long 0x0 12. "AR12,Add Request for Transmit Buffer 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "AR11,Add Request for Transmit Buffer 11" "0,1"
|
|
bitfld.long 0x0 10. "AR10,Add Request for Transmit Buffer 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "AR9,Add Request for Transmit Buffer 9" "0,1"
|
|
bitfld.long 0x0 8. "AR8,Add Request for Transmit Buffer 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "AR7,Add Request for Transmit Buffer 7" "0,1"
|
|
bitfld.long 0x0 6. "AR6,Add Request for Transmit Buffer 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "AR5,Add Request for Transmit Buffer 5" "0,1"
|
|
bitfld.long 0x0 4. "AR4,Add Request for Transmit Buffer 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "AR3,Add Request for Transmit Buffer 3" "0,1"
|
|
bitfld.long 0x0 2. "AR2,Add Request for Transmit Buffer 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "AR1,Add Request for Transmit Buffer 1" "0,1"
|
|
bitfld.long 0x0 0. "AR0,Add Request for Transmit Buffer 0" "0,1"
|
|
line.long 0x4 "TXBCR,Transmit Buffer Cancellation Request Register"
|
|
bitfld.long 0x4 31. "CR31,Cancellation Request for Transmit Buffer 31" "0,1"
|
|
bitfld.long 0x4 30. "CR30,Cancellation Request for Transmit Buffer 30" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "CR29,Cancellation Request for Transmit Buffer 29" "0,1"
|
|
bitfld.long 0x4 28. "CR28,Cancellation Request for Transmit Buffer 28" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "CR27,Cancellation Request for Transmit Buffer 27" "0,1"
|
|
bitfld.long 0x4 26. "CR26,Cancellation Request for Transmit Buffer 26" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "CR25,Cancellation Request for Transmit Buffer 25" "0,1"
|
|
bitfld.long 0x4 24. "CR24,Cancellation Request for Transmit Buffer 24" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CR23,Cancellation Request for Transmit Buffer 23" "0,1"
|
|
bitfld.long 0x4 22. "CR22,Cancellation Request for Transmit Buffer 22" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "CR21,Cancellation Request for Transmit Buffer 21" "0,1"
|
|
bitfld.long 0x4 20. "CR20,Cancellation Request for Transmit Buffer 20" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CR19,Cancellation Request for Transmit Buffer 19" "0,1"
|
|
bitfld.long 0x4 18. "CR18,Cancellation Request for Transmit Buffer 18" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CR17,Cancellation Request for Transmit Buffer 17" "0,1"
|
|
bitfld.long 0x4 16. "CR16,Cancellation Request for Transmit Buffer 16" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CR15,Cancellation Request for Transmit Buffer 15" "0,1"
|
|
bitfld.long 0x4 14. "CR14,Cancellation Request for Transmit Buffer 14" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CR13,Cancellation Request for Transmit Buffer 13" "0,1"
|
|
bitfld.long 0x4 12. "CR12,Cancellation Request for Transmit Buffer 12" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CR11,Cancellation Request for Transmit Buffer 11" "0,1"
|
|
bitfld.long 0x4 10. "CR10,Cancellation Request for Transmit Buffer 10" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CR9,Cancellation Request for Transmit Buffer 9" "0,1"
|
|
bitfld.long 0x4 8. "CR8,Cancellation Request for Transmit Buffer 8" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CR7,Cancellation Request for Transmit Buffer 7" "0,1"
|
|
bitfld.long 0x4 6. "CR6,Cancellation Request for Transmit Buffer 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CR5,Cancellation Request for Transmit Buffer 5" "0,1"
|
|
bitfld.long 0x4 4. "CR4,Cancellation Request for Transmit Buffer 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CR3,Cancellation Request for Transmit Buffer 3" "0,1"
|
|
bitfld.long 0x4 2. "CR2,Cancellation Request for Transmit Buffer 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CR1,Cancellation Request for Transmit Buffer 1" "0,1"
|
|
bitfld.long 0x4 0. "CR0,Cancellation Request for Transmit Buffer 0" "0,1"
|
|
rgroup.long 0xD8++0x7
|
|
line.long 0x0 "TXBTO,Transmit Buffer Transmission Occurred Register"
|
|
bitfld.long 0x0 31. "TO31,Transmission Occurred for Buffer 31" "0,1"
|
|
bitfld.long 0x0 30. "TO30,Transmission Occurred for Buffer 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TO29,Transmission Occurred for Buffer 29" "0,1"
|
|
bitfld.long 0x0 28. "TO28,Transmission Occurred for Buffer 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "TO27,Transmission Occurred for Buffer 27" "0,1"
|
|
bitfld.long 0x0 26. "TO26,Transmission Occurred for Buffer 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TO25,Transmission Occurred for Buffer 25" "0,1"
|
|
bitfld.long 0x0 24. "TO24,Transmission Occurred for Buffer 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TO23,Transmission Occurred for Buffer 23" "0,1"
|
|
bitfld.long 0x0 22. "TO22,Transmission Occurred for Buffer 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TO21,Transmission Occurred for Buffer 21" "0,1"
|
|
bitfld.long 0x0 20. "TO20,Transmission Occurred for Buffer 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TO19,Transmission Occurred for Buffer 19" "0,1"
|
|
bitfld.long 0x0 18. "TO18,Transmission Occurred for Buffer 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TO17,Transmission Occurred for Buffer 17" "0,1"
|
|
bitfld.long 0x0 16. "TO16,Transmission Occurred for Buffer 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TO15,Transmission Occurred for Buffer 15" "0,1"
|
|
bitfld.long 0x0 14. "TO14,Transmission Occurred for Buffer 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TO13,Transmission Occurred for Buffer 13" "0,1"
|
|
bitfld.long 0x0 12. "TO12,Transmission Occurred for Buffer 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TO11,Transmission Occurred for Buffer 11" "0,1"
|
|
bitfld.long 0x0 10. "TO10,Transmission Occurred for Buffer 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TO9,Transmission Occurred for Buffer 9" "0,1"
|
|
bitfld.long 0x0 8. "TO8,Transmission Occurred for Buffer 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TO7,Transmission Occurred for Buffer 7" "0,1"
|
|
bitfld.long 0x0 6. "TO6,Transmission Occurred for Buffer 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TO5,Transmission Occurred for Buffer 5" "0,1"
|
|
bitfld.long 0x0 4. "TO4,Transmission Occurred for Buffer 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TO3,Transmission Occurred for Buffer 3" "0,1"
|
|
bitfld.long 0x0 2. "TO2,Transmission Occurred for Buffer 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TO1,Transmission Occurred for Buffer 1" "0,1"
|
|
bitfld.long 0x0 0. "TO0,Transmission Occurred for Buffer 0" "0,1"
|
|
line.long 0x4 "TXBCF,Transmit Buffer Cancellation Finished Register"
|
|
bitfld.long 0x4 31. "CF31,Cancellation Finished for Transmit Buffer 31" "0,1"
|
|
bitfld.long 0x4 30. "CF30,Cancellation Finished for Transmit Buffer 30" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "CF29,Cancellation Finished for Transmit Buffer 29" "0,1"
|
|
bitfld.long 0x4 28. "CF28,Cancellation Finished for Transmit Buffer 28" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "CF27,Cancellation Finished for Transmit Buffer 27" "0,1"
|
|
bitfld.long 0x4 26. "CF26,Cancellation Finished for Transmit Buffer 26" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "CF25,Cancellation Finished for Transmit Buffer 25" "0,1"
|
|
bitfld.long 0x4 24. "CF24,Cancellation Finished for Transmit Buffer 24" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CF23,Cancellation Finished for Transmit Buffer 23" "0,1"
|
|
bitfld.long 0x4 22. "CF22,Cancellation Finished for Transmit Buffer 22" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "CF21,Cancellation Finished for Transmit Buffer 21" "0,1"
|
|
bitfld.long 0x4 20. "CF20,Cancellation Finished for Transmit Buffer 20" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CF19,Cancellation Finished for Transmit Buffer 19" "0,1"
|
|
bitfld.long 0x4 18. "CF18,Cancellation Finished for Transmit Buffer 18" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CF17,Cancellation Finished for Transmit Buffer 17" "0,1"
|
|
bitfld.long 0x4 16. "CF16,Cancellation Finished for Transmit Buffer 16" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CF15,Cancellation Finished for Transmit Buffer 15" "0,1"
|
|
bitfld.long 0x4 14. "CF14,Cancellation Finished for Transmit Buffer 14" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CF13,Cancellation Finished for Transmit Buffer 13" "0,1"
|
|
bitfld.long 0x4 12. "CF12,Cancellation Finished for Transmit Buffer 12" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CF11,Cancellation Finished for Transmit Buffer 11" "0,1"
|
|
bitfld.long 0x4 10. "CF10,Cancellation Finished for Transmit Buffer 10" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CF9,Cancellation Finished for Transmit Buffer 9" "0,1"
|
|
bitfld.long 0x4 8. "CF8,Cancellation Finished for Transmit Buffer 8" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CF7,Cancellation Finished for Transmit Buffer 7" "0,1"
|
|
bitfld.long 0x4 6. "CF6,Cancellation Finished for Transmit Buffer 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CF5,Cancellation Finished for Transmit Buffer 5" "0,1"
|
|
bitfld.long 0x4 4. "CF4,Cancellation Finished for Transmit Buffer 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CF3,Cancellation Finished for Transmit Buffer 3" "0,1"
|
|
bitfld.long 0x4 2. "CF2,Cancellation Finished for Transmit Buffer 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CF1,Cancellation Finished for Transmit Buffer 1" "0,1"
|
|
bitfld.long 0x4 0. "CF0,Cancellation Finished for Transmit Buffer 0" "0,1"
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "TXBTIE,Transmit Buffer Transmission Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable for Buffer 31" "0,1"
|
|
bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable for Buffer 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable for Buffer 29" "0,1"
|
|
bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable for Buffer 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable for Buffer 27" "0,1"
|
|
bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable for Buffer 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable for Buffer 25" "0,1"
|
|
bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable for Buffer 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable for Buffer 23" "0,1"
|
|
bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable for Buffer 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable for Buffer 21" "0,1"
|
|
bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable for Buffer 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable for Buffer 19" "0,1"
|
|
bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable for Buffer 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable for Buffer 17" "0,1"
|
|
bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable for Buffer 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable for Buffer 15" "0,1"
|
|
bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable for Buffer 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable for Buffer 13" "0,1"
|
|
bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable for Buffer 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable for Buffer 11" "0,1"
|
|
bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable for Buffer 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable for Buffer 9" "0,1"
|
|
bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable for Buffer 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable for Buffer 7" "0,1"
|
|
bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable for Buffer 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable for Buffer 5" "0,1"
|
|
bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable for Buffer 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable for Buffer 3" "0,1"
|
|
bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable for Buffer 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable for Buffer 1" "0,1"
|
|
bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable for Buffer 0" "0,1"
|
|
line.long 0x4 "TXBCIE,Transmit Buffer Cancellation Finished Interrupt Enable Register"
|
|
bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable for Transmit Buffer 31" "0,1"
|
|
bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable for Transmit Buffer 30" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable for Transmit Buffer 29" "0,1"
|
|
bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable for Transmit Buffer 28" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable for Transmit Buffer 27" "0,1"
|
|
bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable for Transmit Buffer 26" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable for Transmit Buffer 25" "0,1"
|
|
bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable for Transmit Buffer 24" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable for Transmit Buffer 23" "0,1"
|
|
bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable for Transmit Buffer 22" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable for Transmit Buffer 21" "0,1"
|
|
bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable for Transmit Buffer 20" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable for Transmit Buffer 19" "0,1"
|
|
bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable for Transmit Buffer 18" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable for Transmit Buffer 17" "0,1"
|
|
bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable for Transmit Buffer 16" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable for Transmit Buffer 15" "0,1"
|
|
bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable for Transmit Buffer 14" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable for Transmit Buffer 13" "0,1"
|
|
bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable for Transmit Buffer 12" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable for Transmit Buffer 11" "0,1"
|
|
bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable for Transmit Buffer 10" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable for Transmit Buffer 9" "0,1"
|
|
bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable for Transmit Buffer 8" "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable for Transmit Buffer 7" "0,1"
|
|
bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable for Transmit Buffer 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable for Transmit Buffer 5" "0,1"
|
|
bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable for Transmit Buffer 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable for Transmit Buffer 3" "0,1"
|
|
bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable for Transmit Buffer 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable for Transmit Buffer 1" "0,1"
|
|
bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable for Transmit Buffer 0" "0,1"
|
|
group.long 0xF0++0x3
|
|
line.long 0x0 "TXEFC,Transmit Event FIFO Configuration Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark"
|
|
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size"
|
|
newline
|
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hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address"
|
|
rgroup.long 0xF4++0x3
|
|
line.long 0x0 "TXEFS,Transmit Event FIFO Status Register"
|
|
bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index"
|
|
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index"
|
|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level"
|
|
group.long 0xF8++0x3
|
|
line.long 0x0 "TXEFA,Transmit Event FIFO Acknowledge Register"
|
|
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index"
|
|
tree.end
|
|
tree.end
|
|
tree "MPDDRC (DDR-SDRAM Controller)"
|
|
base ad:0xF000C000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "MRS,Mode Register Select LPDDR2/LPDDR3"
|
|
newline
|
|
bitfld.long 0x0 4. "DAI,Device Autoinitialization Status (read-only)" "0: DAI complete,1: DAI still in progress"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "MODE,MPDDRC Command Mode" "0: Normal Mode. Any access to the MPDDRC is decoded..,1: The MPDDRC issues a NOP command when the..,2: The MPDDRC issues the All Banks Precharge..,3: The MPDDRC issues a Load Mode Register command..,4: The MPDDRC issues an Autorefresh command when..,5: The MPDDRC issues an Extended Load Mode Register..,6: Deep Power mode: Access to Deep Powerdown..,7: The MPDDRC issues an LPDDR2/LPDDR3 Mode Register.."
|
|
line.long 0x4 "RTR,Refresh Timer Register"
|
|
bitfld.long 0x4 20.--22. "MR4_VALUE,Content of MR4 Register (read-only)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 17. "REF_PB,Refresh Per Bank" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "ADJ_REF,Adjust Refresh Rate" "0,1"
|
|
newline
|
|
hexmask.long.word 0x4 0.--11. 1. "COUNT,MPDDRC Refresh Timer Count"
|
|
line.long 0x8 "CR,Configuration Register"
|
|
bitfld.long 0x8 23. "UNAL,Support Unaligned Access" "0: Unaligned access is not supported.,1: Unaligned access is supported."
|
|
newline
|
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bitfld.long 0x8 22. "DECOD,Type of Decoding" "0: Method for address mapping where banks alternate..,1: Method for address mapping where banks alternate.."
|
|
newline
|
|
bitfld.long 0x8 21. "NDQS,Not DQS" "0: Not DQS is enabled,1: Not DQS is disabled"
|
|
newline
|
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bitfld.long 0x8 20. "NB,Number of Banks" "0: 4-bank memory devices,1: 8 banks. Only possible when using the DDR2-SDRAM.."
|
|
newline
|
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bitfld.long 0x8 19. "LC_LPDDR1,Low-cost Low-power DDR1" "0: Any type of memory devices except of low cost..,1: Low-cost and low-density low-power DDR1. These.."
|
|
newline
|
|
bitfld.long 0x8 17. "ENRDM,Enable Read Measure" "0: DQS/DDR_DATA phase error correction is disabled,1: DQS/DDR_DATA phase error correction is enabled"
|
|
newline
|
|
bitfld.long 0x8 16. "DQMS,Mask Data is Shared" "0: DQM is not shared with another controller,1: DQM is shared with another controller"
|
|
newline
|
|
bitfld.long 0x8 12.--14. "OCD,Off-chip Driver" "0: Exit from OCD Calibration mode and maintain..,?,?,?,?,?,?,7: OCD calibration default"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "ZQ,ZQ Calibration" "0: Calibration command after initialization,1: Long calibration,2: Short calibration,3: ZQ Reset"
|
|
newline
|
|
bitfld.long 0x8 9. "DIS_DLL,DISABLE DLL" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "DIC_DS,Output Driver Impedance Control (Drive Strength)" "0: Normal drive strength (DDR2) - RZQ/6 (40 [NOM]..,1: Weak drive strength (DDR2) - RZQ/7 (34 [NOM] DDR3)"
|
|
newline
|
|
bitfld.long 0x8 7. "DLL,Reset DLL" "0: Disable DLL reset,1: Enable DLL reset"
|
|
newline
|
|
bitfld.long 0x8 4.--6. "CAS,CAS Latency" "?,?,2: LPDDR1 CAS Latency 2,3: LPDDR3/DDR2/LPDDR2/LPDDR1 CAS Latency 3,?,5: DDR3 CAS Latency 5,6: DDR3LPDDR3 CAS Latency 6,?"
|
|
newline
|
|
bitfld.long 0x8 2.--3. "NR,Number of Row Bits" "0: 11 bits to define the row number up to 2048 rows,1: 12 bits to define the row number up to 4096 rows,2: 13 bits to define the row number up to 8192 rows,3: 14 bits to define the row number up to 16384 rows"
|
|
newline
|
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bitfld.long 0x8 0.--1. "NC,Number of Column Bits" "0: 9 bits to define the column number up to 512..,1: 10 bits to define the column number up to 1024..,2: 11 bits to define the column number up to 2048..,3: 12 bits to define the column number up to 4096.."
|
|
line.long 0xC "TPR0,Timing Parameter 0 Register"
|
|
hexmask.long.byte 0xC 28.--31. 1. "TMRD,Load Mode Register Command to Activate or Refresh Command"
|
|
newline
|
|
hexmask.long.byte 0xC 24.--27. 1. "TWTR,Internal Write to Read Delay"
|
|
newline
|
|
hexmask.long.byte 0xC 20.--23. 1. "TRRD,Active BankA to Active BankB"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--19. 1. "TRP,Row Precharge Delay"
|
|
newline
|
|
hexmask.long.byte 0xC 12.--15. 1. "TRC,Row Cycle Delay"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--11. 1. "TWR,Write Recovery Delay"
|
|
newline
|
|
hexmask.long.byte 0xC 4.--7. 1. "TRCD,Row to Column Delay"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--3. 1. "TRAS,Active to Precharge Delay"
|
|
line.long 0x10 "TPR1,Timing Parameter 1 Register"
|
|
hexmask.long.byte 0x10 24.--27. 1. "TXP,Exit Powerdown Delay to First Command"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--23. 1. "TXSRD,Exit Self-refresh Delay to Read Command"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "TXSNR,Exit Self-refresh Delay to Non-Read Command"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--6. 1. "TRFC,Row Cycle Delay"
|
|
line.long 0x14 "TPR2,Timing Parameter 2 Register"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TFAW,Four Active Windows"
|
|
newline
|
|
bitfld.long 0x14 12.--14. "TRTP,Read to Precharge" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--11. 1. "TRPA,Row Precharge All Delay"
|
|
newline
|
|
hexmask.long.byte 0x14 4.--7. 1. "TXARDS,Exit Active Power Down Delay to Read Command in Mode 'Slow Exit'"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--3. 1. "TXARD,Exit Active Power Down Delay to Read Command in Mode 'Fast Exit'"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "LPR,Low-Power Register"
|
|
bitfld.long 0x0 25. "SELF_DONE,Self-refresh is done (read-only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "CHG_FRQ,Change Clock Frequency During Self-refresh Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "UPD_MR,Update Load Mode Register and Extended Mode Register" "0: Update of Load Mode and Extended Mode registers..,1: MPDDRC shares an external bus. Automatic update..,2: MPDDRC does not share an external bus. Automatic..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "APDE,Active Power Down Exit Time" "0: Fast Exit from Power Down. DDR2-SDRAM and..,1: Slow Exit from Power Down. DDR2-SDRAM and.."
|
|
newline
|
|
bitfld.long 0x0 12.--13. "TIMEOUT,Time Between Last Transfer and Low-Power Mode" "0: SDRAM Low-power mode is activated immediately..,1: SDRAM Low-power mode is activated 64 clock..,2: SDRAM Low-power mode is activated 128 clock..,?"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "DS,Drive Strength" "0: Full drive strength,1: Half drive strength,2: Quarter drive strength,3: Octant drive strength,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "PASR,Partial Array Self-refresh" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 3. "LPDDR2_LPDDR3_PWOFF,LPDDR2 - LPDDR3 Power Off Bit" "0: No power-off sequence applied to LPDDR2/LPDDR3.,1: A power-off sequence is applied to the.."
|
|
newline
|
|
bitfld.long 0x0 2. "CLK_FR,Clock Frozen Command Bit" "0: Clock(s) is/are not frozen.,1: Clock(s) is/are frozen."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "LPCB,Low-power Command Bit" "0: Low-power feature is inhibited. No Powerdown..,1: The MPDDRC issues a self-refresh command to the..,2: The MPDDRC issues a Powerdown command to the..,3: The MPDDRC issues a Deep Powerdown command to.."
|
|
line.long 0x4 "MD,Memory Device Register"
|
|
bitfld.long 0x4 30.--31. "IO_WIDTH,Width of Memory (read-only)" "0: The data bus width is 32 bits.,1: The data bus width is 16 bits.,2: The data bus width is 8 bits.,?"
|
|
newline
|
|
hexmask.long.byte 0x4 26.--29. 1. "DENSITY,Density of Memory (read-only)"
|
|
newline
|
|
bitfld.long 0x4 24.--25. "TYPE,DRAM Architecture (read-only)" "0: 4n prefetch architecture,1: 2n prefetch architecture,2: Non-volatile device,3: 8n prefetch architecture"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "REV_ID,Revision Identification (read-only)"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "MANU_ID,Manufacturer Identification (read-only)"
|
|
newline
|
|
bitfld.long 0x4 7. "RL3,Read Latency 3 Option Support (read-only)" "0: Read latency of 3 is supported,1: Read latency 0f 3 is not supported"
|
|
newline
|
|
bitfld.long 0x4 6. "WL,Write Latency (read-only)" "0: Write Latency Set A,1: Write Latency Set B"
|
|
newline
|
|
bitfld.long 0x4 4. "DBW,Data Bus Width" "0: Data bus width is 32 bits,1: Data bus width is 16 bits."
|
|
newline
|
|
bitfld.long 0x4 0.--2. "MD,Memory Device" "?,?,?,3: Low-power DDR1-SDRAM,4: DDR3-SDRAM,5: Low-power DDR3-SDRAM,6: DDR2-SDRAM,7: Low-power DDR2-SDRAM"
|
|
group.long 0x28++0x13
|
|
line.long 0x0 "LPDDR23_LPR,Low-power DDR2 Low-power DDR3 Low-power Register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "DS,Drive Strength"
|
|
newline
|
|
hexmask.long.word 0x0 8.--23. 1. "SEG_MASK,Segment Mask Bit"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "BK_MASK_PASR,Bank Mask Bit/PASR"
|
|
line.long 0x4 "LPDDR2_LPDDR3_DDR3_CAL_MR4,Low-power DDR2 Low-power DDR3 and DDR3 Calibration and MR4 Register"
|
|
hexmask.long.word 0x4 16.--31. 1. "MR4_READ,Mode Register 4 Read Interval"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "COUNT_CAL,LPDDR2 LPDDR3 and DDR3 Calibration Timer Count"
|
|
line.long 0x8 "LPDDR2_LPDDR3_DDR3_TIM_CAL,Low-power DDR2 Low-power DDR3 and DDR3 Timing Calibration Register"
|
|
bitfld.long 0x8 16.--17. "RZQI,Built-in Self-Test for RZQ Information (read-only)" "0: RZQ self test not supported,1: The ZQ pin can be connected to VDDCA or left..,2: The ZQ pin can be shorted to ground.,3: ZQ pin self test complete; no error condition.."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "ZQCS,ZQ Calibration Short"
|
|
line.long 0xC "IO_CALIBR,I/O Calibration Register"
|
|
hexmask.long.byte 0xC 20.--23. 1. "CALCODEN,Number of Transistor N (read-only)"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--19. 1. "CALCODEP,Number of Transistor P (read-only)"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--14. 1. "TZQIO,IO Calibration"
|
|
newline
|
|
bitfld.long 0xC 4. "EN_CALIB,Enable Calibration" "0: Calibration is disabled.,1: Calibration is enabled."
|
|
newline
|
|
bitfld.long 0xC 0.--2. "RDIV,Resistor Divider Output Driver Impedance" "?,1: LPDDR2 serial impedance line = 34.3 ohms..,2: LPDDR2 serial impedance line = 40 ohms LPDDR3..,3: LPDDR2 serial impedance line = 48 ohms LPDDR3..,4: LPDDR2 serial impedance line = 60 ohms LPDDR3..,?,6: LPDDR2 serial impedance line = 80 ohms LPDDR3..,7: LPDDR2 serial impedance line = 120 ohms LPDDR3.."
|
|
line.long 0x10 "OCMS,OCMS Register"
|
|
bitfld.long 0x10 0. "SCR_EN,Scrambling Enable" "0,1"
|
|
wgroup.long 0x3C++0x7
|
|
line.long 0x0 "OCMS_KEY1,OCMS KEY1 Register"
|
|
hexmask.long 0x0 0.--31. 1. "KEY1,Off-chip Memory Scrambling (OCMS) Key Part 1"
|
|
line.long 0x4 "OCMS_KEY2,OCMS KEY2 Register"
|
|
hexmask.long 0x4 0.--31. 1. "KEY2,Off-chip Memory Scrambling (OCMS) Key Part 2"
|
|
group.long 0x44++0xF
|
|
line.long 0x0 "CONF_ARBITER,Configuration Arbiter Register"
|
|
bitfld.long 0x0 31. "BDW_BURST_P7,Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "BDW_BURST_P6,Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "BDW_BURST_P5,Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "BDW_BURST_P4,Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "BDW_BURST_P3,Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "BDW_BURST_P2,Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "BDW_BURST_P1,Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "BDW_BURST_P0,Bandwidth is Reached or Bandwidth and Current Burst Access is Ended on port X" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "MA_PR_P7,Master or Software Provide Information" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "MA_PR_P6,Master or Software Provide Information" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "MA_PR_P5,Master or Software Provide Information" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "MA_PR_P4,Master or Software Provide Information" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "MA_PR_P3,Master or Software Provide Information" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "MA_PR_P2,Master or Software Provide Information" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MA_PR_P1,Master or Software Provide Information" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MA_PR_P0,Master or Software Provide Information" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RQ_WD_P7,Request or Word from Port X" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RQ_WD_P6,Request or Word from Port X" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RQ_WD_P5,Request or Word from Port X" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RQ_WD_P4,Request or Word from Port X" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RQ_WD_P3,Request or Word from Port X" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "RQ_WD_P2,Request or Word from Port X" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RQ_WD_P1,Request or Word from Port X" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RQ_WD_P0,Request or Word from Port X" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "BDW_MAX_CUR,Bandwidth Max or Current" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "ARB,Type of Arbitration" "0: Round Robin,1: Request Policy,2: Bandwidth Policy,?"
|
|
line.long 0x4 "TIMEOUT,Timeout Register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "TIMEOUT_P7,Timeout for Ports 0 1 2 3 4 5 6 and 7"
|
|
newline
|
|
hexmask.long.byte 0x4 24.--27. 1. "TIMEOUT_P6,Timeout for Ports 0 1 2 3 4 5 6 and 7"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "TIMEOUT_P5,Timeout for Ports 0 1 2 3 4 5 6 and 7"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--19. 1. "TIMEOUT_P4,Timeout for Ports 0 1 2 3 4 5 6 and 7"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "TIMEOUT_P3,Timeout for Ports 0 1 2 3 4 5 6 and 7"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "TIMEOUT_P2,Timeout for Ports 0 1 2 3 4 5 6 and 7"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "TIMEOUT_P1,Timeout for Ports 0 1 2 3 4 5 6 and 7"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "TIMEOUT_P0,Timeout for Ports 0 1 2 3 4 5 6 and 7"
|
|
line.long 0x8 "REQ_PORT_0123,Request Port 0-1-2-3 Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. "NRQ_NWD_BDW_P3,Number of Requests Number of Words or Bandwidth Allocation from Port 0-1-2-3"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--23. 1. "NRQ_NWD_BDW_P2,Number of Requests Number of Words or Bandwidth Allocation from Port 0-1-2-3"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "NRQ_NWD_BDW_P1,Number of Requests Number of Words or Bandwidth Allocation from Port 0-1-2-3"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "NRQ_NWD_BDW_P0,Number of Requests Number of Words or Bandwidth Allocation from Port 0-1-2-3"
|
|
line.long 0xC "REQ_PORT_4567,Request Port 4-5-6-7 Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. "NRQ_NWD_BDW_P7,Number of Requests Number of Words or Bandwidth allocation from port 4-5-6-7"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--23. 1. "NRQ_NWD_BDW_P6,Number of Requests Number of Words or Bandwidth allocation from port 4-5-6-7"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "NRQ_NWD_BDW_P5,Number of Requests Number of Words or Bandwidth allocation from port 4-5-6-7"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "NRQ_NWD_BDW_P4,Number of Requests Number of Words or Bandwidth allocation from port 4-5-6-7"
|
|
rgroup.long 0x54++0x7
|
|
line.long 0x0 "BDW_PORT_0123,Current/Maximum Bandwidth Port 0-1-2-3 Register"
|
|
hexmask.long.byte 0x0 24.--30. 1. "BDW_P3,Current/Maximum Bandwidth from Port 0-1-2-3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "BDW_P2,Current/Maximum Bandwidth from Port 0-1-2-3"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "BDW_P1,Current/Maximum Bandwidth from Port 0-1-2-3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "BDW_P0,Current/Maximum Bandwidth from Port 0-1-2-3"
|
|
line.long 0x4 "BDW_PORT_4567,Current/Maximum Bandwidth Port 4-5-6-7 Register"
|
|
hexmask.long.byte 0x4 24.--30. 1. "BDW_P7,Current/Maximum Bandwidth from Port 4-5-6-7"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--22. 1. "BDW_P6,Current/Maximum Bandwidth from Port 4-5-6-7"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--14. 1. "BDW_P5,Current/Maximum Bandwidth from Port 4-5-6-7"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "BDW_P4,Current/Maximum Bandwidth from Port 4-5-6-7"
|
|
group.long 0x5C++0x27
|
|
line.long 0x0 "RD_DATA_PATH,Read Data Path Register"
|
|
bitfld.long 0x0 0.--1. "SHIFT_SAMPLING,Shift Sampling Point of Data" "0: Initial sampling point.,1: Sampling point is shifted by one cycle.,2: Sampling point is shifted by two cycles.,3: Sampling point is shifted by three cycles unique.."
|
|
line.long 0x4 "MCFGR,Monitor Configuration Register"
|
|
bitfld.long 0x4 11.--12. "INFO,Information Type" "0: Information concerning the transfer with the..,1: Number of transfers on the port,2: Total latency on the port,?"
|
|
newline
|
|
bitfld.long 0x4 10. "REFR_CALIB,Refresh Calibration" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "READ_WRITE,Read/Write Access" "0: Read and Write accesses are triggered.,1: Only Write accesses are triggered.,2: Only Read accesses are triggered.,?"
|
|
newline
|
|
bitfld.long 0x4 4. "RUN,Control Monitor" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "SOFT_RESET,Soft Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "EN_MONI,Enable Monitor" "0,1"
|
|
line.long 0x8 "MADDR0,Monitor Address High/Low Port 0 Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "ADDR_HIGH_PORT0,Address High on Port x [x = 0..7]"
|
|
newline
|
|
hexmask.long.word 0x8 0.--15. 1. "ADDR_LOW_PORT0,Address Low on Port x [x = 0..7]"
|
|
line.long 0xC "MADDR1,Monitor Address High/Low Port 1 Register"
|
|
hexmask.long.word 0xC 16.--31. 1. "ADDR_HIGH_PORT1,Address High on Port x [x = 0..7]"
|
|
newline
|
|
hexmask.long.word 0xC 0.--15. 1. "ADDR_LOW_PORT1,Address Low on Port x [x = 0..7]"
|
|
line.long 0x10 "MADDR2,Monitor Address High/Low Port 2 Register"
|
|
hexmask.long.word 0x10 16.--31. 1. "ADDR_HIGH_PORT2,Address High on Port x [x = 0..7]"
|
|
newline
|
|
hexmask.long.word 0x10 0.--15. 1. "ADDR_LOW_PORT2,Address Low on Port x [x = 0..7]"
|
|
line.long 0x14 "MADDR3,Monitor Address High/Low Port 3 Register"
|
|
hexmask.long.word 0x14 16.--31. 1. "ADDR_HIGH_PORT3,Address High on Port x [x = 0..7]"
|
|
newline
|
|
hexmask.long.word 0x14 0.--15. 1. "ADDR_LOW_PORT3,Address Low on Port x [x = 0..7]"
|
|
line.long 0x18 "MADDR4,Monitor Address High/Low Port 4 Register"
|
|
hexmask.long.word 0x18 16.--31. 1. "ADDR_HIGH_PORT4,Address High on Port x [x = 0..7]"
|
|
newline
|
|
hexmask.long.word 0x18 0.--15. 1. "ADDR_LOW_PORT4,Address Low on Port x [x = 0..7]"
|
|
line.long 0x1C "MADDR5,Monitor Address High/Low Port 5 Register"
|
|
hexmask.long.word 0x1C 16.--31. 1. "ADDR_HIGH_PORT5,Address High on Port x [x = 0..7]"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--15. 1. "ADDR_LOW_PORT5,Address Low on Port x [x = 0..7]"
|
|
line.long 0x20 "MADDR6,Monitor Address High/Low Port 6 Register"
|
|
hexmask.long.word 0x20 16.--31. 1. "ADDR_HIGH_PORT6,Address High on Port x [x = 0..7]"
|
|
newline
|
|
hexmask.long.word 0x20 0.--15. 1. "ADDR_LOW_PORT6,Address Low on Port x [x = 0..7]"
|
|
line.long 0x24 "MADDR7,Monitor Address High/Low Port 7 Register"
|
|
hexmask.long.word 0x24 16.--31. 1. "ADDR_HIGH_PORT7,Address High on Port x [x = 0..7]"
|
|
newline
|
|
hexmask.long.word 0x24 0.--15. 1. "ADDR_LOW_PORT7,Address Low on Port x [x = 0..7]"
|
|
rgroup.long 0x84++0x3
|
|
line.long 0x0 "MINFO0_MAX_WAIT_MODE,Monitor Information Port 0 Register"
|
|
bitfld.long 0x0 24. "READ_WRITE,Read or Write Access on Port x [x = 0..7]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--22. "SIZE,Transfer Size on Port x [x = 0..7]" "0: Byte transfer,1: Halfword transfer,2: Word transfer,3: Dword transfer,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "BURST,Type of Burst on Port x [x = 0..7]" "0: Single transfer,1: Incrementing burst of unspecified length,2: 4-beat wrapping burst,3: 4-beat incrementing burst,4: 8-beat wrapping burst,5: 8-beat incrementing burst,6: 16-beat wrapping burst,7: 16-beat incrementing burst"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "MAX_PORT0_WAITING,Address High on Port x [x = 0..7]"
|
|
rgroup.long 0x84++0x3
|
|
line.long 0x0 "MINFO0_NB_TRANSFERS_MODE,Monitor Information Port 0 Register"
|
|
hexmask.long 0x0 0.--31. 1. "P0_NB_TRANSFERS,Number of Transfers on Port x [x = 0..7]"
|
|
rgroup.long 0x84++0x7
|
|
line.long 0x0 "MINFO0_TOTAL_LATENCY_MODE,Monitor Information Port 0 Register"
|
|
hexmask.long 0x0 0.--31. 1. "P0_TOTAL_LATENCY,Total Latency on Port x [x = 0..7]"
|
|
line.long 0x4 "MINFO1_MAX_WAIT_MODE,Monitor Information Port 1 Register"
|
|
bitfld.long 0x4 24. "READ_WRITE,Read or Write Access on Port x [x = 0..7]" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20.--22. "SIZE,Transfer Size on Port x [x = 0..7]" "0: Byte transfer,1: Halfword transfer,2: Word transfer,3: Dword transfer,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x4 16.--18. "BURST,Type of Burst on Port x [x = 0..7]" "0: Single transfer,1: Incrementing burst of unspecified length,2: 4-beat wrapping burst,3: 4-beat incrementing burst,4: 8-beat wrapping burst,5: 8-beat incrementing burst,6: 16-beat wrapping burst,7: 16-beat incrementing burst"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "MAX_PORT1_WAITING,Address High on Port x [x = 0..7]"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "MINFO1_NB_TRANSFERS_MODE,Monitor Information Port 1 Register"
|
|
hexmask.long 0x0 0.--31. 1. "P1_NB_TRANSFERS,Number of Transfers on Port x [x = 0..7]"
|
|
rgroup.long 0x88++0x7
|
|
line.long 0x0 "MINFO1_TOTAL_LATENCY_MODE,Monitor Information Port 1 Register"
|
|
hexmask.long 0x0 0.--31. 1. "P1_TOTAL_LATENCY,Total Latency on Port x [x = 0..7]"
|
|
line.long 0x4 "MINFO2_MAX_WAIT_MODE,Monitor Information Port 2 Register"
|
|
bitfld.long 0x4 24. "READ_WRITE,Read or Write Access on Port x [x = 0..7]" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20.--22. "SIZE,Transfer Size on Port x [x = 0..7]" "0: Byte transfer,1: Halfword transfer,2: Word transfer,3: Dword transfer,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x4 16.--18. "BURST,Type of Burst on Port x [x = 0..7]" "0: Single transfer,1: Incrementing burst of unspecified length,2: 4-beat wrapping burst,3: 4-beat incrementing burst,4: 8-beat wrapping burst,5: 8-beat incrementing burst,6: 16-beat wrapping burst,7: 16-beat incrementing burst"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "MAX_PORT2_WAITING,Address High on Port x [x = 0..7]"
|
|
rgroup.long 0x8C++0x3
|
|
line.long 0x0 "MINFO2_NB_TRANSFERS_MODE,Monitor Information Port 2 Register"
|
|
hexmask.long 0x0 0.--31. 1. "P2_NB_TRANSFERS,Number of Transfers on Port x [x = 0..7]"
|
|
rgroup.long 0x8C++0x7
|
|
line.long 0x0 "MINFO2_TOTAL_LATENCY_MODE,Monitor Information Port 2 Register"
|
|
hexmask.long 0x0 0.--31. 1. "P2_TOTAL_LATENCY,Total Latency on Port x [x = 0..7]"
|
|
line.long 0x4 "MINFO3_MAX_WAIT_MODE,Monitor Information Port 3 Register"
|
|
bitfld.long 0x4 24. "READ_WRITE,Read or Write Access on Port x [x = 0..7]" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20.--22. "SIZE,Transfer Size on Port x [x = 0..7]" "0: Byte transfer,1: Halfword transfer,2: Word transfer,3: Dword transfer,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x4 16.--18. "BURST,Type of Burst on Port x [x = 0..7]" "0: Single transfer,1: Incrementing burst of unspecified length,2: 4-beat wrapping burst,3: 4-beat incrementing burst,4: 8-beat wrapping burst,5: 8-beat incrementing burst,6: 16-beat wrapping burst,7: 16-beat incrementing burst"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "MAX_PORT3_WAITING,Address High on Port x [x = 0..7]"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "MINFO3_NB_TRANSFERS_MODE,Monitor Information Port 3 Register"
|
|
hexmask.long 0x0 0.--31. 1. "P3_NB_TRANSFERS,Number of Transfers on Port x [x = 0..7]"
|
|
rgroup.long 0x90++0x7
|
|
line.long 0x0 "MINFO3_TOTAL_LATENCY_MODE,Monitor Information Port 3 Register"
|
|
hexmask.long 0x0 0.--31. 1. "P3_TOTAL_LATENCY,Total Latency on Port x [x = 0..7]"
|
|
line.long 0x4 "MINFO4_MAX_WAIT_MODE,Monitor Information Port 4 Register"
|
|
bitfld.long 0x4 24. "READ_WRITE,Read or Write Access on Port x [x = 0..7]" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20.--22. "SIZE,Transfer Size on Port x [x = 0..7]" "0: Byte transfer,1: Halfword transfer,2: Word transfer,3: Dword transfer,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x4 16.--18. "BURST,Type of Burst on Port x [x = 0..7]" "0: Single transfer,1: Incrementing burst of unspecified length,2: 4-beat wrapping burst,3: 4-beat incrementing burst,4: 8-beat wrapping burst,5: 8-beat incrementing burst,6: 16-beat wrapping burst,7: 16-beat incrementing burst"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "MAX_PORT4_WAITING,Address High on Port x [x = 0..7]"
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x0 "MINFO4_NB_TRANSFERS_MODE,Monitor Information Port 4 Register"
|
|
hexmask.long 0x0 0.--31. 1. "P4_NB_TRANSFERS,Number of Transfers on Port x [x = 0..7]"
|
|
rgroup.long 0x94++0x7
|
|
line.long 0x0 "MINFO4_TOTAL_LATENCY_MODE,Monitor Information Port 4 Register"
|
|
hexmask.long 0x0 0.--31. 1. "P4_TOTAL_LATENCY,Total Latency on Port x [x = 0..7]"
|
|
line.long 0x4 "MINFO5_MAX_WAIT_MODE,Monitor Information Port 5 Register"
|
|
bitfld.long 0x4 24. "READ_WRITE,Read or Write Access on Port x [x = 0..7]" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20.--22. "SIZE,Transfer Size on Port x [x = 0..7]" "0: Byte transfer,1: Halfword transfer,2: Word transfer,3: Dword transfer,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x4 16.--18. "BURST,Type of Burst on Port x [x = 0..7]" "0: Single transfer,1: Incrementing burst of unspecified length,2: 4-beat wrapping burst,3: 4-beat incrementing burst,4: 8-beat wrapping burst,5: 8-beat incrementing burst,6: 16-beat wrapping burst,7: 16-beat incrementing burst"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "MAX_PORT5_WAITING,Address High on Port x [x = 0..7]"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "MINFO5_NB_TRANSFERS_MODE,Monitor Information Port 5 Register"
|
|
hexmask.long 0x0 0.--31. 1. "P5_NB_TRANSFERS,Number of Transfers on Port x [x = 0..7]"
|
|
rgroup.long 0x98++0x7
|
|
line.long 0x0 "MINFO5_TOTAL_LATENCY_MODE,Monitor Information Port 5 Register"
|
|
hexmask.long 0x0 0.--31. 1. "P5_TOTAL_LATENCY,Total Latency on Port x [x = 0..7]"
|
|
line.long 0x4 "MINFO6_MAX_WAIT_MODE,Monitor Information Port 6 Register"
|
|
bitfld.long 0x4 24. "READ_WRITE,Read or Write Access on Port x [x = 0..7]" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20.--22. "SIZE,Transfer Size on Port x [x = 0..7]" "0: Byte transfer,1: Halfword transfer,2: Word transfer,3: Dword transfer,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x4 16.--18. "BURST,Type of Burst on Port x [x = 0..7]" "0: Single transfer,1: Incrementing burst of unspecified length,2: 4-beat wrapping burst,3: 4-beat incrementing burst,4: 8-beat wrapping burst,5: 8-beat incrementing burst,6: 16-beat wrapping burst,7: 16-beat incrementing burst"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "MAX_PORT6_WAITING,Address High on Port x [x = 0..7]"
|
|
rgroup.long 0x9C++0x3
|
|
line.long 0x0 "MINFO6_NB_TRANSFERS_MODE,Monitor Information Port 6 Register"
|
|
hexmask.long 0x0 0.--31. 1. "P6_NB_TRANSFERS,Number of Transfers on Port x [x = 0..7]"
|
|
rgroup.long 0x9C++0x7
|
|
line.long 0x0 "MINFO6_TOTAL_LATENCY_MODE,Monitor Information Port 6 Register"
|
|
hexmask.long 0x0 0.--31. 1. "P6_TOTAL_LATENCY,Total Latency on Port x [x = 0..7]"
|
|
line.long 0x4 "MINFO7_MAX_WAIT_MODE,Monitor Information Port 7 Register"
|
|
bitfld.long 0x4 24. "READ_WRITE,Read or Write Access on Port x [x = 0..7]" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20.--22. "SIZE,Transfer Size on Port x [x = 0..7]" "0: Byte transfer,1: Halfword transfer,2: Word transfer,3: Dword transfer,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x4 16.--18. "BURST,Type of Burst on Port x [x = 0..7]" "0: Single transfer,1: Incrementing burst of unspecified length,2: 4-beat wrapping burst,3: 4-beat incrementing burst,4: 8-beat wrapping burst,5: 8-beat incrementing burst,6: 16-beat wrapping burst,7: 16-beat incrementing burst"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "MAX_PORT7_WAITING,Address High on Port x [x = 0..7]"
|
|
rgroup.long 0xA0++0x3
|
|
line.long 0x0 "MINFO7_NB_TRANSFERS_MODE,Monitor Information Port 7 Register"
|
|
hexmask.long 0x0 0.--31. 1. "P7_NB_TRANSFERS,Number of Transfers on Port x [x = 0..7]"
|
|
rgroup.long 0xA0++0x3
|
|
line.long 0x0 "MINFO7_TOTAL_LATENCY_MODE,Monitor Information Port 7 Register"
|
|
hexmask.long 0x0 0.--31. 1. "P7_TOTAL_LATENCY,Total Latency on Port x [x = 0..7]"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Enable" "0,1"
|
|
tree.end
|
|
tree "PDMIC (Pulse Density Modulation Interface Controller)"
|
|
base ad:0xF8018000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 4. "ENPDM,Enable PDM" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "MR,Mode Register"
|
|
hexmask.long.byte 0x4 8.--14. 1. "PRESCAL,Prescaler Rate Selection"
|
|
bitfld.long 0x4 4. "CLKS,Clock Source Selection" "0,1"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "CDR,Converted Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data Converted"
|
|
wgroup.long 0x18++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 25. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 24. "DRDY,Data Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 25. "OVRE,General Overrun Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 24. "DRDY,Data Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 25. "OVRE,General Overrun Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 24. "DRDY,Data Ready Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 25. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
bitfld.long 0x4 24. "DRDY,Data Ready (cleared by reading PDMIC_CDR)" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "FIFOCNT,FIFO Count"
|
|
group.long 0x58++0x7
|
|
line.long 0x0 "DSPR0,DSP Configuration Register 0"
|
|
hexmask.long.byte 0x0 12.--15. 1. "SHIFT,Data Shift"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SCALE,Data Scale"
|
|
bitfld.long 0x0 4.--6. "OSR,Global Oversampling Ratio" "0: Global Oversampling ratio is 128 (SINC filter..,1: Global Oversampling ratio is 64 (SINC filter..,?,?,?,?,?,?"
|
|
bitfld.long 0x0 3. "SIZE,Data Size" "0,1"
|
|
bitfld.long 0x0 2. "SINBYP,SINCC Filter Bypass" "0,1"
|
|
bitfld.long 0x0 1. "HPFBYP,High-Pass Filter Bypass" "0,1"
|
|
line.long 0x4 "DSPR1,DSP Configuration Register 1"
|
|
hexmask.long.word 0x4 16.--31. 1. "OFFSET,Offset Correction"
|
|
hexmask.long.word 0x4 0.--14. 1. "DGAIN,Gain Correction"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
tree "PIO (Parallel Input/Output Controller)"
|
|
base ad:0xFC038000
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0xFC038000 ad:0xFC038040 ad:0xFC038080 ad:0xFC0380C0)
|
|
tree "PIO_GROUP[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "MSKR,PIO Mask Register"
|
|
bitfld.long 0x0 31. "MSK31,PIO Line 31 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 30. "MSK30,PIO Line 30 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
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bitfld.long 0x0 29. "MSK29,PIO Line 29 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 28. "MSK28,PIO Line 28 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 27. "MSK27,PIO Line 27 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 26. "MSK26,PIO Line 26 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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|
newline
|
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bitfld.long 0x0 25. "MSK25,PIO Line 25 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 24. "MSK24,PIO Line 24 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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|
newline
|
|
bitfld.long 0x0 23. "MSK23,PIO Line 23 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 22. "MSK22,PIO Line 22 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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newline
|
|
bitfld.long 0x0 21. "MSK21,PIO Line 21 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
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bitfld.long 0x0 20. "MSK20,PIO Line 20 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 19. "MSK19,PIO Line 19 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
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bitfld.long 0x0 18. "MSK18,PIO Line 18 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 17. "MSK17,PIO Line 17 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
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bitfld.long 0x0 16. "MSK16,PIO Line 16 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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|
newline
|
|
bitfld.long 0x0 15. "MSK15,PIO Line 15 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 14. "MSK14,PIO Line 14 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 13. "MSK13,PIO Line 13 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 12. "MSK12,PIO Line 12 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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newline
|
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bitfld.long 0x0 11. "MSK11,PIO Line 11 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
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bitfld.long 0x0 10. "MSK10,PIO Line 10 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 9. "MSK9,PIO Line 9 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
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bitfld.long 0x0 8. "MSK8,PIO Line 8 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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newline
|
|
bitfld.long 0x0 7. "MSK7,PIO Line 7 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 6. "MSK6,PIO Line 6 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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|
newline
|
|
bitfld.long 0x0 5. "MSK5,PIO Line 5 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
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bitfld.long 0x0 4. "MSK4,PIO Line 4 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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newline
|
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bitfld.long 0x0 3. "MSK3,PIO Line 3 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 2. "MSK2,PIO Line 2 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 1. "MSK1,PIO Line 1 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 0. "MSK0,PIO Line 0 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
line.long 0x4 "CFGR,PIO Configuration Register"
|
|
bitfld.long 0x4 30. "ICFS,Interrupt Configuration Freeze Status (read-only)" "0: The fields are not frozen and can be written for..,1: The fields are frozen and cannot be written for.."
|
|
bitfld.long 0x4 29. "PCFS,Physical Configuration Freeze Status (read-only)" "0: The fields are not frozen and can be written for..,1: The fields are frozen and cannot be written for.."
|
|
newline
|
|
bitfld.long 0x4 24.--26. "EVTSEL,Event Selection" "0: Event detection on input falling edge,1: Event detection on input rising edge,2: Event detection on input both edge,3: Event detection on low level input,4: Event detection on high level input,?,?,?"
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|
bitfld.long 0x4 16.--17. "DRVSTR,Drive Strength" "0: Low drive,1: Low drive,2: Medium drive,3: High drive"
|
|
newline
|
|
bitfld.long 0x4 15. "SCHMITT,Schmitt Trigger" "0: Schmitt trigger is enabled for the selected I/O..,1: Schmitt trigger is disabled for the selected I/O.."
|
|
bitfld.long 0x4 14. "OPD,Open-Drain" "0: The open-drain is disabled for the selected I/O..,1: The open-drain is enabled for the selected I/O.."
|
|
newline
|
|
bitfld.long 0x4 13. "IFSCEN,Input Filter Slow Clock Enable" "0: The glitch filter is able to filter glitches..,1: The debouncing filter is able to filter pulses.."
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|
bitfld.long 0x4 12. "IFEN,Input Filter Enable" "0: The input filter is disabled for the selected..,1: The input filter is enabled for the selected I/O.."
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|
newline
|
|
bitfld.long 0x4 10. "PDEN,Pull-Down Enable" "0: Pull-Down is disabled for the selected I/O lines.,1: Pull-Down is enabled for the selected I/O lines.."
|
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bitfld.long 0x4 9. "PUEN,Pull-Up Enable" "0: Pull-Up is disabled for the selected I/O lines.,1: Pull-Up is enabled for the selected I/O lines."
|
|
newline
|
|
bitfld.long 0x4 8. "DIR,Direction" "0: The selected I/O lines are pure inputs.,1: The selected I/O lines are enabled in output."
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|
bitfld.long 0x4 0.--2. "FUNC,I/O Line Function" "0: Select the PIO mode for the selected I/O lines.,1: Select the peripheral A for the selected I/O..,2: Select the peripheral B for the selected I/O..,3: Select the peripheral C for the selected I/O..,4: Select the peripheral D for the selected I/O..,5: Select the peripheral E for the selected I/O..,6: Select the peripheral F for the selected I/O..,7: Select the peripheral G for the selected I/O.."
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rgroup.long ($2+0x8)++0x7
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line.long 0x0 "PDSR,PIO Pin Data Status Register"
|
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bitfld.long 0x0 31. "P31,Input Data Status" "0,1"
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bitfld.long 0x0 30. "P30,Input Data Status" "0,1"
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newline
|
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bitfld.long 0x0 29. "P29,Input Data Status" "0,1"
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bitfld.long 0x0 28. "P28,Input Data Status" "0,1"
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newline
|
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bitfld.long 0x0 27. "P27,Input Data Status" "0,1"
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bitfld.long 0x0 26. "P26,Input Data Status" "0,1"
|
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newline
|
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bitfld.long 0x0 25. "P25,Input Data Status" "0,1"
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bitfld.long 0x0 24. "P24,Input Data Status" "0,1"
|
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newline
|
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bitfld.long 0x0 23. "P23,Input Data Status" "0,1"
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bitfld.long 0x0 22. "P22,Input Data Status" "0,1"
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newline
|
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bitfld.long 0x0 21. "P21,Input Data Status" "0,1"
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bitfld.long 0x0 20. "P20,Input Data Status" "0,1"
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newline
|
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bitfld.long 0x0 19. "P19,Input Data Status" "0,1"
|
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bitfld.long 0x0 18. "P18,Input Data Status" "0,1"
|
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newline
|
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bitfld.long 0x0 17. "P17,Input Data Status" "0,1"
|
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bitfld.long 0x0 16. "P16,Input Data Status" "0,1"
|
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newline
|
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bitfld.long 0x0 15. "P15,Input Data Status" "0,1"
|
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bitfld.long 0x0 14. "P14,Input Data Status" "0,1"
|
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newline
|
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bitfld.long 0x0 13. "P13,Input Data Status" "0,1"
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bitfld.long 0x0 12. "P12,Input Data Status" "0,1"
|
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newline
|
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bitfld.long 0x0 11. "P11,Input Data Status" "0,1"
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bitfld.long 0x0 10. "P10,Input Data Status" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "P9,Input Data Status" "0,1"
|
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bitfld.long 0x0 8. "P8,Input Data Status" "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "P7,Input Data Status" "0,1"
|
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bitfld.long 0x0 6. "P6,Input Data Status" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "P5,Input Data Status" "0,1"
|
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bitfld.long 0x0 4. "P4,Input Data Status" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "P3,Input Data Status" "0,1"
|
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bitfld.long 0x0 2. "P2,Input Data Status" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "P1,Input Data Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Data Status" "0,1"
|
|
line.long 0x4 "LOCKSR,PIO Lock Status Register"
|
|
bitfld.long 0x4 31. "P31,Lock Status" "0,1"
|
|
bitfld.long 0x4 30. "P30,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "P29,Lock Status" "0,1"
|
|
bitfld.long 0x4 28. "P28,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Lock Status" "0,1"
|
|
bitfld.long 0x4 26. "P26,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "P25,Lock Status" "0,1"
|
|
bitfld.long 0x4 24. "P24,Lock Status" "0,1"
|
|
newline
|
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bitfld.long 0x4 23. "P23,Lock Status" "0,1"
|
|
bitfld.long 0x4 22. "P22,Lock Status" "0,1"
|
|
newline
|
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bitfld.long 0x4 21. "P21,Lock Status" "0,1"
|
|
bitfld.long 0x4 20. "P20,Lock Status" "0,1"
|
|
newline
|
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bitfld.long 0x4 19. "P19,Lock Status" "0,1"
|
|
bitfld.long 0x4 18. "P18,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "P17,Lock Status" "0,1"
|
|
bitfld.long 0x4 16. "P16,Lock Status" "0,1"
|
|
newline
|
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bitfld.long 0x4 15. "P15,Lock Status" "0,1"
|
|
bitfld.long 0x4 14. "P14,Lock Status" "0,1"
|
|
newline
|
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bitfld.long 0x4 13. "P13,Lock Status" "0,1"
|
|
bitfld.long 0x4 12. "P12,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Lock Status" "0,1"
|
|
bitfld.long 0x4 10. "P10,Lock Status" "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "P9,Lock Status" "0,1"
|
|
bitfld.long 0x4 8. "P8,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Lock Status" "0,1"
|
|
bitfld.long 0x4 6. "P6,Lock Status" "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "P5,Lock Status" "0,1"
|
|
bitfld.long 0x4 4. "P4,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Lock Status" "0,1"
|
|
bitfld.long 0x4 2. "P2,Lock Status" "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "P1,Lock Status" "0,1"
|
|
bitfld.long 0x4 0. "P0,Lock Status" "0,1"
|
|
wgroup.long ($2+0x10)++0x7
|
|
line.long 0x0 "SODR,PIO Set Output Data Register"
|
|
bitfld.long 0x0 31. "P31,Set Output Data" "0,1"
|
|
bitfld.long 0x0 30. "P30,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "P29,Set Output Data" "0,1"
|
|
bitfld.long 0x0 28. "P28,Set Output Data" "0,1"
|
|
newline
|
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bitfld.long 0x0 27. "P27,Set Output Data" "0,1"
|
|
bitfld.long 0x0 26. "P26,Set Output Data" "0,1"
|
|
newline
|
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bitfld.long 0x0 25. "P25,Set Output Data" "0,1"
|
|
bitfld.long 0x0 24. "P24,Set Output Data" "0,1"
|
|
newline
|
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bitfld.long 0x0 23. "P23,Set Output Data" "0,1"
|
|
bitfld.long 0x0 22. "P22,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "P21,Set Output Data" "0,1"
|
|
bitfld.long 0x0 20. "P20,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Set Output Data" "0,1"
|
|
bitfld.long 0x0 18. "P18,Set Output Data" "0,1"
|
|
newline
|
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bitfld.long 0x0 17. "P17,Set Output Data" "0,1"
|
|
bitfld.long 0x0 16. "P16,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Set Output Data" "0,1"
|
|
bitfld.long 0x0 14. "P14,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P13,Set Output Data" "0,1"
|
|
bitfld.long 0x0 12. "P12,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Set Output Data" "0,1"
|
|
bitfld.long 0x0 10. "P10,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "P9,Set Output Data" "0,1"
|
|
bitfld.long 0x0 8. "P8,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Set Output Data" "0,1"
|
|
bitfld.long 0x0 6. "P6,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Set Output Data" "0,1"
|
|
bitfld.long 0x0 4. "P4,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Set Output Data" "0,1"
|
|
bitfld.long 0x0 2. "P2,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Set Output Data" "0,1"
|
|
bitfld.long 0x0 0. "P0,Set Output Data" "0,1"
|
|
line.long 0x4 "CODR,PIO Clear Output Data Register"
|
|
bitfld.long 0x4 31. "P31,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 30. "P30,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "P29,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 28. "P28,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 26. "P26,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "P25,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 24. "P24,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 22. "P22,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "P21,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 20. "P20,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 18. "P18,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "P17,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 16. "P16,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 14. "P14,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "P13,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 12. "P12,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 10. "P10,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "P9,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 8. "P8,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 6. "P6,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "P5,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 4. "P4,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 2. "P2,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "P1,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 0. "P0,Clear Output Data" "0,1"
|
|
group.long ($2+0x18)++0x3
|
|
line.long 0x0 "ODSR,PIO Output Data Status Register"
|
|
bitfld.long 0x0 31. "P31,Output Data Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "P29,Output Data Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Output Data Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "P25,Output Data Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Output Data Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "P21,Output Data Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Output Data Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "P17,Output Data Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Output Data Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P13,Output Data Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Output Data Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "P9,Output Data Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Output Data Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Output Data Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Output Data Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Output Data Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Output Data Status" "0,1"
|
|
wgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "IER,PIO Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "P31,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "P29,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "P25,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "P21,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "P17,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P13,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "P9,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Change Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,PIO Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "P31,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "P29,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "P25,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "P21,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "P17,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "P13,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "P9,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "P5,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "P1,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Input Change Interrupt Disable" "0,1"
|
|
rgroup.long ($2+0x28)++0x7
|
|
line.long 0x0 "IMR,PIO Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "P31,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "P29,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "P25,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "P21,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "P17,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P13,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "P9,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Change Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,PIO Interrupt Status Register"
|
|
bitfld.long 0x4 31. "P31,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 30. "P30,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "P29,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 28. "P28,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 26. "P26,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "P25,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 24. "P24,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 22. "P22,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "P21,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 20. "P20,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 18. "P18,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "P17,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 16. "P16,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 14. "P14,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "P13,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 12. "P12,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 10. "P10,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "P9,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 8. "P8,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 6. "P6,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "P5,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 4. "P4,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 2. "P2,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "P1,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 0. "P0,Input Change Interrupt Status" "0,1"
|
|
wgroup.long ($2+0x3C)++0x3
|
|
line.long 0x0 "IOFR,PIO I/O Freeze Configuration Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "FRZKEY,Freeze Key"
|
|
bitfld.long 0x0 1. "FINT,Freeze Interrupt Configuration" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "FPHY,Freeze Physical Configuration" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0xFC038000
|
|
group.long 0x5E0++0x3
|
|
line.long 0x0 "WPMR,PIO Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x5E4++0x3
|
|
line.long 0x0 "WPSR,PIO Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
rgroup.long 0x5FC++0x3
|
|
line.long 0x0 "VERSION,PIO Version Register"
|
|
bitfld.long 0x0 16.--18. "MFN,Metal Fix Number" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 0.--11. 1. "VERSION,Hardware Module Version"
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0xFC039000 ad:0xFC039040 ad:0xFC039080 ad:0xFC0390C0)
|
|
tree "PIO_SGROUP[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "S_PIO_MSKR,Secure PIO Mask Register"
|
|
bitfld.long 0x0 31. "MSK31,PIO Line 31 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
|
|
bitfld.long 0x0 30. "MSK30,PIO Line 30 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 29. "MSK29,PIO Line 29 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
|
|
bitfld.long 0x0 28. "MSK28,PIO Line 28 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 27. "MSK27,PIO Line 27 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
|
|
bitfld.long 0x0 26. "MSK26,PIO Line 26 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 25. "MSK25,PIO Line 25 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
|
|
bitfld.long 0x0 24. "MSK24,PIO Line 24 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 23. "MSK23,PIO Line 23 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
|
|
bitfld.long 0x0 22. "MSK22,PIO Line 22 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 21. "MSK21,PIO Line 21 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
|
|
bitfld.long 0x0 20. "MSK20,PIO Line 20 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 19. "MSK19,PIO Line 19 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
|
|
bitfld.long 0x0 18. "MSK18,PIO Line 18 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 17. "MSK17,PIO Line 17 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 16. "MSK16,PIO Line 16 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 15. "MSK15,PIO Line 15 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 14. "MSK14,PIO Line 14 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 13. "MSK13,PIO Line 13 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 12. "MSK12,PIO Line 12 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 11. "MSK11,PIO Line 11 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 10. "MSK10,PIO Line 10 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 9. "MSK9,PIO Line 9 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 8. "MSK8,PIO Line 8 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 7. "MSK7,PIO Line 7 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 6. "MSK6,PIO Line 6 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 5. "MSK5,PIO Line 5 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 4. "MSK4,PIO Line 4 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 3. "MSK3,PIO Line 3 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 2. "MSK2,PIO Line 2 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 1. "MSK1,PIO Line 1 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 0. "MSK0,PIO Line 0 Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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line.long 0x4 "S_PIO_CFGR,Secure PIO Configuration Register"
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bitfld.long 0x4 30. "ICFS,Interrupt Configuration Freeze Status (read-only)" "0: The fields are not frozen and can be written for..,1: The fields are frozen and cannot be written for.."
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bitfld.long 0x4 29. "PCFS,Physical Configuration Freeze Status (read-only)" "0: The fields are not frozen and can be written for..,1: The fields are frozen and cannot be written for.."
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bitfld.long 0x4 24.--26. "EVTSEL,Event Selection" "0: Event detection on input falling edge,1: Event detection on input rising edge,2: Event detection on input both edge,3: Event detection on low level input,4: Event detection on high level input,?,?,?"
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bitfld.long 0x4 16.--17. "DRVSTR,Drive Strength" "0: Low drive,?,2: Medium drive,3: High drive"
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bitfld.long 0x4 15. "SCHMITT,Schmitt Trigger" "0: Schmitt trigger is enabled for the selected I/O..,1: Schmitt trigger is disabled for the selected I/O.."
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bitfld.long 0x4 14. "OPD,Open-Drain" "0: The open-drain is disabled for the selected I/O..,1: The open-drain is enabled for the selected I/O.."
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bitfld.long 0x4 13. "IFSCEN,Input Filter Slow Clock Enable" "0,1"
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bitfld.long 0x4 12. "IFEN,Input Filter Enable" "0: The input filter is disabled for the selected..,1: The input filter is enabled for the selected I/O.."
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bitfld.long 0x4 10. "PDEN,Pull-Down Enable" "0: Pull-Down is disabled for the selected I/O lines.,1: Pull-Down is enabled for the selected I/O lines.."
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bitfld.long 0x4 9. "PUEN,Pull-Up Enable" "0: Pull-Up is disabled for the selected I/O lines.,1: Pull-Up is enabled for the selected I/O lines."
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bitfld.long 0x4 8. "DIR,Direction" "0: The selected I/O lines are pure inputs.,1: The selected I/O lines are enabled in output."
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bitfld.long 0x4 0.--2. "FUNC,I/O Line Function" "0: Select the PIO mode for the selected I/O lines.,1: Select the peripheral A for the selected I/O..,2: Select the peripheral B for the selected I/O..,3: Select the peripheral C for the selected I/O..,4: Select the peripheral D for the selected I/O..,5: Select the peripheral E for the selected I/O..,6: Select the peripheral F for the selected I/O..,7: Select the peripheral G for the selected I/O.."
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rgroup.long ($2+0x8)++0x7
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line.long 0x0 "S_PIO_PDSR,Secure PIO Pin Data Status Register"
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bitfld.long 0x0 31. "P31,Input Data Status" "0,1"
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bitfld.long 0x0 30. "P30,Input Data Status" "0,1"
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bitfld.long 0x0 29. "P29,Input Data Status" "0,1"
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bitfld.long 0x0 28. "P28,Input Data Status" "0,1"
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bitfld.long 0x0 27. "P27,Input Data Status" "0,1"
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bitfld.long 0x0 26. "P26,Input Data Status" "0,1"
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bitfld.long 0x0 25. "P25,Input Data Status" "0,1"
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bitfld.long 0x0 24. "P24,Input Data Status" "0,1"
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bitfld.long 0x0 23. "P23,Input Data Status" "0,1"
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bitfld.long 0x0 22. "P22,Input Data Status" "0,1"
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bitfld.long 0x0 21. "P21,Input Data Status" "0,1"
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bitfld.long 0x0 20. "P20,Input Data Status" "0,1"
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bitfld.long 0x0 19. "P19,Input Data Status" "0,1"
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bitfld.long 0x0 18. "P18,Input Data Status" "0,1"
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bitfld.long 0x0 17. "P17,Input Data Status" "0,1"
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bitfld.long 0x0 16. "P16,Input Data Status" "0,1"
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bitfld.long 0x0 15. "P15,Input Data Status" "0,1"
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bitfld.long 0x0 14. "P14,Input Data Status" "0,1"
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bitfld.long 0x0 13. "P13,Input Data Status" "0,1"
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bitfld.long 0x0 12. "P12,Input Data Status" "0,1"
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bitfld.long 0x0 11. "P11,Input Data Status" "0,1"
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bitfld.long 0x0 10. "P10,Input Data Status" "0,1"
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bitfld.long 0x0 9. "P9,Input Data Status" "0,1"
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bitfld.long 0x0 8. "P8,Input Data Status" "0,1"
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bitfld.long 0x0 7. "P7,Input Data Status" "0,1"
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bitfld.long 0x0 6. "P6,Input Data Status" "0,1"
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bitfld.long 0x0 5. "P5,Input Data Status" "0,1"
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bitfld.long 0x0 4. "P4,Input Data Status" "0,1"
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bitfld.long 0x0 3. "P3,Input Data Status" "0,1"
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bitfld.long 0x0 2. "P2,Input Data Status" "0,1"
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bitfld.long 0x0 1. "P1,Input Data Status" "0,1"
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bitfld.long 0x0 0. "P0,Input Data Status" "0,1"
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line.long 0x4 "S_PIO_LOCKSR,Secure PIO Lock Status Register"
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bitfld.long 0x4 31. "P31,Lock Status" "0,1"
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bitfld.long 0x4 30. "P30,Lock Status" "0,1"
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bitfld.long 0x4 29. "P29,Lock Status" "0,1"
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bitfld.long 0x4 28. "P28,Lock Status" "0,1"
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bitfld.long 0x4 27. "P27,Lock Status" "0,1"
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bitfld.long 0x4 26. "P26,Lock Status" "0,1"
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bitfld.long 0x4 25. "P25,Lock Status" "0,1"
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bitfld.long 0x4 24. "P24,Lock Status" "0,1"
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bitfld.long 0x4 23. "P23,Lock Status" "0,1"
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bitfld.long 0x4 22. "P22,Lock Status" "0,1"
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bitfld.long 0x4 21. "P21,Lock Status" "0,1"
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bitfld.long 0x4 20. "P20,Lock Status" "0,1"
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bitfld.long 0x4 19. "P19,Lock Status" "0,1"
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bitfld.long 0x4 18. "P18,Lock Status" "0,1"
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bitfld.long 0x4 17. "P17,Lock Status" "0,1"
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bitfld.long 0x4 16. "P16,Lock Status" "0,1"
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bitfld.long 0x4 15. "P15,Lock Status" "0,1"
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bitfld.long 0x4 14. "P14,Lock Status" "0,1"
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bitfld.long 0x4 13. "P13,Lock Status" "0,1"
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bitfld.long 0x4 12. "P12,Lock Status" "0,1"
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bitfld.long 0x4 11. "P11,Lock Status" "0,1"
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bitfld.long 0x4 10. "P10,Lock Status" "0,1"
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bitfld.long 0x4 9. "P9,Lock Status" "0,1"
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bitfld.long 0x4 8. "P8,Lock Status" "0,1"
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bitfld.long 0x4 7. "P7,Lock Status" "0,1"
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bitfld.long 0x4 6. "P6,Lock Status" "0,1"
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bitfld.long 0x4 5. "P5,Lock Status" "0,1"
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bitfld.long 0x4 4. "P4,Lock Status" "0,1"
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bitfld.long 0x4 3. "P3,Lock Status" "0,1"
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bitfld.long 0x4 2. "P2,Lock Status" "0,1"
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bitfld.long 0x4 1. "P1,Lock Status" "0,1"
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bitfld.long 0x4 0. "P0,Lock Status" "0,1"
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wgroup.long ($2+0x10)++0x7
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line.long 0x0 "S_PIO_SODR,Secure PIO Set Output Data Register"
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bitfld.long 0x0 31. "P31,Set Output Data" "0,1"
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bitfld.long 0x0 30. "P30,Set Output Data" "0,1"
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bitfld.long 0x0 29. "P29,Set Output Data" "0,1"
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bitfld.long 0x0 28. "P28,Set Output Data" "0,1"
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bitfld.long 0x0 27. "P27,Set Output Data" "0,1"
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bitfld.long 0x0 26. "P26,Set Output Data" "0,1"
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bitfld.long 0x0 25. "P25,Set Output Data" "0,1"
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bitfld.long 0x0 24. "P24,Set Output Data" "0,1"
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bitfld.long 0x0 23. "P23,Set Output Data" "0,1"
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bitfld.long 0x0 22. "P22,Set Output Data" "0,1"
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bitfld.long 0x0 21. "P21,Set Output Data" "0,1"
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bitfld.long 0x0 20. "P20,Set Output Data" "0,1"
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bitfld.long 0x0 19. "P19,Set Output Data" "0,1"
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bitfld.long 0x0 18. "P18,Set Output Data" "0,1"
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bitfld.long 0x0 17. "P17,Set Output Data" "0,1"
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bitfld.long 0x0 16. "P16,Set Output Data" "0,1"
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bitfld.long 0x0 15. "P15,Set Output Data" "0,1"
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bitfld.long 0x0 14. "P14,Set Output Data" "0,1"
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bitfld.long 0x0 13. "P13,Set Output Data" "0,1"
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bitfld.long 0x0 12. "P12,Set Output Data" "0,1"
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bitfld.long 0x0 11. "P11,Set Output Data" "0,1"
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bitfld.long 0x0 10. "P10,Set Output Data" "0,1"
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bitfld.long 0x0 9. "P9,Set Output Data" "0,1"
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bitfld.long 0x0 8. "P8,Set Output Data" "0,1"
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bitfld.long 0x0 7. "P7,Set Output Data" "0,1"
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bitfld.long 0x0 6. "P6,Set Output Data" "0,1"
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bitfld.long 0x0 5. "P5,Set Output Data" "0,1"
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bitfld.long 0x0 4. "P4,Set Output Data" "0,1"
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bitfld.long 0x0 3. "P3,Set Output Data" "0,1"
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bitfld.long 0x0 2. "P2,Set Output Data" "0,1"
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bitfld.long 0x0 1. "P1,Set Output Data" "0,1"
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bitfld.long 0x0 0. "P0,Set Output Data" "0,1"
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line.long 0x4 "S_PIO_CODR,Secure PIO Clear Output Data Register"
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bitfld.long 0x4 31. "P31,Clear Output Data" "0,1"
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bitfld.long 0x4 30. "P30,Clear Output Data" "0,1"
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bitfld.long 0x4 29. "P29,Clear Output Data" "0,1"
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bitfld.long 0x4 28. "P28,Clear Output Data" "0,1"
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bitfld.long 0x4 27. "P27,Clear Output Data" "0,1"
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bitfld.long 0x4 26. "P26,Clear Output Data" "0,1"
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bitfld.long 0x4 25. "P25,Clear Output Data" "0,1"
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bitfld.long 0x4 24. "P24,Clear Output Data" "0,1"
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bitfld.long 0x4 23. "P23,Clear Output Data" "0,1"
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bitfld.long 0x4 22. "P22,Clear Output Data" "0,1"
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bitfld.long 0x4 21. "P21,Clear Output Data" "0,1"
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bitfld.long 0x4 20. "P20,Clear Output Data" "0,1"
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bitfld.long 0x4 19. "P19,Clear Output Data" "0,1"
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bitfld.long 0x4 18. "P18,Clear Output Data" "0,1"
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bitfld.long 0x4 17. "P17,Clear Output Data" "0,1"
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bitfld.long 0x4 16. "P16,Clear Output Data" "0,1"
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bitfld.long 0x4 15. "P15,Clear Output Data" "0,1"
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bitfld.long 0x4 14. "P14,Clear Output Data" "0,1"
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bitfld.long 0x4 13. "P13,Clear Output Data" "0,1"
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bitfld.long 0x4 12. "P12,Clear Output Data" "0,1"
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bitfld.long 0x4 11. "P11,Clear Output Data" "0,1"
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bitfld.long 0x4 10. "P10,Clear Output Data" "0,1"
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bitfld.long 0x4 9. "P9,Clear Output Data" "0,1"
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bitfld.long 0x4 8. "P8,Clear Output Data" "0,1"
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bitfld.long 0x4 7. "P7,Clear Output Data" "0,1"
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bitfld.long 0x4 6. "P6,Clear Output Data" "0,1"
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bitfld.long 0x4 5. "P5,Clear Output Data" "0,1"
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bitfld.long 0x4 4. "P4,Clear Output Data" "0,1"
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bitfld.long 0x4 3. "P3,Clear Output Data" "0,1"
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bitfld.long 0x4 2. "P2,Clear Output Data" "0,1"
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bitfld.long 0x4 1. "P1,Clear Output Data" "0,1"
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bitfld.long 0x4 0. "P0,Clear Output Data" "0,1"
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group.long ($2+0x18)++0x3
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line.long 0x0 "S_PIO_ODSR,Secure PIO Output Data Status Register"
|
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bitfld.long 0x0 31. "P31,Output Data Status" "0,1"
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bitfld.long 0x0 30. "P30,Output Data Status" "0,1"
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newline
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bitfld.long 0x0 29. "P29,Output Data Status" "0,1"
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bitfld.long 0x0 28. "P28,Output Data Status" "0,1"
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newline
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bitfld.long 0x0 27. "P27,Output Data Status" "0,1"
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bitfld.long 0x0 26. "P26,Output Data Status" "0,1"
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newline
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bitfld.long 0x0 25. "P25,Output Data Status" "0,1"
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bitfld.long 0x0 24. "P24,Output Data Status" "0,1"
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newline
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bitfld.long 0x0 23. "P23,Output Data Status" "0,1"
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bitfld.long 0x0 22. "P22,Output Data Status" "0,1"
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newline
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bitfld.long 0x0 21. "P21,Output Data Status" "0,1"
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bitfld.long 0x0 20. "P20,Output Data Status" "0,1"
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newline
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bitfld.long 0x0 19. "P19,Output Data Status" "0,1"
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bitfld.long 0x0 18. "P18,Output Data Status" "0,1"
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newline
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bitfld.long 0x0 17. "P17,Output Data Status" "0,1"
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bitfld.long 0x0 16. "P16,Output Data Status" "0,1"
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newline
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bitfld.long 0x0 15. "P15,Output Data Status" "0,1"
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bitfld.long 0x0 14. "P14,Output Data Status" "0,1"
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newline
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bitfld.long 0x0 13. "P13,Output Data Status" "0,1"
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bitfld.long 0x0 12. "P12,Output Data Status" "0,1"
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newline
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bitfld.long 0x0 11. "P11,Output Data Status" "0,1"
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bitfld.long 0x0 10. "P10,Output Data Status" "0,1"
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bitfld.long 0x0 9. "P9,Output Data Status" "0,1"
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bitfld.long 0x0 8. "P8,Output Data Status" "0,1"
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bitfld.long 0x0 7. "P7,Output Data Status" "0,1"
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bitfld.long 0x0 6. "P6,Output Data Status" "0,1"
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|
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bitfld.long 0x0 5. "P5,Output Data Status" "0,1"
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bitfld.long 0x0 4. "P4,Output Data Status" "0,1"
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newline
|
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bitfld.long 0x0 3. "P3,Output Data Status" "0,1"
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bitfld.long 0x0 2. "P2,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Output Data Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Output Data Status" "0,1"
|
|
wgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "S_PIO_IER,Secure PIO Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "P31,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "P29,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "P25,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "P21,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "P17,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P13,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "P9,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Change Interrupt Enable" "0,1"
|
|
line.long 0x4 "S_PIO_IDR,Secure PIO Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "P31,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "P29,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "P25,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "P21,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "P17,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "P13,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "P9,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "P5,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "P1,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Input Change Interrupt Disable" "0,1"
|
|
rgroup.long ($2+0x28)++0x7
|
|
line.long 0x0 "S_PIO_IMR,Secure PIO Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "P31,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "P29,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "P25,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "P21,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "P17,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P13,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "P9,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Change Interrupt Mask" "0,1"
|
|
line.long 0x4 "S_PIO_ISR,Secure PIO Interrupt Status Register"
|
|
bitfld.long 0x4 31. "P31,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 30. "P30,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "P29,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 28. "P28,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 26. "P26,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "P25,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 24. "P24,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 22. "P22,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "P21,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 20. "P20,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 18. "P18,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "P17,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 16. "P16,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 14. "P14,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "P13,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 12. "P12,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 10. "P10,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "P9,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 8. "P8,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 6. "P6,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "P5,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 4. "P4,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 2. "P2,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "P1,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 0. "P0,Input Change Interrupt Status" "0,1"
|
|
wgroup.long ($2+0x30)++0x7
|
|
line.long 0x0 "S_PIO_SIONR,Secure PIO Set I/O Non-Secure Register"
|
|
bitfld.long 0x0 31. "P31,Set I/O Non-Secure" "0,1"
|
|
bitfld.long 0x0 30. "P30,Set I/O Non-Secure" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "P29,Set I/O Non-Secure" "0,1"
|
|
bitfld.long 0x0 28. "P28,Set I/O Non-Secure" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Set I/O Non-Secure" "0,1"
|
|
bitfld.long 0x0 26. "P26,Set I/O Non-Secure" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "P25,Set I/O Non-Secure" "0,1"
|
|
bitfld.long 0x0 24. "P24,Set I/O Non-Secure" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Set I/O Non-Secure" "0,1"
|
|
bitfld.long 0x0 22. "P22,Set I/O Non-Secure" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "P21,Set I/O Non-Secure" "0,1"
|
|
bitfld.long 0x0 20. "P20,Set I/O Non-Secure" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Set I/O Non-Secure" "0,1"
|
|
bitfld.long 0x0 18. "P18,Set I/O Non-Secure" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "P17,Set I/O Non-Secure" "0,1"
|
|
bitfld.long 0x0 16. "P16,Set I/O Non-Secure" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Set I/O Non-Secure" "0,1"
|
|
bitfld.long 0x0 14. "P14,Set I/O Non-Secure" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P13,Set I/O Non-Secure" "0,1"
|
|
bitfld.long 0x0 12. "P12,Set I/O Non-Secure" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Set I/O Non-Secure" "0,1"
|
|
bitfld.long 0x0 10. "P10,Set I/O Non-Secure" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "P9,Set I/O Non-Secure" "0,1"
|
|
bitfld.long 0x0 8. "P8,Set I/O Non-Secure" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Set I/O Non-Secure" "0,1"
|
|
bitfld.long 0x0 6. "P6,Set I/O Non-Secure" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Set I/O Non-Secure" "0,1"
|
|
bitfld.long 0x0 4. "P4,Set I/O Non-Secure" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Set I/O Non-Secure" "0,1"
|
|
bitfld.long 0x0 2. "P2,Set I/O Non-Secure" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Set I/O Non-Secure" "0,1"
|
|
bitfld.long 0x0 0. "P0,Set I/O Non-Secure" "0,1"
|
|
line.long 0x4 "S_PIO_SIOSR,Secure PIO Set I/O Secure Register"
|
|
bitfld.long 0x4 31. "P31,Set I/O Secure" "0,1"
|
|
bitfld.long 0x4 30. "P30,Set I/O Secure" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "P29,Set I/O Secure" "0,1"
|
|
bitfld.long 0x4 28. "P28,Set I/O Secure" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Set I/O Secure" "0,1"
|
|
bitfld.long 0x4 26. "P26,Set I/O Secure" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "P25,Set I/O Secure" "0,1"
|
|
bitfld.long 0x4 24. "P24,Set I/O Secure" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Set I/O Secure" "0,1"
|
|
bitfld.long 0x4 22. "P22,Set I/O Secure" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "P21,Set I/O Secure" "0,1"
|
|
bitfld.long 0x4 20. "P20,Set I/O Secure" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Set I/O Secure" "0,1"
|
|
bitfld.long 0x4 18. "P18,Set I/O Secure" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "P17,Set I/O Secure" "0,1"
|
|
bitfld.long 0x4 16. "P16,Set I/O Secure" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Set I/O Secure" "0,1"
|
|
bitfld.long 0x4 14. "P14,Set I/O Secure" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "P13,Set I/O Secure" "0,1"
|
|
bitfld.long 0x4 12. "P12,Set I/O Secure" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Set I/O Secure" "0,1"
|
|
bitfld.long 0x4 10. "P10,Set I/O Secure" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "P9,Set I/O Secure" "0,1"
|
|
bitfld.long 0x4 8. "P8,Set I/O Secure" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Set I/O Secure" "0,1"
|
|
bitfld.long 0x4 6. "P6,Set I/O Secure" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "P5,Set I/O Secure" "0,1"
|
|
bitfld.long 0x4 4. "P4,Set I/O Secure" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Set I/O Secure" "0,1"
|
|
bitfld.long 0x4 2. "P2,Set I/O Secure" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "P1,Set I/O Secure" "0,1"
|
|
bitfld.long 0x4 0. "P0,Set I/O Secure" "0,1"
|
|
rgroup.long ($2+0x38)++0x3
|
|
line.long 0x0 "S_PIO_IOSSR,Secure PIO I/O Security Status Register"
|
|
bitfld.long 0x0 31. "P31,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
bitfld.long 0x0 30. "P30,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
newline
|
|
bitfld.long 0x0 29. "P29,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
bitfld.long 0x0 28. "P28,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
newline
|
|
bitfld.long 0x0 27. "P27,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
bitfld.long 0x0 26. "P26,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
newline
|
|
bitfld.long 0x0 25. "P25,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
bitfld.long 0x0 24. "P24,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
newline
|
|
bitfld.long 0x0 23. "P23,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
bitfld.long 0x0 22. "P22,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
newline
|
|
bitfld.long 0x0 21. "P21,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
bitfld.long 0x0 20. "P20,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
newline
|
|
bitfld.long 0x0 19. "P19,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
bitfld.long 0x0 18. "P18,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
newline
|
|
bitfld.long 0x0 17. "P17,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
bitfld.long 0x0 16. "P16,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
newline
|
|
bitfld.long 0x0 15. "P15,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
bitfld.long 0x0 14. "P14,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
newline
|
|
bitfld.long 0x0 13. "P13,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
bitfld.long 0x0 12. "P12,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
newline
|
|
bitfld.long 0x0 11. "P11,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
bitfld.long 0x0 10. "P10,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
newline
|
|
bitfld.long 0x0 9. "P9,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
bitfld.long 0x0 8. "P8,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
newline
|
|
bitfld.long 0x0 7. "P7,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
bitfld.long 0x0 6. "P6,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
newline
|
|
bitfld.long 0x0 5. "P5,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
bitfld.long 0x0 4. "P4,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
newline
|
|
bitfld.long 0x0 3. "P3,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
bitfld.long 0x0 2. "P2,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
newline
|
|
bitfld.long 0x0 1. "P1,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
bitfld.long 0x0 0. "P0,I/O Security Status" "0: The I/O line of the I/O group 0 is in Secure mode.,1: The I/O line of the I/O group 0 is in Non-Secure.."
|
|
wgroup.long ($2+0x3C)++0x3
|
|
line.long 0x0 "S_PIO_IOFR,Secure PIO I/O Freeze Configuration Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "FRZKEY,Freeze Key"
|
|
bitfld.long 0x0 1. "FINT,Freeze Interrupt Configuration" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "FPHY,Freeze Physical Configuration" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0xFC038000
|
|
group.long 0x1500++0x3
|
|
line.long 0x0 "S_PIO_SCDR,Secure PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "DIV,Slow Clock Divider Selection for Debouncing"
|
|
group.long 0x15E0++0x3
|
|
line.long 0x0 "S_PIO_WPMR,Secure PIO Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x15E4++0x3
|
|
line.long 0x0 "S_PIO_WPSR,Secure PIO Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
tree "PIT (Periodic Interval Timer)"
|
|
base ad:0xF8048030
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 25. "PITIEN,Periodic Interval Timer Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 24. "PITEN,Period Interval Timer Enabled" "0,1"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "PIV,Periodic Interval Value"
|
|
rgroup.long 0x4++0xB
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 0. "PITS,Periodic Interval Timer Status" "0,1"
|
|
line.long 0x4 "PIVR,Periodic Interval Value Register"
|
|
hexmask.long.word 0x4 20.--31. 1. "PICNT,Periodic Interval Counter"
|
|
hexmask.long.tbyte 0x4 0.--19. 1. "CPIV,Current Periodic Interval Value"
|
|
line.long 0x8 "PIIR,Periodic Interval Image Register"
|
|
hexmask.long.word 0x8 20.--31. 1. "PICNT,Periodic Interval Counter"
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "CPIV,Current Periodic Interval Value"
|
|
tree.end
|
|
tree "PMC (Power Management Controller)"
|
|
base ad:0xF0014000
|
|
wgroup.long 0x0++0x7
|
|
line.long 0x0 "SCER,System Clock Enable Register"
|
|
bitfld.long 0x0 18. "ISCCK,ISC Clock Enable" "0,1"
|
|
bitfld.long 0x0 10. "PCK2,Programmable Clock 2 Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PCK1,Programmable Clock 1 Output Enable" "0,1"
|
|
bitfld.long 0x0 8. "PCK0,Programmable Clock 0 Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UDP,USB Device Clock Enable" "0,1"
|
|
bitfld.long 0x0 6. "UHP,USB Host OHCI Clocks Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "LCDCK,MCK2x Clock Enable" "0,1"
|
|
bitfld.long 0x0 2. "DDRCK,DDR Clock Enable" "0,1"
|
|
line.long 0x4 "SCDR,System Clock Disable Register"
|
|
bitfld.long 0x4 18. "ISCCK,ISC Clock Disable" "0,1"
|
|
bitfld.long 0x4 10. "PCK2,Programmable Clock 2 Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PCK1,Programmable Clock 1 Output Disable" "0,1"
|
|
bitfld.long 0x4 8. "PCK0,Programmable Clock 0 Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "UDP,USB Device Clock Enable" "0,1"
|
|
bitfld.long 0x4 6. "UHP,USB Host OHCI Clock Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "LCDCK,MCK2x Clock Disable" "0,1"
|
|
bitfld.long 0x4 2. "DDRCK,DDR Clock Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "PCK,Processor Clock Disable" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SCSR,System Clock Status Register"
|
|
bitfld.long 0x0 18. "ISCCK,ISC Clock Status" "0,1"
|
|
bitfld.long 0x0 10. "PCK2,Programmable Clock 2 Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PCK1,Programmable Clock 1 Output Status" "0,1"
|
|
bitfld.long 0x0 8. "PCK0,Programmable Clock 0 Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UDP,USB Device Port Clock Status" "0,1"
|
|
bitfld.long 0x0 6. "UHP,USB Host Port Clock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "LCDCK,MCK2x Clock Status" "0,1"
|
|
bitfld.long 0x0 2. "DDRCK,DDR Clock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PCK,Processor Clock Status" "0,1"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "PCER0,Peripheral Clock Enable Register 0"
|
|
bitfld.long 0x0 31. "PID31,Peripheral Clock 31 Enable" "0,1"
|
|
bitfld.long 0x0 30. "PID30,Peripheral Clock 30 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "PID29,Peripheral Clock 29 Enable" "0,1"
|
|
bitfld.long 0x0 28. "PID28,Peripheral Clock 28 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "PID27,Peripheral Clock 27 Enable" "0,1"
|
|
bitfld.long 0x0 26. "PID26,Peripheral Clock 26 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "PID25,Peripheral Clock 25 Enable" "0,1"
|
|
bitfld.long 0x0 24. "PID24,Peripheral Clock 24 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "PID23,Peripheral Clock 23 Enable" "0,1"
|
|
bitfld.long 0x0 22. "PID22,Peripheral Clock 22 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "PID21,Peripheral Clock 21 Enable" "0,1"
|
|
bitfld.long 0x0 20. "PID20,Peripheral Clock 20 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PID19,Peripheral Clock 19 Enable" "0,1"
|
|
bitfld.long 0x0 18. "PID18,Peripheral Clock 18 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PID17,Peripheral Clock 17 Enable" "0,1"
|
|
bitfld.long 0x0 16. "PID16,Peripheral Clock 16 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "PID15,Peripheral Clock 15 Enable" "0,1"
|
|
bitfld.long 0x0 14. "PID14,Peripheral Clock 14 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PID13,Peripheral Clock 13 Enable" "0,1"
|
|
bitfld.long 0x0 12. "PID12,Peripheral Clock 12 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PID11,Peripheral Clock 11 Enable" "0,1"
|
|
bitfld.long 0x0 10. "PID10,Peripheral Clock 10 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PID9,Peripheral Clock 9 Enable" "0,1"
|
|
bitfld.long 0x0 8. "PID8,Peripheral Clock 8 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PID7,Peripheral Clock 7 Enable" "0,1"
|
|
bitfld.long 0x0 6. "PID6,Peripheral Clock 6 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PID5,Peripheral Clock 5 Enable" "0,1"
|
|
bitfld.long 0x0 4. "PID4,Peripheral Clock 4 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "PID3,Peripheral Clock 3 Enable" "0,1"
|
|
bitfld.long 0x0 2. "PID2,Peripheral Clock 2 Enable" "0,1"
|
|
line.long 0x4 "PCDR0,Peripheral Clock Disable Register 0"
|
|
bitfld.long 0x4 31. "PID31,Peripheral Clock 31 Disable" "0,1"
|
|
bitfld.long 0x4 30. "PID30,Peripheral Clock 30 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "PID29,Peripheral Clock 29 Disable" "0,1"
|
|
bitfld.long 0x4 28. "PID28,Peripheral Clock 28 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "PID27,Peripheral Clock 27 Disable" "0,1"
|
|
bitfld.long 0x4 26. "PID26,Peripheral Clock 26 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "PID25,Peripheral Clock 25 Disable" "0,1"
|
|
bitfld.long 0x4 24. "PID24,Peripheral Clock 24 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "PID23,Peripheral Clock 23 Disable" "0,1"
|
|
bitfld.long 0x4 22. "PID22,Peripheral Clock 22 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "PID21,Peripheral Clock 21 Disable" "0,1"
|
|
bitfld.long 0x4 20. "PID20,Peripheral Clock 20 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PID19,Peripheral Clock 19 Disable" "0,1"
|
|
bitfld.long 0x4 18. "PID18,Peripheral Clock 18 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PID17,Peripheral Clock 17 Disable" "0,1"
|
|
bitfld.long 0x4 16. "PID16,Peripheral Clock 16 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "PID15,Peripheral Clock 15 Disable" "0,1"
|
|
bitfld.long 0x4 14. "PID14,Peripheral Clock 14 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "PID13,Peripheral Clock 13 Disable" "0,1"
|
|
bitfld.long 0x4 12. "PID12,Peripheral Clock 12 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "PID11,Peripheral Clock 11 Disable" "0,1"
|
|
bitfld.long 0x4 10. "PID10,Peripheral Clock 10 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PID9,Peripheral Clock 9 Disable" "0,1"
|
|
bitfld.long 0x4 8. "PID8,Peripheral Clock 8 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PID7,Peripheral Clock 7 Disable" "0,1"
|
|
bitfld.long 0x4 6. "PID6,Peripheral Clock 6 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PID5,Peripheral Clock 5 Disable" "0,1"
|
|
bitfld.long 0x4 4. "PID4,Peripheral Clock 4 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PID3,Peripheral Clock 3 Disable" "0,1"
|
|
bitfld.long 0x4 2. "PID2,Peripheral Clock 2 Disable" "0,1"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "PCSR0,Peripheral Clock Status Register 0"
|
|
bitfld.long 0x0 31. "PID31,Peripheral Clock 31 Status" "0,1"
|
|
bitfld.long 0x0 30. "PID30,Peripheral Clock 30 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "PID29,Peripheral Clock 29 Status" "0,1"
|
|
bitfld.long 0x0 28. "PID28,Peripheral Clock 28 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "PID27,Peripheral Clock 27 Status" "0,1"
|
|
bitfld.long 0x0 26. "PID26,Peripheral Clock 26 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "PID25,Peripheral Clock 25 Status" "0,1"
|
|
bitfld.long 0x0 24. "PID24,Peripheral Clock 24 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "PID23,Peripheral Clock 23 Status" "0,1"
|
|
bitfld.long 0x0 22. "PID22,Peripheral Clock 22 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "PID21,Peripheral Clock 21 Status" "0,1"
|
|
bitfld.long 0x0 20. "PID20,Peripheral Clock 20 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PID19,Peripheral Clock 19 Status" "0,1"
|
|
bitfld.long 0x0 18. "PID18,Peripheral Clock 18 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PID17,Peripheral Clock 17 Status" "0,1"
|
|
bitfld.long 0x0 16. "PID16,Peripheral Clock 16 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "PID15,Peripheral Clock 15 Status" "0,1"
|
|
bitfld.long 0x0 14. "PID14,Peripheral Clock 14 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PID13,Peripheral Clock 13 Status" "0,1"
|
|
bitfld.long 0x0 12. "PID12,Peripheral Clock 12 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PID11,Peripheral Clock 11 Status" "0,1"
|
|
bitfld.long 0x0 10. "PID10,Peripheral Clock 10 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PID9,Peripheral Clock 9 Status" "0,1"
|
|
bitfld.long 0x0 8. "PID8,Peripheral Clock 8 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PID7,Peripheral Clock 7 Status" "0,1"
|
|
bitfld.long 0x0 6. "PID6,Peripheral Clock 6 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PID5,Peripheral Clock 5 Status" "0,1"
|
|
bitfld.long 0x0 4. "PID4,Peripheral Clock 4 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "PID3,Peripheral Clock 3 Status" "0,1"
|
|
bitfld.long 0x0 2. "PID2,Peripheral Clock 2 Status" "0,1"
|
|
group.long 0x1C++0xF
|
|
line.long 0x0 "CKGR_UCKR,UTMI Clock Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "BIASCOUNT,UTMI BIAS Startup Time"
|
|
bitfld.long 0x0 24. "BIASEN,UTMI BIAS Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "UPLLCOUNT,UTMI PLL Startup Time"
|
|
bitfld.long 0x0 16. "UPLLEN,UTMI PLL Enable" "0,1"
|
|
line.long 0x4 "CKGR_MOR,Main Oscillator Register"
|
|
bitfld.long 0x4 25. "CFDEN,Clock Failure Detector Enable" "0,1"
|
|
bitfld.long 0x4 24. "MOSCSEL,Main Clock Oscillator Selection" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "KEY,Password"
|
|
hexmask.long.byte 0x4 8.--15. 1. "MOSCXTST,8 to 24 MHz Crystal Oscillator Startup Time"
|
|
newline
|
|
bitfld.long 0x4 5. "ONE,Must Be Set to 1" "0,1"
|
|
bitfld.long 0x4 3. "MOSCRCEN,12 MHz RC Oscillator Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "WAITMODE,Wait Mode Command (Write-only)" "0,1"
|
|
bitfld.long 0x4 1. "MOSCXTBY,8 to 24 MHz Crystal Oscillator Bypass" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "MOSCXTEN,8 to 24 MHz Crystal Oscillator Enable" "0,1"
|
|
line.long 0x8 "CKGR_MCFR,Main Clock Frequency Register"
|
|
bitfld.long 0x8 24. "CCSS,Counter Clock Source Selection" "0,1"
|
|
bitfld.long 0x8 20. "RCMEAS,RC Oscillator Frequency Measure (write-only)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "MAINFRDY,Main Clock Frequency Measure Ready" "0,1"
|
|
hexmask.long.word 0x8 0.--15. 1. "MAINF,Main Clock Frequency"
|
|
line.long 0xC "CKGR_PLLAR,PLLA Register"
|
|
bitfld.long 0xC 29. "ONE,Must Be Set to 1" "0,1"
|
|
hexmask.long.byte 0xC 18.--24. 1. "MULA,PLLA Multiplier"
|
|
newline
|
|
hexmask.long.byte 0xC 14.--17. 1. "OUTA,PLLA Clock Frequency Range"
|
|
hexmask.long.byte 0xC 8.--13. 1. "PLLACOUNT,PLLA Counter"
|
|
newline
|
|
bitfld.long 0xC 0. "DIVA,Divider A" "0,1"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "MCKR,Master Clock Register"
|
|
bitfld.long 0x0 24. "H32MXDIV,AHB 32-bit Matrix Divisor" "0: The AHB 32-bit Matrix frequency is equal to the..,1: The AHB 32-bit Matrix frequency is equal to the.."
|
|
bitfld.long 0x0 12. "PLLADIV2,PLLA Divisor by 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "MDIV,Master Clock Division" "0: Master Clock is Prescaler Output Clock divided..,1: Master Clock is Prescaler Output Clock divided..,2: Master Clock is Prescaler Output Clock divided..,3: Master Clock is Prescaler Output Clock divided.."
|
|
bitfld.long 0x0 4.--6. "PRES,Master/Processor Clock Prescaler" "0: Selected clock,1: Selected clock divided by 2,2: Selected clock divided by 4,3: Selected clock divided by 8,4: Selected clock divided by 16,5: Selected clock divided by 32,6: Selected clock divided by 64,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CSS,Master/Processor Clock Source Selection" "0: Slow clock is selected,1: Main clock is selected,2: PLLACK is selected,3: UPLL Clock is selected"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "USB,USB Clock Register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "USBDIV,Divider for USB OHCI Clock"
|
|
bitfld.long 0x0 0. "USBS,USB OHCI Input Clock Selection" "0,1"
|
|
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "PCK[$1],Programmable Clock 0 Register"
|
|
hexmask.long.byte 0x0 4.--11. 1. "PRES,Programmable Clock Prescaler"
|
|
bitfld.long 0x0 0.--2. "CSS,Master Clock Source Selection" "0: Slow clock is selected,1: Main clock is selected,2: PLLACK is selected,3: UPLL Clock is selected,4: Master Clock is selected,5: Audio PLL clock is selected,?,?"
|
|
repeat.end
|
|
wgroup.long 0x60++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 18. "CFDEV,Clock Failure Detector Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 17. "MOSCRCS,12 MHz RC Oscillator Status Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MOSCSELS,Main Clock Source Oscillator Selection Status Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 10. "PCKRDY2,Programmable Clock Ready 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PCKRDY1,Programmable Clock Ready 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "PCKRDY0,Programmable Clock Ready 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LOCKU,UTMI PLL Lock Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "MCKRDY,Master Clock Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LOCKA,PLLA Lock Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "MOSCXTS,8 to 24 MHz Crystal Oscillator Status Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 18. "CFDEV,Clock Failure Detector Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 17. "MOSCRCS,12 MHz RC Oscillator Status Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MOSCSELS,Main Oscillator Clock Source Selection Status Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 10. "PCKRDY2,Programmable Clock Ready 2 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PCKRDY1,Programmable Clock Ready 1 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "PCKRDY0,Programmable Clock Ready 0 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "LOCKU,UTMI PLL Lock Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 3. "MCKRDY,Master Clock Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "LOCKA,PLLA Lock Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "MOSCXTS,8 to 24 MHz Crystal Oscillator Status Interrupt Disable" "0,1"
|
|
rgroup.long 0x68++0x7
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 24. "GCKRDY,Generic Clock Status" "0,1"
|
|
bitfld.long 0x0 22. "APLLCKRDY,Audio PLL Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "FOS,Clock Failure Detector Fault Output Status" "0,1"
|
|
bitfld.long 0x0 19. "CFDS,Clock Failure Detector Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CFDEV,Clock Failure Detector Event" "0,1"
|
|
bitfld.long 0x0 17. "MOSCRCS,12 MHz RC Oscillator Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MOSCSELS,Main Oscillator Selection Status" "0,1"
|
|
bitfld.long 0x0 10. "PCKRDY2,Programmable Clock Ready Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PCKRDY1,Programmable Clock Ready Status" "0,1"
|
|
bitfld.long 0x0 8. "PCKRDY0,Programmable Clock Ready Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "OSCSELS,Slow Clock Oscillator Selection" "0,1"
|
|
bitfld.long 0x0 6. "LOCKU,UPLL Clock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MCKRDY,Master Clock Status" "0,1"
|
|
bitfld.long 0x0 1. "LOCKA,PLLA Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MOSCXTS,8 to 24 MHz Crystal Oscillator Status" "0,1"
|
|
line.long 0x4 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x4 18. "CFDEV,Clock Failure Detector Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 17. "MOSCRCS,12 MHz RC Oscillator Status Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MOSCSELS,Main Oscillator Clock Source Selection Status Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 10. "PCKRDY2,Programmable Clock Ready 2 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PCKRDY1,Programmable Clock Ready 1 Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 8. "PCKRDY0,Programmable Clock Ready 0 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MCKRDY,Master Clock Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 1. "LOCKA,PLLA Lock Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "MOSCXTS,8 to 24 MHz Crystal Oscillator Status Interrupt Mask" "0,1"
|
|
group.long 0x70++0x7
|
|
line.long 0x0 "FSMR,Fast Startup Mode Register"
|
|
bitfld.long 0x0 25. "ACC_CE,Fast Startup from Analog Comparator Controller Comparison Enable" "0,1"
|
|
bitfld.long 0x0 24. "RXLP_MCE,Fast Startup from Backup UART Receive Match Condition Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "LPM,Low-power Mode" "0,1"
|
|
bitfld.long 0x0 19. "SDMMC_CD,Fast Startup from SDMMC Card Detect Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "USBAL,Fast Startup from USB Resume Enable" "0,1"
|
|
bitfld.long 0x0 17. "RTCAL,Fast Startup from RTC Alarm Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "FSTT10,Fast Start-up from GMAC Wake-up On LAN Enable" "0,1"
|
|
bitfld.long 0x0 9. "FSTT9,Fast Startup from PIOBU0-7 Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "FSTT8,Fast Startup from PIOBU0-7 Input Enable" "0,1"
|
|
bitfld.long 0x0 7. "FSTT7,Fast Startup from PIOBU0-7 Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FSTT6,Fast Startup from PIOBU0-7 Input Enable" "0,1"
|
|
bitfld.long 0x0 5. "FSTT5,Fast Startup from PIOBU0-7 Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "FSTT4,Fast Startup from PIOBU0-7 Input Enable" "0,1"
|
|
bitfld.long 0x0 3. "FSTT3,Fast Startup from PIOBU0-7 Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "FSTT2,Fast Startup from PIOBU0-7 Input Enable" "0,1"
|
|
bitfld.long 0x0 1. "FSTT1,Fast Startup from Security Module Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "FSTT0,Fast Startup from WKUP Pin Enable" "0,1"
|
|
line.long 0x4 "FSPR,Fast Startup Polarity Register"
|
|
bitfld.long 0x4 10. "FSTP10,GMAC Wake-up On LAN Polarity for Fast Start-up" "0,1"
|
|
bitfld.long 0x4 9. "FSTP9,PIOBU0-7 Pin Polarity for Fast Startup" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FSTP8,PIOBU0-7 Pin Polarity for Fast Startup" "0,1"
|
|
bitfld.long 0x4 7. "FSTP7,PIOBU0-7 Pin Polarity for Fast Startup" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FSTP6,PIOBU0-7 Pin Polarity for Fast Startup" "0,1"
|
|
bitfld.long 0x4 5. "FSTP5,PIOBU0-7 Pin Polarity for Fast Startup" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "FSTP4,PIOBU0-7 Pin Polarity for Fast Startup" "0,1"
|
|
bitfld.long 0x4 3. "FSTP3,PIOBU0-7 Pin Polarity for Fast Startup" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "FSTP2,PIOBU0-7 Pin Polarity for Fast Startup" "0,1"
|
|
bitfld.long 0x4 1. "FSTP1,Security Module Polarity for Fast Startup" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "FSTP0,WKUP Pin Polarity for Fast Startup" "0,1"
|
|
wgroup.long 0x78++0x3
|
|
line.long 0x0 "FOCR,Fault Output Clear Register"
|
|
bitfld.long 0x0 0. "FOCLR,Fault Output Clear" "0,1"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "PLLICPR,PLL Charge Pump Current Register"
|
|
bitfld.long 0x0 24.--25. "IVCO_PLLU,Voltage Control Output Current PLL UTMI" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "ICP_PLLU,Charge Pump Current PLL UTMI" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "ICP_PLLA,Charge Pump Current" "0,1,2,3"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write ProtectIon Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x100++0x7
|
|
line.long 0x0 "PCER1,Peripheral Clock Enable Register 1"
|
|
bitfld.long 0x0 31. "PID63,Peripheral Clock 63 Enable" "0,1"
|
|
bitfld.long 0x0 30. "PID62,Peripheral Clock 62 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "PID61,Peripheral Clock 61 Enable" "0,1"
|
|
bitfld.long 0x0 28. "PID60,Peripheral Clock 60 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "PID59,Peripheral Clock 59 Enable" "0,1"
|
|
bitfld.long 0x0 26. "PID58,Peripheral Clock 58 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "PID57,Peripheral Clock 57 Enable" "0,1"
|
|
bitfld.long 0x0 24. "PID56,Peripheral Clock 56 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "PID55,Peripheral Clock 55 Enable" "0,1"
|
|
bitfld.long 0x0 22. "PID54,Peripheral Clock 54 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "PID53,Peripheral Clock 53 Enable" "0,1"
|
|
bitfld.long 0x0 20. "PID52,Peripheral Clock 52 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PID51,Peripheral Clock 51 Enable" "0,1"
|
|
bitfld.long 0x0 18. "PID50,Peripheral Clock 50 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PID49,Peripheral Clock 49 Enable" "0,1"
|
|
bitfld.long 0x0 16. "PID48,Peripheral Clock 48 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "PID47,Peripheral Clock 47 Enable" "0,1"
|
|
bitfld.long 0x0 14. "PID46,Peripheral Clock 46 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PID45,Peripheral Clock 45 Enable" "0,1"
|
|
bitfld.long 0x0 12. "PID44,Peripheral Clock 44 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PID43,Peripheral Clock 43 Enable" "0,1"
|
|
bitfld.long 0x0 10. "PID42,Peripheral Clock 42 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PID41,Peripheral Clock 41 Enable" "0,1"
|
|
bitfld.long 0x0 8. "PID40,Peripheral Clock 40 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PID39,Peripheral Clock 39 Enable" "0,1"
|
|
bitfld.long 0x0 6. "PID38,Peripheral Clock 38 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PID37,Peripheral Clock 37 Enable" "0,1"
|
|
bitfld.long 0x0 4. "PID36,Peripheral Clock 36 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "PID35,Peripheral Clock 35 Enable" "0,1"
|
|
bitfld.long 0x0 2. "PID34,Peripheral Clock 34 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PID33,Peripheral Clock 33 Enable" "0,1"
|
|
bitfld.long 0x0 0. "PID32,Peripheral Clock 32 Enable" "0,1"
|
|
line.long 0x4 "PCDR1,Peripheral Clock Disable Register 1"
|
|
bitfld.long 0x4 31. "PID63,Peripheral Clock 63 Disable" "0,1"
|
|
bitfld.long 0x4 30. "PID62,Peripheral Clock 62 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "PID61,Peripheral Clock 61 Disable" "0,1"
|
|
bitfld.long 0x4 28. "PID60,Peripheral Clock 60 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "PID59,Peripheral Clock 59 Disable" "0,1"
|
|
bitfld.long 0x4 26. "PID58,Peripheral Clock 58 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "PID57,Peripheral Clock 57 Disable" "0,1"
|
|
bitfld.long 0x4 24. "PID56,Peripheral Clock 56 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "PID55,Peripheral Clock 55 Disable" "0,1"
|
|
bitfld.long 0x4 22. "PID54,Peripheral Clock 54 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "PID53,Peripheral Clock 53 Disable" "0,1"
|
|
bitfld.long 0x4 20. "PID52,Peripheral Clock 52 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PID51,Peripheral Clock 51 Disable" "0,1"
|
|
bitfld.long 0x4 18. "PID50,Peripheral Clock 50 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PID49,Peripheral Clock 49 Disable" "0,1"
|
|
bitfld.long 0x4 16. "PID48,Peripheral Clock 48 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "PID47,Peripheral Clock 47 Disable" "0,1"
|
|
bitfld.long 0x4 14. "PID46,Peripheral Clock 46 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "PID45,Peripheral Clock 45 Disable" "0,1"
|
|
bitfld.long 0x4 12. "PID44,Peripheral Clock 44 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "PID43,Peripheral Clock 43 Disable" "0,1"
|
|
bitfld.long 0x4 10. "PID42,Peripheral Clock 42 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PID41,Peripheral Clock 41 Disable" "0,1"
|
|
bitfld.long 0x4 8. "PID40,Peripheral Clock 40 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PID39,Peripheral Clock 39 Disable" "0,1"
|
|
bitfld.long 0x4 6. "PID38,Peripheral Clock 38 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PID37,Peripheral Clock 37 Disable" "0,1"
|
|
bitfld.long 0x4 4. "PID36,Peripheral Clock 36 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PID35,Peripheral Clock 35 Disable" "0,1"
|
|
bitfld.long 0x4 2. "PID34,Peripheral Clock 34 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "PID33,Peripheral Clock 33 Disable" "0,1"
|
|
bitfld.long 0x4 0. "PID32,Peripheral Clock 32 Disable" "0,1"
|
|
rgroup.long 0x108++0x3
|
|
line.long 0x0 "PCSR1,Peripheral Clock Status Register 1"
|
|
bitfld.long 0x0 31. "PID63,Peripheral Clock 63 Status" "0,1"
|
|
bitfld.long 0x0 30. "PID62,Peripheral Clock 62 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "PID61,Peripheral Clock 61 Status" "0,1"
|
|
bitfld.long 0x0 28. "PID60,Peripheral Clock 60 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "PID59,Peripheral Clock 59 Status" "0,1"
|
|
bitfld.long 0x0 26. "PID58,Peripheral Clock 58 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "PID57,Peripheral Clock 57 Status" "0,1"
|
|
bitfld.long 0x0 24. "PID56,Peripheral Clock 56 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "PID55,Peripheral Clock 55 Status" "0,1"
|
|
bitfld.long 0x0 22. "PID54,Peripheral Clock 54 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "PID53,Peripheral Clock 53 Status" "0,1"
|
|
bitfld.long 0x0 20. "PID52,Peripheral Clock 52 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PID51,Peripheral Clock 51 Status" "0,1"
|
|
bitfld.long 0x0 18. "PID50,Peripheral Clock 50 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PID49,Peripheral Clock 49 Status" "0,1"
|
|
bitfld.long 0x0 16. "PID48,Peripheral Clock 48 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "PID47,Peripheral Clock 47 Status" "0,1"
|
|
bitfld.long 0x0 14. "PID46,Peripheral Clock 46 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PID45,Peripheral Clock 45 Status" "0,1"
|
|
bitfld.long 0x0 12. "PID44,Peripheral Clock 44 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PID43,Peripheral Clock 43 Status" "0,1"
|
|
bitfld.long 0x0 10. "PID42,Peripheral Clock 42 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PID41,Peripheral Clock 41 Status" "0,1"
|
|
bitfld.long 0x0 8. "PID40,Peripheral Clock 40 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PID39,Peripheral Clock 39 Status" "0,1"
|
|
bitfld.long 0x0 6. "PID38,Peripheral Clock 38 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PID37,Peripheral Clock 37 Status" "0,1"
|
|
bitfld.long 0x0 4. "PID36,Peripheral Clock 36 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "PID35,Peripheral Clock 35 Status" "0,1"
|
|
bitfld.long 0x0 2. "PID34,Peripheral Clock 34 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PID33,Peripheral Clock 33 Status" "0,1"
|
|
bitfld.long 0x0 0. "PID32,Peripheral Clock 32 Status" "0,1"
|
|
group.long 0x10C++0x7
|
|
line.long 0x0 "PCR,Peripheral Control Register"
|
|
bitfld.long 0x0 29. "GCKEN,Generic Clock Enable" "0,1"
|
|
bitfld.long 0x0 28. "EN,Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--27. 1. "GCKDIV,Generic Clock Division Ratio"
|
|
bitfld.long 0x0 12. "CMD,Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "GCKCSS,Generic Clock Source Selection" "0: Slow clock is selected,1: Main clock is selected,2: PLLACK is selected,3: UPLL Clock is selected,4: Master Clock is selected,5: Audio PLL clock is selected,?,?"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PID,Peripheral ID"
|
|
line.long 0x4 "OCR,Oscillator Calibration Register"
|
|
bitfld.long 0x4 7. "SEL,Selection of RC Oscillator Calibration Bits" "0,1"
|
|
hexmask.long.byte 0x4 0.--6. 1. "CAL,12 MHz RC Oscillator Calibration Bits"
|
|
wgroup.long 0x114++0x7
|
|
line.long 0x0 "SLPWK_ER0,SleepWalking Enable Register 0"
|
|
bitfld.long 0x0 30. "PID30,Peripheral 30 SleepWalking Enable" "0,1"
|
|
bitfld.long 0x0 29. "PID29,Peripheral 29 SleepWalking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "PID28,Peripheral 28 SleepWalking Enable" "0,1"
|
|
bitfld.long 0x0 27. "PID27,Peripheral 27 SleepWalking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "PID26,Peripheral 26 SleepWalking Enable" "0,1"
|
|
bitfld.long 0x0 25. "PID25,Peripheral 25 SleepWalking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "PID24,Peripheral 24 SleepWalking Enable" "0,1"
|
|
bitfld.long 0x0 23. "PID23,Peripheral 23 SleepWalking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "PID22,Peripheral 22 SleepWalking Enable" "0,1"
|
|
bitfld.long 0x0 21. "PID21,Peripheral 21 SleepWalking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PID20,Peripheral 20 SleepWalking Enable" "0,1"
|
|
bitfld.long 0x0 19. "PID19,Peripheral 19 SleepWalking Enable" "0,1"
|
|
line.long 0x4 "SLPWK_DR0,SleepWalking Disable Register 0"
|
|
bitfld.long 0x4 30. "PID30,Peripheral 30 SleepWalking Disable" "0,1"
|
|
bitfld.long 0x4 29. "PID29,Peripheral 29 SleepWalking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "PID28,Peripheral 28 SleepWalking Disable" "0,1"
|
|
bitfld.long 0x4 27. "PID27,Peripheral 27 SleepWalking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "PID26,Peripheral 26 SleepWalking Disable" "0,1"
|
|
bitfld.long 0x4 25. "PID25,Peripheral 25 SleepWalking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "PID24,Peripheral 24 SleepWalking Disable" "0,1"
|
|
bitfld.long 0x4 23. "PID23,Peripheral 23 SleepWalking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "PID22,Peripheral 22 SleepWalking Disable" "0,1"
|
|
bitfld.long 0x4 21. "PID21,Peripheral 21 SleepWalking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PID20,Peripheral 20 SleepWalking Disable" "0,1"
|
|
bitfld.long 0x4 19. "PID19,Peripheral 19 SleepWalking Disable" "0,1"
|
|
rgroup.long 0x11C++0x7
|
|
line.long 0x0 "SLPWK_SR0,SleepWalking Status Register 0"
|
|
bitfld.long 0x0 30. "PID30,Peripheral 30 SleepWalking Status" "0,1"
|
|
bitfld.long 0x0 29. "PID29,Peripheral 29 SleepWalking Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "PID28,Peripheral 28 SleepWalking Status" "0,1"
|
|
bitfld.long 0x0 27. "PID27,Peripheral 27 SleepWalking Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "PID26,Peripheral 26 SleepWalking Status" "0,1"
|
|
bitfld.long 0x0 25. "PID25,Peripheral 25 SleepWalking Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "PID24,Peripheral 24 SleepWalking Status" "0,1"
|
|
bitfld.long 0x0 23. "PID23,Peripheral 23 SleepWalking Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "PID22,Peripheral 22 SleepWalking Status" "0,1"
|
|
bitfld.long 0x0 21. "PID21,Peripheral 21 SleepWalking Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PID20,Peripheral 20 SleepWalking Status" "0,1"
|
|
bitfld.long 0x0 19. "PID19,Peripheral 19 SleepWalking Status" "0,1"
|
|
line.long 0x4 "SLPWK_ASR0,SleepWalking Activity Status Register 0"
|
|
bitfld.long 0x4 30. "PID30,Peripheral 30 Activity Status" "0,1"
|
|
bitfld.long 0x4 29. "PID29,Peripheral 29 Activity Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "PID28,Peripheral 28 Activity Status" "0,1"
|
|
bitfld.long 0x4 27. "PID27,Peripheral 27 Activity Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "PID26,Peripheral 26 Activity Status" "0,1"
|
|
bitfld.long 0x4 25. "PID25,Peripheral 25 Activity Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "PID24,Peripheral 24 Activity Status" "0,1"
|
|
bitfld.long 0x4 23. "PID23,Peripheral 23 Activity Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "PID22,Peripheral 22 Activity Status" "0,1"
|
|
bitfld.long 0x4 21. "PID21,Peripheral 21 Activity Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "PID20,Peripheral 20 Activity Status" "0,1"
|
|
bitfld.long 0x4 19. "PID19,Peripheral 19 Activity Status" "0,1"
|
|
wgroup.long 0x134++0x7
|
|
line.long 0x0 "SLPWK_ER1,SleepWalking Enable Register 1"
|
|
bitfld.long 0x0 8. "PID40,Peripheral 40 SleepWalking Enable" "0,1"
|
|
bitfld.long 0x0 2. "PID34,Peripheral 34 SleepWalking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PID33,Peripheral 33 SleepWalking Enable" "0,1"
|
|
line.long 0x4 "SLPWK_DR1,SleepWalking Disable Register 1"
|
|
bitfld.long 0x4 8. "PID40,Peripheral 40 SleepWalking Disable" "0,1"
|
|
bitfld.long 0x4 2. "PID34,Peripheral 34 SleepWalking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "PID33,Peripheral 33 SleepWalking Disable" "0,1"
|
|
rgroup.long 0x13C++0xB
|
|
line.long 0x0 "SLPWK_SR1,SleepWalking Status Register 1"
|
|
bitfld.long 0x0 8. "PID40,Peripheral 40 SleepWalking Status" "0,1"
|
|
bitfld.long 0x0 2. "PID34,Peripheral 34 SleepWalking Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PID33,Peripheral 33 SleepWalking Status" "0,1"
|
|
line.long 0x4 "SLPWK_ASR1,SleepWalking Activity Status Register 1"
|
|
bitfld.long 0x4 8. "PID40,Peripheral 40 Activity Status" "0,1"
|
|
bitfld.long 0x4 2. "PID34,Peripheral 34 Activity Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "PID33,Peripheral 33 Activity Status" "0,1"
|
|
line.long 0x8 "SLPWK_AIPR,SleepWalking Activity In Progress Register"
|
|
bitfld.long 0x8 0. "AIP,Activity In Progress" "0,1"
|
|
group.long 0x148++0xB
|
|
line.long 0x0 "SLPWKCR,SleepWalking Control Register"
|
|
bitfld.long 0x0 28. "SLPWKSR,SleepWalking Status Register" "0,1"
|
|
bitfld.long 0x0 16. "ASR,Activity Status Register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD,Command" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PID,Peripheral ID"
|
|
line.long 0x4 "AUDIO_PLL0,Audio PLL Register 0"
|
|
bitfld.long 0x4 28.--29. "DCO_GAIN,Digitally Controlled Oscillator Gain Selection" "0,1,2,3"
|
|
hexmask.long.byte 0x4 24.--27. 1. "DCO_FILTER,Digitally Controlled Oscillator Filter Selection"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--22. 1. "QDPMC,Output Divider Ratio for PMC Clock"
|
|
hexmask.long.byte 0x4 8.--14. 1. "ND,Loop Divider Ratio"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "PLLFLT,PLL Loop Filter Selection"
|
|
bitfld.long 0x4 3. "RESETN,Audio PLL Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "PMCEN,PMC Clock Enable" "0,1"
|
|
bitfld.long 0x4 1. "PADEN,Pad Clock Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "PLLEN,PLL Enable" "0,1"
|
|
line.long 0x8 "AUDIO_PLL1,Audio PLL Register 1"
|
|
hexmask.long.byte 0x8 26.--30. 1. "QDAUDIO,Output Divider Ratio for Pad Clock"
|
|
bitfld.long 0x8 24.--25. "DIV,Divider Value" "?,?,2: Divide by 2,3: Divide by 3"
|
|
newline
|
|
hexmask.long.tbyte 0x8 0.--21. 1. "FRACR,Fractional Loop Divider Setting"
|
|
tree.end
|
|
tree "PTC (Peripheral Touch Controller)"
|
|
base ad:0xFC060000
|
|
wgroup.byte 0x28++0x0
|
|
line.byte 0x0 "CMD,PTC Command Register"
|
|
hexmask.byte 0x0 0.--3. 1. "CMD,Host Command"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "ISR,PTC Interrupt Status Register"
|
|
bitfld.byte 0x0 7. "IRQ3,IRQ3" "0,1"
|
|
bitfld.byte 0x0 6. "IRQ2,IRQ2" "0,1"
|
|
bitfld.byte 0x0 5. "IRQ1,IRQ1" "0,1"
|
|
bitfld.byte 0x0 4. "IRQ0,IRQ0" "0,1"
|
|
bitfld.byte 0x0 0. "NOTIFY0,Notification to the Firmware" "0,1"
|
|
wgroup.byte 0x35++0x0
|
|
line.byte 0x0 "IED,PTC Enable Register"
|
|
bitfld.byte 0x0 7. "IER3,IER3" "0,1"
|
|
bitfld.byte 0x0 6. "IER2,IER2" "0,1"
|
|
bitfld.byte 0x0 5. "IER1,IER1" "0,1"
|
|
bitfld.byte 0x0 4. "IER0,IER0" "0,1"
|
|
tree.end
|
|
tree "PWM (Pulse Width Modulator)"
|
|
base ad:0xF802C000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CLK,PWM Clock Register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "PREB,CLKB Source Clock Selection"
|
|
hexmask.long.byte 0x0 16.--23. 1. "DIVB,CLKB Divide Factor"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "PREA,CLKA Source Clock Selection"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DIVA,CLKA Divide Factor"
|
|
wgroup.long 0x4++0x7
|
|
line.long 0x0 "ENA,PWM Enable Register"
|
|
bitfld.long 0x0 3. "CHID3,Channel ID" "0,1"
|
|
bitfld.long 0x0 2. "CHID2,Channel ID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CHID1,Channel ID" "0,1"
|
|
bitfld.long 0x0 0. "CHID0,Channel ID" "0,1"
|
|
line.long 0x4 "DIS,PWM Disable Register"
|
|
bitfld.long 0x4 3. "CHID3,Channel ID" "0,1"
|
|
bitfld.long 0x4 2. "CHID2,Channel ID" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CHID1,Channel ID" "0,1"
|
|
bitfld.long 0x4 0. "CHID0,Channel ID" "0,1"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "SR,PWM Status Register"
|
|
bitfld.long 0x0 3. "CHID3,Channel ID" "0,1"
|
|
bitfld.long 0x0 2. "CHID2,Channel ID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CHID1,Channel ID" "0,1"
|
|
bitfld.long 0x0 0. "CHID0,Channel ID" "0,1"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER1,PWM Interrupt Enable Register 1"
|
|
bitfld.long 0x0 19. "FCHID3,Fault Protection Trigger on Channel 3 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 18. "FCHID2,Fault Protection Trigger on Channel 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "FCHID1,Fault Protection Trigger on Channel 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "FCHID0,Fault Protection Trigger on Channel 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CHID3,Counter Event on Channel 3 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "CHID2,Counter Event on Channel 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CHID1,Counter Event on Channel 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "CHID0,Counter Event on Channel 0 Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR1,PWM Interrupt Disable Register 1"
|
|
bitfld.long 0x4 19. "FCHID3,Fault Protection Trigger on Channel 3 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 18. "FCHID2,Fault Protection Trigger on Channel 2 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "FCHID1,Fault Protection Trigger on Channel 1 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "FCHID0,Fault Protection Trigger on Channel 0 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CHID3,Counter Event on Channel 3 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "CHID2,Counter Event on Channel 2 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CHID1,Counter Event on Channel 1 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "CHID0,Counter Event on Channel 0 Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "IMR1,PWM Interrupt Mask Register 1"
|
|
bitfld.long 0x0 19. "FCHID3,Fault Protection Trigger on Channel 3 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 18. "FCHID2,Fault Protection Trigger on Channel 2 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "FCHID1,Fault Protection Trigger on Channel 1 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "FCHID0,Fault Protection Trigger on Channel 0 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CHID3,Counter Event on Channel 3 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "CHID2,Counter Event on Channel 2 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CHID1,Counter Event on Channel 1 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "CHID0,Counter Event on Channel 0 Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR1,PWM Interrupt Status Register 1"
|
|
bitfld.long 0x4 19. "FCHID3,Fault Protection Trigger on Channel 3" "0,1"
|
|
bitfld.long 0x4 18. "FCHID2,Fault Protection Trigger on Channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "FCHID1,Fault Protection Trigger on Channel 1" "0,1"
|
|
bitfld.long 0x4 16. "FCHID0,Fault Protection Trigger on Channel 0" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CHID3,Counter Event on Channel 3" "0,1"
|
|
bitfld.long 0x4 2. "CHID2,Counter Event on Channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CHID1,Counter Event on Channel 1" "0,1"
|
|
bitfld.long 0x4 0. "CHID0,Counter Event on Channel 0" "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SCM,PWM Sync Channels Mode Register"
|
|
bitfld.long 0x0 21.--23. "PTRCS,DMA Controller Transfer Request Comparison Selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 20. "PTRM,DMA Controller Transfer Request Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "UPDM,Synchronous Channels Update Mode" "0: Manual write of double buffer registers and..,1: Manual write of double buffer registers and..,2: Automatic write of duty-cycle update registers..,?"
|
|
bitfld.long 0x0 3. "SYNC3,Synchronous Channel 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "SYNC2,Synchronous Channel 2" "0,1"
|
|
bitfld.long 0x0 1. "SYNC1,Synchronous Channel 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SYNC0,Synchronous Channel 0" "0,1"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "DMAR,PWM DMA Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "DMADUTY,Duty-Cycle Holding Register for DMA Access"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "SCUC,PWM Sync Channels Update Control Register"
|
|
bitfld.long 0x0 0. "UPDULOCK,Synchronous Channels Update Unlock" "0,1"
|
|
line.long 0x4 "SCUP,PWM Sync Channels Update Period Register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "UPRCNT,Update Period Counter"
|
|
hexmask.long.byte 0x4 0.--3. 1. "UPR,Update Period"
|
|
wgroup.long 0x30++0xB
|
|
line.long 0x0 "SCUPUPD,PWM Sync Channels Update Period Update Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "UPRUPD,Update Period Update"
|
|
line.long 0x4 "IER2,PWM Interrupt Enable Register 2"
|
|
bitfld.long 0x4 23. "CMPU7,Comparison 7 Update Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 22. "CMPU6,Comparison 6 Update Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "CMPU5,Comparison 5 Update Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 20. "CMPU4,Comparison 4 Update Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CMPU3,Comparison 3 Update Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 18. "CMPU2,Comparison 2 Update Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CMPU1,Comparison 1 Update Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 16. "CMPU0,Comparison 0 Update Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CMPM7,Comparison 7 Match Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 14. "CMPM6,Comparison 6 Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CMPM5,Comparison 5 Match Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 12. "CMPM4,Comparison 4 Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMPM3,Comparison 3 Match Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "CMPM2,Comparison 2 Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CMPM1,Comparison 1 Match Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 8. "CMPM0,Comparison 0 Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "UNRE,Synchronous Channels Update Underrun Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "WRDY,Write Ready for Synchronous Channels Update Interrupt Enable" "0,1"
|
|
line.long 0x8 "IDR2,PWM Interrupt Disable Register 2"
|
|
bitfld.long 0x8 23. "CMPU7,Comparison 7 Update Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 22. "CMPU6,Comparison 6 Update Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "CMPU5,Comparison 5 Update Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 20. "CMPU4,Comparison 4 Update Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "CMPU3,Comparison 3 Update Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 18. "CMPU2,Comparison 2 Update Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "CMPU1,Comparison 1 Update Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 16. "CMPU0,Comparison 0 Update Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "CMPM7,Comparison 7 Match Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 14. "CMPM6,Comparison 6 Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "CMPM5,Comparison 5 Match Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 12. "CMPM4,Comparison 4 Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "CMPM3,Comparison 3 Match Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 10. "CMPM2,Comparison 2 Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "CMPM1,Comparison 1 Match Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 8. "CMPM0,Comparison 0 Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "UNRE,Synchronous Channels Update Underrun Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 0. "WRDY,Write Ready for Synchronous Channels Update Interrupt Disable" "0,1"
|
|
rgroup.long 0x3C++0x7
|
|
line.long 0x0 "IMR2,PWM Interrupt Mask Register 2"
|
|
bitfld.long 0x0 23. "CMPU7,Comparison 7 Update Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 22. "CMPU6,Comparison 6 Update Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "CMPU5,Comparison 5 Update Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 20. "CMPU4,Comparison 4 Update Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CMPU3,Comparison 3 Update Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 18. "CMPU2,Comparison 2 Update Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "CMPU1,Comparison 1 Update Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "CMPU0,Comparison 0 Update Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CMPM7,Comparison 7 Match Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 14. "CMPM6,Comparison 6 Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "CMPM5,Comparison 5 Match Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 12. "CMPM4,Comparison 4 Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMPM3,Comparison 3 Match Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "CMPM2,Comparison 2 Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CMPM1,Comparison 1 Match Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "CMPM0,Comparison 0 Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "UNRE,Synchronous Channels Update Underrun Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "WRDY,Write Ready for Synchronous Channels Update Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR2,PWM Interrupt Status Register 2"
|
|
bitfld.long 0x4 23. "CMPU7,Comparison 7 Update" "0,1"
|
|
bitfld.long 0x4 22. "CMPU6,Comparison 6 Update" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "CMPU5,Comparison 5 Update" "0,1"
|
|
bitfld.long 0x4 20. "CMPU4,Comparison 4 Update" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CMPU3,Comparison 3 Update" "0,1"
|
|
bitfld.long 0x4 18. "CMPU2,Comparison 2 Update" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CMPU1,Comparison 1 Update" "0,1"
|
|
bitfld.long 0x4 16. "CMPU0,Comparison 0 Update" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CMPM7,Comparison 7 Match" "0,1"
|
|
bitfld.long 0x4 14. "CMPM6,Comparison 6 Match" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CMPM5,Comparison 5 Match" "0,1"
|
|
bitfld.long 0x4 12. "CMPM4,Comparison 4 Match" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMPM3,Comparison 3 Match" "0,1"
|
|
bitfld.long 0x4 10. "CMPM2,Comparison 2 Match" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CMPM1,Comparison 1 Match" "0,1"
|
|
bitfld.long 0x4 8. "CMPM0,Comparison 0 Match" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "UNRE,Synchronous Channels Update Underrun Error" "0,1"
|
|
bitfld.long 0x4 0. "WRDY,Write Ready for Synchronous Channels Update" "0,1"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "OOV,PWM Output Override Value Register"
|
|
bitfld.long 0x0 19. "OOVL3,Output Override Value for PWML output of the channel 3" "0,1"
|
|
bitfld.long 0x0 18. "OOVL2,Output Override Value for PWML output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "OOVL1,Output Override Value for PWML output of the channel 1" "0,1"
|
|
bitfld.long 0x0 16. "OOVL0,Output Override Value for PWML output of the channel 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OOVH3,Output Override Value for PWMH output of the channel 3" "0,1"
|
|
bitfld.long 0x0 2. "OOVH2,Output Override Value for PWMH output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OOVH1,Output Override Value for PWMH output of the channel 1" "0,1"
|
|
bitfld.long 0x0 0. "OOVH0,Output Override Value for PWMH output of the channel 0" "0,1"
|
|
line.long 0x4 "OS,PWM Output Selection Register"
|
|
bitfld.long 0x4 19. "OSL3,Output Selection for PWML output of the channel 3" "0,1"
|
|
bitfld.long 0x4 18. "OSL2,Output Selection for PWML output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "OSL1,Output Selection for PWML output of the channel 1" "0,1"
|
|
bitfld.long 0x4 16. "OSL0,Output Selection for PWML output of the channel 0" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OSH3,Output Selection for PWMH output of the channel 3" "0,1"
|
|
bitfld.long 0x4 2. "OSH2,Output Selection for PWMH output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "OSH1,Output Selection for PWMH output of the channel 1" "0,1"
|
|
bitfld.long 0x4 0. "OSH0,Output Selection for PWMH output of the channel 0" "0,1"
|
|
wgroup.long 0x4C++0xF
|
|
line.long 0x0 "OSS,PWM Output Selection Set Register"
|
|
bitfld.long 0x0 19. "OSSL3,Output Selection Set for PWML output of the channel 3" "0,1"
|
|
bitfld.long 0x0 18. "OSSL2,Output Selection Set for PWML output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "OSSL1,Output Selection Set for PWML output of the channel 1" "0,1"
|
|
bitfld.long 0x0 16. "OSSL0,Output Selection Set for PWML output of the channel 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OSSH3,Output Selection Set for PWMH output of the channel 3" "0,1"
|
|
bitfld.long 0x0 2. "OSSH2,Output Selection Set for PWMH output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OSSH1,Output Selection Set for PWMH output of the channel 1" "0,1"
|
|
bitfld.long 0x0 0. "OSSH0,Output Selection Set for PWMH output of the channel 0" "0,1"
|
|
line.long 0x4 "OSC,PWM Output Selection Clear Register"
|
|
bitfld.long 0x4 19. "OSCL3,Output Selection Clear for PWML output of the channel 3" "0,1"
|
|
bitfld.long 0x4 18. "OSCL2,Output Selection Clear for PWML output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "OSCL1,Output Selection Clear for PWML output of the channel 1" "0,1"
|
|
bitfld.long 0x4 16. "OSCL0,Output Selection Clear for PWML output of the channel 0" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OSCH3,Output Selection Clear for PWMH output of the channel 3" "0,1"
|
|
bitfld.long 0x4 2. "OSCH2,Output Selection Clear for PWMH output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "OSCH1,Output Selection Clear for PWMH output of the channel 1" "0,1"
|
|
bitfld.long 0x4 0. "OSCH0,Output Selection Clear for PWMH output of the channel 0" "0,1"
|
|
line.long 0x8 "OSSUPD,PWM Output Selection Set Update Register"
|
|
bitfld.long 0x8 19. "OSSUPL3,Output Selection Set for PWML output of the channel 3" "0,1"
|
|
bitfld.long 0x8 18. "OSSUPL2,Output Selection Set for PWML output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "OSSUPL1,Output Selection Set for PWML output of the channel 1" "0,1"
|
|
bitfld.long 0x8 16. "OSSUPL0,Output Selection Set for PWML output of the channel 0" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "OSSUPH3,Output Selection Set for PWMH output of the channel 3" "0,1"
|
|
bitfld.long 0x8 2. "OSSUPH2,Output Selection Set for PWMH output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "OSSUPH1,Output Selection Set for PWMH output of the channel 1" "0,1"
|
|
bitfld.long 0x8 0. "OSSUPH0,Output Selection Set for PWMH output of the channel 0" "0,1"
|
|
line.long 0xC "OSCUPD,PWM Output Selection Clear Update Register"
|
|
bitfld.long 0xC 19. "OSCUPL3,Output Selection Clear for PWML output of the channel 3" "0,1"
|
|
bitfld.long 0xC 18. "OSCUPL2,Output Selection Clear for PWML output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "OSCUPL1,Output Selection Clear for PWML output of the channel 1" "0,1"
|
|
bitfld.long 0xC 16. "OSCUPL0,Output Selection Clear for PWML output of the channel 0" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "OSCUPH3,Output Selection Clear for PWMH output of the channel 3" "0,1"
|
|
bitfld.long 0xC 2. "OSCUPH2,Output Selection Clear for PWMH output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "OSCUPH1,Output Selection Clear for PWMH output of the channel 1" "0,1"
|
|
bitfld.long 0xC 0. "OSCUPH0,Output Selection Clear for PWMH output of the channel 0" "0,1"
|
|
group.long 0x5C++0x3
|
|
line.long 0x0 "FMR,PWM Fault Mode Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "FFIL,Fault Filtering"
|
|
hexmask.long.byte 0x0 8.--15. 1. "FMOD,Fault Activation Mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "FPOL,Fault Polarity"
|
|
rgroup.long 0x60++0x3
|
|
line.long 0x0 "FSR,PWM Fault Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "FS,Fault Status"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FIV,Fault Input Value"
|
|
wgroup.long 0x64++0x3
|
|
line.long 0x0 "FCR,PWM Fault Clear Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FCLR,Fault Clear"
|
|
group.long 0x68++0x7
|
|
line.long 0x0 "FPV1,PWM Fault Protection Value Register 1"
|
|
bitfld.long 0x0 19. "FPVL3,Fault Protection Value for PWML output on channel 3" "0,1"
|
|
bitfld.long 0x0 18. "FPVL2,Fault Protection Value for PWML output on channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "FPVL1,Fault Protection Value for PWML output on channel 1" "0,1"
|
|
bitfld.long 0x0 16. "FPVL0,Fault Protection Value for PWML output on channel 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FPVH3,Fault Protection Value for PWMH output on channel 3" "0,1"
|
|
bitfld.long 0x0 2. "FPVH2,Fault Protection Value for PWMH output on channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "FPVH1,Fault Protection Value for PWMH output on channel 1" "0,1"
|
|
bitfld.long 0x0 0. "FPVH0,Fault Protection Value for PWMH output on channel 0" "0,1"
|
|
line.long 0x4 "FPE,PWM Fault Protection Enable Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. "FPE3,Fault Protection Enable for channel 3"
|
|
hexmask.long.byte 0x4 16.--23. 1. "FPE2,Fault Protection Enable for channel 2"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "FPE1,Fault Protection Enable for channel 1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "FPE0,Fault Protection Enable for channel 0"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x7C)++0x3
|
|
line.long 0x0 "ELMR[$1],PWM Event Line 0 Mode Register"
|
|
bitfld.long 0x0 7. "CSEL7,Comparison 7 Selection" "0,1"
|
|
bitfld.long 0x0 6. "CSEL6,Comparison 6 Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CSEL5,Comparison 5 Selection" "0,1"
|
|
bitfld.long 0x0 4. "CSEL4,Comparison 4 Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CSEL3,Comparison 3 Selection" "0,1"
|
|
bitfld.long 0x0 2. "CSEL2,Comparison 2 Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CSEL1,Comparison 1 Selection" "0,1"
|
|
bitfld.long 0x0 0. "CSEL0,Comparison 0 Selection" "0,1"
|
|
repeat.end
|
|
group.long 0xA0++0x3
|
|
line.long 0x0 "SSPR,PWM Spread Spectrum Register"
|
|
bitfld.long 0x0 24. "SPRDM,Spread Spectrum Counter Mode" "0,1"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "SPRD,Spread Spectrum Limit Value"
|
|
wgroup.long 0xA4++0x3
|
|
line.long 0x0 "SSPUP,PWM Spread Spectrum Update Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "SPRDUP,Spread Spectrum Limit Value Update"
|
|
group.long 0xB0++0x3
|
|
line.long 0x0 "SMMR,PWM Stepper Motor Mode Register"
|
|
bitfld.long 0x0 17. "DOWN1,Down Count" "0,1"
|
|
bitfld.long 0x0 16. "DOWN0,Down Count" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "GCEN1,Gray Count Enable" "0,1"
|
|
bitfld.long 0x0 0. "GCEN0,Gray Count Enable" "0,1"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "FPV2,PWM Fault Protection Value 2 Register"
|
|
bitfld.long 0x0 19. "FPZL3,Fault Protection to Hi-Z for PWML output on channel 3" "0,1"
|
|
bitfld.long 0x0 18. "FPZL2,Fault Protection to Hi-Z for PWML output on channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "FPZL1,Fault Protection to Hi-Z for PWML output on channel 1" "0,1"
|
|
bitfld.long 0x0 16. "FPZL0,Fault Protection to Hi-Z for PWML output on channel 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FPZH3,Fault Protection to Hi-Z for PWMH output on channel 3" "0,1"
|
|
bitfld.long 0x0 2. "FPZH2,Fault Protection to Hi-Z for PWMH output on channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "FPZH1,Fault Protection to Hi-Z for PWMH output on channel 1" "0,1"
|
|
bitfld.long 0x0 0. "FPZH0,Fault Protection to Hi-Z for PWMH output on channel 0" "0,1"
|
|
wgroup.long 0xE4++0x3
|
|
line.long 0x0 "WPCR,PWM Write Protection Control Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 7. "WPRG5,Write Protection Register Group 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "WPRG4,Write Protection Register Group 4" "0,1"
|
|
bitfld.long 0x0 5. "WPRG3,Write Protection Register Group 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "WPRG2,Write Protection Register Group 2" "0,1"
|
|
bitfld.long 0x0 3. "WPRG1,Write Protection Register Group 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "WPRG0,Write Protection Register Group 0" "0,1"
|
|
bitfld.long 0x0 0.--1. "WPCMD,Write Protection Command" "0: Disables the software write protection of the..,1: Enables the software write protection of the..,2: Enables the hardware write protection of the..,?"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,PWM Write Protection Status Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "WPVSRC,Write Protect Violation Source"
|
|
bitfld.long 0x0 13. "WPHWS5,Write Protect HW Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "WPHWS4,Write Protect HW Status" "0,1"
|
|
bitfld.long 0x0 11. "WPHWS3,Write Protect HW Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "WPHWS2,Write Protect HW Status" "0,1"
|
|
bitfld.long 0x0 9. "WPHWS1,Write Protect HW Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "WPHWS0,Write Protect HW Status" "0,1"
|
|
bitfld.long 0x0 7. "WPVS,Write Protect Violation Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "WPSWS5,Write Protect SW Status" "0,1"
|
|
bitfld.long 0x0 4. "WPSWS4,Write Protect SW Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "WPSWS3,Write Protect SW Status" "0,1"
|
|
bitfld.long 0x0 2. "WPSWS2,Write Protect SW Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPSWS1,Write Protect SW Status" "0,1"
|
|
bitfld.long 0x0 0. "WPSWS0,Write Protect SW Status" "0,1"
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0xF802C130 ad:0xF802C140 ad:0xF802C150 ad:0xF802C160 ad:0xF802C170 ad:0xF802C180 ad:0xF802C190 ad:0xF802C1A0)
|
|
tree "PWM_CMP[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CMPV,PWM Comparison 0 Value Register"
|
|
bitfld.long 0x0 24. "CVM,Comparison x Value Mode" "0: Compare when counter is incrementing,1: Compare when counter is decrementing"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CV,Comparison x Value"
|
|
wgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CMPVUPD,PWM Comparison 0 Value Update Register"
|
|
bitfld.long 0x0 24. "CVMUPD,Comparison x Value Mode Update" "0,1"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CVUPD,Comparison x Value Update"
|
|
group.long ($2+0x8)++0x3
|
|
line.long 0x0 "CMPM,PWM Comparison 0 Mode Register"
|
|
hexmask.long.byte 0x0 20.--23. 1. "CUPRCNT,Comparison x Update Period Counter"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CUPR,Comparison x Update Period"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CPRCNT,Comparison x Period Counter"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CPR,Comparison x Period"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CTR,Comparison x Trigger"
|
|
bitfld.long 0x0 0. "CEN,Comparison x Enable" "0,1"
|
|
wgroup.long ($2+0xC)++0x3
|
|
line.long 0x0 "CMPMUPD,PWM Comparison 0 Mode Update Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CUPRUPD,Comparison x Update Period Update"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CPRUPD,Comparison x Period Update"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CTRUPD,Comparison x Trigger Update"
|
|
bitfld.long 0x0 0. "CENUPD,Comparison x Enable Update" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0xF802C200 ad:0xF802C220 ad:0xF802C240 ad:0xF802C260)
|
|
tree "PWM_CH_NUM[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "CMR,PWM Channel Mode Register"
|
|
bitfld.long 0x0 19. "PPM,Push-Pull Mode" "0,1"
|
|
bitfld.long 0x0 18. "DTLI,Dead-Time PWMLx Output Inverted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "DTHI,Dead-Time PWMHx Output Inverted" "0,1"
|
|
bitfld.long 0x0 16. "DTE,Dead-Time Generator Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TCTS,Timer Counter Trigger Selection" "0,1"
|
|
bitfld.long 0x0 12. "DPOLI,Disabled Polarity Inverted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "UPDS,Update Selection" "0: At the next end of PWM period,1: At the next end of Half PWM period"
|
|
bitfld.long 0x0 10. "CES,Counter Event Selection" "0: At the end of PWM period,1: At half of PWM period AND at the end of PWM period"
|
|
newline
|
|
bitfld.long 0x0 9. "CPOL,Channel Polarity" "0: Waveform starts at low level,1: Waveform starts at high level"
|
|
bitfld.long 0x0 8. "CALG,Channel Alignment" "0: Left aligned,1: Center aligned"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "CPRE,Channel Prescaler"
|
|
line.long 0x4 "CDTY,PWM Channel Duty Cycle Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "CDTY,Channel Duty-Cycle"
|
|
wgroup.long ($2+0x8)++0x3
|
|
line.long 0x0 "CDTYUPD,PWM Channel Duty Cycle Update Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CDTYUPD,Channel Duty-Cycle Update"
|
|
group.long ($2+0xC)++0x3
|
|
line.long 0x0 "CPRD,PWM Channel Period Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CPRD,Channel Period"
|
|
wgroup.long ($2+0x10)++0x3
|
|
line.long 0x0 "CPRDUPD,PWM Channel Period Update Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CPRDUPD,Channel Period Update"
|
|
rgroup.long ($2+0x14)++0x3
|
|
line.long 0x0 "CCNT,PWM Channel Counter Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CNT,Channel Counter Register"
|
|
group.long ($2+0x18)++0x3
|
|
line.long 0x0 "DT,PWM Channel Dead Time Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "DTL,Dead-Time Value for PWMLx Output"
|
|
hexmask.long.word 0x0 0.--15. 1. "DTH,Dead-Time Value for PWMHx Output"
|
|
wgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "DTUPD,PWM Channel Dead Time Update Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "DTLUPD,Dead-Time Value Update for PWMLx Output"
|
|
hexmask.long.word 0x0 0.--15. 1. "DTHUPD,Dead-Time Value Update for PWMHx Output"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0xF802C000
|
|
wgroup.long 0x400++0x3
|
|
line.long 0x0 "CMUPD0,PWM Channel Mode Update Register (ch_num = 0)"
|
|
bitfld.long 0x0 13. "CPOLINVUP,Channel Polarity Inversion Update" "0,1"
|
|
bitfld.long 0x0 9. "CPOLUP,Channel Polarity Update" "0,1"
|
|
wgroup.long 0x420++0x3
|
|
line.long 0x0 "CMUPD1,PWM Channel Mode Update Register (ch_num = 1)"
|
|
bitfld.long 0x0 13. "CPOLINVUP,Channel Polarity Inversion Update" "0,1"
|
|
bitfld.long 0x0 9. "CPOLUP,Channel Polarity Update" "0,1"
|
|
group.long 0x42C++0xF
|
|
line.long 0x0 "ETRG1,PWM External Trigger Register 1"
|
|
bitfld.long 0x0 31. "RFEN,Recoverable Fault Enable" "0,1"
|
|
bitfld.long 0x0 30. "TRGSRC,Trigger Source" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TRGFILT,Filtered input" "0,1"
|
|
bitfld.long 0x0 28. "TRGEDGE,Edge Selection" "0: TRGMODE = 1: TRGINx event detection on falling..,1: TRGMODE = 1: TRGINx event detection on rising.."
|
|
newline
|
|
bitfld.long 0x0 24.--25. "TRGMODE,External Trigger Mode" "0: External trigger is not enabled.,1: External PWM Reset Mode,2: External PWM Start Mode,3: Cycle-by-cycle Duty Mode"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "MAXCNT,Maximum Counter value"
|
|
line.long 0x4 "LEBR1,PWM Leading-Edge Blanking Register 1"
|
|
bitfld.long 0x4 19. "PWMHREN,PWMH Rising Edge Enable" "0,1"
|
|
bitfld.long 0x4 18. "PWMHFEN,PWMH Falling Edge Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PWMLREN,PWML Rising Edge Enable" "0,1"
|
|
bitfld.long 0x4 16. "PWMLFEN,PWML Falling Edge Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "LEBDELAY,Leading-Edge Blanking Delay for TRGINx"
|
|
line.long 0x8 "ETRG2,PWM External Trigger Register 2"
|
|
bitfld.long 0x8 31. "RFEN,Recoverable Fault Enable" "0,1"
|
|
bitfld.long 0x8 30. "TRGSRC,Trigger Source" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "TRGFILT,Filtered input" "0,1"
|
|
bitfld.long 0x8 28. "TRGEDGE,Edge Selection" "0: TRGMODE = 1: TRGINx event detection on falling..,1: TRGMODE = 1: TRGINx event detection on rising.."
|
|
newline
|
|
bitfld.long 0x8 24.--25. "TRGMODE,External Trigger Mode" "0: External trigger is not enabled.,1: External PWM Reset Mode,2: External PWM Start Mode,3: Cycle-by-cycle Duty Mode"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "MAXCNT,Maximum Counter value"
|
|
line.long 0xC "LEBR2,PWM Leading-Edge Blanking Register 2"
|
|
bitfld.long 0xC 19. "PWMHREN,PWMH Rising Edge Enable" "0,1"
|
|
bitfld.long 0xC 18. "PWMHFEN,PWMH Falling Edge Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "PWMLREN,PWML Rising Edge Enable" "0,1"
|
|
bitfld.long 0xC 16. "PWMLFEN,PWML Falling Edge Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--6. 1. "LEBDELAY,Leading-Edge Blanking Delay for TRGINx"
|
|
wgroup.long 0x440++0x3
|
|
line.long 0x0 "CMUPD2,PWM Channel Mode Update Register (ch_num = 2)"
|
|
bitfld.long 0x0 13. "CPOLINVUP,Channel Polarity Inversion Update" "0,1"
|
|
bitfld.long 0x0 9. "CPOLUP,Channel Polarity Update" "0,1"
|
|
wgroup.long 0x460++0x3
|
|
line.long 0x0 "CMUPD3,PWM Channel Mode Update Register (ch_num = 3)"
|
|
bitfld.long 0x0 13. "CPOLINVUP,Channel Polarity Inversion Update" "0,1"
|
|
bitfld.long 0x0 9. "CPOLUP,Channel Polarity Update" "0,1"
|
|
tree.end
|
|
tree "QSPI (Quad Serial Peripheral Interface)"
|
|
base ad:0x0
|
|
tree "QSPI0"
|
|
base ad:0xF0020000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
bitfld.long 0x0 7. "SWRST,QSPI Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "QSPIDIS,QSPI Disable" "0,1"
|
|
bitfld.long 0x0 0. "QSPIEN,QSPI Enable" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYCS,Minimum Inactive QCS Delay"
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
bitfld.long 0x0 14. "PHYCR,Physical Interface Clock Ratio" "0: The physical interface clock is at the same..,1: The physical interface clock is twice as fast as.."
|
|
hexmask.long.byte 0x0 8.--11. 1. "NBBITS,Number Of Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "CSMODE,Chip Select Mode" "0: The chip select is deasserted if QSPI_TDR.TD has..,1: The chip select is deasserted when the bit..,2: The chip select is deasserted systematically..,?"
|
|
bitfld.long 0x0 3. "SMRM,Serial Memory Register Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "WDRBT,Wait Data Read Before Transfer" "0: No effect. In SPI mode a transfer can be..,1: In SPI mode a transfer can start only if the.."
|
|
bitfld.long 0x0 1. "LLB,Local Loopback Enable" "0: Local loopback path disabled.,1: Local loopback path enabled."
|
|
newline
|
|
bitfld.long 0x0 0. "SMM,Serial Memory Mode" "0: The QSPI is in SPI mode.,1: The QSPI is in Serial Memory mode."
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RDR,Receive Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
wgroup.long 0xC++0x3
|
|
line.long 0x0 "TDR,Transmit Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 24. "QSPIENS,QSPI Enable Status" "0,1"
|
|
bitfld.long 0x0 10. "INSTRE,Instruction End Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CSS,Chip Select Status" "0,1"
|
|
bitfld.long 0x0 8. "CSR,Chip Select Rise (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 2. "TXEMPTY,Transmission Registers Empty (cleared by writing QSPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing QSPI_TDR)" "0,1"
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading QSPI_RDR)" "0,1"
|
|
wgroup.long 0x14++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 10. "INSTRE,Instruction End Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 9. "CSS,Chip Select Status Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "CSR,Chip Select Rise Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 10. "INSTRE,Instruction End Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 9. "CSS,Chip Select Status Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "CSR,Chip Select Rise Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
bitfld.long 0x4 1. "TDRE,Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 10. "INSTRE,Instruction End Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 9. "CSS,Chip Select Status Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "CSR,Chip Select Rise Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SCR,Serial Clock Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before QSCK"
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Baud Rate"
|
|
newline
|
|
bitfld.long 0x0 1. "CPHA,Clock Phase" "0,1"
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
group.long 0x30++0xB
|
|
line.long 0x0 "IAR,Instruction Address Register"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Address"
|
|
line.long 0x4 "ICR,Instruction Code Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "OPT,Option Code"
|
|
hexmask.long.byte 0x4 0.--7. 1. "INST,Instruction Code"
|
|
line.long 0x8 "IFR,Instruction Frame Register"
|
|
hexmask.long.byte 0x8 16.--20. 1. "NBDUM,Number Of Dummy Cycles"
|
|
bitfld.long 0x8 14. "CRM,Continuous Read Mode" "0: Continuous Read mode is disabled.,1: Continuous Read mode is enabled."
|
|
newline
|
|
bitfld.long 0x8 12.--13. "TFRTYP,Data Transfer Type" "0: Read transfer from the serial memory.Scrambling..,1: Read data transfer from the serial memory.If..,2: Write transfer into the serial memory.Scrambling..,3: Write data transfer into the serial memory.If.."
|
|
bitfld.long 0x8 10. "ADDRL,Address Length" "0: The address is 24 bits long.,1: The address is 32 bits long."
|
|
newline
|
|
bitfld.long 0x8 8.--9. "OPTL,Option Code Length" "0: The option code is 1 bit long.,1: The option code is 2 bits long.,2: The option code is 4 bits long.,3: The option code is 8 bits long."
|
|
bitfld.long 0x8 7. "DATAEN,Data Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "OPTEN,Option Enable" "0,1"
|
|
bitfld.long 0x8 5. "ADDREN,Address Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "INSTEN,Instruction Enable" "0,1"
|
|
bitfld.long 0x8 0.--2. "WIDTH,Width of Instruction Code Address Option Code and Data" "0: Instruction: Single-bit SPI / Address-Option:..,1: Instruction: Single-bit SPI / Address-Option:..,2: Instruction: Single-bit SPI / Address-Option:..,3: Instruction: Single-bit SPI / Address-Option:..,4: Instruction: Single-bit SPI / Address-Option:..,5: Instruction: Dual SPI / Address-Option: Dual SPI..,6: Instruction: Quad SPI / Address-Option: Quad SPI..,?"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "SMR,Scrambling Mode Register"
|
|
bitfld.long 0x0 1. "RVDIS,Scrambling/Unscrambling Random Value Disable" "0,1"
|
|
bitfld.long 0x0 0. "SCREN,Scrambling/Unscrambling Enable" "0: The scrambling/unscrambling is disabled.,1: The scrambling/unscrambling is enabled."
|
|
wgroup.long 0x44++0x3
|
|
line.long 0x0 "SKR,Scrambling Key Register"
|
|
hexmask.long 0x0 0.--31. 1. "USRK,User Scrambling Key"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
tree "QSPI1"
|
|
base ad:0xF0024000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
bitfld.long 0x0 7. "SWRST,QSPI Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "QSPIDIS,QSPI Disable" "0,1"
|
|
bitfld.long 0x0 0. "QSPIEN,QSPI Enable" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYCS,Minimum Inactive QCS Delay"
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
bitfld.long 0x0 14. "PHYCR,Physical Interface Clock Ratio" "0: The physical interface clock is at the same..,1: The physical interface clock is twice as fast as.."
|
|
hexmask.long.byte 0x0 8.--11. 1. "NBBITS,Number Of Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "CSMODE,Chip Select Mode" "0: The chip select is deasserted if QSPI_TDR.TD has..,1: The chip select is deasserted when the bit..,2: The chip select is deasserted systematically..,?"
|
|
bitfld.long 0x0 3. "SMRM,Serial Memory Register Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "WDRBT,Wait Data Read Before Transfer" "0: No effect. In SPI mode a transfer can be..,1: In SPI mode a transfer can start only if the.."
|
|
bitfld.long 0x0 1. "LLB,Local Loopback Enable" "0: Local loopback path disabled.,1: Local loopback path enabled."
|
|
newline
|
|
bitfld.long 0x0 0. "SMM,Serial Memory Mode" "0: The QSPI is in SPI mode.,1: The QSPI is in Serial Memory mode."
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RDR,Receive Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
wgroup.long 0xC++0x3
|
|
line.long 0x0 "TDR,Transmit Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 24. "QSPIENS,QSPI Enable Status" "0,1"
|
|
bitfld.long 0x0 10. "INSTRE,Instruction End Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CSS,Chip Select Status" "0,1"
|
|
bitfld.long 0x0 8. "CSR,Chip Select Rise (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 2. "TXEMPTY,Transmission Registers Empty (cleared by writing QSPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing QSPI_TDR)" "0,1"
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading QSPI_RDR)" "0,1"
|
|
wgroup.long 0x14++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 10. "INSTRE,Instruction End Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 9. "CSS,Chip Select Status Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "CSR,Chip Select Rise Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 10. "INSTRE,Instruction End Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 9. "CSS,Chip Select Status Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "CSR,Chip Select Rise Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
bitfld.long 0x4 1. "TDRE,Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 10. "INSTRE,Instruction End Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 9. "CSS,Chip Select Status Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "CSR,Chip Select Rise Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SCR,Serial Clock Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before QSCK"
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Baud Rate"
|
|
newline
|
|
bitfld.long 0x0 1. "CPHA,Clock Phase" "0,1"
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
group.long 0x30++0xB
|
|
line.long 0x0 "IAR,Instruction Address Register"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Address"
|
|
line.long 0x4 "ICR,Instruction Code Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "OPT,Option Code"
|
|
hexmask.long.byte 0x4 0.--7. 1. "INST,Instruction Code"
|
|
line.long 0x8 "IFR,Instruction Frame Register"
|
|
hexmask.long.byte 0x8 16.--20. 1. "NBDUM,Number Of Dummy Cycles"
|
|
bitfld.long 0x8 14. "CRM,Continuous Read Mode" "0: Continuous Read mode is disabled.,1: Continuous Read mode is enabled."
|
|
newline
|
|
bitfld.long 0x8 12.--13. "TFRTYP,Data Transfer Type" "0: Read transfer from the serial memory.Scrambling..,1: Read data transfer from the serial memory.If..,2: Write transfer into the serial memory.Scrambling..,3: Write data transfer into the serial memory.If.."
|
|
bitfld.long 0x8 10. "ADDRL,Address Length" "0: The address is 24 bits long.,1: The address is 32 bits long."
|
|
newline
|
|
bitfld.long 0x8 8.--9. "OPTL,Option Code Length" "0: The option code is 1 bit long.,1: The option code is 2 bits long.,2: The option code is 4 bits long.,3: The option code is 8 bits long."
|
|
bitfld.long 0x8 7. "DATAEN,Data Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "OPTEN,Option Enable" "0,1"
|
|
bitfld.long 0x8 5. "ADDREN,Address Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "INSTEN,Instruction Enable" "0,1"
|
|
bitfld.long 0x8 0.--2. "WIDTH,Width of Instruction Code Address Option Code and Data" "0: Instruction: Single-bit SPI / Address-Option:..,1: Instruction: Single-bit SPI / Address-Option:..,2: Instruction: Single-bit SPI / Address-Option:..,3: Instruction: Single-bit SPI / Address-Option:..,4: Instruction: Single-bit SPI / Address-Option:..,5: Instruction: Dual SPI / Address-Option: Dual SPI..,6: Instruction: Quad SPI / Address-Option: Quad SPI..,?"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "SMR,Scrambling Mode Register"
|
|
bitfld.long 0x0 1. "RVDIS,Scrambling/Unscrambling Random Value Disable" "0,1"
|
|
bitfld.long 0x0 0. "SCREN,Scrambling/Unscrambling Enable" "0: The scrambling/unscrambling is disabled.,1: The scrambling/unscrambling is enabled."
|
|
wgroup.long 0x44++0x3
|
|
line.long 0x0 "SKR,Scrambling Key Register"
|
|
hexmask.long 0x0 0.--31. 1. "USRK,User Scrambling Key"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "RSTC (Reset Controller)"
|
|
base ad:0xF8048000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "KEY,Write Access Password"
|
|
bitfld.long 0x0 0. "PROCRST,Processor Reset" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 17. "SRCMP,Software Reset Command in Progress" "0,1"
|
|
bitfld.long 0x0 16. "NRSTL,NRST Pin Level" "0,1"
|
|
bitfld.long 0x0 8.--10. "RSTTYP,Reset Type" "0: Both VDDCORE and VDDBU rising,1: VDDCORE rising,2: Watchdog fault occurred,3: Processor reset required by the software,4: NRST pin detected low,?,?,?"
|
|
bitfld.long 0x0 0. "URSTS,User Reset Status" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "KEY,Write Access Password"
|
|
bitfld.long 0x0 4. "URSTIEN,User Reset Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "URSTEN,User Reset Enable" "0,1"
|
|
tree.end
|
|
tree "RTC (Real-Time Clock)"
|
|
base ad:0xF80480B0
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 16.--17. "CALEVSEL,Calendar Event Selection" "0: Week change (every Monday at time 00:00:00),1: Month change (every 01 of each month at time..,2: Year change (every January 1 at time 00:00:00),?"
|
|
bitfld.long 0x0 8.--9. "TIMEVSEL,Time Event Selection" "0: Minute change,1: Hour change,2: Every day at midnight,3: Every day at noon"
|
|
newline
|
|
bitfld.long 0x0 1. "UPDCAL,Update Request Calendar Register" "0,1"
|
|
bitfld.long 0x0 0. "UPDTIM,Update Request Time Register" "0,1"
|
|
line.long 0x4 "MR,Mode Register"
|
|
bitfld.long 0x4 28.--29. "TPERIOD,Period of the Output Pulse" "0: 1 second,1: 500 ms,2: 250 ms,3: 125 ms"
|
|
bitfld.long 0x4 24.--26. "THIGH,High Duration of the Output Pulse" "0: 31.2 ms,1: 15.6 ms,2: 3.91 ms,3: 976 us,4: 488 us,5: 122 us,6: 30.5 us,7: 15.2 us"
|
|
newline
|
|
bitfld.long 0x4 20.--22. "OUT1,ADC Last Channel Trigger Event Source Selection" "0: No waveform stuck at '0',1: 1 Hz square wave,2: 32 Hz square wave,3: 64 Hz square wave,4: 512 Hz square wave,5: Output toggles when alarm flag rises,6: Output is a copy of the alarm flag,7: Duty cycle programmable pulse"
|
|
bitfld.long 0x4 16.--18. "OUT0,All ADC Channel Trigger Event Source Selection" "0: No waveform stuck at '0',1: 1 Hz square wave,2: 32 Hz square wave,3: 64 Hz square wave,4: 512 Hz square wave,5: Output toggles when alarm flag rises,6: Output is a copy of the alarm flag,7: Duty cycle programmable pulse"
|
|
newline
|
|
bitfld.long 0x4 15. "HIGHPPM,HIGH PPM Correction" "0,1"
|
|
hexmask.long.byte 0x4 8.--14. 1. "CORRECTION,Slow Clock Correction"
|
|
newline
|
|
bitfld.long 0x4 4. "NEGPPM,NEGative PPM Correction" "0,1"
|
|
bitfld.long 0x4 2. "UTC,UTC Time Format" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "PERSIAN,PERSIAN Calendar" "0,1"
|
|
bitfld.long 0x4 0. "HRMOD,12-/24-hour Mode" "0,1"
|
|
line.long 0x8 "TIMR,Time Register"
|
|
bitfld.long 0x8 22. "AMPM,Ante Meridiem Post Meridiem Indicator" "0,1"
|
|
hexmask.long.byte 0x8 16.--21. 1. "HOUR,Current Hour"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--14. 1. "MIN,Current Minute"
|
|
hexmask.long.byte 0x8 0.--6. 1. "SEC,Current Second"
|
|
group.long 0x8++0xB
|
|
line.long 0x0 "TIMR_UTC_MODE_MODE,Time Register"
|
|
hexmask.long 0x0 0.--31. 1. "UTC_TIME,Current UTC Time"
|
|
line.long 0x4 "CALR,Calendar Register"
|
|
hexmask.long.byte 0x4 24.--29. 1. "DATE,Current Day in Current Month"
|
|
bitfld.long 0x4 21.--23. "DAY,Current Day in Current Week" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--20. 1. "MONTH,Current Month"
|
|
hexmask.long.byte 0x4 8.--15. 1. "YEAR,Current Year"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "CENT,Current Century"
|
|
line.long 0x8 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x8 23. "HOUREN,Hour Alarm Enable" "0,1"
|
|
bitfld.long 0x8 22. "AMPM,AM/PM Indicator" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "HOUR,Hour Alarm"
|
|
bitfld.long 0x8 15. "MINEN,Minute Alarm Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--14. 1. "MIN,Minute Alarm"
|
|
bitfld.long 0x8 7. "SECEN,Second Alarm Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--6. 1. "SEC,Second Alarm"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "TIMALR_UTC_MODE_MODE,Time Alarm Register"
|
|
hexmask.long 0x0 0.--31. 1. "UTC_TIME,UTC_TIME Alarm"
|
|
line.long 0x4 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x4 31. "DATEEN,Date Alarm Enable" "0,1"
|
|
hexmask.long.byte 0x4 24.--29. 1. "DATE,Date Alarm"
|
|
newline
|
|
bitfld.long 0x4 23. "MTHEN,Month Alarm Enable" "0,1"
|
|
hexmask.long.byte 0x4 16.--20. 1. "MONTH,Month Alarm"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "CALALR_UTC_MODE_MODE,Calendar Alarm Register"
|
|
bitfld.long 0x0 0. "UTCEN,UTC Alarm Enable" "0,1"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 5. "TDERR,Time and/or Date Free Running Error" "0: The internal free running counters are carrying..,1: The internal free running counters have been.."
|
|
bitfld.long 0x0 4. "CALEV,Calendar Event" "0: No calendar event has occurred since the last..,1: At least one calendar event has occurred since.."
|
|
newline
|
|
bitfld.long 0x0 3. "TIMEV,Time Event" "0: No time event has occurred since the last clear.,1: At least one time event has occurred since the.."
|
|
bitfld.long 0x0 2. "SEC,Second Event" "0: No second event has occurred since the last clear.,1: At least one second event has occurred since the.."
|
|
newline
|
|
bitfld.long 0x0 1. "ALARM,Alarm Flag" "0: No alarm matching condition occurred.,1: An alarm matching condition has occurred."
|
|
bitfld.long 0x0 0. "ACKUPD,Acknowledge for Update" "0: Time and calendar registers cannot be updated.,1: Time and calendar registers can be updated."
|
|
wgroup.long 0x1C++0xB
|
|
line.long 0x0 "SCCR,Status Clear Command Register"
|
|
bitfld.long 0x0 5. "TDERRCLR,Time and/or Date Free Running Error Clear" "0,1"
|
|
bitfld.long 0x0 4. "CALCLR,Calendar Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TIMCLR,Time Clear" "0,1"
|
|
bitfld.long 0x0 2. "SECCLR,Second Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ALRCLR,Alarm Clear" "0,1"
|
|
bitfld.long 0x0 0. "ACKCLR,Acknowledge Clear" "0,1"
|
|
line.long 0x4 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x4 5. "TDERREN,Time and/or Date Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 4. "CALEN,Calendar Event Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TIMEN,Time Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 2. "SECEN,Second Event Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ALREN,Alarm Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "ACKEN,Acknowledge Update Interrupt Enable" "0,1"
|
|
line.long 0x8 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x8 5. "TDERRDIS,Time and/or Date Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 4. "CALDIS,Calendar Event Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "TIMDIS,Time Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 2. "SECDIS,Second Event Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "ALRDIS,Alarm Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 0. "ACKDIS,Acknowledge Update Interrupt Disable" "0,1"
|
|
rgroup.long 0x28++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 5. "TDERR,Time and/or Date Error Mask" "0,1"
|
|
bitfld.long 0x0 4. "CAL,Calendar Event Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TIM,Time Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "SEC,Second Event Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ALR,Alarm Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "ACK,Acknowledge Update Interrupt Mask" "0,1"
|
|
line.long 0x4 "VER,Valid Entry Register"
|
|
bitfld.long 0x4 3. "NVCALALR,Non-valid Calendar Alarm" "0,1"
|
|
bitfld.long 0x4 2. "NVTIMALR,Non-valid Time Alarm" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NVCAL,Non-valid Calendar" "0,1"
|
|
bitfld.long 0x4 0. "NVTIM,Non-valid Time" "0,1"
|
|
repeat 2. (list 0x0 0x1)(list ad:0xF8048160 ad:0xF804816C)
|
|
tree "RTC_TS[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "TSTR,TimeStamp Time Register 0"
|
|
bitfld.long 0x0 31. "BACKUP,System Mode of the Tamper" "0,1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "TEVCNT,Tamper Events Counter"
|
|
bitfld.long 0x0 22. "AMPM,AM/PM Indicator of the Tamper" "0,1"
|
|
hexmask.long.byte 0x0 16.--21. 1. "HOUR,Hours of the Tamper"
|
|
hexmask.long.byte 0x0 8.--14. 1. "MIN,Minutes of the Tamper"
|
|
hexmask.long.byte 0x0 0.--6. 1. "SEC,Seconds of the Tamper"
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "TSTR_UTC_MODE_MODE,TimeStamp Time Register 0"
|
|
bitfld.long 0x0 31. "BACKUP,System Mode of the Tamper (cleared by reading RTC_TSSR0)" "0,1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "TEVCNT,Tamper Events Counter (cleared by reading RTC_TSSR0)"
|
|
line.long 0x4 "TSDR,TimeStamp Date Register 0"
|
|
hexmask.long.byte 0x4 24.--29. 1. "DATE,Date of the Tamper"
|
|
bitfld.long 0x4 21.--23. "DAY,Day of the Tamper" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 16.--20. 1. "MONTH,Month of the Tamper"
|
|
hexmask.long.byte 0x4 8.--15. 1. "YEAR,Year of the Tamper"
|
|
hexmask.long.byte 0x4 0.--6. 1. "CENT,Century of the Tamper"
|
|
rgroup.long ($2+0x4)++0x7
|
|
line.long 0x0 "TSDR_UTC_MODE_MODE,TimeStamp Date Register 0"
|
|
hexmask.long 0x0 0.--31. 1. "UTC_TIME,Time of the Tamper (UTC format)"
|
|
line.long 0x4 "TSSR,TimeStamp Source Register 0"
|
|
bitfld.long 0x4 23. "DET7,PIOBU Intrusion Detector" "0,1"
|
|
bitfld.long 0x4 22. "DET6,PIOBU Intrusion Detector" "0,1"
|
|
bitfld.long 0x4 21. "DET5,PIOBU Intrusion Detector" "0,1"
|
|
bitfld.long 0x4 20. "DET4,PIOBU Intrusion Detector" "0,1"
|
|
bitfld.long 0x4 19. "DET3,PIOBU Intrusion Detector" "0,1"
|
|
bitfld.long 0x4 18. "DET2,PIOBU Intrusion Detector" "0,1"
|
|
bitfld.long 0x4 17. "DET1,PIOBU Intrusion Detector" "0,1"
|
|
bitfld.long 0x4 16. "DET0,PIOBU Intrusion Detector" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "JTAG,JTAG Pins Monitor" "0,1"
|
|
bitfld.long 0x4 2. "TST,Test Pin Monitor" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "RXLP (Low Power Asynchronous Receiver)"
|
|
base ad:0xF8049000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even Parity,1: Odd Parity,2: Parity forced to 0,3: Parity forced to 1,4: No parity,?,?,?"
|
|
bitfld.long 0x0 4. "FILTER,Receiver Digital Filter" "0: RXLP does not filter the receive line.,1: RXLP filters the receive line using a.."
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "RHR,Receive Holding Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXCHR,Received Character"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x0 0.--1. "CD,Clock Divisor" "0,1,2,3"
|
|
line.long 0x4 "CMPR,Comparison Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "VAL2,Second Comparison Value for Received Character"
|
|
hexmask.long.byte 0x4 0.--7. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
tree.end
|
|
tree "SCKC (Slow Clock Controller)"
|
|
base ad:0xF8048050
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR,Slow Clock Controller Configuration Register"
|
|
bitfld.long 0x0 3. "OSCSEL,Slow Clock Selector" "0: Slow clock is the embedded 64 kHz (typical) RC..,1: Slow clock is the 32.768 kHz crystal oscillator."
|
|
tree.end
|
|
tree "SDMMC (Secure Digital MultiMedia Card Controller)"
|
|
base ad:0x0
|
|
tree "SDMMC0"
|
|
base ad:0xA0000000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "SSAR,SDMA System Address / Argument 2 Register"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,SDMA System Address"
|
|
hexmask.long 0x0 0.--31. 1. "ARG2,Argument 2"
|
|
group.word 0x4++0x3
|
|
line.word 0x0 "BSR,Block Size Register"
|
|
bitfld.word 0x0 12.--14. "BOUNDARY,SDMA Buffer Boundary" "0: 4-Kbyte boundary,1: 8-Kbyte boundary,2: 16-Kbyte boundary,3: 32-Kbyte boundary,4: 64-Kbyte boundary,5: 128-Kbyte boundary,6: 256-Kbyte boundary,7: 512-Kbyte boundary"
|
|
hexmask.word 0x0 0.--9. 1. "BLKSIZE,Transfer Block Size"
|
|
line.word 0x2 "BCR,Block Count Register"
|
|
hexmask.word 0x2 0.--15. 1. "BLKCNT,Block Count for Current Transfer"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "ARG1R,Argument 1 Register"
|
|
hexmask.long 0x0 0.--31. 1. "ARG1,Argument 1"
|
|
group.word 0xC++0x3
|
|
line.word 0x0 "TMR,Transfer Mode Register"
|
|
bitfld.word 0x0 5. "MSBSEL,Multi/Single Block Selection" "0,1"
|
|
bitfld.word 0x0 4. "DTDSEL,Data Transfer Direction Selection" "0: Writes data from the SDMMC to the device.,1: Reads data from the device to the SDMMC."
|
|
newline
|
|
bitfld.word 0x0 2.--3. "ACMDEN,Auto Command Enable" "0: Auto Command Disabled,1: Auto CMD12 Enabled,2: Auto CMD23 Enabled,?"
|
|
bitfld.word 0x0 1. "BCEN,Block Count Enable" "0: Block count is disabled.,1: Block count is enabled."
|
|
newline
|
|
bitfld.word 0x0 0. "DMAEN,DMA Enable" "0: DMA functionality is disabled.,1: DMA functionality is enabled."
|
|
line.word 0x2 "CR,Command Register"
|
|
hexmask.word.byte 0x2 8.--13. 1. "CMDIDX,Command Index"
|
|
bitfld.word 0x2 6.--7. "CMDTYP,Command Type" "0: Other commands,1: CMD52 to write 'Bus Suspend' in the Card Common..,2: CMD52 to write 'Function Select' in the Card..,3: CMD12 CMD52 to write 'I/O Abort' in the Card.."
|
|
newline
|
|
bitfld.word 0x2 5. "DPSEL,Data Present Select" "0,1"
|
|
bitfld.word 0x2 4. "CMDICEN,Command Index Check Enable" "0: The Command Index Check is disabled.,1: The Command Index Check is enabled."
|
|
newline
|
|
bitfld.word 0x2 3. "CMDCCEN,Command CRC Check Enable" "0: The Command CRC Check is disabled.,1: The Command CRC Check is enabled."
|
|
bitfld.word 0x2 0.--1. "RESPTYP,Response Type" "0: No Response,1: Response Length 136,2: Response Length 48,3: Response Length 48 with Busy"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x10)++0x3
|
|
line.long 0x0 "RR[$1],Response Register"
|
|
hexmask.long 0x0 0.--31. 1. "CMDRESP,Command Response"
|
|
repeat.end
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "BDPR,Buffer Data Port Register"
|
|
hexmask.long 0x0 0.--31. 1. "BUFDATA,Buffer Data"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "PSR,Present State Register"
|
|
bitfld.long 0x0 24. "CMDLL,CMD Line Level" "0,1"
|
|
hexmask.long.byte 0x0 20.--23. 1. "DATLL,DAT[3:0] Line Level"
|
|
newline
|
|
bitfld.long 0x0 19. "WRPPL,Write Protect Pin Level" "0,1"
|
|
bitfld.long 0x0 18. "CARDDPL,Card Detect Pin Level" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "CARDSS,Card State Stable" "0,1"
|
|
bitfld.long 0x0 16. "CARDINS,Card Inserted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BUFRDEN,Buffer Read Enable" "0,1"
|
|
bitfld.long 0x0 10. "BUFWREN,Buffer Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RTACT,Read Transfer Active" "0,1"
|
|
bitfld.long 0x0 8. "WTACT,Write Transfer Active" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DLACT,DAT Line Active" "0,1"
|
|
bitfld.long 0x0 1. "CMDINHD,Command Inhibit (DAT)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMDINHC,Command Inhibit (CMD)" "0,1"
|
|
group.byte 0x28++0x0
|
|
line.byte 0x0 "HC1R_SD_SDIO_MODE,Host Control 1 Register"
|
|
bitfld.byte 0x0 7. "CARDDSEL,Card Detect Signal Selection" "0,1"
|
|
bitfld.byte 0x0 6. "CARDDTL,Card Detect Test Level" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3.--4. "DMASEL,DMA Select" "0: SDMA is selected,?,2: 32-bit Address ADMA2 is selected,?"
|
|
bitfld.byte 0x0 2. "HSEN,High Speed Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "DW,Data Width" "0: 1-bit mode.,1: 4-bit mode."
|
|
bitfld.byte 0x0 0. "LEDCTRL,LED Control" "0: LED off.,1: LED on."
|
|
group.byte 0x28++0x2
|
|
line.byte 0x0 "HC1R_E_MMC_MODE,Host Control 1 Register"
|
|
bitfld.byte 0x0 5. "EXTDW,Extended Data Width" "0,1"
|
|
bitfld.byte 0x0 3.--4. "DMASEL,DMA Select" "0: SDMA is selected,?,2: 32-bit Address ADMA2 is selected,?"
|
|
newline
|
|
bitfld.byte 0x0 2. "HSEN,High Speed Enable" "0,1"
|
|
bitfld.byte 0x0 1. "DW,Data Width" "0: 1-bit mode.,1: 4-bit mode."
|
|
line.byte 0x1 "PCR,Power Control Register"
|
|
bitfld.byte 0x1 0. "SDBPWR,SD Bus Power" "0,1"
|
|
line.byte 0x2 "BGCR_SD_SDIO_MODE,Block Gap Control Register"
|
|
bitfld.byte 0x2 3. "INTBG,Interrupt at Block Gap" "0: Interrupt detection disabled.,1: Interrupt detection enabled."
|
|
bitfld.byte 0x2 2. "RWCTRL,Read Wait Control" "0,1"
|
|
newline
|
|
bitfld.byte 0x2 1. "CONTR,Continue Request" "0,1"
|
|
bitfld.byte 0x2 0. "STPBGR,Stop At Block Gap Request" "0,1"
|
|
group.byte 0x2A++0x1
|
|
line.byte 0x0 "BGCR_E_MMC_MODE,Block Gap Control Register"
|
|
bitfld.byte 0x0 1. "CONTR,Continue Request" "0,1"
|
|
bitfld.byte 0x0 0. "STPBGR,Stop At Block Gap Request" "0,1"
|
|
line.byte 0x1 "WCR,Wakeup Control Register"
|
|
bitfld.byte 0x1 2. "WKENCREM,Wakeup Event Enable on Card Removal" "0: Wakeup Event disabled.,1: Wakeup Event enabled."
|
|
bitfld.byte 0x1 1. "WKENCINS,Wakeup Event Enable on Card Insertion" "0: Wakeup Event disabled.,1: Wakeup Event enabled."
|
|
newline
|
|
bitfld.byte 0x1 0. "WKENCINT,Wakeup Event Enable on Card Interrupt" "0: Wakeup Event disabled.,1: Wakeup Event enabled."
|
|
group.word 0x2C++0x1
|
|
line.word 0x0 "CCR,Clock Control Register"
|
|
hexmask.word.byte 0x0 8.--15. 1. "SDCLKFSEL,SDCLK Frequency Select"
|
|
bitfld.word 0x0 6.--7. "USDCLKFSEL,Upper Bits of SDCLK Frequency Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 5. "CLKGSEL,Clock Generator Select" "0,1"
|
|
bitfld.word 0x0 2. "SDCLKEN,SD Clock Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "INTCLKS,Internal Clock Stable" "0,1"
|
|
bitfld.word 0x0 0. "INTCLKEN,Internal Clock Enable" "0,1"
|
|
group.byte 0x2E++0x1
|
|
line.byte 0x0 "TCR,Timeout Control Register"
|
|
hexmask.byte 0x0 0.--3. 1. "DTCVAL,Data Timeout Counter Value"
|
|
line.byte 0x1 "SRR,Software Reset Register"
|
|
bitfld.byte 0x1 2. "SWRSTDAT,Software reset for DAT line" "0,1"
|
|
bitfld.byte 0x1 1. "SWRSTCMD,Software reset for CMD line" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 0. "SWRSTALL,Software reset for All" "0,1"
|
|
group.word 0x30++0x1
|
|
line.word 0x0 "NISTR_SD_SDIO_MODE,Normal Interrupt Status Register"
|
|
bitfld.word 0x0 15. "ERRINT,Error Interrupt" "0,1"
|
|
bitfld.word 0x0 8. "CINT,Card Interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "CREM,Card Removal" "0,1"
|
|
bitfld.word 0x0 6. "CINS,Card Insertion" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready" "0,1"
|
|
bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "DMAINT,DMA Interrupt" "0,1"
|
|
bitfld.word 0x0 2. "BLKGE,Block Gap Event" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "TRFC,Transfer Complete" "0,1"
|
|
bitfld.word 0x0 0. "CMDC,Command Complete" "0,1"
|
|
group.word 0x30++0x3
|
|
line.word 0x0 "NISTR_E_MMC_MODE,Normal Interrupt Status Register"
|
|
bitfld.word 0x0 15. "ERRINT,Error Interrupt" "0,1"
|
|
bitfld.word 0x0 14. "BOOTAR,Boot Acknowledge Received" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready" "0,1"
|
|
bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "DMAINT,DMA Interrupt" "0,1"
|
|
bitfld.word 0x0 2. "BLKGE,Block Gap Event" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "TRFC,Transfer Complete" "0,1"
|
|
bitfld.word 0x0 0. "CMDC,Command Complete" "0,1"
|
|
line.word 0x2 "EISTR_SD_SDIO_MODE,Error Interrupt Status Register"
|
|
bitfld.word 0x2 9. "ADMA,ADMA Error" "0,1"
|
|
bitfld.word 0x2 8. "ACMD,Auto CMD Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 7. "CURLIM,Current Limit Error" "0,1"
|
|
bitfld.word 0x2 6. "DATEND,Data End Bit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 5. "DATCRC,Data CRC error" "0,1"
|
|
bitfld.word 0x2 4. "DATTEO,Data Timeout Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 3. "CMDIDX,Command Index Error" "0,1"
|
|
bitfld.word 0x2 2. "CMDEND,Command End Bit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "CMDCRC,Command CRC Error" "0,1"
|
|
bitfld.word 0x2 0. "CMDTEO,Command Timeout Error" "0,1"
|
|
group.word 0x32++0x3
|
|
line.word 0x0 "EISTR_E_MMC_MODE,Error Interrupt Status Register"
|
|
bitfld.word 0x0 12. "BOOTAE,Boot Acknowledge Error" "0,1"
|
|
bitfld.word 0x0 9. "ADMA,ADMA Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 8. "ACMD,Auto CMD Error" "0,1"
|
|
bitfld.word 0x0 7. "CURLIM,Current Limit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "DATEND,Data End Bit Error" "0,1"
|
|
bitfld.word 0x0 5. "DATCRC,Data CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "DATTEO,Data Timeout error" "0,1"
|
|
bitfld.word 0x0 3. "CMDIDX,Command Index Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "CMDEND,Command End Bit Error" "0,1"
|
|
bitfld.word 0x0 1. "CMDCRC,Command CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "CMDTEO,Command Timeout Error" "0,1"
|
|
line.word 0x2 "NISTER_SD_SDIO_MODE,Normal Interrupt Status Enable Register"
|
|
bitfld.word 0x2 8. "CINT,Card Interrupt Status Enable" "0: The CINT status flag in SDMMC_NISTR is masked.,1: The CINT status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x2 7. "CREM,Card Removal Status Enable" "0: The CREM status flag in SDMMC_NISTR is masked.,1: The CREM status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 6. "CINS,Card Insertion Status Enable" "0: The CINS status flag in SDMMC_NISTR is masked.,1: The CINS status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x2 5. "BRDRDY,Buffer Read Ready Status Enable" "0: The BRDRDY status flag in SDMMC_NISTR is masked.,1: The BRDRDY status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 4. "BWRRDY,Buffer Write Ready Status Enable" "0: The BWRRDY status flag in SDMMC_NISTR is masked.,1: The BWRRDY status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x2 3. "DMAINT,DMA Interrupt Status Enable" "0: The DMAINT status flag in SDMMC_NISTR is masked.,1: The DMAINT status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 2. "BLKGE,Block Gap Event Status Enable" "0: The BLKGE status flag in SDMMC_NISTR is masked.,1: The BLKGE status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x2 1. "TRFC,Transfer Complete Status Enable" "0: The TRFC status flag in SDMMC_NISTR is masked.,1: The TRFC status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 0. "CMDC,Command Complete Status Enable" "0: The CMDC status flag in SDMMC_NISTR is masked.,1: The CMDC status flag in SDMMC_NISTR is enabled."
|
|
group.word 0x34++0x3
|
|
line.word 0x0 "NISTER_E_MMC_MODE,Normal Interrupt Status Enable Register"
|
|
bitfld.word 0x0 14. "BOOTAR,Boot Acknowledge Received Status Enable" "0: The BOOTAR status flag in SDMMC_NISTR is masked.,1: The BOOTAR status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready Status Enable" "0: The BRDRDY status flag in SDMMC_NISTR is masked.,1: The BRDRDY status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready Status Enable" "0: The BWRRDY status flag in SDMMC_NISTR is masked.,1: The BWRRDY status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x0 3. "DMAINT,DMA Interrupt Status Enable" "0: The DMAINT status flag in SDMMC_NISTR is masked.,1: The DMAINT status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 2. "BLKGE,Block Gap Event Status Enable" "0: The BLKGE status flag in SDMMC_NISTR is masked.,1: The BLKGE status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x0 1. "TRFC,Transfer Complete Status Enable" "0: The TRFC status flag in SDMMC_NISTR is masked.,1: The TRFC status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 0. "CMDC,Command Complete Status Enable" "0: The CMDC status flag in SDMMC_NISTR is masked.,1: The CMDC status flag in SDMMC_NISTR is enabled."
|
|
line.word 0x2 "EISTER_SD_SDIO_MODE,Error Interrupt Status Enable Register"
|
|
bitfld.word 0x2 9. "ADMA,ADMA Error Status Enable" "0: The ADMA status flag in SDMMC_EISTR is masked.,1: The ADMA status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 8. "ACMD,Auto CMD Error Status Enable" "0: The ACMD status flag in SDMMC_EISTR is masked.,1: The ACMD status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 7. "CURLIM,Current Limit Error Status Enable" "0: The CURLIM status flag in SDMMC_EISTR is masked.,1: The CURLIM status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 6. "DATEND,Data End Bit Error Status Enable" "0: The DATEND status flag in SDMMC_EISTR is masked.,1: The DATEND status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 5. "DATCRC,Data CRC Error Status Enable" "0: The DATCRC status flag in SDMMC_EISTR is masked.,1: The DATCRC status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 4. "DATTEO,Data Timeout Error Status Enable" "0: The DATTEO status flag in SDMMC_EISTR is masked.,1: The DATTEO status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 3. "CMDIDX,Command Index Error Status Enable" "0: The CMDIDX status flag in SDMMC_EISTR is masked.,1: The CMDIDX status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 2. "CMDEND,Command End Bit Error Status Enable" "0: The CMDEND status flag in SDMMC_EISTR is masked.,1: The CMDEND status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 1. "CMDCRC,Command CRC Error Status Enable" "0: The CMDCRC status flag in SDMMC_EISTR is masked.,1: The CMDCRC status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 0. "CMDTEO,Command Timeout Error Status Enable" "0: The CMDTEO status flag in SDMMC_EISTR is masked.,1: The CMDTEO status flag in SDMMC_EISTR is enabled."
|
|
group.word 0x36++0x3
|
|
line.word 0x0 "EISTER_E_MMC_MODE,Error Interrupt Status Enable Register"
|
|
bitfld.word 0x0 12. "BOOTAE,Boot Acknowledge Error Status Enable" "0: The BOOTAE status flag in SDMMC_EISTR is masked.,1: The BOOTAE status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x0 9. "ADMA,ADMA Error Status Enable" "0: The ADMA status flag in SDMMC_EISTR is masked.,1: The ADMA status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 8. "ACMD,Auto CMD Error Status Enable" "0: The ACMD status flag in SDMMC_EISTR is masked.,1: The ACMD status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x0 7. "CURLIM,Current Limit Error Status Enable" "0: The CURLIM status flag in SDMMC_EISTR is masked.,1: The CURLIM status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 6. "DATEND,Data End Bit Error Status Enable" "0: The DATEND status flag in SDMMC_EISTR is masked.,1: The DATEND status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x0 5. "DATCRC,Data CRC Error Status Enable" "0: The DATCRC status flag in SDMMC_EISTR is masked.,1: The DATCRC status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 4. "DATTEO,Data Timeout Error Status Enable" "0: The DATTEO status flag in SDMMC_EISTR is masked.,1: The DATTEO status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x0 3. "CMDIDX,Command Index Error Status Enable" "0: The CMDIDX status flag in SDMMC_EISTR is masked.,1: The CMDIDX status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 2. "CMDEND,Command End Bit Error Status Enable" "0: The CMDEND status flag in SDMMC_EISTR is masked.,1: The CMDEND status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x0 1. "CMDCRC,Command CRC Error Status Enable" "0: The CMDCRC status flag in SDMMC_EISTR is masked.,1: The CMDCRC status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 0. "CMDTEO,Command Timeout Error Status Enable" "0: The CMDTEO status flag in SDMMC_EISTR is masked.,1: The CMDTEO status flag in SDMMC_EISTR is enabled."
|
|
line.word 0x2 "NISIER_SD_SDIO_MODE,Normal Interrupt Signal Enable Register"
|
|
bitfld.word 0x2 8. "CINT,Card Interrupt Signal Enable" "0: No interrupt is generated when the CINT status..,1: An interrupt is generated when the CINT status.."
|
|
bitfld.word 0x2 7. "CREM,Card Removal Signal Enable" "0: No interrupt is generated when the CREM status..,1: An interrupt is generated when the CREM status.."
|
|
newline
|
|
bitfld.word 0x2 6. "CINS,Card Insertion Signal Enable" "0: No interrupt is generated when the CINS status..,1: An interrupt is generated when the CINS status.."
|
|
bitfld.word 0x2 5. "BRDRDY,Buffer Read Ready Signal Enable" "0: No interrupt is generated when the BRDRDY status..,1: An interrupt is generated when the BRDRDY status.."
|
|
newline
|
|
bitfld.word 0x2 4. "BWRRDY,Buffer Write Ready Signal Enable" "0: No interrupt is generated when the BWRRDY status..,1: An interrupt is generated when the BWRRDY status.."
|
|
bitfld.word 0x2 3. "DMAINT,DMA Interrupt Signal Enable" "0: No interrupt is generated when the DMAINT status..,1: An interrupt is generated when the DMAINT status.."
|
|
newline
|
|
bitfld.word 0x2 2. "BLKGE,Block Gap Event Signal Enable" "0: No interrupt is generated when the BLKGE status..,1: An interrupt is generated when the BLKGE status.."
|
|
bitfld.word 0x2 1. "TRFC,Transfer Complete Signal Enable" "0: No interrupt is generated when the TRFC status..,1: An interrupt is generated when the TRFC status.."
|
|
newline
|
|
bitfld.word 0x2 0. "CMDC,Command Complete Signal Enable" "0: No interrupt is generated when the CMDC status..,1: An interrupt is generated when the CMDC status.."
|
|
group.word 0x38++0x3
|
|
line.word 0x0 "NISIER_E_MMC_MODE,Normal Interrupt Signal Enable Register"
|
|
bitfld.word 0x0 14. "BOOTAR,Boot Acknowledge Received Signal Enable" "0: No interrupt is generated when the BOOTAR status..,1: An interrupt is generated when the BOOTAR status.."
|
|
bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready Signal Enable" "0: No interrupt is generated when the BRDRDY status..,1: An interrupt is generated when the BRDRDY status.."
|
|
newline
|
|
bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready Signal Enable" "0: No interrupt is generated when the BWRRDY status..,1: An interrupt is generated when the BWRRDY status.."
|
|
bitfld.word 0x0 3. "DMAINT,DMA Interrupt Signal Enable" "0: No interrupt is generated when the DMAINT status..,1: An interrupt is generated when the DMAINT status.."
|
|
newline
|
|
bitfld.word 0x0 2. "BLKGE,Block Gap Event Signal Enable" "0: No interrupt is generated when the BLKGE status..,1: An interrupt is generated when the BLKGE status.."
|
|
bitfld.word 0x0 1. "TRFC,Transfer Complete Signal Enable" "0: No interrupt is generated when the TRFC status..,1: An interrupt is generated when the TRFC status.."
|
|
newline
|
|
bitfld.word 0x0 0. "CMDC,Command Complete Signal Enable" "0: No interrupt is generated when the CMDC status..,1: An interrupt is generated when the CMDC status.."
|
|
line.word 0x2 "EISIER_SD_SDIO_MODE,Error Interrupt Signal Enable Register"
|
|
bitfld.word 0x2 9. "ADMA,ADMA Error Signal Enable" "0: No interrupt is generated when the ADMA status..,1: An interrupt is generated when the ADMA status.."
|
|
bitfld.word 0x2 8. "ACMD,Auto CMD Error Signal Enable" "0: No interrupt is generated when the ACMD status..,1: An interrupt is generated when the ACMD status.."
|
|
newline
|
|
bitfld.word 0x2 7. "CURLIM,Current Limit Error Signal Enable" "0: No interrupt is generated when the CURLIM status..,1: An interrupt is generated when the CURLIM status.."
|
|
bitfld.word 0x2 6. "DATEND,Data End Bit Error Signal Enable" "0: No interrupt is generated when the DATEND status..,1: An interrupt is generated when the DATEND status.."
|
|
newline
|
|
bitfld.word 0x2 5. "DATCRC,Data CRC Error Signal Enable" "0: No interrupt is generated when the DATCRC status..,1: An interrupt is generated when the DATCRC status.."
|
|
bitfld.word 0x2 4. "DATTEO,Data Timeout Error Signal Enable" "0: No interrupt is generated when the DATTEO status..,1: An interrupt is generated when the DATTEO status.."
|
|
newline
|
|
bitfld.word 0x2 3. "CMDIDX,Command Index Error Signal Enable" "0: No interrupt is generated when the CMDIDX status..,1: An interrupt is generated when the CMDIDX status.."
|
|
bitfld.word 0x2 2. "CMDEND,Command End Bit Error Signal Enable" "0: No interrupt is generated when the CMDEND status..,1: An interrupt is generated when the CMDEND status.."
|
|
newline
|
|
bitfld.word 0x2 1. "CMDCRC,Command CRC Error Signal Enable" "0: No interrupt is generated when the CDMCRC status..,1: An interrupt is generated when the CMDCRC status.."
|
|
bitfld.word 0x2 0. "CMDTEO,Command Timeout Error Signal Enable" "0: No interrupt is generated when the CMDTEO status..,1: An interrupt is generated when the CMDTEO status.."
|
|
group.word 0x3A++0x1
|
|
line.word 0x0 "EISIER_E_MMC_MODE,Error Interrupt Signal Enable Register"
|
|
bitfld.word 0x0 12. "BOOTAE,Boot Acknowledge Error Signal Enable" "0: No interrupt is generated when the BOOTAE status..,1: An interrupt is generated when the BOOTAE status.."
|
|
bitfld.word 0x0 9. "ADMA,ADMA Error Signal Enable" "0: No interrupt is generated when the ADMA status..,1: An interrupt is generated when the ADMA status.."
|
|
newline
|
|
bitfld.word 0x0 8. "ACMD,Auto CMD Error Signal Enable" "0: No interrupt is generated when the ACMD status..,1: An interrupt is generated when the ACMD status.."
|
|
bitfld.word 0x0 7. "CURLIM,Current Limit Error Signal Enable" "0: No interrupt is generated when the CURLIM status..,1: An interrupt is generated when the CURLIM status.."
|
|
newline
|
|
bitfld.word 0x0 6. "DATEND,Data End Bit Error Signal Enable" "0: No interrupt is generated when the DATEND status..,1: An interrupt is generated when the DATEND status.."
|
|
bitfld.word 0x0 5. "DATCRC,Data CRC Error Signal Enable" "0: No interrupt is generated when the DATCRC status..,1: An interrupt is generated when the DATCRC status.."
|
|
newline
|
|
bitfld.word 0x0 4. "DATTEO,Data Timeout Error Signal Enable" "0: No interrupt is generated when the DATTEO status..,1: An interrupt is generated when the DATTEO status.."
|
|
bitfld.word 0x0 3. "CMDIDX,Command Index Error Signal Enable" "0: No interrupt is generated when the CMDIDX status..,1: An interrupt is generated when the CMDIDX status.."
|
|
newline
|
|
bitfld.word 0x0 2. "CMDEND,Command End Bit Error Signal Enable" "0: No interrupt is generated when the CMDEND status..,1: An interrupt is generated when the CMDEND status.."
|
|
bitfld.word 0x0 1. "CMDCRC,Command CRC Error Signal Enable" "0: No interrupt is generated when the CDMCRC status..,1: An interrupt is generated when the CMDCRC status.."
|
|
newline
|
|
bitfld.word 0x0 0. "CMDTEO,Command Timeout Error Signal Enable" "0: No interrupt is generated when the CMDTEO status..,1: An interrupt is generated when the CMDTEO status.."
|
|
rgroup.word 0x3C++0x1
|
|
line.word 0x0 "ACESR,Auto CMD Error Status Register"
|
|
bitfld.word 0x0 7. "CMDNI,Command Not Issued by Auto CMD12 Error" "0,1"
|
|
bitfld.word 0x0 4. "ACMDIDX,Auto CMD Index Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "ACMDEND,Auto CMD End Bit Error" "0,1"
|
|
bitfld.word 0x0 2. "ACMDCRC,Auto CMD CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "ACMDTEO,Auto CMD Timeout Error" "0,1"
|
|
bitfld.word 0x0 0. "ACMD12NE,Auto CMD12 Not Executed" "0,1"
|
|
group.word 0x3E++0x1
|
|
line.word 0x0 "HC2R_SD_SDIO_MODE,Host Control 2 Register"
|
|
bitfld.word 0x0 15. "PVALEN,Preset Value Enable" "0,1"
|
|
bitfld.word 0x0 14. "ASINTEN,Asynchronous Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "SCLKSEL,Sampling Clock Select" "0,1"
|
|
bitfld.word 0x0 6. "EXTUN,Execute Tuning" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4.--5. "DRVSEL,Driver Strength Select" "0: Driver Type B is selected (Default),1: Driver Type A is selected,2: Driver Type C is selected,3: Driver Type D is selected"
|
|
bitfld.word 0x0 3. "VS18EN,1.8V Signaling Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0.--2. "UHSMS,UHS Mode Select" "0: UHS SDR12 Mode,1: UHS SDR25 Mode,2: UHS SDR50 Mode,3: UHS SDR104 Mode,4: UHS DDR50 Mode,?,?,?"
|
|
group.word 0x3E++0x1
|
|
line.word 0x0 "HC2R_E_MMC_MODE,Host Control 2 Register"
|
|
bitfld.word 0x0 15. "PVALEN,Preset Value Enable" "0,1"
|
|
bitfld.word 0x0 7. "SCLKSEL,Sampling Clock Select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "EXTUN,Execute Tuning" "0,1"
|
|
bitfld.word 0x0 4.--5. "DRVSEL,Driver Strength Select" "0: Driver Type B is selected (Default),1: Driver Type A is selected,2: Driver Type C is selected,3: Driver Type D is selected"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--3. 1. "HS200EN,HS200 Mode Enable"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "CA0R,Capabilities 0 Register"
|
|
bitfld.long 0x0 30.--31. "SLTYPE,Slot Type" "0,1,2,3"
|
|
bitfld.long 0x0 29. "ASINTSUP,Asynchronous Interrupt Support" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "SB64SUP,64-Bit System Bus Support" "0,1"
|
|
bitfld.long 0x0 26. "V18VSUP,Voltage Support 1.8V" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "V30VSUP,Voltage Support 3.0V" "0,1"
|
|
bitfld.long 0x0 24. "V33VSUP,Voltage Support 3.3V" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "SRSUP,Suspend/Resume Support" "0,1"
|
|
bitfld.long 0x0 22. "SDMASUP,SDMA Support" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "HSSUP,High Speed Support" "0,1"
|
|
bitfld.long 0x0 19. "ADMA2SUP,ADMA2 Support" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "ED8SUP,8-Bit Support for Embedded Device" "0,1"
|
|
bitfld.long 0x0 16.--17. "MAXBLKL,Max Block Length" "0: 512 bytes,1: 1024 bytes,2: 2048 bytes,?"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "BASECLKF,Base Clock Frequency"
|
|
bitfld.long 0x0 7. "TEOCLKU,Timeout Clock Unit" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TEOCLKF,Timeout Clock Frequency"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "CA1R,Capabilities 1 Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CLKMULT,Clock Multiplier"
|
|
bitfld.long 0x0 14.--15. "RTMOD,Retuning Modes" "0: Timer,1: Timer and Retuning Request,2: Auto Retuning (for transfer) Timer and Retuning..,?"
|
|
newline
|
|
bitfld.long 0x0 13. "TSDR50,Use Tuning for SDR50" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TCNTRT,Timer Count For Retuning"
|
|
newline
|
|
bitfld.long 0x0 6. "DRVDSUP,Driver Type D Support" "0,1"
|
|
bitfld.long 0x0 5. "DRVCSUP,Driver Type C Support" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "DRVASUP,Driver Type A Support" "0,1"
|
|
bitfld.long 0x0 2. "DDR50SUP,DDR50 Support" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SDR104SUP,SDR104 Support" "0,1"
|
|
bitfld.long 0x0 0. "SDR50SUP,SDR50 Support" "0,1"
|
|
line.long 0x4 "MCCAR,Maximum Current Capabilities Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "MAXCUR18V,Maximum Current for 1.8V"
|
|
hexmask.long.byte 0x4 8.--15. 1. "MAXCUR30V,Maximum Current for 3.0V"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "MAXCUR33V,Maximum Current for 3.3V"
|
|
wgroup.word 0x50++0x3
|
|
line.word 0x0 "FERACES,Force Event Register for Auto CMD Error Status"
|
|
bitfld.word 0x0 7. "CMDNI,Force Event for Command Not Issued by Auto CMD12 Error" "0,1"
|
|
bitfld.word 0x0 4. "ACMDIDX,Force Event for Auto CMD Index Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "ACMDEND,Force Event for Auto CMD End Bit Error" "0,1"
|
|
bitfld.word 0x0 2. "ACMDCRC,Force Event for Auto CMD CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "ACMDTEO,Force Event for Auto CMD Timeout Error" "0,1"
|
|
bitfld.word 0x0 0. "ACMD12NE,Force Event for Auto CMD12 Not Executed" "0,1"
|
|
line.word 0x2 "FEREIS,Force Event Register for Error Interrupt Status"
|
|
bitfld.word 0x2 12. "BOOTAE,Force Event for Boot Acknowledge Error" "0,1"
|
|
bitfld.word 0x2 9. "ADMA,Force Event for ADMA Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 8. "ACMD,Force Event for Auto CMD Error" "0,1"
|
|
bitfld.word 0x2 7. "CURLIM,Force Event for Current Limit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 6. "DATEND,Force Event for Data End Bit Error" "0,1"
|
|
bitfld.word 0x2 5. "DATCRC,Force Event for Data CRC error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 4. "DATTEO,Force Event for Data Timeout error" "0,1"
|
|
bitfld.word 0x2 3. "CMDIDX,Force Event for Command Index Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 2. "CMDEND,Force Event for Command End Bit Error" "0,1"
|
|
bitfld.word 0x2 1. "CMDCRC,Force Event for Command CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 0. "CMDTEO,Force Event for Command Timeout Error" "0,1"
|
|
rgroup.byte 0x54++0x0
|
|
line.byte 0x0 "AESR,ADMA Error Status Register"
|
|
bitfld.byte 0x0 2. "LMIS,ADMA Length Mismatch Error" "0,1"
|
|
bitfld.byte 0x0 0.--1. "ERRST,ADMA Error State" "0,1,2,3"
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "ASAR0,ADMA System Address Register 0"
|
|
hexmask.long 0x0 0.--31. 1. "ADMASA,ADMA System Address"
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x60)++0x1
|
|
line.word 0x0 "PVR[$1],Preset Value Register 0 (for initialization)"
|
|
bitfld.word 0x0 14.--15. "DRVSEL,Driver Strength Select" "0,1,2,3"
|
|
bitfld.word 0x0 10. "CLKGSEL,Clock Generator Select" "0,1"
|
|
newline
|
|
hexmask.word 0x0 0.--9. 1. "SDCLKFSEL,SDCLK Frequency Select"
|
|
repeat.end
|
|
rgroup.word 0xFC++0x3
|
|
line.word 0x0 "SISR,Slot Interrupt Status Register"
|
|
bitfld.word 0x0 0.--1. "INTSSL,Interrupt Signal for Each Slot" "0,1,2,3"
|
|
line.word 0x2 "HCVR,Host Controller Version Register"
|
|
hexmask.word.byte 0x2 8.--15. 1. "VVER,Vendor Version Number"
|
|
hexmask.word.byte 0x2 0.--7. 1. "SVER,Specification Version Number"
|
|
rgroup.long 0x200++0x3
|
|
line.long 0x0 "APSR,Additional Present State Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "HDATLL,DAT[7:4] High Line Level"
|
|
group.byte 0x204++0x0
|
|
line.byte 0x0 "MC1R,e.MMC Control 1 Register"
|
|
bitfld.byte 0x0 7. "FCD,e.MMC Force Card Detect" "0,1"
|
|
bitfld.byte 0x0 6. "RSTN,e.MMC Reset Signal" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 5. "BOOTA,e.MMC Boot Acknowledge Enable" "0,1"
|
|
bitfld.byte 0x0 4. "OPD,e.MMC Open Drain Mode" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "DDR,e.MMC HSDDR Mode" "0,1"
|
|
bitfld.byte 0x0 0.--1. "CMDTYP,e.MMC Command Type" "0: The command is not an e.MMC specific command.,1: This bit must be set to 1 when the e.MMC is in..,2: This bit must be set to 1 in the case of Stream..,3: Starts a Boot Operation mode at the next write.."
|
|
wgroup.byte 0x205++0x0
|
|
line.byte 0x0 "MC2R,e.MMC Control 2 Register"
|
|
bitfld.byte 0x0 1. "ABOOT,e.MMC Abort Boot" "0,1"
|
|
bitfld.byte 0x0 0. "SRESP,e.MMC Abort Wait IRQ" "0,1"
|
|
group.long 0x208++0x7
|
|
line.long 0x0 "ACR,AHB Control Register"
|
|
bitfld.long 0x0 0.--1. "BMAX,AHB Maximum Burst" "0: The maximum burst size is INCR16.,1: The maximum burst size is INCR8.,2: The maximum burst size is INCR4.,3: Only SINGLE transfers are performed."
|
|
line.long 0x4 "CC2R,Clock Control 2 Register"
|
|
bitfld.long 0x4 0. "FSDCLKD,Force SDCLK Disabled" "0,1"
|
|
group.byte 0x210++0x0
|
|
line.byte 0x0 "RTC1R,Retuning Timer Control 1 Register"
|
|
bitfld.byte 0x0 0. "TMREN,Retuning Timer Enable" "0: The retuning timer is disabled.,1: The retuning timer is enabled."
|
|
wgroup.byte 0x211++0x0
|
|
line.byte 0x0 "RTC2R,Retuning Timer Control 2 Register"
|
|
bitfld.byte 0x0 0. "RLD,Retuning Timer Reload" "0,1"
|
|
group.long 0x214++0x3
|
|
line.long 0x0 "RTCVR,Retuning Timer Counter Value Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TCVAL,Retuning Timer Counter Value"
|
|
group.byte 0x218++0x1
|
|
line.byte 0x0 "RTISTER,Retuning Timer Interrupt Status Enable Register"
|
|
bitfld.byte 0x0 0. "TEVT,Retuning Timer Event" "0: The TEVT status flag in SDMMC_RTISTR is masked.,1: The TEVT status flag in SDMMC_RTISTR is enabled."
|
|
line.byte 0x1 "RTISIER,Retuning Timer Interrupt Signal Enable Register"
|
|
bitfld.byte 0x1 0. "TEVT,Retuning Timer Event" "0: No interrupt is generated when the TEVT status..,1: An interrupt is generated when the TEVT status.."
|
|
group.byte 0x21C++0x0
|
|
line.byte 0x0 "RTISTR,Retuning Timer Interrupt Status Register"
|
|
bitfld.byte 0x0 0. "TEVT,Retuning Timer Event" "0,1"
|
|
rgroup.byte 0x21D++0x0
|
|
line.byte 0x0 "RTSSR,Retuning Timer Status Slots Register"
|
|
bitfld.byte 0x0 0.--1. "TEVTSLOT,Retuning Timer Event Slots" "0,1,2,3"
|
|
group.long 0x220++0x3
|
|
line.long 0x0 "TUNCR,Tuning Control Register"
|
|
bitfld.long 0x0 0. "SMPLPT,Sampling Point" "0,1"
|
|
group.long 0x230++0x3
|
|
line.long 0x0 "CACR,Capabilities Control Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "KEY,Key"
|
|
bitfld.long 0x0 0. "CAPWREN,Capabilities Write Enable" "0,1"
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "CALCR,Calibration Control Register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "CALP,Calibration P Status"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CALN,Calibration N Status"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CNTVAL,Calibration Counter Value"
|
|
bitfld.long 0x0 5. "TUNDIS,Calibration During Tuning Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ALWYSON,Calibration Analog Always ON" "0,1"
|
|
bitfld.long 0x0 0. "EN,PADs Calibration Enable" "0,1"
|
|
tree.end
|
|
tree "SDMMC1"
|
|
base ad:0xB0000000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "SSAR,SDMA System Address / Argument 2 Register"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,SDMA System Address"
|
|
hexmask.long 0x0 0.--31. 1. "ARG2,Argument 2"
|
|
group.word 0x4++0x3
|
|
line.word 0x0 "BSR,Block Size Register"
|
|
bitfld.word 0x0 12.--14. "BOUNDARY,SDMA Buffer Boundary" "0: 4-Kbyte boundary,1: 8-Kbyte boundary,2: 16-Kbyte boundary,3: 32-Kbyte boundary,4: 64-Kbyte boundary,5: 128-Kbyte boundary,6: 256-Kbyte boundary,7: 512-Kbyte boundary"
|
|
hexmask.word 0x0 0.--9. 1. "BLKSIZE,Transfer Block Size"
|
|
line.word 0x2 "BCR,Block Count Register"
|
|
hexmask.word 0x2 0.--15. 1. "BLKCNT,Block Count for Current Transfer"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "ARG1R,Argument 1 Register"
|
|
hexmask.long 0x0 0.--31. 1. "ARG1,Argument 1"
|
|
group.word 0xC++0x3
|
|
line.word 0x0 "TMR,Transfer Mode Register"
|
|
bitfld.word 0x0 5. "MSBSEL,Multi/Single Block Selection" "0,1"
|
|
bitfld.word 0x0 4. "DTDSEL,Data Transfer Direction Selection" "0: Writes data from the SDMMC to the device.,1: Reads data from the device to the SDMMC."
|
|
newline
|
|
bitfld.word 0x0 2.--3. "ACMDEN,Auto Command Enable" "0: Auto Command Disabled,1: Auto CMD12 Enabled,2: Auto CMD23 Enabled,?"
|
|
bitfld.word 0x0 1. "BCEN,Block Count Enable" "0: Block count is disabled.,1: Block count is enabled."
|
|
newline
|
|
bitfld.word 0x0 0. "DMAEN,DMA Enable" "0: DMA functionality is disabled.,1: DMA functionality is enabled."
|
|
line.word 0x2 "CR,Command Register"
|
|
hexmask.word.byte 0x2 8.--13. 1. "CMDIDX,Command Index"
|
|
bitfld.word 0x2 6.--7. "CMDTYP,Command Type" "0: Other commands,1: CMD52 to write 'Bus Suspend' in the Card Common..,2: CMD52 to write 'Function Select' in the Card..,3: CMD12 CMD52 to write 'I/O Abort' in the Card.."
|
|
newline
|
|
bitfld.word 0x2 5. "DPSEL,Data Present Select" "0,1"
|
|
bitfld.word 0x2 4. "CMDICEN,Command Index Check Enable" "0: The Command Index Check is disabled.,1: The Command Index Check is enabled."
|
|
newline
|
|
bitfld.word 0x2 3. "CMDCCEN,Command CRC Check Enable" "0: The Command CRC Check is disabled.,1: The Command CRC Check is enabled."
|
|
bitfld.word 0x2 0.--1. "RESPTYP,Response Type" "0: No Response,1: Response Length 136,2: Response Length 48,3: Response Length 48 with Busy"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x10)++0x3
|
|
line.long 0x0 "RR[$1],Response Register"
|
|
hexmask.long 0x0 0.--31. 1. "CMDRESP,Command Response"
|
|
repeat.end
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "BDPR,Buffer Data Port Register"
|
|
hexmask.long 0x0 0.--31. 1. "BUFDATA,Buffer Data"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "PSR,Present State Register"
|
|
bitfld.long 0x0 24. "CMDLL,CMD Line Level" "0,1"
|
|
hexmask.long.byte 0x0 20.--23. 1. "DATLL,DAT[3:0] Line Level"
|
|
newline
|
|
bitfld.long 0x0 19. "WRPPL,Write Protect Pin Level" "0,1"
|
|
bitfld.long 0x0 18. "CARDDPL,Card Detect Pin Level" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "CARDSS,Card State Stable" "0,1"
|
|
bitfld.long 0x0 16. "CARDINS,Card Inserted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BUFRDEN,Buffer Read Enable" "0,1"
|
|
bitfld.long 0x0 10. "BUFWREN,Buffer Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RTACT,Read Transfer Active" "0,1"
|
|
bitfld.long 0x0 8. "WTACT,Write Transfer Active" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DLACT,DAT Line Active" "0,1"
|
|
bitfld.long 0x0 1. "CMDINHD,Command Inhibit (DAT)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMDINHC,Command Inhibit (CMD)" "0,1"
|
|
group.byte 0x28++0x0
|
|
line.byte 0x0 "HC1R_SD_SDIO_MODE,Host Control 1 Register"
|
|
bitfld.byte 0x0 7. "CARDDSEL,Card Detect Signal Selection" "0,1"
|
|
bitfld.byte 0x0 6. "CARDDTL,Card Detect Test Level" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3.--4. "DMASEL,DMA Select" "0: SDMA is selected,?,2: 32-bit Address ADMA2 is selected,?"
|
|
bitfld.byte 0x0 2. "HSEN,High Speed Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "DW,Data Width" "0: 1-bit mode.,1: 4-bit mode."
|
|
bitfld.byte 0x0 0. "LEDCTRL,LED Control" "0: LED off.,1: LED on."
|
|
group.byte 0x28++0x2
|
|
line.byte 0x0 "HC1R_E_MMC_MODE,Host Control 1 Register"
|
|
bitfld.byte 0x0 5. "EXTDW,Extended Data Width" "0,1"
|
|
bitfld.byte 0x0 3.--4. "DMASEL,DMA Select" "0: SDMA is selected,?,2: 32-bit Address ADMA2 is selected,?"
|
|
newline
|
|
bitfld.byte 0x0 2. "HSEN,High Speed Enable" "0,1"
|
|
bitfld.byte 0x0 1. "DW,Data Width" "0: 1-bit mode.,1: 4-bit mode."
|
|
line.byte 0x1 "PCR,Power Control Register"
|
|
bitfld.byte 0x1 0. "SDBPWR,SD Bus Power" "0,1"
|
|
line.byte 0x2 "BGCR_SD_SDIO_MODE,Block Gap Control Register"
|
|
bitfld.byte 0x2 3. "INTBG,Interrupt at Block Gap" "0: Interrupt detection disabled.,1: Interrupt detection enabled."
|
|
bitfld.byte 0x2 2. "RWCTRL,Read Wait Control" "0,1"
|
|
newline
|
|
bitfld.byte 0x2 1. "CONTR,Continue Request" "0,1"
|
|
bitfld.byte 0x2 0. "STPBGR,Stop At Block Gap Request" "0,1"
|
|
group.byte 0x2A++0x1
|
|
line.byte 0x0 "BGCR_E_MMC_MODE,Block Gap Control Register"
|
|
bitfld.byte 0x0 1. "CONTR,Continue Request" "0,1"
|
|
bitfld.byte 0x0 0. "STPBGR,Stop At Block Gap Request" "0,1"
|
|
line.byte 0x1 "WCR,Wakeup Control Register"
|
|
bitfld.byte 0x1 2. "WKENCREM,Wakeup Event Enable on Card Removal" "0: Wakeup Event disabled.,1: Wakeup Event enabled."
|
|
bitfld.byte 0x1 1. "WKENCINS,Wakeup Event Enable on Card Insertion" "0: Wakeup Event disabled.,1: Wakeup Event enabled."
|
|
newline
|
|
bitfld.byte 0x1 0. "WKENCINT,Wakeup Event Enable on Card Interrupt" "0: Wakeup Event disabled.,1: Wakeup Event enabled."
|
|
group.word 0x2C++0x1
|
|
line.word 0x0 "CCR,Clock Control Register"
|
|
hexmask.word.byte 0x0 8.--15. 1. "SDCLKFSEL,SDCLK Frequency Select"
|
|
bitfld.word 0x0 6.--7. "USDCLKFSEL,Upper Bits of SDCLK Frequency Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 5. "CLKGSEL,Clock Generator Select" "0,1"
|
|
bitfld.word 0x0 2. "SDCLKEN,SD Clock Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "INTCLKS,Internal Clock Stable" "0,1"
|
|
bitfld.word 0x0 0. "INTCLKEN,Internal Clock Enable" "0,1"
|
|
group.byte 0x2E++0x1
|
|
line.byte 0x0 "TCR,Timeout Control Register"
|
|
hexmask.byte 0x0 0.--3. 1. "DTCVAL,Data Timeout Counter Value"
|
|
line.byte 0x1 "SRR,Software Reset Register"
|
|
bitfld.byte 0x1 2. "SWRSTDAT,Software reset for DAT line" "0,1"
|
|
bitfld.byte 0x1 1. "SWRSTCMD,Software reset for CMD line" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 0. "SWRSTALL,Software reset for All" "0,1"
|
|
group.word 0x30++0x1
|
|
line.word 0x0 "NISTR_SD_SDIO_MODE,Normal Interrupt Status Register"
|
|
bitfld.word 0x0 15. "ERRINT,Error Interrupt" "0,1"
|
|
bitfld.word 0x0 8. "CINT,Card Interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "CREM,Card Removal" "0,1"
|
|
bitfld.word 0x0 6. "CINS,Card Insertion" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready" "0,1"
|
|
bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "DMAINT,DMA Interrupt" "0,1"
|
|
bitfld.word 0x0 2. "BLKGE,Block Gap Event" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "TRFC,Transfer Complete" "0,1"
|
|
bitfld.word 0x0 0. "CMDC,Command Complete" "0,1"
|
|
group.word 0x30++0x3
|
|
line.word 0x0 "NISTR_E_MMC_MODE,Normal Interrupt Status Register"
|
|
bitfld.word 0x0 15. "ERRINT,Error Interrupt" "0,1"
|
|
bitfld.word 0x0 14. "BOOTAR,Boot Acknowledge Received" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready" "0,1"
|
|
bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "DMAINT,DMA Interrupt" "0,1"
|
|
bitfld.word 0x0 2. "BLKGE,Block Gap Event" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "TRFC,Transfer Complete" "0,1"
|
|
bitfld.word 0x0 0. "CMDC,Command Complete" "0,1"
|
|
line.word 0x2 "EISTR_SD_SDIO_MODE,Error Interrupt Status Register"
|
|
bitfld.word 0x2 9. "ADMA,ADMA Error" "0,1"
|
|
bitfld.word 0x2 8. "ACMD,Auto CMD Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 7. "CURLIM,Current Limit Error" "0,1"
|
|
bitfld.word 0x2 6. "DATEND,Data End Bit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 5. "DATCRC,Data CRC error" "0,1"
|
|
bitfld.word 0x2 4. "DATTEO,Data Timeout Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 3. "CMDIDX,Command Index Error" "0,1"
|
|
bitfld.word 0x2 2. "CMDEND,Command End Bit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "CMDCRC,Command CRC Error" "0,1"
|
|
bitfld.word 0x2 0. "CMDTEO,Command Timeout Error" "0,1"
|
|
group.word 0x32++0x3
|
|
line.word 0x0 "EISTR_E_MMC_MODE,Error Interrupt Status Register"
|
|
bitfld.word 0x0 12. "BOOTAE,Boot Acknowledge Error" "0,1"
|
|
bitfld.word 0x0 9. "ADMA,ADMA Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 8. "ACMD,Auto CMD Error" "0,1"
|
|
bitfld.word 0x0 7. "CURLIM,Current Limit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "DATEND,Data End Bit Error" "0,1"
|
|
bitfld.word 0x0 5. "DATCRC,Data CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "DATTEO,Data Timeout error" "0,1"
|
|
bitfld.word 0x0 3. "CMDIDX,Command Index Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "CMDEND,Command End Bit Error" "0,1"
|
|
bitfld.word 0x0 1. "CMDCRC,Command CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "CMDTEO,Command Timeout Error" "0,1"
|
|
line.word 0x2 "NISTER_SD_SDIO_MODE,Normal Interrupt Status Enable Register"
|
|
bitfld.word 0x2 8. "CINT,Card Interrupt Status Enable" "0: The CINT status flag in SDMMC_NISTR is masked.,1: The CINT status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x2 7. "CREM,Card Removal Status Enable" "0: The CREM status flag in SDMMC_NISTR is masked.,1: The CREM status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 6. "CINS,Card Insertion Status Enable" "0: The CINS status flag in SDMMC_NISTR is masked.,1: The CINS status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x2 5. "BRDRDY,Buffer Read Ready Status Enable" "0: The BRDRDY status flag in SDMMC_NISTR is masked.,1: The BRDRDY status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 4. "BWRRDY,Buffer Write Ready Status Enable" "0: The BWRRDY status flag in SDMMC_NISTR is masked.,1: The BWRRDY status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x2 3. "DMAINT,DMA Interrupt Status Enable" "0: The DMAINT status flag in SDMMC_NISTR is masked.,1: The DMAINT status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 2. "BLKGE,Block Gap Event Status Enable" "0: The BLKGE status flag in SDMMC_NISTR is masked.,1: The BLKGE status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x2 1. "TRFC,Transfer Complete Status Enable" "0: The TRFC status flag in SDMMC_NISTR is masked.,1: The TRFC status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 0. "CMDC,Command Complete Status Enable" "0: The CMDC status flag in SDMMC_NISTR is masked.,1: The CMDC status flag in SDMMC_NISTR is enabled."
|
|
group.word 0x34++0x3
|
|
line.word 0x0 "NISTER_E_MMC_MODE,Normal Interrupt Status Enable Register"
|
|
bitfld.word 0x0 14. "BOOTAR,Boot Acknowledge Received Status Enable" "0: The BOOTAR status flag in SDMMC_NISTR is masked.,1: The BOOTAR status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready Status Enable" "0: The BRDRDY status flag in SDMMC_NISTR is masked.,1: The BRDRDY status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready Status Enable" "0: The BWRRDY status flag in SDMMC_NISTR is masked.,1: The BWRRDY status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x0 3. "DMAINT,DMA Interrupt Status Enable" "0: The DMAINT status flag in SDMMC_NISTR is masked.,1: The DMAINT status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 2. "BLKGE,Block Gap Event Status Enable" "0: The BLKGE status flag in SDMMC_NISTR is masked.,1: The BLKGE status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x0 1. "TRFC,Transfer Complete Status Enable" "0: The TRFC status flag in SDMMC_NISTR is masked.,1: The TRFC status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 0. "CMDC,Command Complete Status Enable" "0: The CMDC status flag in SDMMC_NISTR is masked.,1: The CMDC status flag in SDMMC_NISTR is enabled."
|
|
line.word 0x2 "EISTER_SD_SDIO_MODE,Error Interrupt Status Enable Register"
|
|
bitfld.word 0x2 9. "ADMA,ADMA Error Status Enable" "0: The ADMA status flag in SDMMC_EISTR is masked.,1: The ADMA status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 8. "ACMD,Auto CMD Error Status Enable" "0: The ACMD status flag in SDMMC_EISTR is masked.,1: The ACMD status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 7. "CURLIM,Current Limit Error Status Enable" "0: The CURLIM status flag in SDMMC_EISTR is masked.,1: The CURLIM status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 6. "DATEND,Data End Bit Error Status Enable" "0: The DATEND status flag in SDMMC_EISTR is masked.,1: The DATEND status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 5. "DATCRC,Data CRC Error Status Enable" "0: The DATCRC status flag in SDMMC_EISTR is masked.,1: The DATCRC status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 4. "DATTEO,Data Timeout Error Status Enable" "0: The DATTEO status flag in SDMMC_EISTR is masked.,1: The DATTEO status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 3. "CMDIDX,Command Index Error Status Enable" "0: The CMDIDX status flag in SDMMC_EISTR is masked.,1: The CMDIDX status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 2. "CMDEND,Command End Bit Error Status Enable" "0: The CMDEND status flag in SDMMC_EISTR is masked.,1: The CMDEND status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 1. "CMDCRC,Command CRC Error Status Enable" "0: The CMDCRC status flag in SDMMC_EISTR is masked.,1: The CMDCRC status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 0. "CMDTEO,Command Timeout Error Status Enable" "0: The CMDTEO status flag in SDMMC_EISTR is masked.,1: The CMDTEO status flag in SDMMC_EISTR is enabled."
|
|
group.word 0x36++0x3
|
|
line.word 0x0 "EISTER_E_MMC_MODE,Error Interrupt Status Enable Register"
|
|
bitfld.word 0x0 12. "BOOTAE,Boot Acknowledge Error Status Enable" "0: The BOOTAE status flag in SDMMC_EISTR is masked.,1: The BOOTAE status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x0 9. "ADMA,ADMA Error Status Enable" "0: The ADMA status flag in SDMMC_EISTR is masked.,1: The ADMA status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 8. "ACMD,Auto CMD Error Status Enable" "0: The ACMD status flag in SDMMC_EISTR is masked.,1: The ACMD status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x0 7. "CURLIM,Current Limit Error Status Enable" "0: The CURLIM status flag in SDMMC_EISTR is masked.,1: The CURLIM status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 6. "DATEND,Data End Bit Error Status Enable" "0: The DATEND status flag in SDMMC_EISTR is masked.,1: The DATEND status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x0 5. "DATCRC,Data CRC Error Status Enable" "0: The DATCRC status flag in SDMMC_EISTR is masked.,1: The DATCRC status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 4. "DATTEO,Data Timeout Error Status Enable" "0: The DATTEO status flag in SDMMC_EISTR is masked.,1: The DATTEO status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x0 3. "CMDIDX,Command Index Error Status Enable" "0: The CMDIDX status flag in SDMMC_EISTR is masked.,1: The CMDIDX status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 2. "CMDEND,Command End Bit Error Status Enable" "0: The CMDEND status flag in SDMMC_EISTR is masked.,1: The CMDEND status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x0 1. "CMDCRC,Command CRC Error Status Enable" "0: The CMDCRC status flag in SDMMC_EISTR is masked.,1: The CMDCRC status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 0. "CMDTEO,Command Timeout Error Status Enable" "0: The CMDTEO status flag in SDMMC_EISTR is masked.,1: The CMDTEO status flag in SDMMC_EISTR is enabled."
|
|
line.word 0x2 "NISIER_SD_SDIO_MODE,Normal Interrupt Signal Enable Register"
|
|
bitfld.word 0x2 8. "CINT,Card Interrupt Signal Enable" "0: No interrupt is generated when the CINT status..,1: An interrupt is generated when the CINT status.."
|
|
bitfld.word 0x2 7. "CREM,Card Removal Signal Enable" "0: No interrupt is generated when the CREM status..,1: An interrupt is generated when the CREM status.."
|
|
newline
|
|
bitfld.word 0x2 6. "CINS,Card Insertion Signal Enable" "0: No interrupt is generated when the CINS status..,1: An interrupt is generated when the CINS status.."
|
|
bitfld.word 0x2 5. "BRDRDY,Buffer Read Ready Signal Enable" "0: No interrupt is generated when the BRDRDY status..,1: An interrupt is generated when the BRDRDY status.."
|
|
newline
|
|
bitfld.word 0x2 4. "BWRRDY,Buffer Write Ready Signal Enable" "0: No interrupt is generated when the BWRRDY status..,1: An interrupt is generated when the BWRRDY status.."
|
|
bitfld.word 0x2 3. "DMAINT,DMA Interrupt Signal Enable" "0: No interrupt is generated when the DMAINT status..,1: An interrupt is generated when the DMAINT status.."
|
|
newline
|
|
bitfld.word 0x2 2. "BLKGE,Block Gap Event Signal Enable" "0: No interrupt is generated when the BLKGE status..,1: An interrupt is generated when the BLKGE status.."
|
|
bitfld.word 0x2 1. "TRFC,Transfer Complete Signal Enable" "0: No interrupt is generated when the TRFC status..,1: An interrupt is generated when the TRFC status.."
|
|
newline
|
|
bitfld.word 0x2 0. "CMDC,Command Complete Signal Enable" "0: No interrupt is generated when the CMDC status..,1: An interrupt is generated when the CMDC status.."
|
|
group.word 0x38++0x3
|
|
line.word 0x0 "NISIER_E_MMC_MODE,Normal Interrupt Signal Enable Register"
|
|
bitfld.word 0x0 14. "BOOTAR,Boot Acknowledge Received Signal Enable" "0: No interrupt is generated when the BOOTAR status..,1: An interrupt is generated when the BOOTAR status.."
|
|
bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready Signal Enable" "0: No interrupt is generated when the BRDRDY status..,1: An interrupt is generated when the BRDRDY status.."
|
|
newline
|
|
bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready Signal Enable" "0: No interrupt is generated when the BWRRDY status..,1: An interrupt is generated when the BWRRDY status.."
|
|
bitfld.word 0x0 3. "DMAINT,DMA Interrupt Signal Enable" "0: No interrupt is generated when the DMAINT status..,1: An interrupt is generated when the DMAINT status.."
|
|
newline
|
|
bitfld.word 0x0 2. "BLKGE,Block Gap Event Signal Enable" "0: No interrupt is generated when the BLKGE status..,1: An interrupt is generated when the BLKGE status.."
|
|
bitfld.word 0x0 1. "TRFC,Transfer Complete Signal Enable" "0: No interrupt is generated when the TRFC status..,1: An interrupt is generated when the TRFC status.."
|
|
newline
|
|
bitfld.word 0x0 0. "CMDC,Command Complete Signal Enable" "0: No interrupt is generated when the CMDC status..,1: An interrupt is generated when the CMDC status.."
|
|
line.word 0x2 "EISIER_SD_SDIO_MODE,Error Interrupt Signal Enable Register"
|
|
bitfld.word 0x2 9. "ADMA,ADMA Error Signal Enable" "0: No interrupt is generated when the ADMA status..,1: An interrupt is generated when the ADMA status.."
|
|
bitfld.word 0x2 8. "ACMD,Auto CMD Error Signal Enable" "0: No interrupt is generated when the ACMD status..,1: An interrupt is generated when the ACMD status.."
|
|
newline
|
|
bitfld.word 0x2 7. "CURLIM,Current Limit Error Signal Enable" "0: No interrupt is generated when the CURLIM status..,1: An interrupt is generated when the CURLIM status.."
|
|
bitfld.word 0x2 6. "DATEND,Data End Bit Error Signal Enable" "0: No interrupt is generated when the DATEND status..,1: An interrupt is generated when the DATEND status.."
|
|
newline
|
|
bitfld.word 0x2 5. "DATCRC,Data CRC Error Signal Enable" "0: No interrupt is generated when the DATCRC status..,1: An interrupt is generated when the DATCRC status.."
|
|
bitfld.word 0x2 4. "DATTEO,Data Timeout Error Signal Enable" "0: No interrupt is generated when the DATTEO status..,1: An interrupt is generated when the DATTEO status.."
|
|
newline
|
|
bitfld.word 0x2 3. "CMDIDX,Command Index Error Signal Enable" "0: No interrupt is generated when the CMDIDX status..,1: An interrupt is generated when the CMDIDX status.."
|
|
bitfld.word 0x2 2. "CMDEND,Command End Bit Error Signal Enable" "0: No interrupt is generated when the CMDEND status..,1: An interrupt is generated when the CMDEND status.."
|
|
newline
|
|
bitfld.word 0x2 1. "CMDCRC,Command CRC Error Signal Enable" "0: No interrupt is generated when the CDMCRC status..,1: An interrupt is generated when the CMDCRC status.."
|
|
bitfld.word 0x2 0. "CMDTEO,Command Timeout Error Signal Enable" "0: No interrupt is generated when the CMDTEO status..,1: An interrupt is generated when the CMDTEO status.."
|
|
group.word 0x3A++0x1
|
|
line.word 0x0 "EISIER_E_MMC_MODE,Error Interrupt Signal Enable Register"
|
|
bitfld.word 0x0 12. "BOOTAE,Boot Acknowledge Error Signal Enable" "0: No interrupt is generated when the BOOTAE status..,1: An interrupt is generated when the BOOTAE status.."
|
|
bitfld.word 0x0 9. "ADMA,ADMA Error Signal Enable" "0: No interrupt is generated when the ADMA status..,1: An interrupt is generated when the ADMA status.."
|
|
newline
|
|
bitfld.word 0x0 8. "ACMD,Auto CMD Error Signal Enable" "0: No interrupt is generated when the ACMD status..,1: An interrupt is generated when the ACMD status.."
|
|
bitfld.word 0x0 7. "CURLIM,Current Limit Error Signal Enable" "0: No interrupt is generated when the CURLIM status..,1: An interrupt is generated when the CURLIM status.."
|
|
newline
|
|
bitfld.word 0x0 6. "DATEND,Data End Bit Error Signal Enable" "0: No interrupt is generated when the DATEND status..,1: An interrupt is generated when the DATEND status.."
|
|
bitfld.word 0x0 5. "DATCRC,Data CRC Error Signal Enable" "0: No interrupt is generated when the DATCRC status..,1: An interrupt is generated when the DATCRC status.."
|
|
newline
|
|
bitfld.word 0x0 4. "DATTEO,Data Timeout Error Signal Enable" "0: No interrupt is generated when the DATTEO status..,1: An interrupt is generated when the DATTEO status.."
|
|
bitfld.word 0x0 3. "CMDIDX,Command Index Error Signal Enable" "0: No interrupt is generated when the CMDIDX status..,1: An interrupt is generated when the CMDIDX status.."
|
|
newline
|
|
bitfld.word 0x0 2. "CMDEND,Command End Bit Error Signal Enable" "0: No interrupt is generated when the CMDEND status..,1: An interrupt is generated when the CMDEND status.."
|
|
bitfld.word 0x0 1. "CMDCRC,Command CRC Error Signal Enable" "0: No interrupt is generated when the CDMCRC status..,1: An interrupt is generated when the CMDCRC status.."
|
|
newline
|
|
bitfld.word 0x0 0. "CMDTEO,Command Timeout Error Signal Enable" "0: No interrupt is generated when the CMDTEO status..,1: An interrupt is generated when the CMDTEO status.."
|
|
rgroup.word 0x3C++0x1
|
|
line.word 0x0 "ACESR,Auto CMD Error Status Register"
|
|
bitfld.word 0x0 7. "CMDNI,Command Not Issued by Auto CMD12 Error" "0,1"
|
|
bitfld.word 0x0 4. "ACMDIDX,Auto CMD Index Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "ACMDEND,Auto CMD End Bit Error" "0,1"
|
|
bitfld.word 0x0 2. "ACMDCRC,Auto CMD CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "ACMDTEO,Auto CMD Timeout Error" "0,1"
|
|
bitfld.word 0x0 0. "ACMD12NE,Auto CMD12 Not Executed" "0,1"
|
|
group.word 0x3E++0x1
|
|
line.word 0x0 "HC2R_SD_SDIO_MODE,Host Control 2 Register"
|
|
bitfld.word 0x0 15. "PVALEN,Preset Value Enable" "0,1"
|
|
bitfld.word 0x0 14. "ASINTEN,Asynchronous Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "SCLKSEL,Sampling Clock Select" "0,1"
|
|
bitfld.word 0x0 6. "EXTUN,Execute Tuning" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4.--5. "DRVSEL,Driver Strength Select" "0: Driver Type B is selected (Default),1: Driver Type A is selected,2: Driver Type C is selected,3: Driver Type D is selected"
|
|
bitfld.word 0x0 3. "VS18EN,1.8V Signaling Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0.--2. "UHSMS,UHS Mode Select" "0: UHS SDR12 Mode,1: UHS SDR25 Mode,2: UHS SDR50 Mode,3: UHS SDR104 Mode,4: UHS DDR50 Mode,?,?,?"
|
|
group.word 0x3E++0x1
|
|
line.word 0x0 "HC2R_E_MMC_MODE,Host Control 2 Register"
|
|
bitfld.word 0x0 15. "PVALEN,Preset Value Enable" "0,1"
|
|
bitfld.word 0x0 7. "SCLKSEL,Sampling Clock Select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "EXTUN,Execute Tuning" "0,1"
|
|
bitfld.word 0x0 4.--5. "DRVSEL,Driver Strength Select" "0: Driver Type B is selected (Default),1: Driver Type A is selected,2: Driver Type C is selected,3: Driver Type D is selected"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--3. 1. "HS200EN,HS200 Mode Enable"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "CA0R,Capabilities 0 Register"
|
|
bitfld.long 0x0 30.--31. "SLTYPE,Slot Type" "0,1,2,3"
|
|
bitfld.long 0x0 29. "ASINTSUP,Asynchronous Interrupt Support" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "SB64SUP,64-Bit System Bus Support" "0,1"
|
|
bitfld.long 0x0 26. "V18VSUP,Voltage Support 1.8V" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "V30VSUP,Voltage Support 3.0V" "0,1"
|
|
bitfld.long 0x0 24. "V33VSUP,Voltage Support 3.3V" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "SRSUP,Suspend/Resume Support" "0,1"
|
|
bitfld.long 0x0 22. "SDMASUP,SDMA Support" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "HSSUP,High Speed Support" "0,1"
|
|
bitfld.long 0x0 19. "ADMA2SUP,ADMA2 Support" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "ED8SUP,8-Bit Support for Embedded Device" "0,1"
|
|
bitfld.long 0x0 16.--17. "MAXBLKL,Max Block Length" "0: 512 bytes,1: 1024 bytes,2: 2048 bytes,?"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "BASECLKF,Base Clock Frequency"
|
|
bitfld.long 0x0 7. "TEOCLKU,Timeout Clock Unit" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TEOCLKF,Timeout Clock Frequency"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "CA1R,Capabilities 1 Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CLKMULT,Clock Multiplier"
|
|
bitfld.long 0x0 14.--15. "RTMOD,Retuning Modes" "0: Timer,1: Timer and Retuning Request,2: Auto Retuning (for transfer) Timer and Retuning..,?"
|
|
newline
|
|
bitfld.long 0x0 13. "TSDR50,Use Tuning for SDR50" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TCNTRT,Timer Count For Retuning"
|
|
newline
|
|
bitfld.long 0x0 6. "DRVDSUP,Driver Type D Support" "0,1"
|
|
bitfld.long 0x0 5. "DRVCSUP,Driver Type C Support" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "DRVASUP,Driver Type A Support" "0,1"
|
|
bitfld.long 0x0 2. "DDR50SUP,DDR50 Support" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SDR104SUP,SDR104 Support" "0,1"
|
|
bitfld.long 0x0 0. "SDR50SUP,SDR50 Support" "0,1"
|
|
line.long 0x4 "MCCAR,Maximum Current Capabilities Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "MAXCUR18V,Maximum Current for 1.8V"
|
|
hexmask.long.byte 0x4 8.--15. 1. "MAXCUR30V,Maximum Current for 3.0V"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "MAXCUR33V,Maximum Current for 3.3V"
|
|
wgroup.word 0x50++0x3
|
|
line.word 0x0 "FERACES,Force Event Register for Auto CMD Error Status"
|
|
bitfld.word 0x0 7. "CMDNI,Force Event for Command Not Issued by Auto CMD12 Error" "0,1"
|
|
bitfld.word 0x0 4. "ACMDIDX,Force Event for Auto CMD Index Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "ACMDEND,Force Event for Auto CMD End Bit Error" "0,1"
|
|
bitfld.word 0x0 2. "ACMDCRC,Force Event for Auto CMD CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "ACMDTEO,Force Event for Auto CMD Timeout Error" "0,1"
|
|
bitfld.word 0x0 0. "ACMD12NE,Force Event for Auto CMD12 Not Executed" "0,1"
|
|
line.word 0x2 "FEREIS,Force Event Register for Error Interrupt Status"
|
|
bitfld.word 0x2 12. "BOOTAE,Force Event for Boot Acknowledge Error" "0,1"
|
|
bitfld.word 0x2 9. "ADMA,Force Event for ADMA Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 8. "ACMD,Force Event for Auto CMD Error" "0,1"
|
|
bitfld.word 0x2 7. "CURLIM,Force Event for Current Limit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 6. "DATEND,Force Event for Data End Bit Error" "0,1"
|
|
bitfld.word 0x2 5. "DATCRC,Force Event for Data CRC error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 4. "DATTEO,Force Event for Data Timeout error" "0,1"
|
|
bitfld.word 0x2 3. "CMDIDX,Force Event for Command Index Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 2. "CMDEND,Force Event for Command End Bit Error" "0,1"
|
|
bitfld.word 0x2 1. "CMDCRC,Force Event for Command CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 0. "CMDTEO,Force Event for Command Timeout Error" "0,1"
|
|
rgroup.byte 0x54++0x0
|
|
line.byte 0x0 "AESR,ADMA Error Status Register"
|
|
bitfld.byte 0x0 2. "LMIS,ADMA Length Mismatch Error" "0,1"
|
|
bitfld.byte 0x0 0.--1. "ERRST,ADMA Error State" "0,1,2,3"
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "ASAR0,ADMA System Address Register 0"
|
|
hexmask.long 0x0 0.--31. 1. "ADMASA,ADMA System Address"
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x60)++0x1
|
|
line.word 0x0 "PVR[$1],Preset Value Register 0 (for initialization)"
|
|
bitfld.word 0x0 14.--15. "DRVSEL,Driver Strength Select" "0,1,2,3"
|
|
bitfld.word 0x0 10. "CLKGSEL,Clock Generator Select" "0,1"
|
|
newline
|
|
hexmask.word 0x0 0.--9. 1. "SDCLKFSEL,SDCLK Frequency Select"
|
|
repeat.end
|
|
rgroup.word 0xFC++0x3
|
|
line.word 0x0 "SISR,Slot Interrupt Status Register"
|
|
bitfld.word 0x0 0.--1. "INTSSL,Interrupt Signal for Each Slot" "0,1,2,3"
|
|
line.word 0x2 "HCVR,Host Controller Version Register"
|
|
hexmask.word.byte 0x2 8.--15. 1. "VVER,Vendor Version Number"
|
|
hexmask.word.byte 0x2 0.--7. 1. "SVER,Specification Version Number"
|
|
rgroup.long 0x200++0x3
|
|
line.long 0x0 "APSR,Additional Present State Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "HDATLL,DAT[7:4] High Line Level"
|
|
group.byte 0x204++0x0
|
|
line.byte 0x0 "MC1R,e.MMC Control 1 Register"
|
|
bitfld.byte 0x0 7. "FCD,e.MMC Force Card Detect" "0,1"
|
|
bitfld.byte 0x0 6. "RSTN,e.MMC Reset Signal" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 5. "BOOTA,e.MMC Boot Acknowledge Enable" "0,1"
|
|
bitfld.byte 0x0 4. "OPD,e.MMC Open Drain Mode" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "DDR,e.MMC HSDDR Mode" "0,1"
|
|
bitfld.byte 0x0 0.--1. "CMDTYP,e.MMC Command Type" "0: The command is not an e.MMC specific command.,1: This bit must be set to 1 when the e.MMC is in..,2: This bit must be set to 1 in the case of Stream..,3: Starts a Boot Operation mode at the next write.."
|
|
wgroup.byte 0x205++0x0
|
|
line.byte 0x0 "MC2R,e.MMC Control 2 Register"
|
|
bitfld.byte 0x0 1. "ABOOT,e.MMC Abort Boot" "0,1"
|
|
bitfld.byte 0x0 0. "SRESP,e.MMC Abort Wait IRQ" "0,1"
|
|
group.long 0x208++0x7
|
|
line.long 0x0 "ACR,AHB Control Register"
|
|
bitfld.long 0x0 0.--1. "BMAX,AHB Maximum Burst" "0: The maximum burst size is INCR16.,1: The maximum burst size is INCR8.,2: The maximum burst size is INCR4.,3: Only SINGLE transfers are performed."
|
|
line.long 0x4 "CC2R,Clock Control 2 Register"
|
|
bitfld.long 0x4 0. "FSDCLKD,Force SDCLK Disabled" "0,1"
|
|
group.byte 0x210++0x0
|
|
line.byte 0x0 "RTC1R,Retuning Timer Control 1 Register"
|
|
bitfld.byte 0x0 0. "TMREN,Retuning Timer Enable" "0: The retuning timer is disabled.,1: The retuning timer is enabled."
|
|
wgroup.byte 0x211++0x0
|
|
line.byte 0x0 "RTC2R,Retuning Timer Control 2 Register"
|
|
bitfld.byte 0x0 0. "RLD,Retuning Timer Reload" "0,1"
|
|
group.long 0x214++0x3
|
|
line.long 0x0 "RTCVR,Retuning Timer Counter Value Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TCVAL,Retuning Timer Counter Value"
|
|
group.byte 0x218++0x1
|
|
line.byte 0x0 "RTISTER,Retuning Timer Interrupt Status Enable Register"
|
|
bitfld.byte 0x0 0. "TEVT,Retuning Timer Event" "0: The TEVT status flag in SDMMC_RTISTR is masked.,1: The TEVT status flag in SDMMC_RTISTR is enabled."
|
|
line.byte 0x1 "RTISIER,Retuning Timer Interrupt Signal Enable Register"
|
|
bitfld.byte 0x1 0. "TEVT,Retuning Timer Event" "0: No interrupt is generated when the TEVT status..,1: An interrupt is generated when the TEVT status.."
|
|
group.byte 0x21C++0x0
|
|
line.byte 0x0 "RTISTR,Retuning Timer Interrupt Status Register"
|
|
bitfld.byte 0x0 0. "TEVT,Retuning Timer Event" "0,1"
|
|
rgroup.byte 0x21D++0x0
|
|
line.byte 0x0 "RTSSR,Retuning Timer Status Slots Register"
|
|
bitfld.byte 0x0 0.--1. "TEVTSLOT,Retuning Timer Event Slots" "0,1,2,3"
|
|
group.long 0x220++0x3
|
|
line.long 0x0 "TUNCR,Tuning Control Register"
|
|
bitfld.long 0x0 0. "SMPLPT,Sampling Point" "0,1"
|
|
group.long 0x230++0x3
|
|
line.long 0x0 "CACR,Capabilities Control Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "KEY,Key"
|
|
bitfld.long 0x0 0. "CAPWREN,Capabilities Write Enable" "0,1"
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "CALCR,Calibration Control Register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "CALP,Calibration P Status"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CALN,Calibration N Status"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CNTVAL,Calibration Counter Value"
|
|
bitfld.long 0x0 5. "TUNDIS,Calibration During Tuning Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ALWYSON,Calibration Analog Always ON" "0,1"
|
|
bitfld.long 0x0 0. "EN,PADs Calibration Enable" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "SECUMOD (Security Module)"
|
|
base ad:0xFC040000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Password"
|
|
bitfld.long 0x0 9.--10. "SCRAMB,Memory Scrambling Enable" "0,1,2,3"
|
|
bitfld.long 0x0 2. "SWPROT,Software Protection" "0,1"
|
|
bitfld.long 0x0 1. "NORMAL,Normal Mode" "0,1"
|
|
bitfld.long 0x0 0. "BACKUP,Backup Mode" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "SYSR,System Status Register"
|
|
bitfld.long 0x0 7. "SCRAMB,Scrambling Enabled (RO)" "0,1"
|
|
bitfld.long 0x0 6. "AUTOBKP,Automatic Backup Mode Enabled (RO)" "0,1"
|
|
bitfld.long 0x0 3. "SWKUP,SWKUP State (RO)" "0,1"
|
|
bitfld.long 0x0 2. "BACKUP,Backup Mode (RO)" "0,1"
|
|
bitfld.long 0x0 1. "ERASE_ON,Erase Process Ongoing (RO)" "0,1"
|
|
bitfld.long 0x0 0. "ERASE_DONE,Erasable Memories State (RW)" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 23. "DET7,PIOBU Intrusion Detector" "0,1"
|
|
bitfld.long 0x0 22. "DET6,PIOBU Intrusion Detector" "0,1"
|
|
bitfld.long 0x0 21. "DET5,PIOBU Intrusion Detector" "0,1"
|
|
bitfld.long 0x0 20. "DET4,PIOBU Intrusion Detector" "0,1"
|
|
bitfld.long 0x0 19. "DET3,PIOBU Intrusion Detector" "0,1"
|
|
bitfld.long 0x0 18. "DET2,PIOBU Intrusion Detector" "0,1"
|
|
bitfld.long 0x0 17. "DET1,PIOBU Intrusion Detector" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "DET0,PIOBU Intrusion Detector" "0,1"
|
|
wgroup.long 0x10++0x3
|
|
line.long 0x0 "SCR,Status Clear Register"
|
|
bitfld.long 0x0 23. "DET7,PIOBU Intrusion Detector" "0,1"
|
|
bitfld.long 0x0 22. "DET6,PIOBU Intrusion Detector" "0,1"
|
|
bitfld.long 0x0 21. "DET5,PIOBU Intrusion Detector" "0,1"
|
|
bitfld.long 0x0 20. "DET4,PIOBU Intrusion Detector" "0,1"
|
|
bitfld.long 0x0 19. "DET3,PIOBU Intrusion Detector" "0,1"
|
|
bitfld.long 0x0 18. "DET2,PIOBU Intrusion Detector" "0,1"
|
|
bitfld.long 0x0 17. "DET1,PIOBU Intrusion Detector" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "DET0,PIOBU Intrusion Detector" "0,1"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "RAMRDY,RAM Access Ready Register"
|
|
bitfld.long 0x0 0. "READY,Ready for system access flag" "0,1"
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x18)++0x3
|
|
line.long 0x0 "PIOBU[$1],PIO Backup Register"
|
|
bitfld.long 0x0 15. "SWITCH,Switch State for Intrusion Detection" "0,1"
|
|
bitfld.long 0x0 14. "SCHEDULE,Pull-up/Down Scheduled" "0,1"
|
|
bitfld.long 0x0 12.--13. "PULLUP,Programmable Pull-up State" "0,1,2,3"
|
|
bitfld.long 0x0 10. "PIO_PDS,Level on the Pin in Input Mode (OUTPUT = 0) (Read-only)" "0,1"
|
|
bitfld.long 0x0 9. "PIO_SOD,Set/Clear the I/O Line when configured in Output Mode (OUTPUT =1)" "0,1"
|
|
bitfld.long 0x0 8. "OUTPUT,Configure I/O Line in Input/Output" "0,1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PIOBU_RFV,PIOBUx Reset Filter Value"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "PIOBU_AFV,PIOBU Alarm Filter Value"
|
|
repeat.end
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "JTAGCR,JTAG Protection Control Register"
|
|
bitfld.long 0x0 4. "WZO,Write ZERO" "0,1"
|
|
bitfld.long 0x0 1.--3. "CA5_DEBUG_MODE,Cortex-A5 Invasive/Non-Invasive Secure/Non-Secure Debug Permissions" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0. "FNTRST,Force NTRST" "0,1"
|
|
group.long 0x70++0x13
|
|
line.long 0x0 "SCRKEY,Scrambling Key Register"
|
|
hexmask.long 0x0 0.--31. 1. "SCRKEY,Scrambling Key Value"
|
|
line.long 0x4 "RAMACC,RAM Access Rights Register"
|
|
bitfld.long 0x4 10.--11. "RW5,Access right for RAM region [5 Kbytes; 6 Kbytes] (register bank BUREG256b)" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "RW4,Access right for RAM region [4 Kbytes; 5 Kbytes]" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "RW3,Access right for RAM region [3 Kbytes; 4 Kbytes]" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "RW2,Access right for RAM region [2 Kbytes; 3 Kbytes]" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "RW1,Access right for RAM region [1 Kbyte; 2 Kbytes]" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "RW0,Access right for RAM region [0; 1 Kbyte]" "0,1,2,3"
|
|
line.long 0x8 "RAMACCSR,RAM Access Rights Status Register"
|
|
bitfld.long 0x8 10.--11. "RW5,Access right status for RAM region [5 Kbytes; 6 Kbytes] (register bank BUREG256b)" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "RW4,Access right status for RAM region [4 Kbytes; 5 Kbytes]" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "RW3,Access right status for RAM region [3 Kbytes; 4 Kbytes]" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "RW2,Access right status for RAM region [2 Kbytes; 3 Kbytes]" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "RW1,Access right status for RAM region [1 Kbytes; 2 Kbytes]" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "RW0,Access right status for RAM region [0; 1 Kbyte]" "0,1,2,3"
|
|
line.long 0xC "BMPR,Backup Mode Protection Register"
|
|
bitfld.long 0xC 23. "DET7,PIOBU Intrusion Detector Protection" "0,1"
|
|
bitfld.long 0xC 22. "DET6,PIOBU Intrusion Detector Protection" "0,1"
|
|
bitfld.long 0xC 21. "DET5,PIOBU Intrusion Detector Protection" "0,1"
|
|
bitfld.long 0xC 20. "DET4,PIOBU Intrusion Detector Protection" "0,1"
|
|
bitfld.long 0xC 19. "DET3,PIOBU Intrusion Detector Protection" "0,1"
|
|
bitfld.long 0xC 18. "DET2,PIOBU Intrusion Detector Protection" "0,1"
|
|
bitfld.long 0xC 17. "DET1,PIOBU Intrusion Detector Protection" "0,1"
|
|
newline
|
|
bitfld.long 0xC 16. "DET0,PIOBU Intrusion Detector Protection" "0,1"
|
|
line.long 0x10 "NMPR,Normal Mode Protection Register"
|
|
bitfld.long 0x10 23. "DET7,PIOBU Intrusion Detector Protection" "0,1"
|
|
bitfld.long 0x10 22. "DET6,PIOBU Intrusion Detector Protection" "0,1"
|
|
bitfld.long 0x10 21. "DET5,PIOBU Intrusion Detector Protection" "0,1"
|
|
bitfld.long 0x10 20. "DET4,PIOBU Intrusion Detector Protection" "0,1"
|
|
bitfld.long 0x10 19. "DET3,PIOBU Intrusion Detector Protection" "0,1"
|
|
bitfld.long 0x10 18. "DET2,PIOBU Intrusion Detector Protection" "0,1"
|
|
bitfld.long 0x10 17. "DET1,PIOBU Intrusion Detector Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x10 16. "DET0,PIOBU Intrusion Detector Protection" "0,1"
|
|
wgroup.long 0x84++0x7
|
|
line.long 0x0 "NIEPR,Normal Interrupt Enable Protection Register"
|
|
bitfld.long 0x0 23. "DET7,PIOBU Intrusion Detector Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 22. "DET6,PIOBU Intrusion Detector Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 21. "DET5,PIOBU Intrusion Detector Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 20. "DET4,PIOBU Intrusion Detector Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 19. "DET3,PIOBU Intrusion Detector Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 18. "DET2,PIOBU Intrusion Detector Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 17. "DET1,PIOBU Intrusion Detector Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "DET0,PIOBU Intrusion Detector Protection Interrupt Enable" "0,1"
|
|
line.long 0x4 "NIDPR,Normal Interrupt Disable Protection Register"
|
|
bitfld.long 0x4 23. "DET7,PIOBU Intrusion Detector Protection Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 22. "DET6,PIOBU Intrusion Detector Protection Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 21. "DET5,PIOBU Intrusion Detector Protection Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 20. "DET4,PIOBU Intrusion Detector Protection Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 19. "DET3,PIOBU Intrusion Detector Protection Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 18. "DET2,PIOBU Intrusion Detector Protection Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 17. "DET1,PIOBU Intrusion Detector Protection Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "DET0,PIOBU Intrusion Detector Protection Interrupt Disable" "0,1"
|
|
rgroup.long 0x8C++0x3
|
|
line.long 0x0 "NIMPR,Normal Interrupt Mask Protection Register"
|
|
bitfld.long 0x0 23. "DET7,PIOBU Intrusion Detector Protection Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 22. "DET6,PIOBU Intrusion Detector Protection Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 21. "DET5,PIOBU Intrusion Detector Protection Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 20. "DET4,PIOBU Intrusion Detector Protection Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 19. "DET3,PIOBU Intrusion Detector Protection Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 18. "DET2,PIOBU Intrusion Detector Protection Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 17. "DET1,PIOBU Intrusion Detector Protection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "DET0,PIOBU Intrusion Detector Protection Interrupt Mask" "0,1"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "WKPR,Wakeup Protection Register"
|
|
bitfld.long 0x0 23. "DET7,PIOBU Intrusion Detector Protection" "0,1"
|
|
bitfld.long 0x0 22. "DET6,PIOBU Intrusion Detector Protection" "0,1"
|
|
bitfld.long 0x0 21. "DET5,PIOBU Intrusion Detector Protection" "0,1"
|
|
bitfld.long 0x0 20. "DET4,PIOBU Intrusion Detector Protection" "0,1"
|
|
bitfld.long 0x0 19. "DET3,PIOBU Intrusion Detector Protection" "0,1"
|
|
bitfld.long 0x0 18. "DET2,PIOBU Intrusion Detector Protection" "0,1"
|
|
bitfld.long 0x0 17. "DET1,PIOBU Intrusion Detector Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "DET0,PIOBU Intrusion Detector Protection" "0,1"
|
|
tree.end
|
|
tree "SFC (Secure Fuse Controller)"
|
|
base ad:0xF804C000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "KR,SFC Key Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "KEY,Key Code"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,SFC Mode Register"
|
|
bitfld.long 0x0 4. "SASEL,Sense Amplifier Selection" "0,1"
|
|
bitfld.long 0x0 0. "MSK,Mask Data Registers" "0,1"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,SFC Interrupt Enable Register"
|
|
bitfld.long 0x0 17. "ACE,Area Check Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "LCHECK,Live Integrity Check Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "PGMF,Programming Sequence Failed Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "PGMC,Programming Sequence Completed Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,SFC Interrupt Disable Register"
|
|
bitfld.long 0x4 17. "ACE,Area Check Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "LCHECK,Live Integrity Check Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "PGMF,Programming Sequence Failed Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "PGMC,Programming Sequence Completed Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "IMR,SFC Interrupt Mask Register"
|
|
bitfld.long 0x0 17. "ACE,Area Check Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "LCHECK,Live Integrity Checking Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 1. "PGMF,Programming Sequence Failed Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "PGMC,Programming Sequence Completed Interrupt Mask" "0,1"
|
|
line.long 0x4 "SR,SFC Status Register"
|
|
bitfld.long 0x4 17. "ACE,Area Check Error (cleared on read)" "0,1"
|
|
bitfld.long 0x4 16. "APLE,Area Programming Lock Error (cleared on read)" "0,1"
|
|
bitfld.long 0x4 4. "LCHECK,Live Integrity Checking Error (cleared on read)" "0,1"
|
|
bitfld.long 0x4 1. "PGMF,Programming Sequence Failed (cleared on read)" "0,1"
|
|
bitfld.long 0x4 0. "PGMC,Programming Sequence Completed (cleared on read)" "0,1"
|
|
repeat 17. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "DR[$1],SFC Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Fuse Data"
|
|
repeat.end
|
|
tree.end
|
|
tree "SFR (Special Function Registers)"
|
|
base ad:0xF8030000
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "DDRCFG,DDR Configuration Register"
|
|
bitfld.long 0x0 17. "FDQSIEN,Force DDR_DQS Input Buffer Always On" "0,1"
|
|
bitfld.long 0x0 16. "FDQIEN,Force DDR_DQ Input Buffer Always On" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "OHCIICR,OHCI Interrupt Configuration Register"
|
|
bitfld.long 0x0 27. "HSIC_SEL," "0,1"
|
|
bitfld.long 0x0 23. "UDPPUDIS,USB DEVICE PULLUP DISABLE" "0,1"
|
|
bitfld.long 0x0 10. "SUSPEND_C,USB PORT C" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SUSPEND_B,USB PORT B" "0,1"
|
|
bitfld.long 0x0 8. "SUSPEND_A,USB PORT A" "0,1"
|
|
bitfld.long 0x0 5. "APPSTART," "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ARIE,OHCI Asynchronous Resume Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "RES2,USB PORTx RESET" "0,1"
|
|
bitfld.long 0x0 1. "RES1,USB PORTx RESET" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RES0,USB PORTx RESET" "0,1"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "OHCIISR,OHCI Interrupt Status Register"
|
|
bitfld.long 0x0 2. "RIS2,OHCI Resume Interrupt Status Port 2" "0,1"
|
|
bitfld.long 0x0 1. "RIS1,OHCI Resume Interrupt Status Port 1" "0,1"
|
|
bitfld.long 0x0 0. "RIS0,OHCI Resume Interrupt Status Port 0" "0,1"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "SECURE,Security Configuration Register"
|
|
bitfld.long 0x0 8. "FUSE,Disable Access to Fuse Controller" "0,1"
|
|
bitfld.long 0x0 0. "ROM,Disable Access to ROM Code" "0,1"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "UTMICKTRIM,UTMI Clock Trimming Register"
|
|
bitfld.long 0x0 16.--17. "VBG,UTMI Band Gap Voltage Trimming" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "FREQ,UTMI Reference Clock Frequency" "0: 12 MHz reference clock,1: 16 MHz reference clock,2: 24 MHz reference clock,?"
|
|
line.long 0x4 "UTMIHSTRIM,UTMI High-Speed Trimming Register"
|
|
bitfld.long 0x4 16.--18. "SLOPE2,UTMI HS PORTx Transceiver Slope Trimming" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12.--14. "SLOPE1,UTMI HS PORTx Transceiver Slope Trimming" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 8.--10. "SLOPE0,UTMI HS PORTx Transceiver Slope Trimming" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "DISC,UTMI Disconnect Voltage Trimming" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0.--2. "SQUELCH,UTMI HS SQUELCH Voltage Trimming" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "UTMIFSTRIM,UTMI Full-Speed Trimming Register"
|
|
bitfld.long 0x8 20.--22. "ZP,FS Transceiver PMOS Impedance Trimming" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 16.--18. "ZN,FS Transceiver NMOS Impedance Trimming" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 8.--9. "XCVR,FS Transceiver Crossover Voltage Trimming" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 4.--6. "FALL,FS Transceiver Output Falling Slope Trimming" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 0.--2. "RISE,FS Transceiver Output Rising Slope Trimming" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "UTMISWAP,UTMI DP/DM Pin Swapping Register"
|
|
bitfld.long 0xC 2. "PORT2,PORT 2 DP/DM Pin Swapping" "0: DP/DM normal pinout.,1: DP/DM swapped pinout."
|
|
bitfld.long 0xC 1. "PORT1,PORT 1 DP/DM Pin Swapping" "0: DP/DM normal pinout.,1: DP/DM swapped pinout."
|
|
bitfld.long 0xC 0. "PORT0,PORT 0 DP/DM Pin Swapping" "0: DP/DM normal pinout.,1: DP/DM swapped pinout."
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "CAN,CAN Memories Address-based Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "EXT_MEM_CAN1_ADDR,MSB CAN1 DMA Base Address"
|
|
hexmask.long.word 0x0 0.--15. 1. "EXT_MEM_CAN0_ADDR,MSB CAN0 DMA Base Address"
|
|
rgroup.long 0x4C++0x7
|
|
line.long 0x0 "SN0,Serial Number 0 Register"
|
|
hexmask.long 0x0 0.--31. 1. "SN0,Serial Number 0"
|
|
line.long 0x4 "SN1,Serial Number 1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "SN1,Serial Number 1"
|
|
group.long 0x54++0x7
|
|
line.long 0x0 "AICREDIR,AIC Interrupt Redirection Register"
|
|
hexmask.long 0x0 1.--31. 1. "AICREDIRKEY,Unlock Key"
|
|
bitfld.long 0x0 0. "NSAIC,Interrupt Redirection to Non-Secure AIC" "0,1"
|
|
line.long 0x4 "L2CC_HRAMC,L2CC_HRAMC1"
|
|
bitfld.long 0x4 0. "SRAM_SEL,SRAM Selector" "0,1"
|
|
group.long 0x90++0x7
|
|
line.long 0x0 "I2SCLKSEL,I2SC Register"
|
|
bitfld.long 0x0 1. "CLKSEL1,Clock Selection 1" "0,1"
|
|
bitfld.long 0x0 0. "CLKSEL0,Clock Selection 0" "0,1"
|
|
line.long 0x4 "QSPICLK_REG,QSPI Clock Pad Supply Select Register"
|
|
bitfld.long 0x4 0. "SUP_SEL,Supply Selection" "0,1"
|
|
tree.end
|
|
tree "SFRBU (Special Function Registers Backup)"
|
|
base ad:0xFC05C000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "PSWBUCTRL,Power Switch BU Control Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "KEYPSWMODE,"
|
|
bitfld.long 0x0 3. "STATE,Power Switch BU state (Read-only)" "0,1"
|
|
bitfld.long 0x0 2. "SMCTRL,Allow Power Switch BU Control by Security Module Autobackup (Hardware)" "0,1"
|
|
bitfld.long 0x0 1. "SSWCTRL,Power Switch BU Source Selection" "0,1"
|
|
bitfld.long 0x0 0. "SCTRL,Power Switch BU Software Control" "0,1"
|
|
line.long 0x4 "TSRANGECFG,TS Range Configuration Register"
|
|
bitfld.long 0x4 0. "TSHRSEL,Temperature Sensor Range Selection" "0,1"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "DDRBUMCR,DDR BU Mode Control Register"
|
|
bitfld.long 0x0 0. "BUMEN,DDR BU Mode Enable" "0,1"
|
|
line.long 0x4 "RXLPPUCR,RXLP Pull-Up Control Register"
|
|
bitfld.long 0x4 0. "RXDPUCTRL,RXLP RXD Pull-Up Control" "0,1"
|
|
tree.end
|
|
tree "SHA (Secure Hash Algorithm)"
|
|
base ad:0xF0028000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 13. "WUIEHV,Write User Initial or Expected Hash Values" "0,1"
|
|
bitfld.long 0x0 12. "WUIHV,Write User Initial Hash Values" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SWRST,Software Reset" "0,1"
|
|
bitfld.long 0x0 4. "FIRST,First Block of a Message" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Start Processing" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "CHKCNT,Check Counter"
|
|
bitfld.long 0x0 24.--25. "CHECK,Hash Check" "0: No check is performed,1: Check is performed with expected hash stored in..,2: Check is performed with expected hash provided..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "DUALBUFF,Dual Input Buffer" "0: SHA_IDATARx and SHA_IODATARx cannot be written..,1: SHA_IDATARx and SHA_IODATARx can be written.."
|
|
hexmask.long.byte 0x0 8.--11. 1. "ALGO,SHA Algorithm"
|
|
newline
|
|
bitfld.long 0x0 6. "UIEHV,User Initial or Expected Hash Value Registers" "0,1"
|
|
bitfld.long 0x0 5. "UIHV,User Initial Hash Value Registers" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PROCDLY,Processing Delay" "0: SHA processing runtime is the shortest one,1: SHA processing runtime is the longest one.."
|
|
bitfld.long 0x0 0.--1. "SMOD,Start Mode" "0: Manual mode,1: Auto mode,2: SHA_IDATAR0 access only mode (mandatory when DMA..,?"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 16. "CHECKF,Check Done Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "URAD,Unspecified Register Access Detection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 16. "CHECKF,Check Done Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "URAD,Unspecified Register Access Detection Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 16. "CHECKF,Check Done Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "URAD,Unspecified Register Access Detection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
hexmask.long.byte 0x4 20.--23. 1. "CHKST,Check Status (cleared by writing START or SWRST bits in SHA_CR or by reading SHA_IODATARx)"
|
|
bitfld.long 0x4 16. "CHECKF,Check Done Status (cleared by writing START or SWRST bits in SHA_CR or by reading SHA_IODATARx)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12.--14. "URAT,Unspecified Register Access Type (cleared by writing a 1 to SWRST bit in SHA_CR)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 8. "URAD,Unspecified Register Access Detection Status (cleared by writing a 1 to SWRST bit in SHA_CR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "WRDY,Input Data Register Write Ready" "0,1"
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready (cleared by writing a 1 to bit SWRST or START in SHA_CR or by reading SHA_IODATARx)" "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "MSR,Message Size Register"
|
|
hexmask.long 0x0 0.--31. 1. "MSGSIZE,Message Size"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "BCR,Bytes Count Register"
|
|
hexmask.long 0x0 0.--31. 1. "BYTCNT,Remaining Byte Count Before Auto Padding"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x40)++0x3
|
|
line.long 0x0 "IDATAR[$1],Input Data 0 Register"
|
|
hexmask.long 0x0 0.--31. 1. "IDATA,Input Data"
|
|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x80)++0x3
|
|
line.long 0x0 "IODATAR[$1],Input/Output Data 0 Register"
|
|
hexmask.long 0x0 0.--31. 1. "IODATA,Input/Output Data"
|
|
repeat.end
|
|
tree.end
|
|
tree "SHDWC (Shutdown Controller)"
|
|
base ad:0xF8048010
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "SHDW_CR,Shutdown Control Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "KEY,Password"
|
|
bitfld.long 0x0 0. "SHDW,Shutdown Command" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "SHDW_MR,Shutdown Mode Register"
|
|
bitfld.long 0x0 24.--26. "WKUPDBC,Wake-up Inputs Debouncer Period" "0: Immediate no debouncing detected active at least..,1: PIOBUx shall be in its active state for at least..,2: PIOBUx shall be in its active state for at least..,3: PIOBUx shall be in its active state for at least..,4: PIOBUx shall be in its active state for at least..,5: PIOBUx shall be in its active state for at least..,?,?"
|
|
bitfld.long 0x0 19. "RXLPWKEN,Debug Unit Wake-up Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "ACCWKEN,Analog Comparator Controller Wake-up Enable" "0,1"
|
|
bitfld.long 0x0 17. "RTCWKEN,Real-time Clock Wake-up Enable" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SHDW_SR,Shutdown Status Register"
|
|
bitfld.long 0x0 25. "WKUPIS9,Wake-up 9 Input Status" "0: The corresponding wake-up input is disabled or..,1: The corresponding wake-up input was active at.."
|
|
bitfld.long 0x0 24. "WKUPIS8,Wake-up 8 Input Status" "0: The corresponding wake-up input is disabled or..,1: The corresponding wake-up input was active at.."
|
|
newline
|
|
bitfld.long 0x0 23. "WKUPIS7,Wake-up 7 Input Status" "0: The corresponding wake-up input is disabled or..,1: The corresponding wake-up input was active at.."
|
|
bitfld.long 0x0 22. "WKUPIS6,Wake-up 6 Input Status" "0: The corresponding wake-up input is disabled or..,1: The corresponding wake-up input was active at.."
|
|
newline
|
|
bitfld.long 0x0 21. "WKUPIS5,Wake-up 5 Input Status" "0: The corresponding wake-up input is disabled or..,1: The corresponding wake-up input was active at.."
|
|
bitfld.long 0x0 20. "WKUPIS4,Wake-up 4 Input Status" "0: The corresponding wake-up input is disabled or..,1: The corresponding wake-up input was active at.."
|
|
newline
|
|
bitfld.long 0x0 19. "WKUPIS3,Wake-up 3 Input Status" "0: The corresponding wake-up input is disabled or..,1: The corresponding wake-up input was active at.."
|
|
bitfld.long 0x0 18. "WKUPIS2,Wake-up 2 Input Status" "0: The corresponding wake-up input is disabled or..,1: The corresponding wake-up input was active at.."
|
|
newline
|
|
bitfld.long 0x0 17. "WKUPIS1,Wake-up 1 Input Status" "0: The corresponding wake-up input is disabled or..,1: The corresponding wake-up input was active at.."
|
|
bitfld.long 0x0 16. "WKUPIS0,Wake-up 0 Input Status" "0: The corresponding wake-up input is disabled or..,1: The corresponding wake-up input was active at.."
|
|
newline
|
|
bitfld.long 0x0 7. "RXLPWK,Debug Unit Wake-up" "0,1"
|
|
bitfld.long 0x0 6. "ACCWK,Analog Comparator Controller Wake-up" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RTCWK," "0,1"
|
|
bitfld.long 0x0 0. "WKUPS,PIOBU WKUP Wake-up Status" "0: No wake-up due to the assertion of the PIOBU..,1: At least one wake-up due to the assertion of the.."
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "SHDW_WUIR,Shutdown Wake-up Inputs Register"
|
|
bitfld.long 0x0 25. "WKUPT9,Wake-up 9 Input Type" "0: A falling edge followed by a low level for a..,1: A rising edge followed by a high level for a.."
|
|
bitfld.long 0x0 24. "WKUPT8,Wake-up 8 Input Type" "0: A falling edge followed by a low level for a..,1: A rising edge followed by a high level for a.."
|
|
newline
|
|
bitfld.long 0x0 23. "WKUPT7,Wake-up 7 Input Type" "0: A falling edge followed by a low level for a..,1: A rising edge followed by a high level for a.."
|
|
bitfld.long 0x0 22. "WKUPT6,Wake-up 6 Input Type" "0: A falling edge followed by a low level for a..,1: A rising edge followed by a high level for a.."
|
|
newline
|
|
bitfld.long 0x0 21. "WKUPT5,Wake-up 5 Input Type" "0: A falling edge followed by a low level for a..,1: A rising edge followed by a high level for a.."
|
|
bitfld.long 0x0 20. "WKUPT4,Wake-up 4 Input Type" "0: A falling edge followed by a low level for a..,1: A rising edge followed by a high level for a.."
|
|
newline
|
|
bitfld.long 0x0 19. "WKUPT3,Wake-up 3 Input Type" "0: A falling edge followed by a low level for a..,1: A rising edge followed by a high level for a.."
|
|
bitfld.long 0x0 18. "WKUPT2,Wake-up 2 Input Type" "0: A falling edge followed by a low level for a..,1: A rising edge followed by a high level for a.."
|
|
newline
|
|
bitfld.long 0x0 17. "WKUPT1,Wake-up 1 Input Type" "0: A falling edge followed by a low level for a..,1: A rising edge followed by a high level for a.."
|
|
bitfld.long 0x0 16. "WKUPT0,Wake-up 0 Input Type" "0: A falling edge followed by a low level for a..,1: A rising edge followed by a high level for a.."
|
|
newline
|
|
bitfld.long 0x0 9. "WKUPEN9,Wake-up 9 Input Enable" "0: The corresponding wake-up input has no wake-up..,1: The corresponding wake-up input forces the.."
|
|
bitfld.long 0x0 8. "WKUPEN8,Wake-up 8 Input Enable" "0: The corresponding wake-up input has no wake-up..,1: The corresponding wake-up input forces the.."
|
|
newline
|
|
bitfld.long 0x0 7. "WKUPEN7,Wake-up 7 Input Enable" "0: The corresponding wake-up input has no wake-up..,1: The corresponding wake-up input forces the.."
|
|
bitfld.long 0x0 6. "WKUPEN6,Wake-up 6 Input Enable" "0: The corresponding wake-up input has no wake-up..,1: The corresponding wake-up input forces the.."
|
|
newline
|
|
bitfld.long 0x0 5. "WKUPEN5,Wake-up 5 Input Enable" "0: The corresponding wake-up input has no wake-up..,1: The corresponding wake-up input forces the.."
|
|
bitfld.long 0x0 4. "WKUPEN4,Wake-up 4 Input Enable" "0: The corresponding wake-up input has no wake-up..,1: The corresponding wake-up input forces the.."
|
|
newline
|
|
bitfld.long 0x0 3. "WKUPEN3,Wake-up 3 Input Enable" "0: The corresponding wake-up input has no wake-up..,1: The corresponding wake-up input forces the.."
|
|
bitfld.long 0x0 2. "WKUPEN2,Wake-up 2 Input Enable" "0: The corresponding wake-up input has no wake-up..,1: The corresponding wake-up input forces the.."
|
|
newline
|
|
bitfld.long 0x0 1. "WKUPEN1,Wake-up 1 Input Enable" "0: The corresponding wake-up input has no wake-up..,1: The corresponding wake-up input forces the.."
|
|
bitfld.long 0x0 0. "WKUPEN0,Wake-up 0 Input Enable" "0: The corresponding wake-up input has no wake-up..,1: The corresponding wake-up input forces the.."
|
|
tree.end
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
base ad:0x0
|
|
tree "SPI0"
|
|
base ad:0xF8000000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
|
|
bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
bitfld.long 0x0 8. "LSBHALF,LSB Timing Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
|
|
bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
|
|
bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: PMC GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
|
|
bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0: Slave,1: Master"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RDR,Receive Data Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RDR_FIFO_MULTI_DATA_8_MODE,Receive Data Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RD8_3,Receive Data"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD8_2,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RD8_1,Receive Data"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RD8_0,Receive Data"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RDR_FIFO_MULTI_DATA_16_MODE,Receive Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RD16_1,Receive Data"
|
|
hexmask.long.word 0x0 0.--15. 1. "RD16_0,Receive Data"
|
|
wgroup.long 0xC++0x3
|
|
line.long 0x0 "TDR,Transmit Data Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
wgroup.long 0xC++0x3
|
|
line.long 0x0 "TDR_FIFO_MULTI_DATA_MODE,Transmit Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
|
|
hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
|
|
bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0,1"
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading SPI_RDR)" "0,1"
|
|
wgroup.long 0x14++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x30)++0x3
|
|
line.long 0x0 "CSR[$1],Chip Select Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
|
bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (ignored if CSAAT = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0: Data is valid on clock trailing edge (NCPHA=0),1: Data is valid on clock leading edge (NCPHA=1)"
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0: Clock is low when inactive (CPOL=0),1: Clock is high when inactive (CPOL=1)"
|
|
repeat.end
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "FMR,FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
|
|
rgroup.long 0x44++0x7
|
|
line.long 0x0 "FLR,FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
line.long 0x4 "CMPR,Comparison Register"
|
|
hexmask.long.word 0x4 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
|
hexmask.long.word 0x4 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
tree "SPI1"
|
|
base ad:0xFC000000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
|
|
bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
bitfld.long 0x0 8. "LSBHALF,LSB Timing Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
|
|
bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
|
|
bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: PMC GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
|
|
bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0: Slave,1: Master"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RDR,Receive Data Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RDR_FIFO_MULTI_DATA_8_MODE,Receive Data Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RD8_3,Receive Data"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD8_2,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RD8_1,Receive Data"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RD8_0,Receive Data"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RDR_FIFO_MULTI_DATA_16_MODE,Receive Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RD16_1,Receive Data"
|
|
hexmask.long.word 0x0 0.--15. 1. "RD16_0,Receive Data"
|
|
wgroup.long 0xC++0x3
|
|
line.long 0x0 "TDR,Transmit Data Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
wgroup.long 0xC++0x3
|
|
line.long 0x0 "TDR_FIFO_MULTI_DATA_MODE,Transmit Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
|
|
hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
|
|
bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0,1"
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading SPI_RDR)" "0,1"
|
|
wgroup.long 0x14++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x30)++0x3
|
|
line.long 0x0 "CSR[$1],Chip Select Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
|
bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (ignored if CSAAT = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0: Data is valid on clock trailing edge (NCPHA=0),1: Data is valid on clock leading edge (NCPHA=1)"
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0: Clock is low when inactive (CPOL=0),1: Clock is high when inactive (CPOL=1)"
|
|
repeat.end
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "FMR,FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
|
|
rgroup.long 0x44++0x7
|
|
line.long 0x0 "FLR,FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
line.long 0x4 "CMPR,Comparison Register"
|
|
hexmask.long.word 0x4 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
|
hexmask.long.word 0x4 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "SSC (Synchronous Serial Controller)"
|
|
base ad:0x0
|
|
tree "SSC0"
|
|
base ad:0xF8004000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 15. "SWRST,Software Reset" "0,1"
|
|
bitfld.long 0x0 9. "TXDIS,Transmit Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXEN,Transmit Enable" "0,1"
|
|
bitfld.long 0x0 1. "RXDIS,Receive Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXEN,Receive Enable" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "CMR,Clock Mode Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "DIV,Clock Divider"
|
|
group.long 0x10++0xF
|
|
line.long 0x0 "RCMR,Receive Clock Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PERIOD,Receive Period Divider Selection"
|
|
hexmask.long.byte 0x0 16.--23. 1. "STTDLY,Receive Start Delay"
|
|
newline
|
|
bitfld.long 0x0 12. "STOP,Receive Stop Selection" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "START,Receive Start Selection"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CKG,Receive Clock Gating Selection" "0: None,1: Receive Clock enabled only if RF Low,2: Receive Clock enabled only if RF High,?"
|
|
bitfld.long 0x0 5. "CKI,Receive Clock Inversion" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "CKO,Receive Clock Output Mode Selection" "0: None RK pin is an input,1: Continuous Receive Clock RK pin is an output,2: Receive Clock only during data transfers RK pin..,?,?,?,?,?"
|
|
bitfld.long 0x0 0.--1. "CKS,Receive Clock Selection" "0: Divided Clock,1: TK Clock signal,2: RK pin,?"
|
|
line.long 0x4 "RFMR,Receive Frame Mode Register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "FSLEN_EXT,FSLEN Field Extension"
|
|
bitfld.long 0x4 24. "FSEDGE,Frame Sync Edge Detection" "0: Positive Edge Detection,1: Negative Edge Detection"
|
|
newline
|
|
bitfld.long 0x4 20.--22. "FSOS,Receive Frame Sync Output Selection" "0: None RF pin is an input,1: Negative Pulse RF pin is an output,2: Positive Pulse RF pin is an output,3: Driven Low during data transfer RF pin is an..,4: Driven High during data transfer RF pin is an..,5: Toggling at each start of data transfer RF pin..,?,?"
|
|
hexmask.long.byte 0x4 16.--19. 1. "FSLEN,Receive Frame Sync Length"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "DATNB,Data Number per Frame"
|
|
bitfld.long 0x4 7. "MSBF,Most Significant Bit First" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "LOOP,Loop Mode" "0,1"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DATLEN,Data Length"
|
|
line.long 0x8 "TCMR,Transmit Clock Mode Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. "PERIOD,Transmit Period Divider Selection"
|
|
hexmask.long.byte 0x8 16.--23. 1. "STTDLY,Transmit Start Delay"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "START,Transmit Start Selection"
|
|
bitfld.long 0x8 6.--7. "CKG,Transmit Clock Gating Selection" "0: None,1: Transmit Clock enabled only if TF Low,2: Transmit Clock enabled only if TF High,?"
|
|
newline
|
|
bitfld.long 0x8 5. "CKI,Transmit Clock Inversion" "0,1"
|
|
bitfld.long 0x8 2.--4. "CKO,Transmit Clock Output Mode Selection" "0: None TK pin is an input,1: Continuous Transmit Clock TK pin is an output,2: Transmit Clock only during data transfers TK pin..,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "CKS,Transmit Clock Selection" "0: Divided Clock,1: RK Clock signal,2: TK pin,?"
|
|
line.long 0xC "TFMR,Transmit Frame Mode Register"
|
|
hexmask.long.byte 0xC 28.--31. 1. "FSLEN_EXT,FSLEN Field Extension"
|
|
bitfld.long 0xC 24. "FSEDGE,Frame Sync Edge Detection" "0: Positive Edge Detection,1: Negative Edge Detection"
|
|
newline
|
|
bitfld.long 0xC 23. "FSDEN,Frame Sync Data Enable" "0,1"
|
|
bitfld.long 0xC 20.--22. "FSOS,Transmit Frame Sync Output Selection" "0: None TF pin is an input,1: Negative Pulse TF pin is an output,2: Positive Pulse TF pin is an output,3: Driven Low during data transfer,4: Driven High during data transfer,5: Toggling at each start of data transfer,?,?"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--19. 1. "FSLEN,Transmit Frame Sync Length"
|
|
hexmask.long.byte 0xC 8.--11. 1. "DATNB,Data Number per Frame"
|
|
newline
|
|
bitfld.long 0xC 7. "MSBF,Most Significant Bit First" "0,1"
|
|
bitfld.long 0xC 5. "DATDEF,Data Default Value" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--4. 1. "DATLEN,Data Length"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "RHR,Receive Holding Register"
|
|
hexmask.long 0x0 0.--31. 1. "RDAT,Receive Data"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "THR,Transmit Holding Register"
|
|
hexmask.long 0x0 0.--31. 1. "TDAT,Transmit Data"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "RSHR,Receive Sync. Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RSDAT,Receive Synchronization Data"
|
|
group.long 0x34++0xB
|
|
line.long 0x0 "TSHR,Transmit Sync. Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TSDAT,Transmit Synchronization Data"
|
|
line.long 0x4 "RC0R,Receive Compare 0 Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "CP0,Receive Compare Data 0"
|
|
line.long 0x8 "RC1R,Receive Compare 1 Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "CP1,Receive Compare Data 1"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 17. "RXEN,Receive Enable" "0,1"
|
|
bitfld.long 0x0 16. "TXEN,Transmit Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RXSYN,Receive Sync" "0,1"
|
|
bitfld.long 0x0 10. "TXSYN,Transmit Sync" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CP1,Compare 1" "0,1"
|
|
bitfld.long 0x0 8. "CP0,Compare 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRUN,Receive Overrun" "0,1"
|
|
bitfld.long 0x0 4. "RXRDY,Receive Ready" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXEMPTY,Transmit Empty" "0,1"
|
|
bitfld.long 0x0 0. "TXRDY,Transmit Ready" "0,1"
|
|
wgroup.long 0x44++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 11. "RXSYN,Rx Sync Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 10. "TXSYN,Tx Sync Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CP1,Compare 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "CP0,Compare 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRUN,Receive Overrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "RXRDY,Receive Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXEMPTY,Transmit Empty Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "TXRDY,Transmit Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 11. "RXSYN,Rx Sync Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "TXSYN,Tx Sync Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CP1,Compare 1 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "CP0,Compare 0 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRUN,Receive Overrun Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "RXRDY,Receive Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXEMPTY,Transmit Empty Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "TXRDY,Transmit Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 11. "RXSYN,Rx Sync Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "TXSYN,Tx Sync Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CP1,Compare 1 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "CP0,Compare 0 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRUN,Receive Overrun Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "RXRDY,Receive Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXEMPTY,Transmit Empty Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "TXRDY,Transmit Ready Interrupt Mask" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protect Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
tree "SSC1"
|
|
base ad:0xFC004000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 15. "SWRST,Software Reset" "0,1"
|
|
bitfld.long 0x0 9. "TXDIS,Transmit Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXEN,Transmit Enable" "0,1"
|
|
bitfld.long 0x0 1. "RXDIS,Receive Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXEN,Receive Enable" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "CMR,Clock Mode Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "DIV,Clock Divider"
|
|
group.long 0x10++0xF
|
|
line.long 0x0 "RCMR,Receive Clock Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PERIOD,Receive Period Divider Selection"
|
|
hexmask.long.byte 0x0 16.--23. 1. "STTDLY,Receive Start Delay"
|
|
newline
|
|
bitfld.long 0x0 12. "STOP,Receive Stop Selection" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "START,Receive Start Selection"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CKG,Receive Clock Gating Selection" "0: None,1: Receive Clock enabled only if RF Low,2: Receive Clock enabled only if RF High,?"
|
|
bitfld.long 0x0 5. "CKI,Receive Clock Inversion" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "CKO,Receive Clock Output Mode Selection" "0: None RK pin is an input,1: Continuous Receive Clock RK pin is an output,2: Receive Clock only during data transfers RK pin..,?,?,?,?,?"
|
|
bitfld.long 0x0 0.--1. "CKS,Receive Clock Selection" "0: Divided Clock,1: TK Clock signal,2: RK pin,?"
|
|
line.long 0x4 "RFMR,Receive Frame Mode Register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "FSLEN_EXT,FSLEN Field Extension"
|
|
bitfld.long 0x4 24. "FSEDGE,Frame Sync Edge Detection" "0: Positive Edge Detection,1: Negative Edge Detection"
|
|
newline
|
|
bitfld.long 0x4 20.--22. "FSOS,Receive Frame Sync Output Selection" "0: None RF pin is an input,1: Negative Pulse RF pin is an output,2: Positive Pulse RF pin is an output,3: Driven Low during data transfer RF pin is an..,4: Driven High during data transfer RF pin is an..,5: Toggling at each start of data transfer RF pin..,?,?"
|
|
hexmask.long.byte 0x4 16.--19. 1. "FSLEN,Receive Frame Sync Length"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "DATNB,Data Number per Frame"
|
|
bitfld.long 0x4 7. "MSBF,Most Significant Bit First" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "LOOP,Loop Mode" "0,1"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DATLEN,Data Length"
|
|
line.long 0x8 "TCMR,Transmit Clock Mode Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. "PERIOD,Transmit Period Divider Selection"
|
|
hexmask.long.byte 0x8 16.--23. 1. "STTDLY,Transmit Start Delay"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "START,Transmit Start Selection"
|
|
bitfld.long 0x8 6.--7. "CKG,Transmit Clock Gating Selection" "0: None,1: Transmit Clock enabled only if TF Low,2: Transmit Clock enabled only if TF High,?"
|
|
newline
|
|
bitfld.long 0x8 5. "CKI,Transmit Clock Inversion" "0,1"
|
|
bitfld.long 0x8 2.--4. "CKO,Transmit Clock Output Mode Selection" "0: None TK pin is an input,1: Continuous Transmit Clock TK pin is an output,2: Transmit Clock only during data transfers TK pin..,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "CKS,Transmit Clock Selection" "0: Divided Clock,1: RK Clock signal,2: TK pin,?"
|
|
line.long 0xC "TFMR,Transmit Frame Mode Register"
|
|
hexmask.long.byte 0xC 28.--31. 1. "FSLEN_EXT,FSLEN Field Extension"
|
|
bitfld.long 0xC 24. "FSEDGE,Frame Sync Edge Detection" "0: Positive Edge Detection,1: Negative Edge Detection"
|
|
newline
|
|
bitfld.long 0xC 23. "FSDEN,Frame Sync Data Enable" "0,1"
|
|
bitfld.long 0xC 20.--22. "FSOS,Transmit Frame Sync Output Selection" "0: None TF pin is an input,1: Negative Pulse TF pin is an output,2: Positive Pulse TF pin is an output,3: Driven Low during data transfer,4: Driven High during data transfer,5: Toggling at each start of data transfer,?,?"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--19. 1. "FSLEN,Transmit Frame Sync Length"
|
|
hexmask.long.byte 0xC 8.--11. 1. "DATNB,Data Number per Frame"
|
|
newline
|
|
bitfld.long 0xC 7. "MSBF,Most Significant Bit First" "0,1"
|
|
bitfld.long 0xC 5. "DATDEF,Data Default Value" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--4. 1. "DATLEN,Data Length"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "RHR,Receive Holding Register"
|
|
hexmask.long 0x0 0.--31. 1. "RDAT,Receive Data"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "THR,Transmit Holding Register"
|
|
hexmask.long 0x0 0.--31. 1. "TDAT,Transmit Data"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "RSHR,Receive Sync. Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RSDAT,Receive Synchronization Data"
|
|
group.long 0x34++0xB
|
|
line.long 0x0 "TSHR,Transmit Sync. Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TSDAT,Transmit Synchronization Data"
|
|
line.long 0x4 "RC0R,Receive Compare 0 Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "CP0,Receive Compare Data 0"
|
|
line.long 0x8 "RC1R,Receive Compare 1 Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "CP1,Receive Compare Data 1"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 17. "RXEN,Receive Enable" "0,1"
|
|
bitfld.long 0x0 16. "TXEN,Transmit Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RXSYN,Receive Sync" "0,1"
|
|
bitfld.long 0x0 10. "TXSYN,Transmit Sync" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CP1,Compare 1" "0,1"
|
|
bitfld.long 0x0 8. "CP0,Compare 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRUN,Receive Overrun" "0,1"
|
|
bitfld.long 0x0 4. "RXRDY,Receive Ready" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXEMPTY,Transmit Empty" "0,1"
|
|
bitfld.long 0x0 0. "TXRDY,Transmit Ready" "0,1"
|
|
wgroup.long 0x44++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 11. "RXSYN,Rx Sync Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 10. "TXSYN,Tx Sync Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CP1,Compare 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "CP0,Compare 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRUN,Receive Overrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "RXRDY,Receive Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXEMPTY,Transmit Empty Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "TXRDY,Transmit Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 11. "RXSYN,Rx Sync Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "TXSYN,Tx Sync Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CP1,Compare 1 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "CP0,Compare 0 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRUN,Receive Overrun Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "RXRDY,Receive Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXEMPTY,Transmit Empty Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "TXRDY,Transmit Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 11. "RXSYN,Rx Sync Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "TXSYN,Tx Sync Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CP1,Compare 1 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "CP0,Compare 0 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRUN,Receive Overrun Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "RXRDY,Receive Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXEMPTY,Transmit Empty Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "TXRDY,Transmit Ready Interrupt Mask" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protect Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "TC (Timer/Counter)"
|
|
base ad:0x0
|
|
tree "TC0"
|
|
base ad:0xF800C000
|
|
repeat 3. (list 0x0 0x1 0x2)(list ad:0xF800C000 ad:0xF800C040 ad:0xF800C080)
|
|
tree "TC_CHANNEL[$1]"
|
|
base $2
|
|
wgroup.long ($2)++0x3
|
|
line.long 0x0 "CCR,Channel Control Register"
|
|
bitfld.long 0x0 2. "SWTRG,Software Trigger Command" "0,1"
|
|
bitfld.long 0x0 1. "CLKDIS,Counter Clock Disable Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CLKEN,Counter Clock Enable Command" "0,1"
|
|
group.long ($2+0x4)++0x3
|
|
line.long 0x0 "CMR_CAPTURE_MODE,Channel Mode Register"
|
|
bitfld.long 0x0 20.--22. "SBSMPLR,Loading Edge Subsampling Ratio" "0: Load a Capture register each selected edge,1: Load a Capture register every 2 selected edges,2: Load a Capture register every 4 selected edges,3: Load a Capture register every 8 selected edges,4: Load a Capture register every 16 selected edges,?,?,?"
|
|
bitfld.long 0x0 18.--19. "LDRB,RB Loading Edge Selection" "0: None,1: Rising edge of TIOAx,2: Falling edge of TIOAx,3: Each edge of TIOAx"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "LDRA,RA Loading Edge Selection" "0: None,1: Rising edge of TIOAx,2: Falling edge of TIOAx,3: Each edge of TIOAx"
|
|
bitfld.long 0x0 15. "WAVE,Waveform Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "CPCTRG,RC Compare Trigger Enable" "0,1"
|
|
bitfld.long 0x0 10. "ABETRG,TIOAx or TIOBx External Trigger Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "ETRGEDG,External Trigger Edge Selection" "0: The clock is not gated by an external signal.,1: Rising edge,2: Falling edge,3: Each edge"
|
|
bitfld.long 0x0 7. "LDBDIS,Counter Clock Disable with RB Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LDBSTOP,Counter Clock Stopped with RB Loading" "0,1"
|
|
bitfld.long 0x0 4.--5. "BURST,Burst Signal Selection" "0: The clock is not gated by an external signal.,1: XC0 is ANDed with the selected clock.,2: XC1 is ANDed with the selected clock.,3: XC2 is ANDed with the selected clock."
|
|
newline
|
|
bitfld.long 0x0 3. "CLKI,Clock Invert" "0,1"
|
|
bitfld.long 0x0 0.--2. "TCCLKS,Clock Selection" "0: Clock selected: internal GCLK [35] GCLK [36]..,1: Clock selected: internal System bus clock..,2: Clock selected: internal System bus clock..,3: Clock selected: internal System bus clock..,4: Clock selected: internal slow_clock clock signal..,5: Clock selected: XC0,6: Clock selected: XC1,7: Clock selected: XC2"
|
|
group.long ($2+0x4)++0x7
|
|
line.long 0x0 "CMR_WAVEFORM_MODE,Channel Mode Register"
|
|
bitfld.long 0x0 30.--31. "BSWTRG,Software Trigger Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 28.--29. "BEEVT,External Event Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "BCPC,RC Compare Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 24.--25. "BCPB,RB Compare Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "ASWTRG,Software Trigger Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 20.--21. "AEEVT,External Event Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "ACPC,RC Compare Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 16.--17. "ACPA,RA Compare Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 15. "WAVE,Waveform Mode" "0,1"
|
|
bitfld.long 0x0 13.--14. "WAVSEL,Waveform Selection" "0: UP mode without automatic trigger on RC Compare,1: UPDOWN mode without automatic trigger on RC..,2: UP mode with automatic trigger on RC Compare,3: UPDOWN mode with automatic trigger on RC Compare"
|
|
newline
|
|
bitfld.long 0x0 12. "ENETRG,External Event Trigger Enable" "0,1"
|
|
bitfld.long 0x0 10.--11. "EEVT,External Event Selection" "0: TIOB,1: XC0,2: XC1,3: XC2"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "EEVTEDG,External Event Edge Selection" "0: None,1: Rising edge,2: Falling edge,3: Each edge"
|
|
bitfld.long 0x0 7. "CPCDIS,Counter Clock Disable with RC Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "CPCSTOP,Counter Clock Stopped with RC Compare" "0,1"
|
|
bitfld.long 0x0 4.--5. "BURST,Burst Signal Selection" "0: The clock is not gated by an external signal.,1: XC0 is ANDed with the selected clock.,2: XC1 is ANDed with the selected clock.,3: XC2 is ANDed with the selected clock."
|
|
newline
|
|
bitfld.long 0x0 3. "CLKI,Clock Invert" "0,1"
|
|
bitfld.long 0x0 0.--2. "TCCLKS,Clock Selection" "0: Clock selected: internal GCLK [35] GCLK [36]..,1: Clock selected: internal System bus clock..,2: Clock selected: internal System bus clock..,3: Clock selected: internal System bus clock..,4: Clock selected: internal slow_clock clock signal..,5: Clock selected: XC0,6: Clock selected: XC1,7: Clock selected: XC2"
|
|
line.long 0x4 "SMMR,Stepper Motor Mode Register"
|
|
bitfld.long 0x4 1. "DOWN,Down Count" "0,1"
|
|
bitfld.long 0x4 0. "GCEN,Gray Count Enable" "0,1"
|
|
rgroup.long ($2+0xC)++0x7
|
|
line.long 0x0 "RAB,Register AB"
|
|
hexmask.long 0x0 0.--31. 1. "RAB,Register A or Register B"
|
|
line.long 0x4 "CV,Counter Value"
|
|
hexmask.long 0x4 0.--31. 1. "CV,Counter Value"
|
|
group.long ($2+0x14)++0xB
|
|
line.long 0x0 "RA,Register A"
|
|
hexmask.long 0x0 0.--31. 1. "RA,Register A"
|
|
line.long 0x4 "RB,Register B"
|
|
hexmask.long 0x4 0.--31. 1. "RB,Register B"
|
|
line.long 0x8 "RC,Register C"
|
|
hexmask.long 0x8 0.--31. 1. "RC,Register C"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "SR,Interrupt Status Register"
|
|
bitfld.long 0x0 18. "MTIOB,TIOBx Mirror" "0,1"
|
|
bitfld.long 0x0 17. "MTIOA,TIOAx Mirror" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CLKSTA,Clock Enabling Status" "0,1"
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CPCS,RC Compare Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 3. "CPBS,RB Compare Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPAS,RA Compare Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow Status (cleared on read)" "0,1"
|
|
wgroup.long ($2+0x24)++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger" "0,1"
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading" "0,1"
|
|
bitfld.long 0x0 4. "CPCS,RC Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPBS,RB Compare" "0,1"
|
|
bitfld.long 0x0 2. "CPAS,RA Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun" "0,1"
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "ETRGS,External Trigger" "0,1"
|
|
bitfld.long 0x4 6. "LDRBS,RB Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "LDRAS,RA Loading" "0,1"
|
|
bitfld.long 0x4 4. "CPCS,RC Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CPBS,RB Compare" "0,1"
|
|
bitfld.long 0x4 2. "CPAS,RA Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "LOVRS,Load Overrun" "0,1"
|
|
bitfld.long 0x4 0. "COVFS,Counter Overflow" "0,1"
|
|
rgroup.long ($2+0x2C)++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "ETRGS," "0,1"
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading" "0,1"
|
|
bitfld.long 0x0 4. "CPCS,RC Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPBS,RB Compare" "0,1"
|
|
bitfld.long 0x0 2. "CPAS,RA Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun" "0,1"
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow" "0,1"
|
|
group.long ($2+0x30)++0x3
|
|
line.long 0x0 "EMR,Extended Mode Register"
|
|
bitfld.long 0x0 8. "NODIVCLK,No Divided Clock" "0,1"
|
|
bitfld.long 0x0 4.--5. "TRIGSRCB,Trigger Source for Input B" "0: The trigger/capture input B is driven by..,1: For TC0 to TC10: The trigger/capture input B is..,?,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TRIGSRCA,Trigger Source for Input A" "0: The trigger/capture input A is driven by..,1: The trigger/capture input A is driven internally..,?,?"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0xF800C000
|
|
wgroup.long 0xC0++0x3
|
|
line.long 0x0 "BCR,Block Control Register"
|
|
bitfld.long 0x0 0. "SYNC,Synchro Command" "0,1"
|
|
group.long 0xC4++0x3
|
|
line.long 0x0 "BMR,Block Mode Register"
|
|
hexmask.long.byte 0x0 26.--29. 1. "MAXCMP,Maximum Consecutive Missing Pulses"
|
|
hexmask.long.byte 0x0 20.--25. 1. "MAXFILT,Maximum Filter"
|
|
bitfld.long 0x0 18. "AUTOC,AutoCorrection of missing pulses" "0: The detection and autocorrection function is..,1: The detection and autocorrection function is.."
|
|
newline
|
|
bitfld.long 0x0 17. "IDXPHB,Index Pin is PHB Pin" "0,1"
|
|
bitfld.long 0x0 16. "SWAP,Swap PHA and PHB" "0,1"
|
|
bitfld.long 0x0 15. "INVIDX,Inverted Index" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "INVB,Inverted PHB" "0,1"
|
|
bitfld.long 0x0 13. "INVA,Inverted PHA" "0,1"
|
|
bitfld.long 0x0 12. "EDGPHA,Edge on PHA Count Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "QDTRANS,Quadrature Decoding Transparent" "0,1"
|
|
bitfld.long 0x0 10. "SPEEDEN,Speed Enabled" "0,1"
|
|
bitfld.long 0x0 9. "POSEN,Position Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "QDEN,Quadrature Decoder Enabled" "0,1"
|
|
bitfld.long 0x0 4.--5. "TC2XC2S,External Clock Signal 2 Selection" "0: Signal connected to XC2: TCLK2,?,2: Signal connected to XC2: TIOA0,3: Signal connected to XC2: TIOA1"
|
|
bitfld.long 0x0 2.--3. "TC1XC1S,External Clock Signal 1 Selection" "0: Signal connected to XC1: TCLK1,?,2: Signal connected to XC1: TIOA0,3: Signal connected to XC1: TIOA2"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TC0XC0S,External Clock Signal 0 Selection" "0: Signal connected to XC0: TCLK0,?,2: Signal connected to XC0: TIOA1,3: Signal connected to XC0: TIOA2"
|
|
wgroup.long 0xC8++0x7
|
|
line.long 0x0 "QIER,QDEC Interrupt Enable Register"
|
|
bitfld.long 0x0 3. "MPE,Consecutive Missing Pulse Error" "0,1"
|
|
bitfld.long 0x0 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x0 1. "DIRCHG,Direction Change" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IDX,Index" "0,1"
|
|
line.long 0x4 "QIDR,QDEC Interrupt Disable Register"
|
|
bitfld.long 0x4 3. "MPE,Consecutive Missing Pulse Error" "0,1"
|
|
bitfld.long 0x4 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x4 1. "DIRCHG,Direction Change" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IDX,Index" "0,1"
|
|
rgroup.long 0xD0++0x7
|
|
line.long 0x0 "QIMR,QDEC Interrupt Mask Register"
|
|
bitfld.long 0x0 3. "MPE,Consecutive Missing Pulse Error" "0,1"
|
|
bitfld.long 0x0 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x0 1. "DIRCHG,Direction Change" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IDX,Index" "0,1"
|
|
line.long 0x4 "QISR,QDEC Interrupt Status Register"
|
|
bitfld.long 0x4 8. "DIR,Direction" "0,1"
|
|
bitfld.long 0x4 3. "MPE,Consecutive Missing Pulse Error" "0,1"
|
|
bitfld.long 0x4 2. "QERR,Quadrature Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DIRCHG,Direction Change" "0,1"
|
|
bitfld.long 0x4 0. "IDX,Index" "0,1"
|
|
group.long 0xD8++0x3
|
|
line.long 0x0 "FMR,Fault Mode Register"
|
|
bitfld.long 0x0 1. "ENCF1,Enable Compare Fault Channel 1" "0,1"
|
|
bitfld.long 0x0 0. "ENCF0,Enable Compare Fault Channel 0" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
tree.end
|
|
tree "TC1"
|
|
base ad:0xF8010000
|
|
repeat 3. (list 0x0 0x1 0x2)(list ad:0xF8010000 ad:0xF8010040 ad:0xF8010080)
|
|
tree "TC_CHANNEL[$1]"
|
|
base $2
|
|
wgroup.long ($2)++0x3
|
|
line.long 0x0 "CCR,Channel Control Register"
|
|
bitfld.long 0x0 2. "SWTRG,Software Trigger Command" "0,1"
|
|
bitfld.long 0x0 1. "CLKDIS,Counter Clock Disable Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CLKEN,Counter Clock Enable Command" "0,1"
|
|
group.long ($2+0x4)++0x3
|
|
line.long 0x0 "CMR_CAPTURE_MODE,Channel Mode Register"
|
|
bitfld.long 0x0 20.--22. "SBSMPLR,Loading Edge Subsampling Ratio" "0: Load a Capture register each selected edge,1: Load a Capture register every 2 selected edges,2: Load a Capture register every 4 selected edges,3: Load a Capture register every 8 selected edges,4: Load a Capture register every 16 selected edges,?,?,?"
|
|
bitfld.long 0x0 18.--19. "LDRB,RB Loading Edge Selection" "0: None,1: Rising edge of TIOAx,2: Falling edge of TIOAx,3: Each edge of TIOAx"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "LDRA,RA Loading Edge Selection" "0: None,1: Rising edge of TIOAx,2: Falling edge of TIOAx,3: Each edge of TIOAx"
|
|
bitfld.long 0x0 15. "WAVE,Waveform Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "CPCTRG,RC Compare Trigger Enable" "0,1"
|
|
bitfld.long 0x0 10. "ABETRG,TIOAx or TIOBx External Trigger Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "ETRGEDG,External Trigger Edge Selection" "0: The clock is not gated by an external signal.,1: Rising edge,2: Falling edge,3: Each edge"
|
|
bitfld.long 0x0 7. "LDBDIS,Counter Clock Disable with RB Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LDBSTOP,Counter Clock Stopped with RB Loading" "0,1"
|
|
bitfld.long 0x0 4.--5. "BURST,Burst Signal Selection" "0: The clock is not gated by an external signal.,1: XC0 is ANDed with the selected clock.,2: XC1 is ANDed with the selected clock.,3: XC2 is ANDed with the selected clock."
|
|
newline
|
|
bitfld.long 0x0 3. "CLKI,Clock Invert" "0,1"
|
|
bitfld.long 0x0 0.--2. "TCCLKS,Clock Selection" "0: Clock selected: internal GCLK [35] GCLK [36]..,1: Clock selected: internal System bus clock..,2: Clock selected: internal System bus clock..,3: Clock selected: internal System bus clock..,4: Clock selected: internal slow_clock clock signal..,5: Clock selected: XC0,6: Clock selected: XC1,7: Clock selected: XC2"
|
|
group.long ($2+0x4)++0x7
|
|
line.long 0x0 "CMR_WAVEFORM_MODE,Channel Mode Register"
|
|
bitfld.long 0x0 30.--31. "BSWTRG,Software Trigger Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 28.--29. "BEEVT,External Event Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "BCPC,RC Compare Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 24.--25. "BCPB,RB Compare Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "ASWTRG,Software Trigger Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 20.--21. "AEEVT,External Event Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "ACPC,RC Compare Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 16.--17. "ACPA,RA Compare Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 15. "WAVE,Waveform Mode" "0,1"
|
|
bitfld.long 0x0 13.--14. "WAVSEL,Waveform Selection" "0: UP mode without automatic trigger on RC Compare,1: UPDOWN mode without automatic trigger on RC..,2: UP mode with automatic trigger on RC Compare,3: UPDOWN mode with automatic trigger on RC Compare"
|
|
newline
|
|
bitfld.long 0x0 12. "ENETRG,External Event Trigger Enable" "0,1"
|
|
bitfld.long 0x0 10.--11. "EEVT,External Event Selection" "0: TIOB,1: XC0,2: XC1,3: XC2"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "EEVTEDG,External Event Edge Selection" "0: None,1: Rising edge,2: Falling edge,3: Each edge"
|
|
bitfld.long 0x0 7. "CPCDIS,Counter Clock Disable with RC Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "CPCSTOP,Counter Clock Stopped with RC Compare" "0,1"
|
|
bitfld.long 0x0 4.--5. "BURST,Burst Signal Selection" "0: The clock is not gated by an external signal.,1: XC0 is ANDed with the selected clock.,2: XC1 is ANDed with the selected clock.,3: XC2 is ANDed with the selected clock."
|
|
newline
|
|
bitfld.long 0x0 3. "CLKI,Clock Invert" "0,1"
|
|
bitfld.long 0x0 0.--2. "TCCLKS,Clock Selection" "0: Clock selected: internal GCLK [35] GCLK [36]..,1: Clock selected: internal System bus clock..,2: Clock selected: internal System bus clock..,3: Clock selected: internal System bus clock..,4: Clock selected: internal slow_clock clock signal..,5: Clock selected: XC0,6: Clock selected: XC1,7: Clock selected: XC2"
|
|
line.long 0x4 "SMMR,Stepper Motor Mode Register"
|
|
bitfld.long 0x4 1. "DOWN,Down Count" "0,1"
|
|
bitfld.long 0x4 0. "GCEN,Gray Count Enable" "0,1"
|
|
rgroup.long ($2+0xC)++0x7
|
|
line.long 0x0 "RAB,Register AB"
|
|
hexmask.long 0x0 0.--31. 1. "RAB,Register A or Register B"
|
|
line.long 0x4 "CV,Counter Value"
|
|
hexmask.long 0x4 0.--31. 1. "CV,Counter Value"
|
|
group.long ($2+0x14)++0xB
|
|
line.long 0x0 "RA,Register A"
|
|
hexmask.long 0x0 0.--31. 1. "RA,Register A"
|
|
line.long 0x4 "RB,Register B"
|
|
hexmask.long 0x4 0.--31. 1. "RB,Register B"
|
|
line.long 0x8 "RC,Register C"
|
|
hexmask.long 0x8 0.--31. 1. "RC,Register C"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "SR,Interrupt Status Register"
|
|
bitfld.long 0x0 18. "MTIOB,TIOBx Mirror" "0,1"
|
|
bitfld.long 0x0 17. "MTIOA,TIOAx Mirror" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CLKSTA,Clock Enabling Status" "0,1"
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CPCS,RC Compare Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 3. "CPBS,RB Compare Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPAS,RA Compare Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow Status (cleared on read)" "0,1"
|
|
wgroup.long ($2+0x24)++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger" "0,1"
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading" "0,1"
|
|
bitfld.long 0x0 4. "CPCS,RC Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPBS,RB Compare" "0,1"
|
|
bitfld.long 0x0 2. "CPAS,RA Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun" "0,1"
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "ETRGS,External Trigger" "0,1"
|
|
bitfld.long 0x4 6. "LDRBS,RB Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "LDRAS,RA Loading" "0,1"
|
|
bitfld.long 0x4 4. "CPCS,RC Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CPBS,RB Compare" "0,1"
|
|
bitfld.long 0x4 2. "CPAS,RA Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "LOVRS,Load Overrun" "0,1"
|
|
bitfld.long 0x4 0. "COVFS,Counter Overflow" "0,1"
|
|
rgroup.long ($2+0x2C)++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "ETRGS," "0,1"
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading" "0,1"
|
|
bitfld.long 0x0 4. "CPCS,RC Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPBS,RB Compare" "0,1"
|
|
bitfld.long 0x0 2. "CPAS,RA Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun" "0,1"
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow" "0,1"
|
|
group.long ($2+0x30)++0x3
|
|
line.long 0x0 "EMR,Extended Mode Register"
|
|
bitfld.long 0x0 8. "NODIVCLK,No Divided Clock" "0,1"
|
|
bitfld.long 0x0 4.--5. "TRIGSRCB,Trigger Source for Input B" "0: The trigger/capture input B is driven by..,1: For TC0 to TC10: The trigger/capture input B is..,?,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TRIGSRCA,Trigger Source for Input A" "0: The trigger/capture input A is driven by..,1: The trigger/capture input A is driven internally..,?,?"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0xF8010000
|
|
wgroup.long 0xC0++0x3
|
|
line.long 0x0 "BCR,Block Control Register"
|
|
bitfld.long 0x0 0. "SYNC,Synchro Command" "0,1"
|
|
group.long 0xC4++0x3
|
|
line.long 0x0 "BMR,Block Mode Register"
|
|
hexmask.long.byte 0x0 26.--29. 1. "MAXCMP,Maximum Consecutive Missing Pulses"
|
|
hexmask.long.byte 0x0 20.--25. 1. "MAXFILT,Maximum Filter"
|
|
bitfld.long 0x0 18. "AUTOC,AutoCorrection of missing pulses" "0: The detection and autocorrection function is..,1: The detection and autocorrection function is.."
|
|
newline
|
|
bitfld.long 0x0 17. "IDXPHB,Index Pin is PHB Pin" "0,1"
|
|
bitfld.long 0x0 16. "SWAP,Swap PHA and PHB" "0,1"
|
|
bitfld.long 0x0 15. "INVIDX,Inverted Index" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "INVB,Inverted PHB" "0,1"
|
|
bitfld.long 0x0 13. "INVA,Inverted PHA" "0,1"
|
|
bitfld.long 0x0 12. "EDGPHA,Edge on PHA Count Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "QDTRANS,Quadrature Decoding Transparent" "0,1"
|
|
bitfld.long 0x0 10. "SPEEDEN,Speed Enabled" "0,1"
|
|
bitfld.long 0x0 9. "POSEN,Position Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "QDEN,Quadrature Decoder Enabled" "0,1"
|
|
bitfld.long 0x0 4.--5. "TC2XC2S,External Clock Signal 2 Selection" "0: Signal connected to XC2: TCLK2,?,2: Signal connected to XC2: TIOA0,3: Signal connected to XC2: TIOA1"
|
|
bitfld.long 0x0 2.--3. "TC1XC1S,External Clock Signal 1 Selection" "0: Signal connected to XC1: TCLK1,?,2: Signal connected to XC1: TIOA0,3: Signal connected to XC1: TIOA2"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TC0XC0S,External Clock Signal 0 Selection" "0: Signal connected to XC0: TCLK0,?,2: Signal connected to XC0: TIOA1,3: Signal connected to XC0: TIOA2"
|
|
wgroup.long 0xC8++0x7
|
|
line.long 0x0 "QIER,QDEC Interrupt Enable Register"
|
|
bitfld.long 0x0 3. "MPE,Consecutive Missing Pulse Error" "0,1"
|
|
bitfld.long 0x0 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x0 1. "DIRCHG,Direction Change" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IDX,Index" "0,1"
|
|
line.long 0x4 "QIDR,QDEC Interrupt Disable Register"
|
|
bitfld.long 0x4 3. "MPE,Consecutive Missing Pulse Error" "0,1"
|
|
bitfld.long 0x4 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x4 1. "DIRCHG,Direction Change" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IDX,Index" "0,1"
|
|
rgroup.long 0xD0++0x7
|
|
line.long 0x0 "QIMR,QDEC Interrupt Mask Register"
|
|
bitfld.long 0x0 3. "MPE,Consecutive Missing Pulse Error" "0,1"
|
|
bitfld.long 0x0 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x0 1. "DIRCHG,Direction Change" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IDX,Index" "0,1"
|
|
line.long 0x4 "QISR,QDEC Interrupt Status Register"
|
|
bitfld.long 0x4 8. "DIR,Direction" "0,1"
|
|
bitfld.long 0x4 3. "MPE,Consecutive Missing Pulse Error" "0,1"
|
|
bitfld.long 0x4 2. "QERR,Quadrature Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DIRCHG,Direction Change" "0,1"
|
|
bitfld.long 0x4 0. "IDX,Index" "0,1"
|
|
group.long 0xD8++0x3
|
|
line.long 0x0 "FMR,Fault Mode Register"
|
|
bitfld.long 0x0 1. "ENCF1,Enable Compare Fault Channel 1" "0,1"
|
|
bitfld.long 0x0 0. "ENCF0,Enable Compare Fault Channel 0" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "TDES (Triple Data Encryption Standard)"
|
|
base ad:0xFC044000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 8. "SWRST,Software Reset" "0,1"
|
|
bitfld.long 0x0 0. "START,Start Processing" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 16.--17. "CFBS,Cipher Feedback Data Size" "0: 64-bit,1: 32-bit,2: 16-bit,3: 8-bit"
|
|
bitfld.long 0x0 15. "LOD,Last Output Data Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "OPMOD,Operating Mode" "0: Electronic Code Book mode,1: Cipher Block Chaining mode,2: Output Feedback mode,3: Cipher Feedback mode"
|
|
bitfld.long 0x0 8.--9. "SMOD,Start Mode" "0: Manual Mode,1: Auto Mode,2: TDES_IDATAR0 accesses only Auto Mode,?"
|
|
newline
|
|
bitfld.long 0x0 4. "KEYMOD,Key Mode" "0,1"
|
|
bitfld.long 0x0 1.--2. "TDESMOD,ALGORITHM Mode" "0: Single DES processing using Key 1 Registers,1: Triple DES processing using Key 1 Key 2 and Key..,2: XTEA processing using Key 1 and Key 2 Registers,?"
|
|
newline
|
|
bitfld.long 0x0 0. "CIPHER,Processing Mode" "0: Decrypts data.,1: Encrypts data."
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 8. "URAD,Unspecified Register Access Detection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 8. "URAD,Unspecified Register Access Detection Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 8. "URAD,Unspecified Register Access Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 12.--13. "URAT,Unspecified Register Access (cleared by setting bit TDES_CR.SWRST)" "0: Input Data Register written during data..,1: Output Data Register read during data processing.,2: Mode Register written during data processing.,3: Write-only register read access."
|
|
bitfld.long 0x4 8. "URAD,Unspecified Register Access Detection Status (cleared by setting bit TDES_CR.SWRST)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready (cleared by setting bit START or bit SWRST in TDES_CR or by reading TDES_ODATARx)" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "KEY1WR[$1],Key 1 Word Register"
|
|
hexmask.long 0x0 0.--31. 1. "KEY1W,Key 1 Word"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x28)++0x3
|
|
line.long 0x0 "KEY2WR[$1],Key 2 Word Register"
|
|
hexmask.long 0x0 0.--31. 1. "KEY2W,Key 2 Word"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x30)++0x3
|
|
line.long 0x0 "KEY3WR[$1],Key 3 Word Register"
|
|
hexmask.long 0x0 0.--31. 1. "KEY3W,Key 3 Word"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x40)++0x3
|
|
line.long 0x0 "IDATAR[$1],Input Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "IDATA,Input Data"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x50)++0x3
|
|
line.long 0x0 "ODATAR[$1],Output Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "ODATA,Output Data"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x60)++0x3
|
|
line.long 0x0 "IVR[$1],Initialization Vector Register"
|
|
hexmask.long 0x0 0.--31. 1. "IV,Initialization Vector"
|
|
repeat.end
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "XTEA_RNDR,XTEA Rounds Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "XTEA_RNDS,Number of Rounds"
|
|
tree.end
|
|
tree "TRNG (True Random Number Generator)"
|
|
base ad:0xFC01C000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WAKEY,Register Write Access Key"
|
|
bitfld.long 0x0 0. "ENABLE,Enables the TRNG to Provide Random Values" "0,1"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready (cleared on read)" "0,1"
|
|
rgroup.long 0x50++0x3
|
|
line.long 0x0 "ODATA,Output Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "ODATA,Output Data"
|
|
tree.end
|
|
tree "TWIHS (Two-wire Interface)"
|
|
base ad:0x0
|
|
tree "TWIHS0"
|
|
base ad:0xF8028000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
|
|
bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWIHS High-Speed Mode Disabled" "0,1"
|
|
bitfld.long 0x0 8. "HSEN,TWIHS High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWIHS Slave Mode Disabled" "0,1"
|
|
bitfld.long 0x0 4. "SVEN,TWIHS Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWIHS Master Mode Disabled" "0,1"
|
|
bitfld.long 0x0 2. "MSEN,TWIHS Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR_FIFO_ENABLED_MODE,Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
bitfld.long 0x0 9. "HSDIS,TWIHS High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWIHS High-Speed Mode Enabled" "0,1"
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
bitfld.long 0x0 5. "SVDIS,TWIHS Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWIHS Slave Mode Enabled" "0,1"
|
|
bitfld.long 0x0 3. "MSDIS,TWIHS Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWIHS Master Mode Enabled" "0,1"
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
group.long 0x4++0xF
|
|
line.long 0x0 "MMR,Master Mode Register"
|
|
hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
|
bitfld.long 0x0 12. "MREAD,Master Read Direction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
|
line.long 0x4 "SMR,Slave Mode Register"
|
|
bitfld.long 0x4 31. "DATAMEN,Data Matching Enable" "0,1"
|
|
bitfld.long 0x4 30. "SADR3EN,Slave Address 3 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "SADR2EN,Slave Address 2 Enable" "0,1"
|
|
bitfld.long 0x4 28. "SADR1EN,Slave Address 1 Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
|
|
hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
|
|
newline
|
|
bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
|
|
bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
|
|
bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK enable" "0,1"
|
|
line.long 0x8 "IADR,Internal Address Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "CWGR,Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--28. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
|
bitfld.long 0xC 20. "CKSRC,Transfer Rate Clock Source" "0: Peripheral clock is used to generate the TWIHS..,1: GCLK is used to generate the TWIHS baud rate."
|
|
newline
|
|
bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LOCK,TWIHS Lock due to Frame Errors (cleared by writing a one to bit LOCKCLR in TWIHS_CR)" "0,1"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing TWIHS_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared by reading TWIHS_RHR)" "0,1"
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing TWIHS_THR)" "0,1"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "SR_FIFO_ENABLED_MODE,Status Register"
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing TWIHS_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared by reading TWIHS_RHR)" "0,1"
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing TWIHS_THR)" "0,1"
|
|
wgroup.long 0x24++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
|
|
rgroup.long 0x2C++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
|
|
line.long 0x4 "RHR,Receive Holding Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "RHR_FIFO_ENABLED_MODE,Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
|
|
wgroup.long 0x34++0x3
|
|
line.long 0x0 "THR,Transmit Holding Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
|
|
wgroup.long 0x34++0x3
|
|
line.long 0x0 "THR_FIFO_ENABLED_MODE,Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 02"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "SMBTR,SMBus Timing Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
|
|
hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
|
|
group.long 0x40++0x7
|
|
line.long 0x0 "ACR,Alternative Command Register"
|
|
bitfld.long 0x0 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
|
|
bitfld.long 0x0 24. "NDIR,Next Transfer Direction" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "NDATAL,Next Data Length"
|
|
bitfld.long 0x0 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DIR,Transfer Direction" "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATAL,Data Length"
|
|
line.long 0x4 "FILTR,Filter Register"
|
|
bitfld.long 0x4 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 2. "PADFCFG,PAD Filter Config" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "PADFEN,PAD Filter Enable" "0,1"
|
|
bitfld.long 0x4 0. "FILT,RX Digital Filter" "0,1"
|
|
group.long 0x4C++0x7
|
|
line.long 0x0 "SWMR,SleepWalking Matching Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DATAM,Data Match"
|
|
hexmask.long.byte 0x0 16.--22. 1. "SADR3,Slave Address 3"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "SADR2,Slave Address 2"
|
|
hexmask.long.byte 0x0 0.--6. 1. "SADR1,Slave Address 1"
|
|
line.long 0x4 "FMR,FIFO Mode Register"
|
|
hexmask.long.byte 0x4 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
hexmask.long.byte 0x4 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
|
|
bitfld.long 0x4 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x54++0x3
|
|
line.long 0x0 "FLR,FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
rgroup.long 0x60++0x3
|
|
line.long 0x0 "FSR,FIFO Status Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
wgroup.long 0x64++0x7
|
|
line.long 0x0 "FIER,FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FIDR,FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x6C++0x3
|
|
line.long 0x0 "FIMR,FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
rgroup.long 0xD0++0x3
|
|
line.long 0x0 "DR,Debug Register"
|
|
bitfld.long 0x0 3. "TRP,Transfer Pending" "0,1"
|
|
bitfld.long 0x0 2. "SWMATCH,SleepWalking Match" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKRQ,Clock Request" "0,1"
|
|
bitfld.long 0x0 0. "SWEN,SleepWalking Enable" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
tree "TWIHS1"
|
|
base ad:0xFC028000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
|
|
bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWIHS High-Speed Mode Disabled" "0,1"
|
|
bitfld.long 0x0 8. "HSEN,TWIHS High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWIHS Slave Mode Disabled" "0,1"
|
|
bitfld.long 0x0 4. "SVEN,TWIHS Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWIHS Master Mode Disabled" "0,1"
|
|
bitfld.long 0x0 2. "MSEN,TWIHS Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR_FIFO_ENABLED_MODE,Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
bitfld.long 0x0 9. "HSDIS,TWIHS High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWIHS High-Speed Mode Enabled" "0,1"
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
bitfld.long 0x0 5. "SVDIS,TWIHS Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWIHS Slave Mode Enabled" "0,1"
|
|
bitfld.long 0x0 3. "MSDIS,TWIHS Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWIHS Master Mode Enabled" "0,1"
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
group.long 0x4++0xF
|
|
line.long 0x0 "MMR,Master Mode Register"
|
|
hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
|
bitfld.long 0x0 12. "MREAD,Master Read Direction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
|
line.long 0x4 "SMR,Slave Mode Register"
|
|
bitfld.long 0x4 31. "DATAMEN,Data Matching Enable" "0,1"
|
|
bitfld.long 0x4 30. "SADR3EN,Slave Address 3 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "SADR2EN,Slave Address 2 Enable" "0,1"
|
|
bitfld.long 0x4 28. "SADR1EN,Slave Address 1 Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
|
|
hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
|
|
newline
|
|
bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
|
|
bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
|
|
bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK enable" "0,1"
|
|
line.long 0x8 "IADR,Internal Address Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "CWGR,Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--28. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
|
bitfld.long 0xC 20. "CKSRC,Transfer Rate Clock Source" "0: Peripheral clock is used to generate the TWIHS..,1: GCLK is used to generate the TWIHS baud rate."
|
|
newline
|
|
bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LOCK,TWIHS Lock due to Frame Errors (cleared by writing a one to bit LOCKCLR in TWIHS_CR)" "0,1"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing TWIHS_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared by reading TWIHS_RHR)" "0,1"
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing TWIHS_THR)" "0,1"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "SR_FIFO_ENABLED_MODE,Status Register"
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing TWIHS_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared by reading TWIHS_RHR)" "0,1"
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing TWIHS_THR)" "0,1"
|
|
wgroup.long 0x24++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
|
|
rgroup.long 0x2C++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
|
|
line.long 0x4 "RHR,Receive Holding Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "RHR_FIFO_ENABLED_MODE,Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
|
|
wgroup.long 0x34++0x3
|
|
line.long 0x0 "THR,Transmit Holding Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
|
|
wgroup.long 0x34++0x3
|
|
line.long 0x0 "THR_FIFO_ENABLED_MODE,Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 02"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "SMBTR,SMBus Timing Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
|
|
hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
|
|
group.long 0x40++0x7
|
|
line.long 0x0 "ACR,Alternative Command Register"
|
|
bitfld.long 0x0 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
|
|
bitfld.long 0x0 24. "NDIR,Next Transfer Direction" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "NDATAL,Next Data Length"
|
|
bitfld.long 0x0 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DIR,Transfer Direction" "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATAL,Data Length"
|
|
line.long 0x4 "FILTR,Filter Register"
|
|
bitfld.long 0x4 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 2. "PADFCFG,PAD Filter Config" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "PADFEN,PAD Filter Enable" "0,1"
|
|
bitfld.long 0x4 0. "FILT,RX Digital Filter" "0,1"
|
|
group.long 0x4C++0x7
|
|
line.long 0x0 "SWMR,SleepWalking Matching Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DATAM,Data Match"
|
|
hexmask.long.byte 0x0 16.--22. 1. "SADR3,Slave Address 3"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "SADR2,Slave Address 2"
|
|
hexmask.long.byte 0x0 0.--6. 1. "SADR1,Slave Address 1"
|
|
line.long 0x4 "FMR,FIFO Mode Register"
|
|
hexmask.long.byte 0x4 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
hexmask.long.byte 0x4 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
|
|
bitfld.long 0x4 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x54++0x3
|
|
line.long 0x0 "FLR,FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
rgroup.long 0x60++0x3
|
|
line.long 0x0 "FSR,FIFO Status Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
wgroup.long 0x64++0x7
|
|
line.long 0x0 "FIER,FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FIDR,FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x6C++0x3
|
|
line.long 0x0 "FIMR,FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
rgroup.long 0xD0++0x3
|
|
line.long 0x0 "DR,Debug Register"
|
|
bitfld.long 0x0 3. "TRP,Transfer Pending" "0,1"
|
|
bitfld.long 0x0 2. "SWMATCH,SleepWalking Match" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKRQ,Clock Request" "0,1"
|
|
bitfld.long 0x0 0. "SWEN,SleepWalking Enable" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "UART (Universal Asynchronous Receiver Transmitter)"
|
|
base ad:0x0
|
|
tree "UART0"
|
|
base ad:0xF801C000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 15. "DBGE,Debug Enable" "0,1"
|
|
bitfld.long 0x0 12. "REQCLR,Request Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "STTTO,Start Time-out" "0,1"
|
|
bitfld.long 0x0 10. "RETTO,Rearm Time-out" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status" "0,1"
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic echo,2: Local loopback,3: Remote loopback"
|
|
bitfld.long 0x0 12. "BRSRCCK,Baud Rate Source Clock" "0: The baud rate is driven by the peripheral clock,1: The baud rate is driven by a PMC-programmable.."
|
|
newline
|
|
bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even Parity,1: Odd Parity,2: Space: parity forced to 0,3: Mark: parity forced to 1,4: No parity,?,?,?"
|
|
bitfld.long 0x0 4. "FILTER,Receiver Digital Filter" "0: UART does not filter the receive line.,1: UART filters the receive line using a.."
|
|
wgroup.long 0x8++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 15. "CMP,Enable Comparison Interrupt" "0,1"
|
|
bitfld.long 0x0 9. "TXEMPTY,Enable TXEMPTY Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Enable Time-out Interrupt" "0,1"
|
|
bitfld.long 0x0 7. "PARE,Enable Parity Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Enable Framing Error Interrupt" "0,1"
|
|
bitfld.long 0x0 5. "OVRE,Enable Overrun Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Enable TXRDY Interrupt" "0,1"
|
|
bitfld.long 0x0 0. "RXRDY,Enable RXRDY Interrupt" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 15. "CMP,Disable Comparison Interrupt" "0,1"
|
|
bitfld.long 0x4 9. "TXEMPTY,Disable TXEMPTY Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Disable Time-out Interrupt" "0,1"
|
|
bitfld.long 0x4 7. "PARE,Disable Parity Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Disable Framing Error Interrupt" "0,1"
|
|
bitfld.long 0x4 5. "OVRE,Disable Overrun Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,Disable TXRDY Interrupt" "0,1"
|
|
bitfld.long 0x4 0. "RXRDY,Disable RXRDY Interrupt" "0,1"
|
|
rgroup.long 0x10++0xB
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 15. "CMP,Mask Comparison Interrupt" "0,1"
|
|
bitfld.long 0x0 9. "TXEMPTY,Mask TXEMPTY Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Mask Time-out Interrupt" "0,1"
|
|
bitfld.long 0x0 7. "PARE,Mask Parity Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Mask Framing Error Interrupt" "0,1"
|
|
bitfld.long 0x0 5. "OVRE,Mask Overrun Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Disable TXRDY Interrupt" "0,1"
|
|
bitfld.long 0x0 0. "RXRDY,Mask RXRDY Interrupt" "0,1"
|
|
line.long 0x4 "SR,Status Register"
|
|
bitfld.long 0x4 23. "WKUPREQ,Wake-Up Request" "0,1"
|
|
bitfld.long 0x4 22. "CLKREQ,Clock Request" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "SWES,SleepWalking Enable Status" "0,1"
|
|
bitfld.long 0x4 15. "CMP,Comparison Match" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty" "0,1"
|
|
bitfld.long 0x4 8. "TIMEOUT,Receiver Time-out" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
|
|
bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
|
|
bitfld.long 0x4 1. "TXRDY,Transmitter Ready" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Receiver Ready" "0,1"
|
|
line.long 0x8 "RHR,Receive Holding Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RXCHR,Received Character"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "THR,Transmit Holding Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXCHR,Character to be Transmitted"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "BRGR,Baud Rate Generator Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divisor"
|
|
line.long 0x4 "CMPR,Comparison Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "VAL2,Second Comparison Value for Received Character"
|
|
bitfld.long 0x4 14. "CMPPAR,Compare Parity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
hexmask.long.byte 0x4 0.--7. 1. "VAL1,First Comparison Value for Received Character"
|
|
line.long 0x8 "RTOR,Receiver Time-out Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "TO,Time-out Value"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
tree.end
|
|
tree "UART1"
|
|
base ad:0xF8020000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 15. "DBGE,Debug Enable" "0,1"
|
|
bitfld.long 0x0 12. "REQCLR,Request Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "STTTO,Start Time-out" "0,1"
|
|
bitfld.long 0x0 10. "RETTO,Rearm Time-out" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status" "0,1"
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic echo,2: Local loopback,3: Remote loopback"
|
|
bitfld.long 0x0 12. "BRSRCCK,Baud Rate Source Clock" "0: The baud rate is driven by the peripheral clock,1: The baud rate is driven by a PMC-programmable.."
|
|
newline
|
|
bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even Parity,1: Odd Parity,2: Space: parity forced to 0,3: Mark: parity forced to 1,4: No parity,?,?,?"
|
|
bitfld.long 0x0 4. "FILTER,Receiver Digital Filter" "0: UART does not filter the receive line.,1: UART filters the receive line using a.."
|
|
wgroup.long 0x8++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 15. "CMP,Enable Comparison Interrupt" "0,1"
|
|
bitfld.long 0x0 9. "TXEMPTY,Enable TXEMPTY Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Enable Time-out Interrupt" "0,1"
|
|
bitfld.long 0x0 7. "PARE,Enable Parity Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Enable Framing Error Interrupt" "0,1"
|
|
bitfld.long 0x0 5. "OVRE,Enable Overrun Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Enable TXRDY Interrupt" "0,1"
|
|
bitfld.long 0x0 0. "RXRDY,Enable RXRDY Interrupt" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 15. "CMP,Disable Comparison Interrupt" "0,1"
|
|
bitfld.long 0x4 9. "TXEMPTY,Disable TXEMPTY Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Disable Time-out Interrupt" "0,1"
|
|
bitfld.long 0x4 7. "PARE,Disable Parity Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Disable Framing Error Interrupt" "0,1"
|
|
bitfld.long 0x4 5. "OVRE,Disable Overrun Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,Disable TXRDY Interrupt" "0,1"
|
|
bitfld.long 0x4 0. "RXRDY,Disable RXRDY Interrupt" "0,1"
|
|
rgroup.long 0x10++0xB
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 15. "CMP,Mask Comparison Interrupt" "0,1"
|
|
bitfld.long 0x0 9. "TXEMPTY,Mask TXEMPTY Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Mask Time-out Interrupt" "0,1"
|
|
bitfld.long 0x0 7. "PARE,Mask Parity Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Mask Framing Error Interrupt" "0,1"
|
|
bitfld.long 0x0 5. "OVRE,Mask Overrun Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Disable TXRDY Interrupt" "0,1"
|
|
bitfld.long 0x0 0. "RXRDY,Mask RXRDY Interrupt" "0,1"
|
|
line.long 0x4 "SR,Status Register"
|
|
bitfld.long 0x4 23. "WKUPREQ,Wake-Up Request" "0,1"
|
|
bitfld.long 0x4 22. "CLKREQ,Clock Request" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "SWES,SleepWalking Enable Status" "0,1"
|
|
bitfld.long 0x4 15. "CMP,Comparison Match" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty" "0,1"
|
|
bitfld.long 0x4 8. "TIMEOUT,Receiver Time-out" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
|
|
bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
|
|
bitfld.long 0x4 1. "TXRDY,Transmitter Ready" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Receiver Ready" "0,1"
|
|
line.long 0x8 "RHR,Receive Holding Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RXCHR,Received Character"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "THR,Transmit Holding Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXCHR,Character to be Transmitted"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "BRGR,Baud Rate Generator Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divisor"
|
|
line.long 0x4 "CMPR,Comparison Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "VAL2,Second Comparison Value for Received Character"
|
|
bitfld.long 0x4 14. "CMPPAR,Compare Parity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
hexmask.long.byte 0x4 0.--7. 1. "VAL1,First Comparison Value for Received Character"
|
|
line.long 0x8 "RTOR,Receiver Time-out Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "TO,Time-out Value"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
tree.end
|
|
tree "UART2"
|
|
base ad:0xF8024000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 15. "DBGE,Debug Enable" "0,1"
|
|
bitfld.long 0x0 12. "REQCLR,Request Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "STTTO,Start Time-out" "0,1"
|
|
bitfld.long 0x0 10. "RETTO,Rearm Time-out" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status" "0,1"
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic echo,2: Local loopback,3: Remote loopback"
|
|
bitfld.long 0x0 12. "BRSRCCK,Baud Rate Source Clock" "0: The baud rate is driven by the peripheral clock,1: The baud rate is driven by a PMC-programmable.."
|
|
newline
|
|
bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even Parity,1: Odd Parity,2: Space: parity forced to 0,3: Mark: parity forced to 1,4: No parity,?,?,?"
|
|
bitfld.long 0x0 4. "FILTER,Receiver Digital Filter" "0: UART does not filter the receive line.,1: UART filters the receive line using a.."
|
|
wgroup.long 0x8++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 15. "CMP,Enable Comparison Interrupt" "0,1"
|
|
bitfld.long 0x0 9. "TXEMPTY,Enable TXEMPTY Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Enable Time-out Interrupt" "0,1"
|
|
bitfld.long 0x0 7. "PARE,Enable Parity Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Enable Framing Error Interrupt" "0,1"
|
|
bitfld.long 0x0 5. "OVRE,Enable Overrun Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Enable TXRDY Interrupt" "0,1"
|
|
bitfld.long 0x0 0. "RXRDY,Enable RXRDY Interrupt" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 15. "CMP,Disable Comparison Interrupt" "0,1"
|
|
bitfld.long 0x4 9. "TXEMPTY,Disable TXEMPTY Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Disable Time-out Interrupt" "0,1"
|
|
bitfld.long 0x4 7. "PARE,Disable Parity Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Disable Framing Error Interrupt" "0,1"
|
|
bitfld.long 0x4 5. "OVRE,Disable Overrun Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,Disable TXRDY Interrupt" "0,1"
|
|
bitfld.long 0x4 0. "RXRDY,Disable RXRDY Interrupt" "0,1"
|
|
rgroup.long 0x10++0xB
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 15. "CMP,Mask Comparison Interrupt" "0,1"
|
|
bitfld.long 0x0 9. "TXEMPTY,Mask TXEMPTY Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Mask Time-out Interrupt" "0,1"
|
|
bitfld.long 0x0 7. "PARE,Mask Parity Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Mask Framing Error Interrupt" "0,1"
|
|
bitfld.long 0x0 5. "OVRE,Mask Overrun Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Disable TXRDY Interrupt" "0,1"
|
|
bitfld.long 0x0 0. "RXRDY,Mask RXRDY Interrupt" "0,1"
|
|
line.long 0x4 "SR,Status Register"
|
|
bitfld.long 0x4 23. "WKUPREQ,Wake-Up Request" "0,1"
|
|
bitfld.long 0x4 22. "CLKREQ,Clock Request" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "SWES,SleepWalking Enable Status" "0,1"
|
|
bitfld.long 0x4 15. "CMP,Comparison Match" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty" "0,1"
|
|
bitfld.long 0x4 8. "TIMEOUT,Receiver Time-out" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
|
|
bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
|
|
bitfld.long 0x4 1. "TXRDY,Transmitter Ready" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Receiver Ready" "0,1"
|
|
line.long 0x8 "RHR,Receive Holding Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RXCHR,Received Character"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "THR,Transmit Holding Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXCHR,Character to be Transmitted"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "BRGR,Baud Rate Generator Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divisor"
|
|
line.long 0x4 "CMPR,Comparison Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "VAL2,Second Comparison Value for Received Character"
|
|
bitfld.long 0x4 14. "CMPPAR,Compare Parity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
hexmask.long.byte 0x4 0.--7. 1. "VAL1,First Comparison Value for Received Character"
|
|
line.long 0x8 "RTOR,Receiver Time-out Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "TO,Time-out Value"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
tree.end
|
|
tree "UART3"
|
|
base ad:0xFC008000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 15. "DBGE,Debug Enable" "0,1"
|
|
bitfld.long 0x0 12. "REQCLR,Request Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "STTTO,Start Time-out" "0,1"
|
|
bitfld.long 0x0 10. "RETTO,Rearm Time-out" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status" "0,1"
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic echo,2: Local loopback,3: Remote loopback"
|
|
bitfld.long 0x0 12. "BRSRCCK,Baud Rate Source Clock" "0: The baud rate is driven by the peripheral clock,1: The baud rate is driven by a PMC-programmable.."
|
|
newline
|
|
bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even Parity,1: Odd Parity,2: Space: parity forced to 0,3: Mark: parity forced to 1,4: No parity,?,?,?"
|
|
bitfld.long 0x0 4. "FILTER,Receiver Digital Filter" "0: UART does not filter the receive line.,1: UART filters the receive line using a.."
|
|
wgroup.long 0x8++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 15. "CMP,Enable Comparison Interrupt" "0,1"
|
|
bitfld.long 0x0 9. "TXEMPTY,Enable TXEMPTY Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Enable Time-out Interrupt" "0,1"
|
|
bitfld.long 0x0 7. "PARE,Enable Parity Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Enable Framing Error Interrupt" "0,1"
|
|
bitfld.long 0x0 5. "OVRE,Enable Overrun Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Enable TXRDY Interrupt" "0,1"
|
|
bitfld.long 0x0 0. "RXRDY,Enable RXRDY Interrupt" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 15. "CMP,Disable Comparison Interrupt" "0,1"
|
|
bitfld.long 0x4 9. "TXEMPTY,Disable TXEMPTY Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Disable Time-out Interrupt" "0,1"
|
|
bitfld.long 0x4 7. "PARE,Disable Parity Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Disable Framing Error Interrupt" "0,1"
|
|
bitfld.long 0x4 5. "OVRE,Disable Overrun Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,Disable TXRDY Interrupt" "0,1"
|
|
bitfld.long 0x4 0. "RXRDY,Disable RXRDY Interrupt" "0,1"
|
|
rgroup.long 0x10++0xB
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 15. "CMP,Mask Comparison Interrupt" "0,1"
|
|
bitfld.long 0x0 9. "TXEMPTY,Mask TXEMPTY Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Mask Time-out Interrupt" "0,1"
|
|
bitfld.long 0x0 7. "PARE,Mask Parity Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Mask Framing Error Interrupt" "0,1"
|
|
bitfld.long 0x0 5. "OVRE,Mask Overrun Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Disable TXRDY Interrupt" "0,1"
|
|
bitfld.long 0x0 0. "RXRDY,Mask RXRDY Interrupt" "0,1"
|
|
line.long 0x4 "SR,Status Register"
|
|
bitfld.long 0x4 23. "WKUPREQ,Wake-Up Request" "0,1"
|
|
bitfld.long 0x4 22. "CLKREQ,Clock Request" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "SWES,SleepWalking Enable Status" "0,1"
|
|
bitfld.long 0x4 15. "CMP,Comparison Match" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty" "0,1"
|
|
bitfld.long 0x4 8. "TIMEOUT,Receiver Time-out" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
|
|
bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
|
|
bitfld.long 0x4 1. "TXRDY,Transmitter Ready" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Receiver Ready" "0,1"
|
|
line.long 0x8 "RHR,Receive Holding Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RXCHR,Received Character"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "THR,Transmit Holding Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXCHR,Character to be Transmitted"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "BRGR,Baud Rate Generator Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divisor"
|
|
line.long 0x4 "CMPR,Comparison Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "VAL2,Second Comparison Value for Received Character"
|
|
bitfld.long 0x4 14. "CMPPAR,Compare Parity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
hexmask.long.byte 0x4 0.--7. 1. "VAL1,First Comparison Value for Received Character"
|
|
line.long 0x8 "RTOR,Receiver Time-out Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "TO,Time-out Value"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
tree.end
|
|
tree "UART4"
|
|
base ad:0xFC00C000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 15. "DBGE,Debug Enable" "0,1"
|
|
bitfld.long 0x0 12. "REQCLR,Request Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "STTTO,Start Time-out" "0,1"
|
|
bitfld.long 0x0 10. "RETTO,Rearm Time-out" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status" "0,1"
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic echo,2: Local loopback,3: Remote loopback"
|
|
bitfld.long 0x0 12. "BRSRCCK,Baud Rate Source Clock" "0: The baud rate is driven by the peripheral clock,1: The baud rate is driven by a PMC-programmable.."
|
|
newline
|
|
bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even Parity,1: Odd Parity,2: Space: parity forced to 0,3: Mark: parity forced to 1,4: No parity,?,?,?"
|
|
bitfld.long 0x0 4. "FILTER,Receiver Digital Filter" "0: UART does not filter the receive line.,1: UART filters the receive line using a.."
|
|
wgroup.long 0x8++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 15. "CMP,Enable Comparison Interrupt" "0,1"
|
|
bitfld.long 0x0 9. "TXEMPTY,Enable TXEMPTY Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Enable Time-out Interrupt" "0,1"
|
|
bitfld.long 0x0 7. "PARE,Enable Parity Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Enable Framing Error Interrupt" "0,1"
|
|
bitfld.long 0x0 5. "OVRE,Enable Overrun Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Enable TXRDY Interrupt" "0,1"
|
|
bitfld.long 0x0 0. "RXRDY,Enable RXRDY Interrupt" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 15. "CMP,Disable Comparison Interrupt" "0,1"
|
|
bitfld.long 0x4 9. "TXEMPTY,Disable TXEMPTY Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Disable Time-out Interrupt" "0,1"
|
|
bitfld.long 0x4 7. "PARE,Disable Parity Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Disable Framing Error Interrupt" "0,1"
|
|
bitfld.long 0x4 5. "OVRE,Disable Overrun Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,Disable TXRDY Interrupt" "0,1"
|
|
bitfld.long 0x4 0. "RXRDY,Disable RXRDY Interrupt" "0,1"
|
|
rgroup.long 0x10++0xB
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 15. "CMP,Mask Comparison Interrupt" "0,1"
|
|
bitfld.long 0x0 9. "TXEMPTY,Mask TXEMPTY Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Mask Time-out Interrupt" "0,1"
|
|
bitfld.long 0x0 7. "PARE,Mask Parity Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Mask Framing Error Interrupt" "0,1"
|
|
bitfld.long 0x0 5. "OVRE,Mask Overrun Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Disable TXRDY Interrupt" "0,1"
|
|
bitfld.long 0x0 0. "RXRDY,Mask RXRDY Interrupt" "0,1"
|
|
line.long 0x4 "SR,Status Register"
|
|
bitfld.long 0x4 23. "WKUPREQ,Wake-Up Request" "0,1"
|
|
bitfld.long 0x4 22. "CLKREQ,Clock Request" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "SWES,SleepWalking Enable Status" "0,1"
|
|
bitfld.long 0x4 15. "CMP,Comparison Match" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty" "0,1"
|
|
bitfld.long 0x4 8. "TIMEOUT,Receiver Time-out" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
|
|
bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
|
|
bitfld.long 0x4 1. "TXRDY,Transmitter Ready" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Receiver Ready" "0,1"
|
|
line.long 0x8 "RHR,Receive Holding Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RXCHR,Received Character"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "THR,Transmit Holding Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXCHR,Character to be Transmitted"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "BRGR,Baud Rate Generator Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divisor"
|
|
line.long 0x4 "CMPR,Comparison Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "VAL2,Second Comparison Value for Received Character"
|
|
bitfld.long 0x4 14. "CMPPAR,Compare Parity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
hexmask.long.byte 0x4 0.--7. 1. "VAL1,First Comparison Value for Received Character"
|
|
line.long 0x8 "RTOR,Receiver Time-out Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "TO,Time-out Value"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "UDPHS (USB Device High Speed Port)"
|
|
base ad:0xFC02C000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,UDPHS Control Register"
|
|
bitfld.long 0x0 11. "PULLD_DIS,Pulldown Disable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 10. "REWAKEUP,Send Remote Wakeup (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 9. "DETACH,Detach Command" "0,1"
|
|
bitfld.long 0x0 8. "EN_UDPHS,UDPHS Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "FADDR_EN,Function Address Enable (cleared upon USB reset)" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "DEV_ADDR,UDPHS Address (cleared upon USB reset)"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "FNUM,UDPHS Frame Number Register"
|
|
bitfld.long 0x0 31. "FNUM_ERR,Frame Number CRC Error (cleared upon USB reset)" "0,1"
|
|
hexmask.long.word 0x0 3.--13. 1. "FRAME_NUMBER,Frame Number as defined in the Packet Field Formats (cleared upon USB reset)"
|
|
bitfld.long 0x0 0.--2. "MICRO_FRAME_NUM,Microframe Number (cleared upon USB reset)" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "IEN,UDPHS Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "DMA_7,DMA Channel 7 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 30. "DMA_6,DMA Channel 6 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 29. "DMA_5,DMA Channel 5 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 28. "DMA_4,DMA Channel 4 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "DMA_3,DMA Channel 3 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 26. "DMA_2,DMA Channel 2 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 25. "DMA_1,DMA Channel 1 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 23. "EPT_15,Endpoint 15 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "EPT_14,Endpoint 14 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 21. "EPT_13,Endpoint 13 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 20. "EPT_12,Endpoint 12 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 19. "EPT_11,Endpoint 11 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "EPT_10,Endpoint 10 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 17. "EPT_9,Endpoint 9 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 16. "EPT_8,Endpoint 8 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 15. "EPT_7,Endpoint 7 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "EPT_6,Endpoint 6 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 13. "EPT_5,Endpoint 5 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 12. "EPT_4,Endpoint 4 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 11. "EPT_3,Endpoint 3 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EPT_2,Endpoint 2 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 9. "EPT_1,Endpoint 1 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 8. "EPT_0,Endpoint 0 Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 7. "UPSTR_RES,Upstream Resume Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "ENDOFRSM,End Of Resume Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 5. "WAKE_UP,Wake Up CPU Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 4. "ENDRESET,End Of Reset Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 3. "INT_SOF,SOF Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MICRO_SOF,Micro-SOF Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 1. "DET_SUSPD,Suspend Interrupt Enable (cleared upon USB reset)" "0,1"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "INTSTA,UDPHS Interrupt Status Register"
|
|
bitfld.long 0x0 31. "DMA_7,DMA Channel 7 Interrupt" "0,1"
|
|
bitfld.long 0x0 30. "DMA_6,DMA Channel 6 Interrupt" "0,1"
|
|
bitfld.long 0x0 29. "DMA_5,DMA Channel 5 Interrupt" "0,1"
|
|
bitfld.long 0x0 28. "DMA_4,DMA Channel 4 Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "DMA_3,DMA Channel 3 Interrupt" "0,1"
|
|
bitfld.long 0x0 26. "DMA_2,DMA Channel 2 Interrupt" "0,1"
|
|
bitfld.long 0x0 25. "DMA_1,DMA Channel 1 Interrupt" "0,1"
|
|
bitfld.long 0x0 23. "EPT_15,Endpoint 15 Interrupt (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "EPT_14,Endpoint 14 Interrupt (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 21. "EPT_13,Endpoint 13 Interrupt (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 20. "EPT_12,Endpoint 12 Interrupt (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 19. "EPT_11,Endpoint 11 Interrupt (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "EPT_10,Endpoint 10 Interrupt (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 17. "EPT_9,Endpoint 9 Interrupt (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 16. "EPT_8,Endpoint 8 Interrupt (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 15. "EPT_7,Endpoint 7 Interrupt (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "EPT_6,Endpoint 6 Interrupt (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 13. "EPT_5,Endpoint 5 Interrupt (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 12. "EPT_4,Endpoint 4 Interrupt (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 11. "EPT_3,Endpoint 3 Interrupt (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EPT_2,Endpoint 2 Interrupt (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 9. "EPT_1,Endpoint 1 Interrupt (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 8. "EPT_0,Endpoint 0 Interrupt (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 7. "UPSTR_RES,Upstream Resume Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "ENDOFRSM,End Of Resume Interrupt" "0,1"
|
|
bitfld.long 0x0 5. "WAKE_UP,Wake Up CPU Interrupt" "0,1"
|
|
bitfld.long 0x0 4. "ENDRESET,End Of Reset Interrupt" "0,1"
|
|
bitfld.long 0x0 3. "INT_SOF,Start Of Frame Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MICRO_SOF,Micro Start Of Frame Interrupt" "0,1"
|
|
bitfld.long 0x0 1. "DET_SUSPD,Suspend Interrupt" "0,1"
|
|
bitfld.long 0x0 0. "SPEED,Speed Status" "0,1"
|
|
wgroup.long 0x18++0x7
|
|
line.long 0x0 "CLRINT,UDPHS Clear Interrupt Register"
|
|
bitfld.long 0x0 7. "UPSTR_RES,Upstream Resume Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 6. "ENDOFRSM,End Of Resume Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 5. "WAKE_UP,Wake Up CPU Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 4. "ENDRESET,End Of Reset Interrupt Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_SOF,Start Of Frame Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 2. "MICRO_SOF,Micro Start Of Frame Interrupt Clear" "0,1"
|
|
bitfld.long 0x0 1. "DET_SUSPD,Suspend Interrupt Clear" "0,1"
|
|
line.long 0x4 "EPTRST,UDPHS Endpoints Reset Register"
|
|
bitfld.long 0x4 15. "EPT_15,Endpoint 15 Reset" "0,1"
|
|
bitfld.long 0x4 14. "EPT_14,Endpoint 14 Reset" "0,1"
|
|
bitfld.long 0x4 13. "EPT_13,Endpoint 13 Reset" "0,1"
|
|
bitfld.long 0x4 12. "EPT_12,Endpoint 12 Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "EPT_11,Endpoint 11 Reset" "0,1"
|
|
bitfld.long 0x4 10. "EPT_10,Endpoint 10 Reset" "0,1"
|
|
bitfld.long 0x4 9. "EPT_9,Endpoint 9 Reset" "0,1"
|
|
bitfld.long 0x4 8. "EPT_8,Endpoint 8 Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "EPT_7,Endpoint 7 Reset" "0,1"
|
|
bitfld.long 0x4 6. "EPT_6,Endpoint 6 Reset" "0,1"
|
|
bitfld.long 0x4 5. "EPT_5,Endpoint 5 Reset" "0,1"
|
|
bitfld.long 0x4 4. "EPT_4,Endpoint 4 Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "EPT_3,Endpoint 3 Reset" "0,1"
|
|
bitfld.long 0x4 2. "EPT_2,Endpoint 2 Reset" "0,1"
|
|
bitfld.long 0x4 1. "EPT_1,Endpoint 1 Reset" "0,1"
|
|
bitfld.long 0x4 0. "EPT_0,Endpoint 0 Reset" "0,1"
|
|
group.long 0xE0++0x3
|
|
line.long 0x0 "TST,UDPHS Test Register"
|
|
bitfld.long 0x0 5. "OPMODE2,OpMode2" "0,1"
|
|
bitfld.long 0x0 4. "TST_PKT,Test Packet Mode" "0,1"
|
|
bitfld.long 0x0 3. "TST_K,Test K Mode" "0,1"
|
|
bitfld.long 0x0 2. "TST_J,Test J Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SPEED_CFG,Speed Configuration" "0: Normal mode: The macro is in Full Speed mode..,?,2: Force High Speed: Set this value to force the..,3: Force Full Speed: Set this value to force the.."
|
|
rgroup.long 0xEC++0x3
|
|
line.long 0x0 "ADDRSIZE,UDPHS IP Address Size Register"
|
|
hexmask.long 0x0 0.--31. 1. "ADDRSIZE,Peripheral Bus Address Size"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0xF0)++0x3
|
|
line.long 0x0 "IPNAME[$1],UDPHS IP Name1 Register"
|
|
hexmask.long 0x0 0.--31. 1. "IPNAME,IP Name in ASCII Format"
|
|
repeat.end
|
|
rgroup.long 0xF8++0x3
|
|
line.long 0x0 "FEATURES,UDPHS Features Register"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0xFC02C100 ad:0xFC02C120 ad:0xFC02C140 ad:0xFC02C160 ad:0xFC02C180 ad:0xFC02C1A0 ad:0xFC02C1C0 ad:0xFC02C1E0 ad:0xFC02C200 ad:0xFC02C220 ad:0xFC02C240 ad:0xFC02C260 ad:0xFC02C280 ad:0xFC02C2A0 ad:0xFC02C2C0 ad:0xFC02C2E0)
|
|
tree "UDPHS_EPT[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "EPTCFG,UDPHS Endpoint Configuration Register (endpoint = 0)"
|
|
bitfld.long 0x0 31. "EPT_MAPD,Endpoint Mapped (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 8.--9. "NB_TRANS,Number Of Transaction per Microframe (cleared upon USB reset)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "BK_NUMBER,Number of Banks (cleared upon USB reset)" "0: Zero bank the endpoint is not mapped in memory,1: One bank (bank 0),2: Double bank (Ping-Pong: bank0/bank1),3: Triple bank (bank0/bank1/bank2)"
|
|
bitfld.long 0x0 4.--5. "EPT_TYPE,Endpoint Type (cleared upon USB reset)" "0: Control endpoint,1: Isochronous endpoint,2: Bulk endpoint,3: Interrupt endpoint"
|
|
newline
|
|
bitfld.long 0x0 3. "EPT_DIR,Endpoint Direction (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 0.--2. "EPT_SIZE,Endpoint Size (cleared upon USB reset)" "0: 8 bytes,1: 16 bytes,2: 32 bytes,3: 64 bytes,4: 128 bytes,5: 256 bytes,6: 512 bytes,7: 1024 bytes"
|
|
wgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "EPTCTLENB,UDPHS Endpoint Control Enable Register (endpoint = 0)"
|
|
bitfld.long 0x0 31. "SHRT_PCKT,Short Packet Send/Short Packet Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 18. "BUSY_BANK,Busy Bank Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "NAK_OUT,NAKOUT Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 14. "NAK_IN,NAKIN Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "STALL_SNT,Stall Sent Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 12. "RX_SETUP,Received SETUP" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXRDY,TX Packet Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 10. "TX_COMPLT,Transmitted IN Data Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RXRDY_TXKL,Received OUT Data Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "ERR_OVFLW,Overflow Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "NYET_DIS,NYET Disable (Only for High Speed Bulk OUT endpoints)" "0,1"
|
|
bitfld.long 0x0 3. "INTDIS_DMA,Interrupts Disable DMA" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "AUTO_VALID,Packet Auto-Valid Enable" "0,1"
|
|
bitfld.long 0x0 0. "EPT_ENABL,Endpoint Enable" "0,1"
|
|
wgroup.long ($2+0x4)++0x7
|
|
line.long 0x0 "EPTCTLENB_ISOENDPT_MODE,UDPHS Endpoint Control Enable Register (endpoint = 0)"
|
|
bitfld.long 0x0 31. "SHRT_PCKT,Short Packet Send/Short Packet Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 18. "BUSY_BANK,Busy Bank Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "ERR_FLUSH,Bank Flush Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 13. "ERR_CRC_NTR,ISO CRC Error/Number of Transaction Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ERR_FL_ISO,Error Flow Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 11. "TXRDY_TRER,TX Packet Ready/Transaction Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "TX_COMPLT,Transmitted IN Data Complete Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 9. "RXRDY_TXKL,Received OUT Data Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ERR_OVFLW,Overflow Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 7. "MDATA_RX,MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "DATAX_RX,DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)" "0,1"
|
|
bitfld.long 0x0 3. "INTDIS_DMA,Interrupts Disable DMA" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "AUTO_VALID,Packet Auto-Valid Enable" "0,1"
|
|
bitfld.long 0x0 0. "EPT_ENABL,Endpoint Enable" "0,1"
|
|
line.long 0x4 "EPTCTLDIS,UDPHS Endpoint Control Disable Register (endpoint = 0)"
|
|
bitfld.long 0x4 31. "SHRT_PCKT,Short Packet Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 18. "BUSY_BANK,Busy Bank Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "NAK_OUT,NAKOUT Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 14. "NAK_IN,NAKIN Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "STALL_SNT,Stall Sent Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 12. "RX_SETUP,Received SETUP Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TXRDY,TX Packet Ready Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 10. "TX_COMPLT,Transmitted IN Data Complete Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "RXRDY_TXKL,Received OUT Data Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "ERR_OVFLW,Overflow Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "NYET_DIS,NYET Enable (Only for High Speed Bulk OUT endpoints)" "0,1"
|
|
bitfld.long 0x4 3. "INTDIS_DMA,Interrupts Disable DMA" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "AUTO_VALID,Packet Auto-Valid Disable" "0,1"
|
|
bitfld.long 0x4 0. "EPT_DISABL,Endpoint Disable" "0,1"
|
|
wgroup.long ($2+0x8)++0x3
|
|
line.long 0x0 "EPTCTLDIS_ISOENDPT_MODE,UDPHS Endpoint Control Disable Register (endpoint = 0)"
|
|
bitfld.long 0x0 31. "SHRT_PCKT,Short Packet Interrupt Disable" "0,1"
|
|
bitfld.long 0x0 18. "BUSY_BANK,Busy Bank Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "ERR_FLUSH,bank flush error Interrupt Disable" "0,1"
|
|
bitfld.long 0x0 13. "ERR_CRC_NTR,ISO CRC Error/Number of Transaction Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ERR_FL_ISO,Error Flow Interrupt Disable" "0,1"
|
|
bitfld.long 0x0 11. "TXRDY_TRER,TX Packet Ready/Transaction Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "TX_COMPLT,Transmitted IN Data Complete Interrupt Disable" "0,1"
|
|
bitfld.long 0x0 9. "RXRDY_TXKL,Received OUT Data Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ERR_OVFLW,Overflow Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x0 7. "MDATA_RX,MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "DATAX_RX,DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints)" "0,1"
|
|
bitfld.long 0x0 3. "INTDIS_DMA,Interrupts Disable DMA" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "AUTO_VALID,Packet Auto-Valid Disable" "0,1"
|
|
bitfld.long 0x0 0. "EPT_DISABL,Endpoint Disable" "0,1"
|
|
rgroup.long ($2+0xC)++0x3
|
|
line.long 0x0 "EPTCTL,UDPHS Endpoint Control Register (endpoint = 0)"
|
|
bitfld.long 0x0 31. "SHRT_PCKT,Short Packet Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 18. "BUSY_BANK,Busy Bank Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "NAK_OUT,NAKOUT Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 14. "NAK_IN,NAKIN Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "STALL_SNT,Stall Sent Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 12. "RX_SETUP,Received SETUP Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXRDY,TX Packet Ready Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 10. "TX_COMPLT,Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RXRDY_TXKL,Received OUT Data Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 8. "ERR_OVFLW,Overflow Error Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "NYET_DIS,NYET Disable (Only for High Speed Bulk OUT Endpoints) (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 3. "INTDIS_DMA,Interrupt Disables DMA (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "AUTO_VALID,Packet Auto-Valid Enabled (Not for CONTROL Endpoints) (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 0. "EPT_ENABL,Endpoint Enable (cleared upon USB reset)" "0,1"
|
|
rgroup.long ($2+0xC)++0x3
|
|
line.long 0x0 "EPTCTL_ISOENDPT_MODE,UDPHS Endpoint Control Register (endpoint = 0)"
|
|
bitfld.long 0x0 31. "SHRT_PCKT,Short Packet Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 18. "BUSY_BANK,Busy Bank Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "ERR_FLUSH,Bank Flush Error Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 13. "ERR_CRC_NTR,ISO CRC Error/Number of Transaction Error Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ERR_FL_ISO,Error Flow Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 11. "TXRDY_TRER,TX Packet Ready/Transaction Error Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "TX_COMPLT,Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 9. "RXRDY_TXKL,Received OUT Data Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ERR_OVFLW,Overflow Error Interrupt Enabled (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 7. "MDATA_RX,MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "DATAX_RX,DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 3. "INTDIS_DMA,Interrupt Disables DMA (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "AUTO_VALID,Packet Auto-Valid Enabled (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 0. "EPT_ENABL,Endpoint Enable (cleared upon USB reset)" "0,1"
|
|
wgroup.long ($2+0x14)++0x3
|
|
line.long 0x0 "EPTSETSTA,UDPHS Endpoint Set Status Register (endpoint = 0)"
|
|
bitfld.long 0x0 11. "TXRDY,TX Packet Ready Set" "0,1"
|
|
bitfld.long 0x0 9. "RXRDY_TXKL,KILL Bank Set (for IN Endpoint)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "FRCESTALL,Stall Handshake Request Set" "0,1"
|
|
wgroup.long ($2+0x14)++0x7
|
|
line.long 0x0 "EPTSETSTA_ISOENDPT_MODE,UDPHS Endpoint Set Status Register (endpoint = 0)"
|
|
bitfld.long 0x0 11. "TXRDY_TRER,TX Packet Ready Set" "0,1"
|
|
bitfld.long 0x0 9. "RXRDY_TXKL,KILL Bank Set (for IN Endpoint)" "0,1"
|
|
line.long 0x4 "EPTCLRSTA,UDPHS Endpoint Clear Status Register (endpoint = 0)"
|
|
bitfld.long 0x4 15. "NAK_OUT,NAKOUT Clear" "0,1"
|
|
bitfld.long 0x4 14. "NAK_IN,NAKIN Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "STALL_SNT,Stall Sent Clear" "0,1"
|
|
bitfld.long 0x4 12. "RX_SETUP,Received SETUP Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "TX_COMPLT,Transmitted IN Data Complete Clear" "0,1"
|
|
bitfld.long 0x4 9. "RXRDY_TXKL,Received OUT Data Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TOGGLESQ,Data Toggle Clear" "0,1"
|
|
bitfld.long 0x4 5. "FRCESTALL,Stall Handshake Request Clear" "0,1"
|
|
wgroup.long ($2+0x18)++0x3
|
|
line.long 0x0 "EPTCLRSTA_ISOENDPT_MODE,UDPHS Endpoint Clear Status Register (endpoint = 0)"
|
|
bitfld.long 0x0 14. "ERR_FLUSH,Bank Flush Error Clear" "0,1"
|
|
bitfld.long 0x0 13. "ERR_CRC_NTR,Number of Transaction Error Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ERR_FL_ISO,Error Flow Clear" "0,1"
|
|
bitfld.long 0x0 10. "TX_COMPLT,Transmitted IN Data Complete Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RXRDY_TXKL,Received OUT Data Clear" "0,1"
|
|
bitfld.long 0x0 6. "TOGGLESQ,Data Toggle Clear" "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "EPTSTA,UDPHS Endpoint Status Register (endpoint = 0)"
|
|
bitfld.long 0x0 31. "SHRT_PCKT,Short Packet (cleared upon USB reset)" "0,1"
|
|
hexmask.long.word 0x0 20.--30. 1. "BYTE_COUNT,UDPHS Byte Count (cleared upon USB reset)"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "BUSY_BANK_STA,Busy Bank Number (cleared upon USB reset)" "0: All banks are free,1: 1 busy bank,2: 2 busy banks,3: 3 busy banks"
|
|
bitfld.long 0x0 16.--17. "CURBK_CTLDIR,Current Bank/Control Direction (cleared upon USB reset)" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 15. "NAK_OUT,NAK OUT (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 14. "NAK_IN,NAK IN (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "STALL_SNT,Stall Sent (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 12. "RX_SETUP,Received SETUP (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXRDY,TX Packet Ready (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 10. "TX_COMPLT,Transmitted IN Data Complete (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RXRDY_TXKL,Received OUT Data/KILL Bank (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 8. "ERR_OVFLW,Overflow Error (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "TOGGLESQ_STA,Toggle Sequencing (cleared upon USB reset)" "0: DATA0,1: DATA1,2: Reserved for High Bandwidth Isochronous Endpoint,3: Reserved for High Bandwidth Isochronous Endpoint"
|
|
bitfld.long 0x0 5. "FRCESTALL,Stall Handshake Request (cleared upon USB reset)" "0,1"
|
|
rgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "EPTSTA_ISOENDPT_MODE,UDPHS Endpoint Status Register (endpoint = 0)"
|
|
bitfld.long 0x0 31. "SHRT_PCKT,Short Packet (cleared upon USB reset)" "0,1"
|
|
hexmask.long.word 0x0 20.--30. 1. "BYTE_COUNT,UDPHS Byte Count (cleared upon USB reset)"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "BUSY_BANK_STA,Busy Bank Number (cleared upon USB reset)" "0: All banks are free,1: 1 busy bank,2: 2 busy banks,3: 3 busy banks"
|
|
bitfld.long 0x0 16.--17. "CURBK,Current Bank (cleared upon USB reset)" "0: Bank 0 (or single bank),1: Bank 1,2: Bank 2,?"
|
|
newline
|
|
bitfld.long 0x0 14. "ERR_FLUSH,Bank Flush Error (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 13. "ERR_CRC_NTR,CRC ISO Error/Number of Transaction Error (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ERR_FL_ISO,Error Flow (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 11. "TXRDY_TRER,TX Packet Ready/Transaction Error (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "TX_COMPLT,Transmitted IN Data Complete (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 9. "RXRDY_TXKL,Received OUT Data/KILL Bank (cleared upon USB reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ERR_OVFLW,Overflow Error (cleared upon USB reset)" "0,1"
|
|
bitfld.long 0x0 6.--7. "TOGGLESQ_STA,Toggle Sequencing (cleared upon USB reset)" "0: DATA0,1: DATA1,2: Data2 (only for High Bandwidth Isochronous..,3: MData (only for High Bandwidth Isochronous.."
|
|
tree.end
|
|
repeat.end
|
|
repeat 7. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6)(list ad:0xFC02C300 ad:0xFC02C310 ad:0xFC02C320 ad:0xFC02C330 ad:0xFC02C340 ad:0xFC02C350 ad:0xFC02C360)
|
|
tree "UDPHS_DMA[$1]"
|
|
base $2
|
|
group.long ($2)++0xF
|
|
line.long 0x0 "DMANXTDSC,UDPHS DMA Next Descriptor Address Register (channel = 0)"
|
|
hexmask.long 0x0 0.--31. 1. "NXT_DSC_ADD,Next Descriptor Address"
|
|
line.long 0x4 "DMAADDRESS,UDPHS DMA Channel Address Register (channel = 0)"
|
|
hexmask.long 0x4 0.--31. 1. "BUFF_ADD,Buffer Address"
|
|
line.long 0x8 "DMACONTROL,UDPHS DMA Channel Control Register (channel = 0)"
|
|
hexmask.long.word 0x8 16.--31. 1. "BUFF_LENGTH,Buffer Byte Length (Write-only)"
|
|
bitfld.long 0x8 7. "BURST_LCK,Burst Lock Enable" "0,1"
|
|
bitfld.long 0x8 6. "DESC_LD_IT,Descriptor Loaded Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 5. "END_BUFFIT,End of Buffer Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 4. "END_TR_IT,End of Transfer Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 3. "END_B_EN,End of Buffer Enable (Control)" "0,1"
|
|
bitfld.long 0x8 2. "END_TR_EN,End of Transfer Enable (Control)" "0,1"
|
|
bitfld.long 0x8 1. "LDNXT_DSC,Load Next Channel Transfer Descriptor Enable (Command)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "CHANN_ENB,(Channel Enable Command)" "0,1"
|
|
line.long 0xC "DMASTATUS,UDPHS DMA Channel Status Register (channel = 0)"
|
|
hexmask.long.word 0xC 16.--31. 1. "BUFF_COUNT,Buffer Byte Count"
|
|
bitfld.long 0xC 6. "DESC_LDST,Descriptor Loaded Status" "0,1"
|
|
bitfld.long 0xC 5. "END_BF_ST,End of Channel Buffer Status" "0,1"
|
|
bitfld.long 0xC 4. "END_TR_ST,End of Channel Transfer Status" "0,1"
|
|
bitfld.long 0xC 1. "CHANN_ACT,Channel Active Status" "0,1"
|
|
bitfld.long 0xC 0. "CHANN_ENB,Channel Enable Status" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0xF8048040
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "KEY,Password"
|
|
bitfld.long 0x0 4. "LOCKMR,Lock Mode Register Write Access" "0,1"
|
|
bitfld.long 0x0 0. "WDRSTT,Watchdog Restart" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 29. "WDIDLEHLT,Watchdog Idle Halt" "0,1"
|
|
bitfld.long 0x0 28. "WDDBGHLT,Watchdog Debug Halt" "0,1"
|
|
hexmask.long.word 0x0 16.--27. 1. "WDD,Watchdog Delta Value"
|
|
bitfld.long 0x0 15. "WDDIS,Watchdog Disable" "0,1"
|
|
bitfld.long 0x0 13. "WDRSTEN,Watchdog Reset Enable" "0,1"
|
|
bitfld.long 0x0 12. "WDFIEN,Watchdog Fault Interrupt Enable" "0,1"
|
|
hexmask.long.word 0x0 0.--11. 1. "WDV,Watchdog Counter Value"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 1. "WDERR,Watchdog Error (cleared on read)" "0,1"
|
|
bitfld.long 0x0 0. "WDUNF,Watchdog Underflow (cleared on read)" "0,1"
|
|
tree.end
|
|
tree "XDMAC (Extensible DMA Controller)"
|
|
base ad:0x0
|
|
tree "XDMAC0"
|
|
base ad:0xF0010000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "GTYPE,Global Type Register"
|
|
hexmask.long.byte 0x0 16.--22. 1. "NB_REQ,Number of Peripheral Requests Minus One"
|
|
hexmask.long.word 0x0 5.--15. 1. "FIFO_SZ,Number of Bytes"
|
|
hexmask.long.byte 0x0 0.--4. 1. "NB_CH,Number of Channels Minus One"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "GCFG,Global Configuration Register"
|
|
bitfld.long 0x0 8. "BXKBEN,Boundary X Kilobyte Enable" "0,1"
|
|
bitfld.long 0x0 3. "CGDISIF,Bus Interface Clock Gating Disable" "0,1"
|
|
bitfld.long 0x0 2. "CGDISFIFO,FIFO Clock Gating Disable" "0,1"
|
|
bitfld.long 0x0 1. "CGDISPIPE,Pipeline Clock Gating Disable" "0,1"
|
|
bitfld.long 0x0 0. "CGDISREG,Configuration Registers Clock Gating Disable" "0,1"
|
|
line.long 0x4 "GWAC,Global Weighted Arbiter Configuration Register"
|
|
hexmask.long.byte 0x4 12.--15. 1. "PW3,Pool Weight 3"
|
|
hexmask.long.byte 0x4 8.--11. 1. "PW2,Pool Weight 2"
|
|
hexmask.long.byte 0x4 4.--7. 1. "PW1,Pool Weight 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PW0,Pool Weight 0"
|
|
wgroup.long 0xC++0x7
|
|
line.long 0x0 "GIE,Global Interrupt Enable Register"
|
|
bitfld.long 0x0 15. "IE15,XDMAC Channel 15 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 14. "IE14,XDMAC Channel 14 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 13. "IE13,XDMAC Channel 13 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 12. "IE12,XDMAC Channel 12 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 11. "IE11,XDMAC Channel 11 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 10. "IE10,XDMAC Channel 10 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 9. "IE9,XDMAC Channel 9 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 8. "IE8,XDMAC Channel 8 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 7. "IE7,XDMAC Channel 7 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 6. "IE6,XDMAC Channel 6 Interrupt Enable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IE5,XDMAC Channel 5 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 4. "IE4,XDMAC Channel 4 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 3. "IE3,XDMAC Channel 3 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 2. "IE2,XDMAC Channel 2 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 1. "IE1,XDMAC Channel 1 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 0. "IE0,XDMAC Channel 0 Interrupt Enable Bit" "0,1"
|
|
line.long 0x4 "GID,Global Interrupt Disable Register"
|
|
bitfld.long 0x4 15. "ID15,XDMAC Channel 15 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 14. "ID14,XDMAC Channel 14 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 13. "ID13,XDMAC Channel 13 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 12. "ID12,XDMAC Channel 12 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 11. "ID11,XDMAC Channel 11 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 10. "ID10,XDMAC Channel 10 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 9. "ID9,XDMAC Channel 9 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 8. "ID8,XDMAC Channel 8 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 7. "ID7,XDMAC Channel 7 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 6. "ID6,XDMAC Channel 6 Interrupt Disable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "ID5,XDMAC Channel 5 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 4. "ID4,XDMAC Channel 4 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 3. "ID3,XDMAC Channel 3 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 2. "ID2,XDMAC Channel 2 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 1. "ID1,XDMAC Channel 1 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 0. "ID0,XDMAC Channel 0 Interrupt Disable Bit" "0,1"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "GIM,Global Interrupt Mask Register"
|
|
bitfld.long 0x0 15. "IM15,XDMAC Channel 15 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 14. "IM14,XDMAC Channel 14 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 13. "IM13,XDMAC Channel 13 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 12. "IM12,XDMAC Channel 12 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 11. "IM11,XDMAC Channel 11 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 10. "IM10,XDMAC Channel 10 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 9. "IM9,XDMAC Channel 9 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 8. "IM8,XDMAC Channel 8 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 7. "IM7,XDMAC Channel 7 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 6. "IM6,XDMAC Channel 6 Interrupt Mask Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IM5,XDMAC Channel 5 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 4. "IM4,XDMAC Channel 4 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 3. "IM3,XDMAC Channel 3 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 2. "IM2,XDMAC Channel 2 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 1. "IM1,XDMAC Channel 1 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 0. "IM0,XDMAC Channel 0 Interrupt Mask Bit" "0,1"
|
|
line.long 0x4 "GIS,Global Interrupt Status Register"
|
|
bitfld.long 0x4 15. "IS15,XDMAC Channel 15 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 14. "IS14,XDMAC Channel 14 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 13. "IS13,XDMAC Channel 13 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 12. "IS12,XDMAC Channel 12 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 11. "IS11,XDMAC Channel 11 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 10. "IS10,XDMAC Channel 10 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 9. "IS9,XDMAC Channel 9 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 8. "IS8,XDMAC Channel 8 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 7. "IS7,XDMAC Channel 7 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 6. "IS6,XDMAC Channel 6 Interrupt Status Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "IS5,XDMAC Channel 5 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 4. "IS4,XDMAC Channel 4 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 3. "IS3,XDMAC Channel 3 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 2. "IS2,XDMAC Channel 2 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 1. "IS1,XDMAC Channel 1 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 0. "IS0,XDMAC Channel 0 Interrupt Status Bit" "0,1"
|
|
wgroup.long 0x1C++0x7
|
|
line.long 0x0 "GE,Global Channel Enable Register"
|
|
bitfld.long 0x0 15. "EN15,XDMAC Channel 15 Enable Bit" "0,1"
|
|
bitfld.long 0x0 14. "EN14,XDMAC Channel 14 Enable Bit" "0,1"
|
|
bitfld.long 0x0 13. "EN13,XDMAC Channel 13 Enable Bit" "0,1"
|
|
bitfld.long 0x0 12. "EN12,XDMAC Channel 12 Enable Bit" "0,1"
|
|
bitfld.long 0x0 11. "EN11,XDMAC Channel 11 Enable Bit" "0,1"
|
|
bitfld.long 0x0 10. "EN10,XDMAC Channel 10 Enable Bit" "0,1"
|
|
bitfld.long 0x0 9. "EN9,XDMAC Channel 9 Enable Bit" "0,1"
|
|
bitfld.long 0x0 8. "EN8,XDMAC Channel 8 Enable Bit" "0,1"
|
|
bitfld.long 0x0 7. "EN7,XDMAC Channel 7 Enable Bit" "0,1"
|
|
bitfld.long 0x0 6. "EN6,XDMAC Channel 6 Enable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EN5,XDMAC Channel 5 Enable Bit" "0,1"
|
|
bitfld.long 0x0 4. "EN4,XDMAC Channel 4 Enable Bit" "0,1"
|
|
bitfld.long 0x0 3. "EN3,XDMAC Channel 3 Enable Bit" "0,1"
|
|
bitfld.long 0x0 2. "EN2,XDMAC Channel 2 Enable Bit" "0,1"
|
|
bitfld.long 0x0 1. "EN1,XDMAC Channel 1 Enable Bit" "0,1"
|
|
bitfld.long 0x0 0. "EN0,XDMAC Channel 0 Enable Bit" "0,1"
|
|
line.long 0x4 "GD,Global Channel Disable Register"
|
|
bitfld.long 0x4 15. "DI15,XDMAC Channel 15 Disable Bit" "0,1"
|
|
bitfld.long 0x4 14. "DI14,XDMAC Channel 14 Disable Bit" "0,1"
|
|
bitfld.long 0x4 13. "DI13,XDMAC Channel 13 Disable Bit" "0,1"
|
|
bitfld.long 0x4 12. "DI12,XDMAC Channel 12 Disable Bit" "0,1"
|
|
bitfld.long 0x4 11. "DI11,XDMAC Channel 11 Disable Bit" "0,1"
|
|
bitfld.long 0x4 10. "DI10,XDMAC Channel 10 Disable Bit" "0,1"
|
|
bitfld.long 0x4 9. "DI9,XDMAC Channel 9 Disable Bit" "0,1"
|
|
bitfld.long 0x4 8. "DI8,XDMAC Channel 8 Disable Bit" "0,1"
|
|
bitfld.long 0x4 7. "DI7,XDMAC Channel 7 Disable Bit" "0,1"
|
|
bitfld.long 0x4 6. "DI6,XDMAC Channel 6 Disable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DI5,XDMAC Channel 5 Disable Bit" "0,1"
|
|
bitfld.long 0x4 4. "DI4,XDMAC Channel 4 Disable Bit" "0,1"
|
|
bitfld.long 0x4 3. "DI3,XDMAC Channel 3 Disable Bit" "0,1"
|
|
bitfld.long 0x4 2. "DI2,XDMAC Channel 2 Disable Bit" "0,1"
|
|
bitfld.long 0x4 1. "DI1,XDMAC Channel 1 Disable Bit" "0,1"
|
|
bitfld.long 0x4 0. "DI0,XDMAC Channel 0 Disable Bit" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "GS,Global Channel Status Register"
|
|
bitfld.long 0x0 15. "ST15,XDMAC Channel 15 Status Bit" "0,1"
|
|
bitfld.long 0x0 14. "ST14,XDMAC Channel 14 Status Bit" "0,1"
|
|
bitfld.long 0x0 13. "ST13,XDMAC Channel 13 Status Bit" "0,1"
|
|
bitfld.long 0x0 12. "ST12,XDMAC Channel 12 Status Bit" "0,1"
|
|
bitfld.long 0x0 11. "ST11,XDMAC Channel 11 Status Bit" "0,1"
|
|
bitfld.long 0x0 10. "ST10,XDMAC Channel 10 Status Bit" "0,1"
|
|
bitfld.long 0x0 9. "ST9,XDMAC Channel 9 Status Bit" "0,1"
|
|
bitfld.long 0x0 8. "ST8,XDMAC Channel 8 Status Bit" "0,1"
|
|
bitfld.long 0x0 7. "ST7,XDMAC Channel 7 Status Bit" "0,1"
|
|
bitfld.long 0x0 6. "ST6,XDMAC Channel 6 Status Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ST5,XDMAC Channel 5 Status Bit" "0,1"
|
|
bitfld.long 0x0 4. "ST4,XDMAC Channel 4 Status Bit" "0,1"
|
|
bitfld.long 0x0 3. "ST3,XDMAC Channel 3 Status Bit" "0,1"
|
|
bitfld.long 0x0 2. "ST2,XDMAC Channel 2 Status Bit" "0,1"
|
|
bitfld.long 0x0 1. "ST1,XDMAC Channel 1 Status Bit" "0,1"
|
|
bitfld.long 0x0 0. "ST0,XDMAC Channel 0 Status Bit" "0,1"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "GRS,Global Channel Read Suspend Register"
|
|
bitfld.long 0x0 15. "RS15,XDMAC Channel 15 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 14. "RS14,XDMAC Channel 14 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 13. "RS13,XDMAC Channel 13 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 12. "RS12,XDMAC Channel 12 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 11. "RS11,XDMAC Channel 11 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 10. "RS10,XDMAC Channel 10 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 9. "RS9,XDMAC Channel 9 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 8. "RS8,XDMAC Channel 8 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 7. "RS7,XDMAC Channel 7 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 6. "RS6,XDMAC Channel 6 Read Suspend Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RS5,XDMAC Channel 5 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 4. "RS4,XDMAC Channel 4 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 3. "RS3,XDMAC Channel 3 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 2. "RS2,XDMAC Channel 2 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 1. "RS1,XDMAC Channel 1 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 0. "RS0,XDMAC Channel 0 Read Suspend Bit" "0,1"
|
|
line.long 0x4 "GWS,Global Channel Write Suspend Register"
|
|
bitfld.long 0x4 15. "WS15,XDMAC Channel 15 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 14. "WS14,XDMAC Channel 14 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 13. "WS13,XDMAC Channel 13 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 12. "WS12,XDMAC Channel 12 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 11. "WS11,XDMAC Channel 11 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 10. "WS10,XDMAC Channel 10 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 9. "WS9,XDMAC Channel 9 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 8. "WS8,XDMAC Channel 8 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 7. "WS7,XDMAC Channel 7 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 6. "WS6,XDMAC Channel 6 Write Suspend Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "WS5,XDMAC Channel 5 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 4. "WS4,XDMAC Channel 4 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 3. "WS3,XDMAC Channel 3 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 2. "WS2,XDMAC Channel 2 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 1. "WS1,XDMAC Channel 1 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 0. "WS0,XDMAC Channel 0 Write Suspend Bit" "0,1"
|
|
wgroup.long 0x30++0xB
|
|
line.long 0x0 "GRWS,Global Channel Read Write Suspend Register"
|
|
bitfld.long 0x0 15. "RWS15,XDMAC Channel 15 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 14. "RWS14,XDMAC Channel 14 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 13. "RWS13,XDMAC Channel 13 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 12. "RWS12,XDMAC Channel 12 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 11. "RWS11,XDMAC Channel 11 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 10. "RWS10,XDMAC Channel 10 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 9. "RWS9,XDMAC Channel 9 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 8. "RWS8,XDMAC Channel 8 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 7. "RWS7,XDMAC Channel 7 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 6. "RWS6,XDMAC Channel 6 Read Write Suspend Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RWS5,XDMAC Channel 5 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 4. "RWS4,XDMAC Channel 4 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 3. "RWS3,XDMAC Channel 3 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 2. "RWS2,XDMAC Channel 2 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 1. "RWS1,XDMAC Channel 1 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 0. "RWS0,XDMAC Channel 0 Read Write Suspend Bit" "0,1"
|
|
line.long 0x4 "GRWR,Global Channel Read Write Resume Register"
|
|
bitfld.long 0x4 15. "RWR15,XDMAC Channel 15 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 14. "RWR14,XDMAC Channel 14 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 13. "RWR13,XDMAC Channel 13 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 12. "RWR12,XDMAC Channel 12 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 11. "RWR11,XDMAC Channel 11 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 10. "RWR10,XDMAC Channel 10 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 9. "RWR9,XDMAC Channel 9 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 8. "RWR8,XDMAC Channel 8 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 7. "RWR7,XDMAC Channel 7 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 6. "RWR6,XDMAC Channel 6 Read Write Resume Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RWR5,XDMAC Channel 5 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 4. "RWR4,XDMAC Channel 4 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 3. "RWR3,XDMAC Channel 3 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 2. "RWR2,XDMAC Channel 2 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 1. "RWR1,XDMAC Channel 1 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 0. "RWR0,XDMAC Channel 0 Read Write Resume Bit" "0,1"
|
|
line.long 0x8 "GSWR,Global Channel Software Request Register"
|
|
bitfld.long 0x8 15. "SWREQ15,XDMAC Channel 15 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 14. "SWREQ14,XDMAC Channel 14 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 13. "SWREQ13,XDMAC Channel 13 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 12. "SWREQ12,XDMAC Channel 12 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 11. "SWREQ11,XDMAC Channel 11 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 10. "SWREQ10,XDMAC Channel 10 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 9. "SWREQ9,XDMAC Channel 9 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 8. "SWREQ8,XDMAC Channel 8 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 7. "SWREQ7,XDMAC Channel 7 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 6. "SWREQ6,XDMAC Channel 6 Software Request Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SWREQ5,XDMAC Channel 5 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 4. "SWREQ4,XDMAC Channel 4 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 3. "SWREQ3,XDMAC Channel 3 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 2. "SWREQ2,XDMAC Channel 2 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 1. "SWREQ1,XDMAC Channel 1 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 0. "SWREQ0,XDMAC Channel 0 Software Request Bit" "0,1"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "GSWS,Global Channel Software Request Status Register"
|
|
bitfld.long 0x0 15. "SWRS15,XDMAC Channel 15 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 14. "SWRS14,XDMAC Channel 14 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 13. "SWRS13,XDMAC Channel 13 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 12. "SWRS12,XDMAC Channel 12 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 11. "SWRS11,XDMAC Channel 11 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 10. "SWRS10,XDMAC Channel 10 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 9. "SWRS9,XDMAC Channel 9 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 8. "SWRS8,XDMAC Channel 8 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 7. "SWRS7,XDMAC Channel 7 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 6. "SWRS6,XDMAC Channel 6 Software Request Status Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SWRS5,XDMAC Channel 5 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 4. "SWRS4,XDMAC Channel 4 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 3. "SWRS3,XDMAC Channel 3 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 2. "SWRS2,XDMAC Channel 2 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 1. "SWRS1,XDMAC Channel 1 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 0. "SWRS0,XDMAC Channel 0 Software Request Status Bit" "0,1"
|
|
wgroup.long 0x40++0x3
|
|
line.long 0x0 "GSWF,Global Channel Software Flush Request Register"
|
|
bitfld.long 0x0 15. "SWF15,XDMAC Channel 15 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 14. "SWF14,XDMAC Channel 14 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 13. "SWF13,XDMAC Channel 13 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 12. "SWF12,XDMAC Channel 12 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 11. "SWF11,XDMAC Channel 11 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 10. "SWF10,XDMAC Channel 10 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 9. "SWF9,XDMAC Channel 9 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 8. "SWF8,XDMAC Channel 8 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 7. "SWF7,XDMAC Channel 7 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 6. "SWF6,XDMAC Channel 6 Software Flush Request Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SWF5,XDMAC Channel 5 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 4. "SWF4,XDMAC Channel 4 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 3. "SWF3,XDMAC Channel 3 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 2. "SWF2,XDMAC Channel 2 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 1. "SWF1,XDMAC Channel 1 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 0. "SWF0,XDMAC Channel 0 Software Flush Request Bit" "0,1"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0xF0010050 ad:0xF0010090 ad:0xF00100D0 ad:0xF0010110 ad:0xF0010150 ad:0xF0010190 ad:0xF00101D0 ad:0xF0010210 ad:0xF0010250 ad:0xF0010290 ad:0xF00102D0 ad:0xF0010310 ad:0xF0010350 ad:0xF0010390 ad:0xF00103D0 ad:0xF0010410)
|
|
tree "XDMAC_CHID[$1]"
|
|
base $2
|
|
wgroup.long ($2)++0x7
|
|
line.long 0x0 "CIE,Channel Interrupt Enable Register"
|
|
bitfld.long 0x0 6. "ROIE,Request Overflow Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 5. "WBIE,Write Bus Error Interrupt Enable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RBIE,Read Bus Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 3. "FIE,End of Flush Interrupt Enable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DIE,End of Disable Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 1. "LIE,End of Linked List Interrupt Enable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BIE,End of Block Interrupt Enable Bit" "0,1"
|
|
line.long 0x4 "CID,Channel Interrupt Disable Register"
|
|
bitfld.long 0x4 6. "ROID,Request Overflow Error Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 5. "WBEID,Write Bus Error Interrupt Disable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RBEID,Read Bus Error Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 3. "FID,End of Flush Interrupt Disable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DID,End of Disable Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 1. "LID,End of Linked List Interrupt Disable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "BID,End of Block Interrupt Disable Bit" "0,1"
|
|
rgroup.long ($2+0x8)++0x7
|
|
line.long 0x0 "CIM,Channel Interrupt Mask Register"
|
|
bitfld.long 0x0 6. "ROIM,Request Overflow Error Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 5. "WBEIM,Write Bus Error Interrupt Mask Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RBEIM,Read Bus Error Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 3. "FIM,End of Flush Interrupt Mask Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DIM,End of Disable Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 1. "LIM,End of Linked List Interrupt Mask Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BIM,End of Block Interrupt Mask Bit" "0,1"
|
|
line.long 0x4 "CIS,Channel Interrupt Status Register"
|
|
bitfld.long 0x4 6. "ROIS,Request Overflow Error Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 5. "WBEIS,Write Bus Error Interrupt Status Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RBEIS,Read Bus Error Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 3. "FIS,End of Flush Interrupt Status Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DIS,End of Disable Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 1. "LIS,End of Linked List Interrupt Status Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "BIS,End of Block Interrupt Status Bit" "0,1"
|
|
group.long ($2+0x10)++0x27
|
|
line.long 0x0 "CSA,Channel Source Address Register"
|
|
hexmask.long 0x0 0.--31. 1. "SA,Channel x Source Address"
|
|
line.long 0x4 "CDA,Channel Destination Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "DA,Channel x Destination Address"
|
|
line.long 0x8 "CNDA,Channel Next Descriptor Address Register"
|
|
hexmask.long 0x8 2.--31. 1. "NDA,Channel x Next Descriptor Address"
|
|
bitfld.long 0x8 0. "NDAIF,Channel x Next Descriptor Interface" "0,1"
|
|
line.long 0xC "CNDC,Channel Next Descriptor Control Register"
|
|
bitfld.long 0xC 3.--4. "NDVIEW,Channel x Next Descriptor View" "0: Next Descriptor View 0,1: Next Descriptor View 1,2: Next Descriptor View 2,3: Next Descriptor View 3"
|
|
bitfld.long 0xC 2. "NDDUP,Channel x Next Descriptor Destination Update" "0: Destination parameters remain unchanged.,1: Destination parameters are updated when the.."
|
|
newline
|
|
bitfld.long 0xC 1. "NDSUP,Channel x Next Descriptor Source Update" "0: Source parameters remain unchanged.,1: Source parameters are updated when the.."
|
|
bitfld.long 0xC 0. "NDE,Channel x Next Descriptor Enable" "0: Descriptor fetch is disabled.,1: Descriptor fetch is enabled."
|
|
line.long 0x10 "CUBC,Channel Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "UBLEN,Channel x Microblock Length"
|
|
line.long 0x14 "CBC,Channel Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. "BLEN,Channel x Block Length"
|
|
line.long 0x18 "CC,Channel Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. "PERID,Channel x Peripheral Hardware Request Line Identifier"
|
|
bitfld.long 0x18 23. "WRIP,Write in Progress (this bit is read-only)" "0: No active write transaction on the bus.,1: A write transaction is in progress."
|
|
newline
|
|
bitfld.long 0x18 22. "RDIP,Read in Progress (this bit is read-only)" "0: No active read transaction on the bus.,1: A read transaction is in progress."
|
|
bitfld.long 0x18 21. "INITD,Channel Initialization Done (this bit is read-only)" "0: Channel initialization is in progress.,1: Channel initialization is completed."
|
|
newline
|
|
bitfld.long 0x18 18.--19. "DAM,Channel x Destination Addressing Mode" "0: The address remains unchanged.,1: The addressing mode is incremented (the..,2: The microblock stride is added at the microblock..,3: The microblock stride is added at the microblock.."
|
|
bitfld.long 0x18 16.--17. "SAM,Channel x Source Addressing Mode" "0: The address remains unchanged.,1: The addressing mode is incremented (the..,2: The microblock stride is added at the microblock..,3: The microblock stride is added at the microblock.."
|
|
newline
|
|
bitfld.long 0x18 14. "DIF,Channel x Destination Interface Identifier" "0: The data is written through the system bus..,1: The data is written though the system bus.."
|
|
bitfld.long 0x18 13. "SIF,Channel x Source Interface Identifier" "0: The data is read through the system bus..,1: The data is read through the system bus.."
|
|
newline
|
|
bitfld.long 0x18 11.--12. "DWIDTH,Channel x Data Width" "0: The data size is set to 8 bits,1: The data size is set to 16 bits,2: The data size is set to 32 bits,3: The data size is set to 64 bits"
|
|
bitfld.long 0x18 8.--10. "CSIZE,Channel x Chunk Size" "0: 1 data transferred,1: 2 data transferred,2: 4 data transferred,3: 8 data transferred,4: 16 data transferred,?,?,?"
|
|
newline
|
|
bitfld.long 0x18 7. "MEMSET,Channel x Fill Block of Memory" "0: Memset is not activated.,1: Sets the block of memory pointed by DA field to.."
|
|
bitfld.long 0x18 6. "SWREQ,Channel x Software Request Trigger" "0: Hardware request line is connected to the..,1: Software request is connected to the peripheral.."
|
|
newline
|
|
bitfld.long 0x18 5. "PROT,Channel x Protection" "0: Channel is secured.,1: Channel is unsecured."
|
|
bitfld.long 0x18 4. "DSYNC,Channel x Synchronization" "0: Peripheral-to-memory transfer.,1: Memory-to-peripheral transfer."
|
|
newline
|
|
bitfld.long 0x18 1.--2. "MBSIZE,Channel x Memory Burst Size" "0: The memory burst size is set to one.,1: The memory burst size is set to four.,2: The memory burst size is set to eight.,3: The memory burst size is set to sixteen."
|
|
bitfld.long 0x18 0. "TYPE,Channel x Transfer Type" "0: Self-triggered mode (memory-to-memory transfer).,1: Synchronized mode (peripheral-to-memory or.."
|
|
line.long 0x1C "CDS_MSP,Channel Data Stride Memory Set Pattern"
|
|
hexmask.long.word 0x1C 16.--31. 1. "DDS_MSP,Channel x Destination Data Stride or Memory Set Pattern"
|
|
hexmask.long.word 0x1C 0.--15. 1. "SDS_MSP,Channel x Source Data stride or Memory Set Pattern"
|
|
line.long 0x20 "CSUS,Channel Source Microblock Stride"
|
|
hexmask.long.tbyte 0x20 0.--23. 1. "SUBS,Channel x Source Microblock Stride"
|
|
line.long 0x24 "CDUS,Channel Destination Microblock Stride"
|
|
hexmask.long.tbyte 0x24 0.--23. 1. "DUBS,Channel x Destination Microblock Stride"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "XDMAC1"
|
|
base ad:0xF0004000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "GTYPE,Global Type Register"
|
|
hexmask.long.byte 0x0 16.--22. 1. "NB_REQ,Number of Peripheral Requests Minus One"
|
|
hexmask.long.word 0x0 5.--15. 1. "FIFO_SZ,Number of Bytes"
|
|
hexmask.long.byte 0x0 0.--4. 1. "NB_CH,Number of Channels Minus One"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "GCFG,Global Configuration Register"
|
|
bitfld.long 0x0 8. "BXKBEN,Boundary X Kilobyte Enable" "0,1"
|
|
bitfld.long 0x0 3. "CGDISIF,Bus Interface Clock Gating Disable" "0,1"
|
|
bitfld.long 0x0 2. "CGDISFIFO,FIFO Clock Gating Disable" "0,1"
|
|
bitfld.long 0x0 1. "CGDISPIPE,Pipeline Clock Gating Disable" "0,1"
|
|
bitfld.long 0x0 0. "CGDISREG,Configuration Registers Clock Gating Disable" "0,1"
|
|
line.long 0x4 "GWAC,Global Weighted Arbiter Configuration Register"
|
|
hexmask.long.byte 0x4 12.--15. 1. "PW3,Pool Weight 3"
|
|
hexmask.long.byte 0x4 8.--11. 1. "PW2,Pool Weight 2"
|
|
hexmask.long.byte 0x4 4.--7. 1. "PW1,Pool Weight 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PW0,Pool Weight 0"
|
|
wgroup.long 0xC++0x7
|
|
line.long 0x0 "GIE,Global Interrupt Enable Register"
|
|
bitfld.long 0x0 15. "IE15,XDMAC Channel 15 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 14. "IE14,XDMAC Channel 14 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 13. "IE13,XDMAC Channel 13 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 12. "IE12,XDMAC Channel 12 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 11. "IE11,XDMAC Channel 11 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 10. "IE10,XDMAC Channel 10 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 9. "IE9,XDMAC Channel 9 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 8. "IE8,XDMAC Channel 8 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 7. "IE7,XDMAC Channel 7 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 6. "IE6,XDMAC Channel 6 Interrupt Enable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IE5,XDMAC Channel 5 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 4. "IE4,XDMAC Channel 4 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 3. "IE3,XDMAC Channel 3 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 2. "IE2,XDMAC Channel 2 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 1. "IE1,XDMAC Channel 1 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 0. "IE0,XDMAC Channel 0 Interrupt Enable Bit" "0,1"
|
|
line.long 0x4 "GID,Global Interrupt Disable Register"
|
|
bitfld.long 0x4 15. "ID15,XDMAC Channel 15 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 14. "ID14,XDMAC Channel 14 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 13. "ID13,XDMAC Channel 13 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 12. "ID12,XDMAC Channel 12 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 11. "ID11,XDMAC Channel 11 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 10. "ID10,XDMAC Channel 10 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 9. "ID9,XDMAC Channel 9 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 8. "ID8,XDMAC Channel 8 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 7. "ID7,XDMAC Channel 7 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 6. "ID6,XDMAC Channel 6 Interrupt Disable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "ID5,XDMAC Channel 5 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 4. "ID4,XDMAC Channel 4 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 3. "ID3,XDMAC Channel 3 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 2. "ID2,XDMAC Channel 2 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 1. "ID1,XDMAC Channel 1 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 0. "ID0,XDMAC Channel 0 Interrupt Disable Bit" "0,1"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "GIM,Global Interrupt Mask Register"
|
|
bitfld.long 0x0 15. "IM15,XDMAC Channel 15 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 14. "IM14,XDMAC Channel 14 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 13. "IM13,XDMAC Channel 13 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 12. "IM12,XDMAC Channel 12 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 11. "IM11,XDMAC Channel 11 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 10. "IM10,XDMAC Channel 10 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 9. "IM9,XDMAC Channel 9 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 8. "IM8,XDMAC Channel 8 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 7. "IM7,XDMAC Channel 7 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 6. "IM6,XDMAC Channel 6 Interrupt Mask Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IM5,XDMAC Channel 5 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 4. "IM4,XDMAC Channel 4 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 3. "IM3,XDMAC Channel 3 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 2. "IM2,XDMAC Channel 2 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 1. "IM1,XDMAC Channel 1 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 0. "IM0,XDMAC Channel 0 Interrupt Mask Bit" "0,1"
|
|
line.long 0x4 "GIS,Global Interrupt Status Register"
|
|
bitfld.long 0x4 15. "IS15,XDMAC Channel 15 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 14. "IS14,XDMAC Channel 14 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 13. "IS13,XDMAC Channel 13 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 12. "IS12,XDMAC Channel 12 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 11. "IS11,XDMAC Channel 11 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 10. "IS10,XDMAC Channel 10 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 9. "IS9,XDMAC Channel 9 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 8. "IS8,XDMAC Channel 8 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 7. "IS7,XDMAC Channel 7 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 6. "IS6,XDMAC Channel 6 Interrupt Status Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "IS5,XDMAC Channel 5 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 4. "IS4,XDMAC Channel 4 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 3. "IS3,XDMAC Channel 3 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 2. "IS2,XDMAC Channel 2 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 1. "IS1,XDMAC Channel 1 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 0. "IS0,XDMAC Channel 0 Interrupt Status Bit" "0,1"
|
|
wgroup.long 0x1C++0x7
|
|
line.long 0x0 "GE,Global Channel Enable Register"
|
|
bitfld.long 0x0 15. "EN15,XDMAC Channel 15 Enable Bit" "0,1"
|
|
bitfld.long 0x0 14. "EN14,XDMAC Channel 14 Enable Bit" "0,1"
|
|
bitfld.long 0x0 13. "EN13,XDMAC Channel 13 Enable Bit" "0,1"
|
|
bitfld.long 0x0 12. "EN12,XDMAC Channel 12 Enable Bit" "0,1"
|
|
bitfld.long 0x0 11. "EN11,XDMAC Channel 11 Enable Bit" "0,1"
|
|
bitfld.long 0x0 10. "EN10,XDMAC Channel 10 Enable Bit" "0,1"
|
|
bitfld.long 0x0 9. "EN9,XDMAC Channel 9 Enable Bit" "0,1"
|
|
bitfld.long 0x0 8. "EN8,XDMAC Channel 8 Enable Bit" "0,1"
|
|
bitfld.long 0x0 7. "EN7,XDMAC Channel 7 Enable Bit" "0,1"
|
|
bitfld.long 0x0 6. "EN6,XDMAC Channel 6 Enable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EN5,XDMAC Channel 5 Enable Bit" "0,1"
|
|
bitfld.long 0x0 4. "EN4,XDMAC Channel 4 Enable Bit" "0,1"
|
|
bitfld.long 0x0 3. "EN3,XDMAC Channel 3 Enable Bit" "0,1"
|
|
bitfld.long 0x0 2. "EN2,XDMAC Channel 2 Enable Bit" "0,1"
|
|
bitfld.long 0x0 1. "EN1,XDMAC Channel 1 Enable Bit" "0,1"
|
|
bitfld.long 0x0 0. "EN0,XDMAC Channel 0 Enable Bit" "0,1"
|
|
line.long 0x4 "GD,Global Channel Disable Register"
|
|
bitfld.long 0x4 15. "DI15,XDMAC Channel 15 Disable Bit" "0,1"
|
|
bitfld.long 0x4 14. "DI14,XDMAC Channel 14 Disable Bit" "0,1"
|
|
bitfld.long 0x4 13. "DI13,XDMAC Channel 13 Disable Bit" "0,1"
|
|
bitfld.long 0x4 12. "DI12,XDMAC Channel 12 Disable Bit" "0,1"
|
|
bitfld.long 0x4 11. "DI11,XDMAC Channel 11 Disable Bit" "0,1"
|
|
bitfld.long 0x4 10. "DI10,XDMAC Channel 10 Disable Bit" "0,1"
|
|
bitfld.long 0x4 9. "DI9,XDMAC Channel 9 Disable Bit" "0,1"
|
|
bitfld.long 0x4 8. "DI8,XDMAC Channel 8 Disable Bit" "0,1"
|
|
bitfld.long 0x4 7. "DI7,XDMAC Channel 7 Disable Bit" "0,1"
|
|
bitfld.long 0x4 6. "DI6,XDMAC Channel 6 Disable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DI5,XDMAC Channel 5 Disable Bit" "0,1"
|
|
bitfld.long 0x4 4. "DI4,XDMAC Channel 4 Disable Bit" "0,1"
|
|
bitfld.long 0x4 3. "DI3,XDMAC Channel 3 Disable Bit" "0,1"
|
|
bitfld.long 0x4 2. "DI2,XDMAC Channel 2 Disable Bit" "0,1"
|
|
bitfld.long 0x4 1. "DI1,XDMAC Channel 1 Disable Bit" "0,1"
|
|
bitfld.long 0x4 0. "DI0,XDMAC Channel 0 Disable Bit" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "GS,Global Channel Status Register"
|
|
bitfld.long 0x0 15. "ST15,XDMAC Channel 15 Status Bit" "0,1"
|
|
bitfld.long 0x0 14. "ST14,XDMAC Channel 14 Status Bit" "0,1"
|
|
bitfld.long 0x0 13. "ST13,XDMAC Channel 13 Status Bit" "0,1"
|
|
bitfld.long 0x0 12. "ST12,XDMAC Channel 12 Status Bit" "0,1"
|
|
bitfld.long 0x0 11. "ST11,XDMAC Channel 11 Status Bit" "0,1"
|
|
bitfld.long 0x0 10. "ST10,XDMAC Channel 10 Status Bit" "0,1"
|
|
bitfld.long 0x0 9. "ST9,XDMAC Channel 9 Status Bit" "0,1"
|
|
bitfld.long 0x0 8. "ST8,XDMAC Channel 8 Status Bit" "0,1"
|
|
bitfld.long 0x0 7. "ST7,XDMAC Channel 7 Status Bit" "0,1"
|
|
bitfld.long 0x0 6. "ST6,XDMAC Channel 6 Status Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ST5,XDMAC Channel 5 Status Bit" "0,1"
|
|
bitfld.long 0x0 4. "ST4,XDMAC Channel 4 Status Bit" "0,1"
|
|
bitfld.long 0x0 3. "ST3,XDMAC Channel 3 Status Bit" "0,1"
|
|
bitfld.long 0x0 2. "ST2,XDMAC Channel 2 Status Bit" "0,1"
|
|
bitfld.long 0x0 1. "ST1,XDMAC Channel 1 Status Bit" "0,1"
|
|
bitfld.long 0x0 0. "ST0,XDMAC Channel 0 Status Bit" "0,1"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "GRS,Global Channel Read Suspend Register"
|
|
bitfld.long 0x0 15. "RS15,XDMAC Channel 15 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 14. "RS14,XDMAC Channel 14 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 13. "RS13,XDMAC Channel 13 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 12. "RS12,XDMAC Channel 12 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 11. "RS11,XDMAC Channel 11 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 10. "RS10,XDMAC Channel 10 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 9. "RS9,XDMAC Channel 9 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 8. "RS8,XDMAC Channel 8 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 7. "RS7,XDMAC Channel 7 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 6. "RS6,XDMAC Channel 6 Read Suspend Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RS5,XDMAC Channel 5 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 4. "RS4,XDMAC Channel 4 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 3. "RS3,XDMAC Channel 3 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 2. "RS2,XDMAC Channel 2 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 1. "RS1,XDMAC Channel 1 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 0. "RS0,XDMAC Channel 0 Read Suspend Bit" "0,1"
|
|
line.long 0x4 "GWS,Global Channel Write Suspend Register"
|
|
bitfld.long 0x4 15. "WS15,XDMAC Channel 15 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 14. "WS14,XDMAC Channel 14 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 13. "WS13,XDMAC Channel 13 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 12. "WS12,XDMAC Channel 12 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 11. "WS11,XDMAC Channel 11 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 10. "WS10,XDMAC Channel 10 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 9. "WS9,XDMAC Channel 9 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 8. "WS8,XDMAC Channel 8 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 7. "WS7,XDMAC Channel 7 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 6. "WS6,XDMAC Channel 6 Write Suspend Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "WS5,XDMAC Channel 5 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 4. "WS4,XDMAC Channel 4 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 3. "WS3,XDMAC Channel 3 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 2. "WS2,XDMAC Channel 2 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 1. "WS1,XDMAC Channel 1 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 0. "WS0,XDMAC Channel 0 Write Suspend Bit" "0,1"
|
|
wgroup.long 0x30++0xB
|
|
line.long 0x0 "GRWS,Global Channel Read Write Suspend Register"
|
|
bitfld.long 0x0 15. "RWS15,XDMAC Channel 15 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 14. "RWS14,XDMAC Channel 14 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 13. "RWS13,XDMAC Channel 13 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 12. "RWS12,XDMAC Channel 12 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 11. "RWS11,XDMAC Channel 11 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 10. "RWS10,XDMAC Channel 10 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 9. "RWS9,XDMAC Channel 9 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 8. "RWS8,XDMAC Channel 8 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 7. "RWS7,XDMAC Channel 7 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 6. "RWS6,XDMAC Channel 6 Read Write Suspend Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RWS5,XDMAC Channel 5 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 4. "RWS4,XDMAC Channel 4 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 3. "RWS3,XDMAC Channel 3 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 2. "RWS2,XDMAC Channel 2 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 1. "RWS1,XDMAC Channel 1 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 0. "RWS0,XDMAC Channel 0 Read Write Suspend Bit" "0,1"
|
|
line.long 0x4 "GRWR,Global Channel Read Write Resume Register"
|
|
bitfld.long 0x4 15. "RWR15,XDMAC Channel 15 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 14. "RWR14,XDMAC Channel 14 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 13. "RWR13,XDMAC Channel 13 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 12. "RWR12,XDMAC Channel 12 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 11. "RWR11,XDMAC Channel 11 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 10. "RWR10,XDMAC Channel 10 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 9. "RWR9,XDMAC Channel 9 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 8. "RWR8,XDMAC Channel 8 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 7. "RWR7,XDMAC Channel 7 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 6. "RWR6,XDMAC Channel 6 Read Write Resume Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RWR5,XDMAC Channel 5 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 4. "RWR4,XDMAC Channel 4 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 3. "RWR3,XDMAC Channel 3 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 2. "RWR2,XDMAC Channel 2 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 1. "RWR1,XDMAC Channel 1 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 0. "RWR0,XDMAC Channel 0 Read Write Resume Bit" "0,1"
|
|
line.long 0x8 "GSWR,Global Channel Software Request Register"
|
|
bitfld.long 0x8 15. "SWREQ15,XDMAC Channel 15 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 14. "SWREQ14,XDMAC Channel 14 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 13. "SWREQ13,XDMAC Channel 13 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 12. "SWREQ12,XDMAC Channel 12 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 11. "SWREQ11,XDMAC Channel 11 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 10. "SWREQ10,XDMAC Channel 10 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 9. "SWREQ9,XDMAC Channel 9 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 8. "SWREQ8,XDMAC Channel 8 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 7. "SWREQ7,XDMAC Channel 7 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 6. "SWREQ6,XDMAC Channel 6 Software Request Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SWREQ5,XDMAC Channel 5 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 4. "SWREQ4,XDMAC Channel 4 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 3. "SWREQ3,XDMAC Channel 3 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 2. "SWREQ2,XDMAC Channel 2 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 1. "SWREQ1,XDMAC Channel 1 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 0. "SWREQ0,XDMAC Channel 0 Software Request Bit" "0,1"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "GSWS,Global Channel Software Request Status Register"
|
|
bitfld.long 0x0 15. "SWRS15,XDMAC Channel 15 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 14. "SWRS14,XDMAC Channel 14 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 13. "SWRS13,XDMAC Channel 13 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 12. "SWRS12,XDMAC Channel 12 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 11. "SWRS11,XDMAC Channel 11 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 10. "SWRS10,XDMAC Channel 10 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 9. "SWRS9,XDMAC Channel 9 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 8. "SWRS8,XDMAC Channel 8 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 7. "SWRS7,XDMAC Channel 7 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 6. "SWRS6,XDMAC Channel 6 Software Request Status Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SWRS5,XDMAC Channel 5 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 4. "SWRS4,XDMAC Channel 4 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 3. "SWRS3,XDMAC Channel 3 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 2. "SWRS2,XDMAC Channel 2 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 1. "SWRS1,XDMAC Channel 1 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 0. "SWRS0,XDMAC Channel 0 Software Request Status Bit" "0,1"
|
|
wgroup.long 0x40++0x3
|
|
line.long 0x0 "GSWF,Global Channel Software Flush Request Register"
|
|
bitfld.long 0x0 15. "SWF15,XDMAC Channel 15 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 14. "SWF14,XDMAC Channel 14 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 13. "SWF13,XDMAC Channel 13 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 12. "SWF12,XDMAC Channel 12 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 11. "SWF11,XDMAC Channel 11 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 10. "SWF10,XDMAC Channel 10 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 9. "SWF9,XDMAC Channel 9 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 8. "SWF8,XDMAC Channel 8 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 7. "SWF7,XDMAC Channel 7 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 6. "SWF6,XDMAC Channel 6 Software Flush Request Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SWF5,XDMAC Channel 5 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 4. "SWF4,XDMAC Channel 4 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 3. "SWF3,XDMAC Channel 3 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 2. "SWF2,XDMAC Channel 2 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 1. "SWF1,XDMAC Channel 1 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 0. "SWF0,XDMAC Channel 0 Software Flush Request Bit" "0,1"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0xF0004050 ad:0xF0004090 ad:0xF00040D0 ad:0xF0004110 ad:0xF0004150 ad:0xF0004190 ad:0xF00041D0 ad:0xF0004210 ad:0xF0004250 ad:0xF0004290 ad:0xF00042D0 ad:0xF0004310 ad:0xF0004350 ad:0xF0004390 ad:0xF00043D0 ad:0xF0004410)
|
|
tree "XDMAC_CHID[$1]"
|
|
base $2
|
|
wgroup.long ($2)++0x7
|
|
line.long 0x0 "CIE,Channel Interrupt Enable Register"
|
|
bitfld.long 0x0 6. "ROIE,Request Overflow Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 5. "WBIE,Write Bus Error Interrupt Enable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RBIE,Read Bus Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 3. "FIE,End of Flush Interrupt Enable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DIE,End of Disable Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 1. "LIE,End of Linked List Interrupt Enable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BIE,End of Block Interrupt Enable Bit" "0,1"
|
|
line.long 0x4 "CID,Channel Interrupt Disable Register"
|
|
bitfld.long 0x4 6. "ROID,Request Overflow Error Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 5. "WBEID,Write Bus Error Interrupt Disable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RBEID,Read Bus Error Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 3. "FID,End of Flush Interrupt Disable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DID,End of Disable Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 1. "LID,End of Linked List Interrupt Disable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "BID,End of Block Interrupt Disable Bit" "0,1"
|
|
rgroup.long ($2+0x8)++0x7
|
|
line.long 0x0 "CIM,Channel Interrupt Mask Register"
|
|
bitfld.long 0x0 6. "ROIM,Request Overflow Error Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 5. "WBEIM,Write Bus Error Interrupt Mask Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RBEIM,Read Bus Error Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 3. "FIM,End of Flush Interrupt Mask Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DIM,End of Disable Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 1. "LIM,End of Linked List Interrupt Mask Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BIM,End of Block Interrupt Mask Bit" "0,1"
|
|
line.long 0x4 "CIS,Channel Interrupt Status Register"
|
|
bitfld.long 0x4 6. "ROIS,Request Overflow Error Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 5. "WBEIS,Write Bus Error Interrupt Status Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RBEIS,Read Bus Error Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 3. "FIS,End of Flush Interrupt Status Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DIS,End of Disable Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 1. "LIS,End of Linked List Interrupt Status Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "BIS,End of Block Interrupt Status Bit" "0,1"
|
|
group.long ($2+0x10)++0x27
|
|
line.long 0x0 "CSA,Channel Source Address Register"
|
|
hexmask.long 0x0 0.--31. 1. "SA,Channel x Source Address"
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line.long 0x4 "CDA,Channel Destination Address Register"
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hexmask.long 0x4 0.--31. 1. "DA,Channel x Destination Address"
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line.long 0x8 "CNDA,Channel Next Descriptor Address Register"
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hexmask.long 0x8 2.--31. 1. "NDA,Channel x Next Descriptor Address"
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bitfld.long 0x8 0. "NDAIF,Channel x Next Descriptor Interface" "0,1"
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line.long 0xC "CNDC,Channel Next Descriptor Control Register"
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bitfld.long 0xC 3.--4. "NDVIEW,Channel x Next Descriptor View" "0: Next Descriptor View 0,1: Next Descriptor View 1,2: Next Descriptor View 2,3: Next Descriptor View 3"
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bitfld.long 0xC 2. "NDDUP,Channel x Next Descriptor Destination Update" "0: Destination parameters remain unchanged.,1: Destination parameters are updated when the.."
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bitfld.long 0xC 1. "NDSUP,Channel x Next Descriptor Source Update" "0: Source parameters remain unchanged.,1: Source parameters are updated when the.."
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bitfld.long 0xC 0. "NDE,Channel x Next Descriptor Enable" "0: Descriptor fetch is disabled.,1: Descriptor fetch is enabled."
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line.long 0x10 "CUBC,Channel Microblock Control Register"
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hexmask.long.tbyte 0x10 0.--23. 1. "UBLEN,Channel x Microblock Length"
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line.long 0x14 "CBC,Channel Block Control Register"
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hexmask.long.word 0x14 0.--11. 1. "BLEN,Channel x Block Length"
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line.long 0x18 "CC,Channel Configuration Register"
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hexmask.long.byte 0x18 24.--30. 1. "PERID,Channel x Peripheral Hardware Request Line Identifier"
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bitfld.long 0x18 23. "WRIP,Write in Progress (this bit is read-only)" "0: No active write transaction on the bus.,1: A write transaction is in progress."
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bitfld.long 0x18 22. "RDIP,Read in Progress (this bit is read-only)" "0: No active read transaction on the bus.,1: A read transaction is in progress."
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bitfld.long 0x18 21. "INITD,Channel Initialization Done (this bit is read-only)" "0: Channel initialization is in progress.,1: Channel initialization is completed."
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bitfld.long 0x18 18.--19. "DAM,Channel x Destination Addressing Mode" "0: The address remains unchanged.,1: The addressing mode is incremented (the..,2: The microblock stride is added at the microblock..,3: The microblock stride is added at the microblock.."
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bitfld.long 0x18 16.--17. "SAM,Channel x Source Addressing Mode" "0: The address remains unchanged.,1: The addressing mode is incremented (the..,2: The microblock stride is added at the microblock..,3: The microblock stride is added at the microblock.."
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bitfld.long 0x18 14. "DIF,Channel x Destination Interface Identifier" "0: The data is written through the system bus..,1: The data is written though the system bus.."
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bitfld.long 0x18 13. "SIF,Channel x Source Interface Identifier" "0: The data is read through the system bus..,1: The data is read through the system bus.."
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bitfld.long 0x18 11.--12. "DWIDTH,Channel x Data Width" "0: The data size is set to 8 bits,1: The data size is set to 16 bits,2: The data size is set to 32 bits,3: The data size is set to 64 bits"
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bitfld.long 0x18 8.--10. "CSIZE,Channel x Chunk Size" "0: 1 data transferred,1: 2 data transferred,2: 4 data transferred,3: 8 data transferred,4: 16 data transferred,?,?,?"
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bitfld.long 0x18 7. "MEMSET,Channel x Fill Block of Memory" "0: Memset is not activated.,1: Sets the block of memory pointed by DA field to.."
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bitfld.long 0x18 6. "SWREQ,Channel x Software Request Trigger" "0: Hardware request line is connected to the..,1: Software request is connected to the peripheral.."
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bitfld.long 0x18 5. "PROT,Channel x Protection" "0: Channel is secured.,1: Channel is unsecured."
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bitfld.long 0x18 4. "DSYNC,Channel x Synchronization" "0: Peripheral-to-memory transfer.,1: Memory-to-peripheral transfer."
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bitfld.long 0x18 1.--2. "MBSIZE,Channel x Memory Burst Size" "0: The memory burst size is set to one.,1: The memory burst size is set to four.,2: The memory burst size is set to eight.,3: The memory burst size is set to sixteen."
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bitfld.long 0x18 0. "TYPE,Channel x Transfer Type" "0: Self-triggered mode (memory-to-memory transfer).,1: Synchronized mode (peripheral-to-memory or.."
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line.long 0x1C "CDS_MSP,Channel Data Stride Memory Set Pattern"
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hexmask.long.word 0x1C 16.--31. 1. "DDS_MSP,Channel x Destination Data Stride or Memory Set Pattern"
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hexmask.long.word 0x1C 0.--15. 1. "SDS_MSP,Channel x Source Data stride or Memory Set Pattern"
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line.long 0x20 "CSUS,Channel Source Microblock Stride"
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hexmask.long.tbyte 0x20 0.--23. 1. "SUBS,Channel x Source Microblock Stride"
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line.long 0x24 "CDUS,Channel Destination Microblock Stride"
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hexmask.long.tbyte 0x24 0.--23. 1. "DUBS,Channel x Destination Microblock Stride"
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tree.end
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repeat.end
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tree.end
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tree.end
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AUTOINDENT.OFF
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