22004 lines
1.5 MiB
22004 lines
1.5 MiB
; --------------------------------------------------------------------------------
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; @Title: AT91SAM4E On-Chip Peripherals
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; @Props: Released
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; @Author: TPP, ZAK
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; @Changelog: 2013-04-22
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; @Manufacturer: ATMEL - Atmel Corporation
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; @Doc:
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; Atmel_11157_32-bit-Cortex-M4-Microcontroller_SAM4E_Datasheet.pdf (2013-11-01)
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; @Core: Cortex-M4
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; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: peratsam4e.per 17736 2024-04-08 09:26:07Z kwisniewski $
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tree.close "Core Registers (Cortex-M4F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
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bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
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bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
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group.long 0x10++0x0B
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
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bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x07
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line.long 0x00 "HFSR,Hard Fault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
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bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
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group.long 0xD34++0x0B
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line.long 0x00 "MMFAR,MemManage Fault Address Register"
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line.long 0x04 "BFAR,BusFault Address Register"
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line.long 0x08 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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width 10.
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tree "Feature Registers"
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
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bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
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textline " "
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bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
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bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
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textline " "
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bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
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line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
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|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
config 16. 8.
|
|
tree "CHIPID (Chip Identifier)"
|
|
base ad:0x400E0740
|
|
width 13.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "CHIPID_CIDR,Chip ID Register"
|
|
bitfld.long 0x00 31. " EXT ,Extension Flag" "Not implemented,Implemented"
|
|
bitfld.long 0x00 28.--30. " NVPTYP ,Nonvolatile Program Memory Type" "ROM,ROMless/Flash,Embedded Flash,ROM & Embedded Flash,SRAM emulating ROM,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 20.--27. 1. " ARCH ,Architecture Identifier"
|
|
bitfld.long 0x00 16.--19. " SRAMSIZ ,Internal SRAM Size" "48K,192K,2K,6K,24K,4K,80K,160K,8K,16K,32K,64K,128K,256K,96K,512K"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " NVPSIZ2 ,Second Nonvolatile Program Memory Size" "NONE,8K,16K,32K,,64K,,128K,,256K,512K,,1024K,,2048K,?..."
|
|
bitfld.long 0x00 8.--11. " NVPSIZ ,Nonvolatile Program Memory Size" "NONE,8K,16K,32K,,64K,,128K,,256K,512K,,1024K,,2048K,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " EPROC ,Embedded Processor" ",ARM946ES,ARM7TDMI,CM3,ARM920T,ARM926EJS,CA5,CM4"
|
|
bitfld.long 0x00 0.--4. " VERSION ,Version of the Device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "EXID,Chip ID Extension"
|
|
hexmask.long 0x04 5.--31. 1. " CHIPID_EXID[31:5] ,Product Number"
|
|
bitfld.long 0x04 2.--4. " CHIPID_EXID[4:2] ,Flash Size" "1024 Kbytes,512 Kbytes,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " CHIPID_EXID[1:0] ,Package Type" "144,100,?..."
|
|
width 0x0b
|
|
tree.end
|
|
tree "RSTC (Reset Controller)"
|
|
base ad:0x400E1800
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "RSTC_CR,Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password"
|
|
sif !cpuis("ATSAMA5D2?")
|
|
bitfld.long 0x00 3. " EXTRST ,External Reset" "No effect,NRST asserted"
|
|
endif
|
|
sif (cpuis("ATSAMV7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " PROCRST ,Processor Reset" "No effect,Processor reset"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 2. " PERRST ,Peripheral Reset" "No effect,Peripherals reset"
|
|
bitfld.long 0x00 0. " PROCRST ,Processor Reset" "No effect,Processor reset"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "RSTC_SR,Status Register"
|
|
in
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RSTC_MR,Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password"
|
|
sif (!cpuis("ATSAMA5D41")&&!cpuis("ATSAMA5D42")&&!cpuis("ATSAMA5D43")&&!cpuis("ATSAMA5D44")&&!cpuis("ATSAMA5D2?"))
|
|
bitfld.long 0x00 8.--11. " ERSTL ,External Reset Length" "2 slow clock cycles (60 us),4 slow clock cycles (120 us),8 slow clock cycles (240 us),16 slow clock cycles (480 us),32 slow clock cycles (960 us),64 slow clock cycles (1.92 ms),128 slow clock cycles (3.84 ms),256 slow clock cycles (7.68 ms),512 slow clock cycles (15.36 ms),1024 slow clock cycles (30.72 ms),2048 slow clock cycles (61.44 ms),4096 slow clock cycles (122.88 ms),8192 slow clock cycles (245.76 ms),16384 slow clock cycles (491.52 ms),32768 slow clock cycles (0.98304 s),65536 slow clock cycles (1.96608 s)"
|
|
endif
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36"))
|
|
textline " "
|
|
bitfld.long 0x00 4. " URSTIEN ,User Reset Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " URSTEN ,User Reset Enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "RTT (Real-time Timer)"
|
|
base ad:0x400E1830
|
|
width 4.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "MR,Real-Time Timer Mode Register"
|
|
sif (cpuis("ATSAM4E*")||cpuis("ATSAM4N*")||cpuis("ATSAM4S*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*"))
|
|
bitfld.long 0x00 24. " RTC1HZ ,Real-time clock 1Hz clock selection" "16-bit prescaler,RTC 1 Hz clock"
|
|
bitfld.long 0x00 20. " RTTDIS ,Real-time timer disable" "No,Yes"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " RTTRST ,Real-time timer restart" "No restart,Restart"
|
|
bitfld.long 0x00 17. " RTTINCIEN ,Real-time timer increment interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ALMIEN ,Alarm interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--15. 1. " RTPRES ,Real-time timer prescaler value"
|
|
line.long 0x04 "AR,Real-Time Timer Alarm Register"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "VR,Real-Time Timer Value Register"
|
|
newline
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "SR,Real-Time Timer Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree "RTC (Real-time Clock)"
|
|
base ad:0x400E1860
|
|
width 12.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "RTC_CR,Control Register"
|
|
bitfld.long 0x00 16.--17. " CALEVSEL ,Calendar Event Selection" "Week change,Month change,Year change,Year change"
|
|
bitfld.long 0x00 8.--9. " TIMEVSEL ,Time Event Selection" "Minute change,Hour change,Every day at midnight,Every day at noon"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UPDCAL ,Update Request Calendar Register" "No effect,Stopped"
|
|
bitfld.long 0x00 0. " UPDTIM ,Update Request Time Register" "No effect,Stopped"
|
|
line.long 0x04 "RTC_MR,RTC Mode Register"
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
sif !cpuis("ATSAM4N*")
|
|
bitfld.long 0x04 28.--29. " TPERIO ,Period of the Output Pulse" "1 s,500 ms,250 ms,125 ms"
|
|
bitfld.long 0x04 24.--26. " THIGH ,High Duration of the Output Pulse" "31.2 ms,15.6 ms,3.91 ms,967 u_s,488 u_s,122 u_s,30.5 u_s,15.2 u_s"
|
|
textline " "
|
|
bitfld.long 0x04 20.--22. " OUT1 ,RTCOUT1 Output Source Selection" "No waveform,1 Hz square wave,32 Hz square wave,64 Hz square wave,512 Hz square wave,Output toggles when alarm flag rises,Output is a copy of the alarm flag,Duty cycle programmable pulse"
|
|
textline " "
|
|
bitfld.long 0x04 16.--18. " OUT0 ,RTCOUT0 Output Source Selection" "No waveform,1 Hz square wave,32 Hz square wave,64 Hz square wave,512 Hz square wave,Output toggles when alarm flag rises,Output is a copy of the alarm flag,Duty cycle programmable pulse"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 15. " HIGHPPM ,HIGH PPM Correction" "Lower,Higher"
|
|
hexmask.long.byte 0x04 8.--14. 1. " CORRECTION ,Correction"
|
|
textline " "
|
|
bitfld.long 0x04 4. " NEGPPM ,NEGative PPM Correction" "Positive,Negative"
|
|
bitfld.long 0x04 1. " PERSIAN ,PERSIAN Calendar" "Gregorian,Persian"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 0. " HRMOD ,12/24 Hour Mode" "24,12"
|
|
if ((data.long(ad:0x400E1860+0x04)&0x1)==0x1)
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "RTC_TIMR,Time Register"
|
|
bitfld.long 0x00 22. " AMPM ,Ante Meridiem Post Meridiem Indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RTC_TIMR,Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
endif
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" ",1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "0,1,2,3,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
if ((d.l(ad:0x400E1860+0x04)&0x00000001)==0x00000001)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RTC_TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AMPM ,AM/PM Indicator" "AM,PM"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " MINEN ,Minute Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SECEN ,Second Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RTC_TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " MINEN ,Minute Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SECEN ,Second Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
endif
|
|
width 12.
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
width 12.
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "RTC_SR,Status Register"
|
|
sif (cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 5. " TDERR ,Time and/or Date Free Running Error" "Not occurred,Occurred"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " CALEV ,Calendar Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " TIMEV ,Time Event" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEC ,Second Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " ALARM ,Alarm Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACKUPD ,Acknowledge for Update" "No,Yes"
|
|
wgroup.long 0x1C++0x0B
|
|
line.long 0x00 "RTC_SCCR,Status Clear Register"
|
|
sif (cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 5. " TDERRCLR ,Time and/or Date Free Running Error Clear" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " CALCLR ,Calendar Event Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " TIMCLR ,Time Event Interrupt Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SECCLR ,Second Event Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " ALRCLR ,Alarm Flag Interrupt Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACKCLR ,Acknowledge for Update Interrupt Clear" "No effect,Clear"
|
|
line.long 0x04 "RTC_IER,Interrupt Enable Register"
|
|
sif (cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x04 5. " TDERREN ,Time and/or Date Free Running Error Interrupt Enable" "No effect,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 4. " CALEN ,Calendar Event Interrupt Enable" "No effect,Enabled"
|
|
bitfld.long 0x04 3. " TIMEN ,Time Event Interrupt Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " SECEN ,Second Event Interrupt Enable" "No effect,Enabled"
|
|
bitfld.long 0x04 1. " ALREN ,Alarm Flag Interrupt Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ACKEN ,Acknowledge for Update Interrupt Enable" "No effect,Enabled"
|
|
line.long 0x08 "RTC_IDR,Interrupt Disable Register"
|
|
sif (cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x08 5. " TDERRDIS ,Time and/or Date Free Running Error Interrupt Disable" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 4. " CALDIS ,Calendar Event Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x08 3. " TIMDIS ,Time Event Interrupt Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SECDIS ,Second Event Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x08 1. " ALRDIS ,Alarm Flag Interrupt Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 0. " ACKDIS ,Acknowledge for Update Interrupt Disable" "No,Yes"
|
|
rgroup.long 0x28++0x7
|
|
line.long 0x00 "RTC_IMR,Interrupt Mask Register"
|
|
bitfld.long 0x00 4. " CAL ,Calendar Event Interrupt Mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TIM ,Time Event Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEC ,Second Event Interrupt Mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ALR ,Alarm Flag Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACK ,Acknowledge for Update Interrupt Mask" "Disabled,Enabled"
|
|
line.long 0x04 "RTC_VER,Valid Entry Register"
|
|
bitfld.long 0x04 3. " NVCAL ,Non-Valid Calendar Alarm" "Not detected,Detected"
|
|
bitfld.long 0x04 2. " NVTAL ,Non-Valid Time Alarm" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 1. " NVC ,Non-Valid Calendar" "Not detected,Detected"
|
|
bitfld.long 0x04 0. " NVT ,Non-Valid Time" "Not detected,Detected"
|
|
sif (cpuis("AT91SAM3N*")||cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "RTC_WPMR,RTC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect access key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0x400E1850
|
|
width 4.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password"
|
|
bitfld.long 0x00 0. " WDRSTT ,Watchdog restart" "No effect,Restart"
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D4*")||cpuis("ATSAMA5D2*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 29. " WDIDLEHLT ,Watchdog idle halt" "Not halted,Halted"
|
|
bitfld.long 0x00 28. " WDDBGHLT ,Watchdog debug halt" "Not halted,Halted"
|
|
hexmask.long.word 0x00 16.--27. 1. " WDD ,Watchdog delta value"
|
|
bitfld.long 0x00 15. " WDDIS ,Watchdog disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13. " WDRSTEN ,Watchdog reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WDFIEN ,Watchdog fault interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--11. 1. " WDV ,Watchdog counter value"
|
|
else
|
|
if ((per.l(ad:0x400E1850+0x04)&0x2000)==0x2000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 29. " WDIDLEHLT ,Watchdog idle halt" "Running,Stopped"
|
|
bitfld.long 0x00 28. " WDDBGHLT ,Watchdog debug halt" "Running,Stopped"
|
|
hexmask.long.word 0x00 16.--27. 1. " WDD ,Watchdog delta value"
|
|
bitfld.long 0x00 15. " WDDIS ,Watchdog disable" "No,Yes"
|
|
bitfld.long 0x00 14. " WDRPROC ,Watchdog reset processor" "All resets,Processor reset"
|
|
newline
|
|
bitfld.long 0x00 13. " WDRSTEN ,Watchdog reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WDFIEN ,Watchdog fault interrupt enable" "No effect,Interrupt"
|
|
hexmask.long.word 0x00 0.--11. 1. " WDV ,Watchdog counter value"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 29. " WDIDLEHLT ,Watchdog idle halt" "Running,Stopped"
|
|
bitfld.long 0x00 28. " WDDBGHLT ,Watchdog debug halt" "Running,Stopped"
|
|
hexmask.long.word 0x00 16.--27. 1. " WDD ,Watchdog delta value"
|
|
bitfld.long 0x00 15. " WDDIS ,Watchdog disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13. " WDRSTEN ,Watchdog reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WDFIEN ,Watchdog fault interrupt enable" "No effect,Interrupt"
|
|
hexmask.long.word 0x00 0.--11. 1. " WDV ,Watchdog counter value"
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "SR,Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree "SUPC (Supply Controller)"
|
|
base ad:0x400E1810
|
|
width 12.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SUPC_CR,Supply Controller Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password Key"
|
|
bitfld.long 0x00 3. " XTALSEL , Crystal Oscillator Select " "No effect,Oscillator output"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VROFF , Voltage Regulator Off" "No effect,Off"
|
|
group.long 0x04++0x0f
|
|
line.long 0x00 "SUPC_SMMR,Supply Controller Supply Monitor Mode Register"
|
|
bitfld.long 0x00 13. " SMIEN , Supply Monitor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SMRSTEN , Supply Monitor Reset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " SMSMPL , Supply Monitor Sampling Period" "Disabled,Continuous,Every 32 SLCK,Every 256 SLCK,Every 2048 SLCK,?..."
|
|
textline " "
|
|
sif cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 0.--3. " SMTH ,Supply Monitor Threshold" "1.6 V,1.72 V,1.84 V,1.96 V,2.08 V,2.2 V,2.32 V,2.44 V,2.56 V,2.68 V,2.8 V,2.92 V,3.04 V,3.16 V,3.28 V,3.4 V"
|
|
else
|
|
bitfld.long 0x00 0.--3. " SMTH ,Supply Monitor Threshold" "1.9 V,2.0 V,2.1 V,2.2 V,2.3 V,2.4 V,2.5 V,2.6 V,2.7 V,2.8 V,2.9 V,3.0 V,3.1 V,3.2 V,3.3 V,3.4 V"
|
|
endif
|
|
line.long 0x04 "SUPC_MR,Supply Controller Mode Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " KEY ,Password Key"
|
|
bitfld.long 0x04 20. " OSCBYPASS , Oscillator Bypass" "No effect,Bypass"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3N*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x04 14. " ONREG ,Voltage Regulator Enabled" "Not used,Used"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 14. " VDDIORDY ,VDDIO Ready" "Removed,Present"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 13. " BODDIS , Brownout Detector Disable" "No,Yes"
|
|
bitfld.long 0x04 12. " BODRSTEN , Brownout Detector Reset Enable" "Disabled,Enabled"
|
|
line.long 0x08 "SUPC_WUMR,Supply Controller Wake Up Mode Register"
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x08 16.--18. " LPDBC ,Low Power DeBounCer Period" "Disabled,2_RTCOUT0,3_RTCOUT0,4_RTCOUT0,5_RTCOUT0,6_RTCOUT0,7_RTCOUT0,8_RTCOUT0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 12.--14. " WKUPDBC , Wake Up Inputs Debouncer" "1 SLCK,3 SLCK,32 SLCK,512 SLCK,4096 SLCK,32768 SLCK,?..."
|
|
textline " "
|
|
sif (cpuis("AT91SAM3U*")||cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x08 8.--10. " FWUPDBC , Force Wake Up Debouncer" "1 SLCK,3 SLCK,32 SLCK,512 SLCK,4096 SLCK,32768 SLCK,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x08 7. " LPDBCCLR ,Low power Debouncer Clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " LPDBCEN1 ,Low power Debouncer ENable WKUP1" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " LPDBCEN0 ,Low power Debouncer ENable WKUP0" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 3. " RTCEN , Real Time Clock Wake Up Enable " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " RTTEN , Real Time Timer Wake Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " SMEN , Supply Monitor Wake Up Enable" "Disabled,Enabled"
|
|
sif (cpuis("AT91SAM3U*")||cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x08 0. " FWUPEN , Force Wake Up Enable" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x0c "SUPC_WUIR,System Controller Wake Up Inputs Register"
|
|
sif (cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x0c 31. " WKUPT15 , Wake Up Input Transition" "Low,High"
|
|
bitfld.long 0x0c 30. " WKUPT14 , Wake Up Input Transition" "Low,High"
|
|
bitfld.long 0x0c 29. " WKUPT13 , Wake Up Input Transition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0c 28. " WKUPT12 , Wake Up Input Transition" "Low,High"
|
|
bitfld.long 0x0c 27. " WKUPT11 , Wake Up Input Transition" "Low,High"
|
|
bitfld.long 0x0c 26. " WKUPT10 , Wake Up Input Transition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " WKUPT9 , Wake Up Input Transition" "Low,High"
|
|
bitfld.long 0x0c 24. " WKUPT8 , Wake Up Input Transition" "Low,High"
|
|
bitfld.long 0x0c 23. " WKUPT7 , Wake Up Input Transition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0c 22. " WKUPT6 , Wake Up Input Transition" "Low,High"
|
|
bitfld.long 0x0c 21. " WKUPT5 , Wake Up Input Transition" "Low,High"
|
|
bitfld.long 0x0c 20. " WKUPT4 , Wake Up Input Transition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " WKUPT3 , Wake Up Input Transition" "Low,High"
|
|
bitfld.long 0x0c 18. " WKUPT2 , Wake Up Input Transition" "Low,High"
|
|
bitfld.long 0x0c 17. " WKUPT1 , Wake Up Input Transition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0c 16. " WKUPT0 , Wake Up Input Transition" "Low,High"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0c 31. " WKUPT15 , Wake Up Input Transition" "High to low,Low to high"
|
|
bitfld.long 0x0c 30. " WKUPT14 , Wake Up Input Transition" "High to low,Low to high"
|
|
bitfld.long 0x0c 29. " WKUPT13 , Wake Up Input Transition" "High to low,Low to high"
|
|
textline " "
|
|
bitfld.long 0x0c 28. " WKUPT12 , Wake Up Input Transition" "High to low,Low to high"
|
|
bitfld.long 0x0c 27. " WKUPT11 , Wake Up Input Transition" "High to low,Low to high"
|
|
bitfld.long 0x0c 26. " WKUPT10 , Wake Up Input Transition" "High to low,Low to high"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " WKUPT9 , Wake Up Input Transition" "High to low,Low to high"
|
|
bitfld.long 0x0c 24. " WKUPT8 , Wake Up Input Transition" "High to low,Low to high"
|
|
bitfld.long 0x0c 23. " WKUPT7 , Wake Up Input Transition" "High to low,Low to high"
|
|
textline " "
|
|
bitfld.long 0x0c 22. " WKUPT6 , Wake Up Input Transition" "High to low,Low to high"
|
|
bitfld.long 0x0c 21. " WKUPT5 , Wake Up Input Transition" "High to low,Low to high"
|
|
bitfld.long 0x0c 20. " WKUPT4 , Wake Up Input Transition" "High to low,Low to high"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " WKUPT3 , Wake Up Input Transition" "High to low,Low to high"
|
|
bitfld.long 0x0c 18. " WKUPT2 , Wake Up Input Transition" "High to low,Low to high"
|
|
bitfld.long 0x0c 17. " WKUPT1 , Wake Up Input Transition" "High to low,Low to high"
|
|
textline " "
|
|
bitfld.long 0x0c 16. " WKUPT0 , Wake Up Input Transition" "High to low,Low to high"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0c 15. " WKUPEN15 , Wake Up Input Transition" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " WKUPEN14 , Wake Up Input Transition" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " WKUPEN13 , Wake Up Input Transition" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " WKUPEN12 , Wake Up Input Transition" "Disabled,Enabled"
|
|
bitfld.long 0x0c 11. " WKUPEN11 , Wake Up Input Transition" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 10. " WKUPEN10 , Wake Up Input Transition" "Disabled,Enabled"
|
|
bitfld.long 0x0c 9. " WKUPEN9 , Wake Up Input Transition" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " WKUPEN8 , Wake Up Input Transition" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " WKUPEN7 , Wake Up Input Transition" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " WKUPEN6 , Wake Up Input Transition" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " WKUPEN5 , Wake Up Input Transition" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 4. " WKUPEN4 , Wake Up Input Transition" "Disabled,Enabled"
|
|
bitfld.long 0x0c 3. " WKUPEN3 , Wake Up Input Transition" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " WKUPEN2 , Wake Up Input Transition" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " WKUPEN1 , Wake Up Input Transition" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " WKUPEN0 , Wake Up Input Transition" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "SUPC_SR,Supply Controller Status Register"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree "GPBR (General Purpose Backup Registers)"
|
|
base ad:0x400E1890
|
|
width 8.
|
|
sif (cpuis("AT91SAM3S8*")||cpuis("AT91SAM3N*")||cpuis("ATSAM4N*")||cpuis("ATSAM4S*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMG5*"))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "GPBR0,General Purpose Backup Register 0"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "GPBR1,General Purpose Backup Register 1"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "GPBR2,General Purpose Backup Register 2"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "GPBR3,General Purpose Backup Register 3"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GPBR4,General Purpose Backup Register 4"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPBR5,General Purpose Backup Register 5"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "GPBR6,General Purpose Backup Register 6"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPBR7,General Purpose Backup Register 7"
|
|
elif (cpuis("ATSAM4E*"))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "GPBR0,General Purpose Backup Register 0"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "GPBR1,General Purpose Backup Register 1"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "GPBR2,General Purpose Backup Register 2"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "GPBR3,General Purpose Backup Register 3"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GPBR4,General Purpose Backup Register 4"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPBR5,General Purpose Backup Register 5"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "GPBR6,General Purpose Backup Register 6"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPBR7,General Purpose Backup Register 7"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPBR8,General Purpose Backup Register 8"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GPBR9,General Purpose Backup Register 9"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "GPBR10,General Purpose Backup Register 10"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "GPBR11,General Purpose Backup Register 11"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "GPBR12,General Purpose Backup Register 12"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "GPBR13,General Purpose Backup Register 13"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "GPBR14,General Purpose Backup Register 14"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "GPBR15,General Purpose Backup Register 15"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPBR16,General Purpose Backup Register 16"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "GPBR17,General Purpose Backup Register 17"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "GPBR18,General Purpose Backup Register 18"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "GPBR19,General Purpose Backup Register 19"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "GPBR0,General Purpose Backup Register 0"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "GPBR1,General Purpose Backup Register 1"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "GPBR2,General Purpose Backup Register 2"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "GPBR3,General Purpose Backup Register 3"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "EEFC (Enhanced Embedded Flash Controller)"
|
|
base ad:0x400E0A00
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EEFC_FMR,EEFC Flash Mode Register"
|
|
sif (cpuis("ATSAM4S*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 26. " CLOE ,Code Loops Optimization Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24. " FAM , Flash Access Mode" "128-bit,64-bit"
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4S*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
textline " "
|
|
bitfld.long 0x00 16. " SCOD ,Sequential Code Optimization Disable" "No,Yes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " FWS ,Flash Wait State" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FRDY ,Flash Ready Interrupt Enable" "Disabled,Enabled"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "EEFC_FCR,EEFC Flash Command Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " FKEY , Flash Writing Protection Key"
|
|
textline " "
|
|
hexmask.long.word 0x00 8.--23. 1. " FARG ,Flash Command Argument"
|
|
textline " "
|
|
sif (cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--4. " FCMD ,Flash Command" "GETD,WP,WPL,EWP,EWPL,EA,,EPA,SLB,CLB,GLB,SGPB,CGPB,GGPB,STUI,SPUI,GCALB,ES,WUS,EUS,STUS,SPUS,?..."
|
|
else
|
|
hexmask.long.byte 0x00 0.--7. 1. " FCMD ,Flash Command"
|
|
endif
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "EEFC_FSR,EEFC Flash Status Register"
|
|
in
|
|
rgroup.long 0x0c++0x03
|
|
line.long 0x00 "EEFC_FRR,EEFC Flash Result Register"
|
|
hexmask.long 0x00 0.--31. 1. " FVALUE , Flash Result Value"
|
|
width 0xb
|
|
tree.end
|
|
tree "CMCC (Cortex M Cache Controller)"
|
|
base ad:0x400C4000
|
|
width 13.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "CMCC_TYPE,Cache Controller Type Register"
|
|
bitfld.long 0x00 11.--13. " CLSIZE ,Cache Line Size" "4 bytes,8 bytes,16 bytes,32 bytes,?..."
|
|
bitfld.long 0x00 8.--10. " CSIZE ,Cache Size" "1 KBytes,2 KBytes,4 KBytes,8 KBytes,?..."
|
|
bitfld.long 0x00 7. " LCKDOWN ,Lock Down Supported" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " WAYNUM ,Number of Way" "Direct Cache,2-WAY,4-WAY,8-WAY"
|
|
bitfld.long 0x00 4. " RRP ,Random Selection Policy Supported" "Not supported,Supported"
|
|
bitfld.long 0x00 3. " LRUP ,Least Recently Used Policy Supported" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RANDP ,Random Selection Policy Supported" "Not supported,Supported"
|
|
bitfld.long 0x00 1. " GCLK ,Dynamic Clock Gating Supported" "Not supported,Supported"
|
|
bitfld.long 0x00 0. " AP ,Access Port Access Allowed" "Disabled,Enabled"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "CMCC_CFG,Cache Controller Configuration Register"
|
|
bitfld.long 0x00 0. " GCLKDIS ,Disable Clock Gating" "No,Yes"
|
|
sif (cpuis("ATSAM4E*")||cpuis("ATSAM4S*"))
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x00 "CMCC_CTRL,Cache Controller Control Register"
|
|
bitfld.long 0x00 0. " CEN ,Cache Controller Enable" "Disable,Enable"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CMCC_SR,Cache Controller Status Register"
|
|
bitfld.long 0x00 0. " CSTS ,Cache Controller Status" "Disabled,Enabled"
|
|
else
|
|
wgroup.long 0x08++0x7
|
|
line.long 0x00 "CMCC_CTRL,Cache Controller Control Register"
|
|
bitfld.long 0x00 0. " CEN ,Cache Controller Enable" "Disabled,Enabled"
|
|
line.long 0x04 "CMCC_SR,Cache Controller Status Register"
|
|
bitfld.long 0x04 0. " CSTS ,Cache Controller Status" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x20++0x13
|
|
line.long 0x00 "CMCC_MAINT0,Cache Controller Maintenance Register 0"
|
|
bitfld.long 0x00 0. " INVALL ,Cache Controller Invalidate All" "No effect,Invalidate"
|
|
line.long 0x04 "CMCC_MAINT1,Cache Controller Maintenance Register 1"
|
|
bitfld.long 0x04 30.--31. " WAY ,Invalidate Way" "Way 0,Way 1,Way 2,Way 3"
|
|
sif (cpuis("ATSAM4E*")||cpuis("ATSAM4S*"))
|
|
bitfld.long 0x04 4.--8. " INDEX ,Invalidate Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
bitfld.long 0x04 4.--7. " INDEX ,Invalidate Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x28++0x7
|
|
line.long 0x00 "CMCC_MCFG,Cache Controller Monitor Configuration Register"
|
|
bitfld.long 0x00 0.--1. " MODE ,Cache Controller Monitor Counter Mode" "Cycle counter,Instruction hit,Data hit,?..."
|
|
line.long 0x04 "CMCC_MEN,Cache Controller Monitor Enable Register"
|
|
bitfld.long 0x04 0. " MENABLE ,Cache Controller Monitor Enable" "Disabled,Enabled"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "CMCC_MCTRL,Cache Controller Monitor Control Register"
|
|
bitfld.long 0x00 0. " SWRST ,Monitor" "No effect,Reset"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "CMCC_MSR,Cache Controller Monitor Status Register"
|
|
width 0xB
|
|
tree.end
|
|
tree "MATRIX (Bus Matrix User Interface)"
|
|
base ad:0x400E0200
|
|
tree "Bus Matrix Master Configuration Registers"
|
|
width 15.
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "MATRIX_MCFG0,Bus Matrix Master Configuration 0 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "MATRIX_MCFG1,Bus Matrix Master Configuration 1 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "MATRIX_MCFG2,Bus Matrix Master Configuration 2 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "MATRIX_MCFG3,Bus Matrix Master Configuration 3 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MATRIX_MCFG4,Bus Matrix Master Configuration 4 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MATRIX_MCFG5,Bus Matrix Master Configuration 5 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MATRIX_MCFG6,Bus Matrix Master Configuration 6 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "MATRIX_MCFG7,Bus Matrix Master Configuration 7 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MATRIX_MCFG8,Bus Matrix Master Configuration 8 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MATRIX_MCFG9,Bus Matrix Master Configuration 9 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "MATRIX_MCFG10,Bus Matrix Master Configuration 10 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "MATRIX_MCFG11,Bus Matrix Master Configuration 11 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "MATRIX_MCFG12,Bus Matrix Master Configuration 12 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "MATRIX_MCFG13,Bus Matrix Master Configuration 13 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "MATRIX_MCFG14,Bus Matrix Master Configuration 14 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "MATRIX_MCFG15,Bus Matrix Master Configuration 15 Register"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Unlimited Length Burst,Single Access,4-beat Burst,8-beat Burst,16-beat Burst,32-beat Burst,64-beat Burst,128-beat Burst"
|
|
tree.end
|
|
tree "Bus Matrix Slave Configuration Registers"
|
|
width 17.
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MATRIX_SCFG0,Bus Matrix Slave Configuration 0 Register"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "MATRIX_SCFG1,Bus Matrix Slave Configuration 1 Register"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "MATRIX_SCFG2,Bus Matrix Slave Configuration 2 Register"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "MATRIX_SCFG3,Bus Matrix Slave Configuration 3 Register"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "MATRIX_SCFG4,Bus Matrix Slave Configuration 4 Register"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "MATRIX_SCFG5,Bus Matrix Slave Configuration 5 Register"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MATRIX_SCFG6,Bus Matrix Slave Configuration 6 Register"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "MATRIX_SCFG7,Bus Matrix Slave Configuration 7 Register"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "MATRIX_SCFG8,Bus Matrix Slave Configuration 8 Register"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "MATRIX_SCFG9,Bus Matrix Slave Configuration 9 Register"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "MATRIX_SCFG10,Bus Matrix Slave Configuration 10 Register"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "MATRIX_SCFG11,Bus Matrix Slave Configuration 11 Register"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "MATRIX_SCFG12,Bus Matrix Slave Configuration 12 Register"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "MATRIX_SCFG13,Bus Matrix Slave Configuration 13 Register"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "MATRIX_SCFG14,Bus Matrix Slave Configuration 14 Register"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "MATRIX_SCFG15,Bus Matrix Slave Configuration 15 Register"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "No Default Master,Last Default Master,Fixed Default Master,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " SLOT_CYCLE ,Maximum Bus Grant Duration for Masters"
|
|
tree.end
|
|
width 15.
|
|
tree "Bus Matrix Priority Registers A-B For Slaves"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "MATRIX_PRAS0,Bus Matrix Priority Register 0 A For Slaves"
|
|
sif !cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
sif !cpuis("ATSAM4N*")
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS0,Bus Matrix Priority Register 0 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "MATRIX_PRAS1,Bus Matrix Priority Register 1 A For Slaves"
|
|
sif !cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
sif !cpuis("ATSAM4N*")
|
|
group.long (0x88+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS1,Bus Matrix Priority Register 1 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
endif
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "MATRIX_PRAS2,Bus Matrix Priority Register 2 A For Slaves"
|
|
sif !cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
sif !cpuis("ATSAM4N*")
|
|
group.long (0x90+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS2,Bus Matrix Priority Register 2 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
endif
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "MATRIX_PRAS3,Bus Matrix Priority Register 3 A For Slaves"
|
|
sif !cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
sif !cpuis("ATSAM4N*")
|
|
group.long (0x98+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS3,Bus Matrix Priority Register 3 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
endif
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "MATRIX_PRAS4,Bus Matrix Priority Register 4 A For Slaves"
|
|
sif !cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
sif !cpuis("ATSAM4N*")
|
|
group.long (0xA0+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS4,Bus Matrix Priority Register 4 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
endif
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "MATRIX_PRAS5,Bus Matrix Priority Register 5 A For Slaves"
|
|
sif !cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
sif !cpuis("ATSAM4N*")
|
|
group.long (0xA8+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS5,Bus Matrix Priority Register 5 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
endif
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "MATRIX_PRAS6,Bus Matrix Priority Register 6 A For Slaves"
|
|
sif !cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
sif !cpuis("ATSAM4N*")
|
|
group.long (0xB0+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS6,Bus Matrix Priority Register 6 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
endif
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "MATRIX_PRAS7,Bus Matrix Priority Register 7 A For Slaves"
|
|
sif !cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
sif !cpuis("ATSAM4N*")
|
|
group.long (0xB8+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS7,Bus Matrix Priority Register 7 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
endif
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "MATRIX_PRAS8,Bus Matrix Priority Register 8 A For Slaves"
|
|
sif !cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
sif !cpuis("ATSAM4N*")
|
|
group.long (0xC0+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS8,Bus Matrix Priority Register 8 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
endif
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "MATRIX_PRAS9,Bus Matrix Priority Register 9 A For Slaves"
|
|
sif !cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
sif !cpuis("ATSAM4N*")
|
|
group.long (0xC8+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS9,Bus Matrix Priority Register 9 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
endif
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "MATRIX_PRAS10,Bus Matrix Priority Register 10 A For Slaves"
|
|
sif !cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
sif !cpuis("ATSAM4N*")
|
|
group.long (0xD0+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS10,Bus Matrix Priority Register 10 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
endif
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "MATRIX_PRAS11,Bus Matrix Priority Register 11 A For Slaves"
|
|
sif !cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
sif !cpuis("ATSAM4N*")
|
|
group.long (0xD8+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS11,Bus Matrix Priority Register 11 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
endif
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "MATRIX_PRAS12,Bus Matrix Priority Register 12 A For Slaves"
|
|
sif !cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
sif !cpuis("ATSAM4N*")
|
|
group.long (0xE0+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS12,Bus Matrix Priority Register 12 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
endif
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "MATRIX_PRAS13,Bus Matrix Priority Register 13 A For Slaves"
|
|
sif !cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
sif !cpuis("ATSAM4N*")
|
|
group.long (0xE8+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS13,Bus Matrix Priority Register 13 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
endif
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "MATRIX_PRAS14,Bus Matrix Priority Register 14 A For Slaves"
|
|
sif !cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
sif !cpuis("ATSAM4N*")
|
|
group.long (0xF0+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS14,Bus Matrix Priority Register 14 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
endif
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "MATRIX_PRAS15,Bus Matrix Priority Register 15 A For Slaves"
|
|
sif !cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
sif !cpuis("ATSAM4N*")
|
|
group.long (0xF8+0x04)++0x03
|
|
line.long 0x00 "MATRIX_PRBS15,Bus Matrix Priority Register 15 B For Slaves"
|
|
bitfld.long 0x00 28.--29. " M15PR ,Master 15 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 24.--25. " M14PR ,Master 14 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " M13PR ,Master 13 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 16.--17. " M12PR ,Master 12 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " M11PR ,Master 11 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 8.--9. " M10PR ,Master 10 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M9PR ,Master 9 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
bitfld.long 0x00 0.--1. " M8PR ,Master 8 Priority" "Round-robin - Lowest,Fixed priority,Fixed priority,Round-robin - Highest"
|
|
endif
|
|
tree.end
|
|
width 14.
|
|
sif !cpuis("ATSAM4N*")
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "MATRIX_MRCR,Bus Matrix Master Remap Control Register"
|
|
bitfld.long 0x00 15. " RCB15 ,Remap Command Bit for Master 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCB14 ,Remap Command Bit for Master 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCB13 ,Remap Command Bit for Master 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCB12 ,Remap Command Bit for Master 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCB11 ,Remap Command Bit for Master 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCB10 ,Remap Command Bit for Master 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCB9 ,Remap Command Bit for Master 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCB8 ,Remap Command Bit for Master 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCB7 ,Remap Command Bit for Master 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCB6 ,Remap Command Bit for Master 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCB5 ,Remap Command Bit for Master 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCB4 ,Remap Command Bit for Master 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCB3 ,Remap Command Bit for Master 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCB2 ,Remap Command Bit for Master 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCB1 ,Remap Command Bit for Master 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCB0 ,Remap Command Bit for Master 0" "Disabled,Enabled"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "MATRIX_SFR0,Bus Matrix Special Function Register 0"
|
|
endif
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "CCFG_SYSIO,System I/O Configuration Register"
|
|
bitfld.long 0x00 12. " SYSIO12 ,PB12(PWML1) or ERASE Assignment" "ERASE,PWML1"
|
|
sif cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 7. " SYSIO7 ,PB7 or TCK/SWCLK Assignment" "TCK/SWCLK,PB7"
|
|
else
|
|
bitfld.long 0x00 11. " SYSIO11 ,PB11 or DDP Assignment" "DDP,PB11"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SYSIO10 ,PB10 or DDM Assignment" "DDM,PB10"
|
|
bitfld.long 0x00 7. " SYSIO7 ,PB7 or TCK/SWCLK Assignment" "TCK/SWCLK,PB7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " SYSIO6 ,PB6 or TMS/SWDIO Assignment" "TMS/SWDIO,PB6"
|
|
bitfld.long 0x00 5. " SYSIO5 ,PB5(TWCK1/PWML0) or TDO/TRACESWO Assignment" "TDO/TRACESWO,TWCK1/PWML0"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SYSIO4 ,PB4(TWD1/PWMH2) or TDI Assignment" "TDI,TWD1/PWMH2"
|
|
sif !cpuis("ATSAM4N*")
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "CCFG_SMCNFCS,SMC NAND Flash Chip select Configuration Register"
|
|
bitfld.long 0x00 3. " SMC_NFCS3 ,SMC NAND Flash Chip Select 3 Assignment" "Not assigned,Assigned"
|
|
bitfld.long 0x00 2. " SMC_NFCS2 ,SMC NAND Flash Chip Select 2 Assignment" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SMC_NFCS1 ,SMC NAND Flash Chip Select 1 Assignment" "Not assigned,Assigned"
|
|
bitfld.long 0x00 0. " SMC_NFCS0 ,SMC NAND Flash Chip Select 0 Assignment" "Not assigned,Assigned"
|
|
endif
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "MATRIX_WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
rgroup.long 0x1E8++0x03
|
|
line.long 0x00 "MATRIX_WPSR,Write Protect Status Register"
|
|
hexmask.long.word 0x00 8.--23. 1. " WPVSRC ,Write Protect Violation Source"
|
|
bitfld.long 0x00 0. " WPVS ,Write Protect Violation Status" "No Write Protect,One Write Protect"
|
|
width 0xB
|
|
tree.end
|
|
tree "DMAC (Direct Memory Access Controller)"
|
|
base ad:0x400C0000
|
|
width 13.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMAC_GCFG,DMAC Global Configuration Register"
|
|
bitfld.long 0x00 4. " ARB_CFG ,Arbiter configuration" "Fixed,Round robin"
|
|
line.long 0x04 "DMAC_EN,DMAC Enable Register"
|
|
bitfld.long 0x04 0. " ENABLE ,DMA Controller Enable" "Disabled,Enabled"
|
|
line.long 0x08 "DMAC_SREQ,Software Single Request Register"
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x08 11. " DSREQ5 ,Request a destination single transfer on channel 5" "Not requested,Requested"
|
|
bitfld.long 0x08 10. " SSREQ5 ,Request a source single transfer on channel 5" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 9. " DSREQ4 ,Request a destination single transfer on channel 4" "Not requested,Requested"
|
|
bitfld.long 0x08 8. " SSREQ4 ,Request a source single transfer on channel 4" "Not requested,Requested"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 7. " DSREQ3 ,Request a destination single transfer on channel 3" "Not requested,Requested"
|
|
bitfld.long 0x08 6. " SSREQ3 ,Request a source single transfer on channel 3" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 5. " DSREQ2 ,Request a destination single transfer on channel 2" "Not requested,Requested"
|
|
bitfld.long 0x08 4. " SSREQ2 ,Request a source single transfer on channel 2" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DSREQ1 ,Request a destination single transfer on channel 1" "Not requested,Requested"
|
|
bitfld.long 0x08 2. " SSREQ1 ,Request a source single transfer on channel 1" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 1. " DSREQ0 ,Request a destination single transfer on channel 0" "Not requested,Requested"
|
|
bitfld.long 0x08 0. " SSREQ0 ,Request a source single transfer on channel 0" "Not requested,Requested"
|
|
line.long 0x0C "DMAC_CREQ,Software Chunk Transfer Request Register"
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x0C 11. " DCREQ5 ,Request a destination chunk transfer on channel 5" "Not requested,Requested"
|
|
bitfld.long 0x0C 10. " SCREQ5 ,Request a source chunk transfer on channel 5" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " DCREQ4 ,Request a destination chunk transfer on channel 4" "Not requested,Requested"
|
|
bitfld.long 0x0C 8. " SCREQ4 ,Request a source chunk transfer on channel 4" "Not requested,Requested"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 7. " DCREQ3 ,Request a destination chunk transfer on channel 3" "Not requested,Requested"
|
|
bitfld.long 0x0C 6. " SCREQ3 ,Request a source chunk transfer on channel 3" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " DCREQ2 ,Request a destination chunk transfer on channel 2" "Not requested,Requested"
|
|
bitfld.long 0x0C 4. " SCREQ2 ,Request a source chunk transfer on channel 2" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " DCREQ1 ,Request a destination chunk transfer on channel 1" "Not requested,Requested"
|
|
bitfld.long 0x0C 2. " SCREQ1 ,Request a source chunk transfer on channel 1" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " DCREQ0 ,Request a destination chunk transfer on channel 0" "Not requested,Requested"
|
|
bitfld.long 0x0C 0. " SCREQ0 ,Request a source chunk transfer on channel 0" "Not requested,Requested"
|
|
line.long 0x10 "DMAC_LAST,Software Last Transfer Flag Register"
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x10 11. " DLAST5 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 10. " SLAST5 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 9. " DLAST4 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 8. " SLAST4 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 7. " DLAST3 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 6. " SLAST3 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 5. " DLAST2 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 4. " SLAST2 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 3. " DLAST1 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 2. " SLAST1 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 1. " DLAST0 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 0. " SLAST0 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "DMAC_EBCIMR, DMAC Error Buffer Transfer and Chained Buffer Transfer Mask Register"
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " ERR5_set/clr ,Access Error Interrupt Enable Register" "Masked,Not masked"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " ERR4_set/clr ,Access Error Interrupt Enable Register" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " ERR3_set/clr ,Access Error Interrupt Enable Register" "Masked,Not masked"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " ERR2_set/clr ,Access Error Interrupt Enable Register" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " ERR1_set/clr ,Access Error Interrupt Enable Register" "Masked,Not masked"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " ERR0_set/clr ,Access Error Interrupt Enable Register" "Masked,Not masked"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " CBTC5_set/clr ,Chained Buffer Transfer Completed " "Masked,Not masked"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " CBTC4_set/clr ,Chained Buffer Transfer Completed " "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " CBTC3_set/clr , Chained Buffer Transfer Completed " "Masked,Not masked"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " CBTC2_set/clr , Chained Buffer Transfer Completed " "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " CBTC1_set/clr , Chained Buffer Transfer Completed " "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " CBTC0_set/clr , Chained Buffer Transfer Completed " "Masked,Not masked"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " BTC5_set/clr ,Buffer Transfer Completed" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " BTC4_set/clr ,Buffer Transfer Completed" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " BTC3_set/clr ,Buffer Transfer Completed" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " BTC2_set/clr ,Buffer Transfer Completed" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " BTC1_set/clr ,Buffer Transfer Completed" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BTC0_set/clr ,Buffer Transfer Completed" "Masked,Not masked"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x00 "DMAC_EBCISR, DMAC Error Buffer Transfer and Chained Buffer Transfer Status Register"
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 21. " ERR5 , Access Error Interrupt Enable Register" "No error,Error"
|
|
bitfld.long 0x00 20. " ERR4 , Access Error Interrupt Enable Register" "No error,Error"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " ERR3 , Access Error Interrupt Enable Register" "No error,Error"
|
|
bitfld.long 0x00 18. " ERR2 , Access Error Interrupt Enable Register" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ERR1 , Access Error Interrupt Enable Register" "No error,Error"
|
|
bitfld.long 0x00 16. " ERR0 , Access Error Interrupt Enable Register" "No error,Error"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 13. " CBTC5 ,Channel 5 Chained buffer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 12. " CBTC4 , Channel 4 Chained buffer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " CBTC3 ,Channel 3 Chained buffer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 10. " CBTC2 ,Channel 2 Chained buffer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CBTC1 ,Channel 1 Chained buffer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 8. " CBTC0 ,Channel 0 Chained buffer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 5. " BTC5 , Channel 5 buffer transfer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 4. " BTC4 , Channel 4 buffer transfer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " BTC3 ,Channel 3 buffer transfer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 2. " BTC2 ,Channel 2 buffer transfer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BTC1 ,Channel 1 buffer transfer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 0. " BTC0 ,Channel 0 buffer transfer has terminated" "Not terminated,Terminated"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x00 "DMAC_CHER, DMAC Channel Handler Enable Register"
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 29. " KEEP5 ,Resume the current channel from an automatic stall state" "Not resumed,Resumed"
|
|
bitfld.long 0x00 28. " KEEP4 ,Resume the current channel from an automatic stall state" "Not resumed,Resumed"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " KEEP3 ,Resume the current channel from an automatic stall state" "Not resumed,Resumed"
|
|
bitfld.long 0x00 26. " KEEP2 ,Resume the current channel from an automatic stall state" "Not resumed,Resumed"
|
|
textline " "
|
|
bitfld.long 0x00 25. " KEEP1 ,Resume the current channel from an automatic stall state" "Not resumed,Resumed"
|
|
bitfld.long 0x00 24. " KEEP0 ,Resume the current channel from an automatic stall state" "Not resumed,Resumed"
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
textline " "
|
|
bitfld.long 0x00 13. " SUSP5 ,Freez the relevant channel and its current context" "Not resumed,Resumed"
|
|
bitfld.long 0x00 12. " SUSP4 ,Freez the relevant channel and its current context" "Not resumed,Resumed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SUSP3 ,Freez the relevant channel and its current context" "Not resumed,Resumed"
|
|
bitfld.long 0x00 10. " SUSP2 ,Freez the relevant channel and its current context" "Not resumed,Resumed"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SUSP1 ,Freez the relevant channel and its current context" "Not resumed,Resumed"
|
|
bitfld.long 0x00 8. " SUSP0 ,Freez the relevant channel and its current context" "Not resumed,Resumed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ENA5 ,Enable the relevant channel" "Not resumed,Resumed"
|
|
bitfld.long 0x00 4. " ENA4 ,Enable the relevant channel" "Not resumed,Resumed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENA3 ,Enable the relevant channel" "Not resumed,Resumed"
|
|
bitfld.long 0x00 2. " ENA2 ,Enable the relevant channel" "Not resumed,Resumed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENA1 ,Enable the relevant channel" "Not resumed,Resumed"
|
|
bitfld.long 0x00 0. " ENA0 ,Enable the relevant channel" "Not resumed,Resumed"
|
|
endif
|
|
group.long 0x030++0x3
|
|
line.long 0x00 "DMAC_CHSR, DMAC Channel Handler Status Register"
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 29. " STAL5 , Relevant channel enabled" "Not stalled,Stalled"
|
|
bitfld.long 0x00 28. " STAL4 , Relevant channel enabled" "Not stalled,Stalled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " STAL3 , Relevant channel enabled" "Not stalled,Stalled"
|
|
bitfld.long 0x00 26. " STAL2 , Relevant channel enabled" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " STAL1 , Relevant channel enabled" "Not stalled,Stalled"
|
|
bitfld.long 0x00 24. " STAL0 ,Relevant channel enabled" "Not stalled,Stalled"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 21. " EMPT5 ,Relevant channel is empty" "Not Empty,Empty"
|
|
bitfld.long 0x00 20. " EMPT4 ,Relevant channel is empty" "Not Empty,Empty"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " EMPT3 ,Relevant channel is empty" "Not Empty,Empty"
|
|
bitfld.long 0x00 18. " EMPT2 ,Relevant channel is empty" "Not Empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EMPT1 ,Relevant channel is empty" "Not Empty,Empty"
|
|
bitfld.long 0x00 16. " EMPT0 ,Relevant channel is empty" "Not Empty,Empty"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " SUSP5_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " SUSP4_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " SUSP3_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " SUSP2_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " SUSP1_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " SUSP0_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " ENA5_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENA4_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENA3_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " ENA2_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " ENA1_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " ENA0_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
tree "Channel 0"
|
|
group.long 0x3C++0x17
|
|
line.long 0x00 "DMAC_SADDR0,DMAC Channel 0 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR0, DMAC Channel 0 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR0,DMAC Channel 0 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " DSCR0 , Buffer Transfer descriptor address"
|
|
line.long 0x0c "DMAC_CTRLA0,DMAC Channel 0 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "In progress,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB0,DMAC Channel 0 Control B Register"
|
|
bitfld.long 0x10 30. " IEN , BTC[0] flag enable" "Enabled,Disabled"
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
line.long 0x14 "DMAC_CFG0,DMAC Channel 0 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
textline " "
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 0 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 0 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 0 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Channel 1"
|
|
group.long 0x64++0x17
|
|
line.long 0x00 "DMAC_SADDR1,DMAC Channel 1 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR1, DMAC Channel 1 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR1,DMAC Channel 1 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " DSCR1 , Buffer Transfer descriptor address"
|
|
line.long 0x0c "DMAC_CTRLA1,DMAC Channel 1 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "In progress,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB1,DMAC Channel 1 Control B Register"
|
|
bitfld.long 0x10 30. " IEN , BTC[1] flag enable" "Enabled,Disabled"
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
line.long 0x14 "DMAC_CFG1,DMAC Channel 1 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
textline " "
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 1 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 1 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 1 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Channel 2"
|
|
group.long 0x8C++0x17
|
|
line.long 0x00 "DMAC_SADDR2,DMAC Channel 2 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR2, DMAC Channel 2 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR2,DMAC Channel 2 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " DSCR2 , Buffer Transfer descriptor address"
|
|
line.long 0x0c "DMAC_CTRLA2,DMAC Channel 2 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "In progress,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB2,DMAC Channel 2 Control B Register"
|
|
bitfld.long 0x10 30. " IEN , BTC[2] flag enable" "Enabled,Disabled"
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
line.long 0x14 "DMAC_CFG2,DMAC Channel 2 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
textline " "
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 2 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 2 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 2 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Channel 3"
|
|
group.long 0xB4++0x17
|
|
line.long 0x00 "DMAC_SADDR3,DMAC Channel 3 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR3, DMAC Channel 3 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR3,DMAC Channel 3 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " DSCR3 , Buffer Transfer descriptor address"
|
|
line.long 0x0c "DMAC_CTRLA3,DMAC Channel 3 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "In progress,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB3,DMAC Channel 3 Control B Register"
|
|
bitfld.long 0x10 30. " IEN , BTC[3] flag enable" "Enabled,Disabled"
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
line.long 0x14 "DMAC_CFG3,DMAC Channel 3 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
textline " "
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 3 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 3 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 3 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Channel 4"
|
|
group.long 0xDC++0x17
|
|
line.long 0x00 "DMAC_SADDR4,DMAC Channel 4 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR4, DMAC Channel 4 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR4,DMAC Channel 4 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " DSCR4 , Buffer Transfer descriptor address"
|
|
line.long 0x0c "DMAC_CTRLA4,DMAC Channel 4 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "In progress,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB4,DMAC Channel 4 Control B Register"
|
|
bitfld.long 0x10 30. " IEN , BTC[4] flag enable" "Enabled,Disabled"
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
line.long 0x14 "DMAC_CFG4,DMAC Channel 4 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
textline " "
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 4 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 4 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 4 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Channel 5"
|
|
group.long 0x104++0x17
|
|
line.long 0x00 "DMAC_SADDR5,DMAC Channel 5 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR5, DMAC Channel 5 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR5,DMAC Channel 5 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " DSCR5 , Buffer Transfer descriptor address"
|
|
line.long 0x0c "DMAC_CTRLA5,DMAC Channel 5 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "In progress,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB5,DMAC Channel 5 Control B Register"
|
|
bitfld.long 0x10 30. " IEN , BTC[5] flag enable" "Enabled,Disabled"
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
line.long 0x14 "DMAC_CFG5,DMAC Channel 5 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
textline " "
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 5 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 5 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 5 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
else
|
|
tree "Channel 0"
|
|
group.long 0x3C++0x17
|
|
line.long 0x00 "DMAC_SADDR0,DMAC Channel 0 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR0, DMAC Channel 0 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR0,DMAC Channel 0 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " DSCR0 , Buffer Transfer descriptor address"
|
|
line.long 0x0c "DMAC_CTRLA0,DMAC Channel 0 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "In progress,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X8C"))
|
|
textline " "
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
elif (cpuis("ATSAM4E*"))
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x0c 20. " DCSIZE , Destination Chunk Transfer size" "1,4"
|
|
textline " "
|
|
bitfld.long 0x0c 16. " SCSIZE , Source Chunk Transfer Size" "1,4"
|
|
hexmask.long.word 0x0c 0.--11. 1. " BTSIZE ,Buffer Transfer Size"
|
|
endif
|
|
line.long 0x10 "DMAC_CTRLB0,DMAC Channel 0 Control B Register"
|
|
bitfld.long 0x10 30. " IEN , BTC[0] flag enable" "Enabled,Disabled"
|
|
sif (cpuis("ATSAM4E*"))
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 21.--22. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA"
|
|
else
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
line.long 0x14 "DMAC_CFG0,DMAC Channel 0 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
textline " "
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 0 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 0 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 0 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Channel 1"
|
|
group.long 0x64++0x17
|
|
line.long 0x00 "DMAC_SADDR1,DMAC Channel 1 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR1, DMAC Channel 1 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR1,DMAC Channel 1 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " DSCR1 , Buffer Transfer descriptor address"
|
|
line.long 0x0c "DMAC_CTRLA1,DMAC Channel 1 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "In progress,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X8C"))
|
|
textline " "
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
elif (cpuis("ATSAM4E*"))
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x0c 20. " DCSIZE , Destination Chunk Transfer size" "1,4"
|
|
textline " "
|
|
bitfld.long 0x0c 16. " SCSIZE , Source Chunk Transfer Size" "1,4"
|
|
hexmask.long.word 0x0c 0.--11. 1. " BTSIZE ,Buffer Transfer Size"
|
|
endif
|
|
line.long 0x10 "DMAC_CTRLB1,DMAC Channel 1 Control B Register"
|
|
bitfld.long 0x10 30. " IEN , BTC[1] flag enable" "Enabled,Disabled"
|
|
sif (cpuis("ATSAM4E*"))
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 21.--22. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA"
|
|
else
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
line.long 0x14 "DMAC_CFG1,DMAC Channel 1 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
textline " "
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 1 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 1 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 1 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Channel 2"
|
|
group.long 0x8C++0x17
|
|
line.long 0x00 "DMAC_SADDR2,DMAC Channel 2 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR2, DMAC Channel 2 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR2,DMAC Channel 2 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " DSCR2 , Buffer Transfer descriptor address"
|
|
line.long 0x0c "DMAC_CTRLA2,DMAC Channel 2 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "In progress,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X8C"))
|
|
textline " "
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
elif (cpuis("ATSAM4E*"))
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x0c 20. " DCSIZE , Destination Chunk Transfer size" "1,4"
|
|
textline " "
|
|
bitfld.long 0x0c 16. " SCSIZE , Source Chunk Transfer Size" "1,4"
|
|
hexmask.long.word 0x0c 0.--11. 1. " BTSIZE ,Buffer Transfer Size"
|
|
endif
|
|
line.long 0x10 "DMAC_CTRLB2,DMAC Channel 2 Control B Register"
|
|
bitfld.long 0x10 30. " IEN , BTC[2] flag enable" "Enabled,Disabled"
|
|
sif (cpuis("ATSAM4E*"))
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 21.--22. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA"
|
|
else
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
line.long 0x14 "DMAC_CFG2,DMAC Channel 2 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
textline " "
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 2 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 2 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 2 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Channel 3"
|
|
group.long 0xB4++0x17
|
|
line.long 0x00 "DMAC_SADDR3,DMAC Channel 3 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR3, DMAC Channel 3 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR3,DMAC Channel 3 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " DSCR3 , Buffer Transfer descriptor address"
|
|
line.long 0x0c "DMAC_CTRLA3,DMAC Channel 3 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "In progress,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X8C"))
|
|
textline " "
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
elif (cpuis("ATSAM4E*"))
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x0c 20. " DCSIZE , Destination Chunk Transfer size" "1,4"
|
|
textline " "
|
|
bitfld.long 0x0c 16. " SCSIZE , Source Chunk Transfer Size" "1,4"
|
|
hexmask.long.word 0x0c 0.--11. 1. " BTSIZE ,Buffer Transfer Size"
|
|
endif
|
|
line.long 0x10 "DMAC_CTRLB3,DMAC Channel 3 Control B Register"
|
|
bitfld.long 0x10 30. " IEN , BTC[3] flag enable" "Enabled,Disabled"
|
|
sif (cpuis("ATSAM4E*"))
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 21.--22. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA"
|
|
else
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
line.long 0x14 "DMAC_CFG3,DMAC Channel 3 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
textline " "
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 3 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 3 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 3 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4E*"))
|
|
sif (cpuis("ATSAM4E*"))
|
|
group.long 0x1E4++0x3
|
|
else
|
|
group.long 0xE4++0x3
|
|
endif
|
|
line.long 0x00 "DMAC_WPMR,DMAC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
sif (cpuis("ATSAM4E*"))
|
|
hgroup.long 0x1E8++0x3
|
|
else
|
|
hgroup.long 0xE8++0x3
|
|
endif
|
|
hide.long 0x00 "DMAC_WPSR,DMAC Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "SMC (Static Memory Controller)"
|
|
base ad:0x40060000
|
|
width 13.
|
|
tree "CS 0"
|
|
group.long 0x0++0x0F
|
|
line.long 0x00 "SMC_SETUP0,SMC Setup Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--22. 1. " NRD_SETUP ,NRD Setup Length"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
hexmask.long.byte 0x00 0.--6. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x04 "SMC_PULSE0,SMC Pulse Register"
|
|
hexmask.long.byte 0x04 24.--29. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x04 16.--21. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--13. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
hexmask.long.byte 0x04 0.--5. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x08 "SMC_CYCLE0,SMC Cycle Register"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
line.long 0x0C "SMC_MODE0,SMC MODE Register"
|
|
bitfld.long 0x0C 28.--29. " PS ,Page Size" "4-byte page,8-byte page,16-byte page,32-byte page"
|
|
bitfld.long 0x0C 20. " PMEN ,Page Mode Enabled" "Standard,Asynchronous burst"
|
|
textline " "
|
|
bitfld.long 0x0C 16.--19. " TDF_CYCLES ,Data Float Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " WRITE_MODE ,States will be inserted after the setup of NWE/NCS" "NCS,NWE"
|
|
bitfld.long 0x0C 0. " READ_MODE ,Read operation is controlled by the NRD/NCS signal" "NCS,NRD"
|
|
tree.end
|
|
tree "CS 1"
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "SMC_SETUP1,SMC Setup Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--22. 1. " NRD_SETUP ,NRD Setup Length"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
hexmask.long.byte 0x00 0.--6. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x04 "SMC_PULSE1,SMC Pulse Register"
|
|
hexmask.long.byte 0x04 24.--29. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x04 16.--21. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--13. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
hexmask.long.byte 0x04 0.--5. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x08 "SMC_CYCLE1,SMC Cycle Register"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
line.long 0x0C "SMC_MODE1,SMC MODE Register"
|
|
bitfld.long 0x0C 28.--29. " PS ,Page Size" "4-byte page,8-byte page,16-byte page,32-byte page"
|
|
bitfld.long 0x0C 20. " PMEN ,Page Mode Enabled" "Standard,Asynchronous burst"
|
|
textline " "
|
|
bitfld.long 0x0C 16.--19. " TDF_CYCLES ,Data Float Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " WRITE_MODE ,States will be inserted after the setup of NWE/NCS" "NCS,NWE"
|
|
bitfld.long 0x0C 0. " READ_MODE ,Read operation is controlled by the NRD/NCS signal" "NCS,NRD"
|
|
tree.end
|
|
tree "CS 2"
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "SMC_SETUP2,SMC Setup Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--22. 1. " NRD_SETUP ,NRD Setup Length"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
hexmask.long.byte 0x00 0.--6. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x04 "SMC_PULSE2,SMC Pulse Register"
|
|
hexmask.long.byte 0x04 24.--29. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x04 16.--21. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--13. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
hexmask.long.byte 0x04 0.--5. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x08 "SMC_CYCLE2,SMC Cycle Register"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
line.long 0x0C "SMC_MODE2,SMC MODE Register"
|
|
bitfld.long 0x0C 28.--29. " PS ,Page Size" "4-byte page,8-byte page,16-byte page,32-byte page"
|
|
bitfld.long 0x0C 20. " PMEN ,Page Mode Enabled" "Standard,Asynchronous burst"
|
|
textline " "
|
|
bitfld.long 0x0C 16.--19. " TDF_CYCLES ,Data Float Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " WRITE_MODE ,States will be inserted after the setup of NWE/NCS" "NCS,NWE"
|
|
bitfld.long 0x0C 0. " READ_MODE ,Read operation is controlled by the NRD/NCS signal" "NCS,NRD"
|
|
tree.end
|
|
tree "CS 3"
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "SMC_SETUP3,SMC Setup Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--22. 1. " NRD_SETUP ,NRD Setup Length"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
hexmask.long.byte 0x00 0.--6. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x04 "SMC_PULSE3,SMC Pulse Register"
|
|
hexmask.long.byte 0x04 24.--29. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x04 16.--21. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--13. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
hexmask.long.byte 0x04 0.--5. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x08 "SMC_CYCLE3,SMC Cycle Register"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
line.long 0x0C "SMC_MODE3,SMC MODE Register"
|
|
bitfld.long 0x0C 28.--29. " PS ,Page Size" "4-byte page,8-byte page,16-byte page,32-byte page"
|
|
bitfld.long 0x0C 20. " PMEN ,Page Mode Enabled" "Standard,Asynchronous burst"
|
|
textline " "
|
|
bitfld.long 0x0C 16.--19. " TDF_CYCLES ,Data Float Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " WRITE_MODE ,States will be inserted after the setup of NWE/NCS" "NCS,NWE"
|
|
bitfld.long 0x0C 0. " READ_MODE ,Read operation is controlled by the NRD/NCS signal" "NCS,NRD"
|
|
tree.end
|
|
width 10.
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SMC_OCMS,SMC OCMS Mode Register"
|
|
bitfld.long 0x00 19. " CS3SE ,Chip Select 3 Scrambling Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CS2SE ,Chip Select 2 Scrambling Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CS1SE ,Chip Select 1 Scrambling Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CS0SE ,Chip Select 0 Scrambling Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SMSE ,Static Memory Controller Scrambling Enable" "Disabled,Enabled"
|
|
wgroup.long 0x84++0x07
|
|
line.long 0x00 "SMC_KEY1,SMC OCMS Key1 Register"
|
|
line.long 0x04 "SMC_KEY2,SMC OCMS Key2 Register"
|
|
rgroup.long 0xe4++0x3
|
|
line.long 0x00 "SMC_WPCR,SMC Write Protection Control"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WP_KEY ,Write Protection KEY password"
|
|
bitfld.long 0x00 0. " WP_PEN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "SMC_WPSR,SMC Write Protection Status"
|
|
in
|
|
width 0xB
|
|
tree.end
|
|
tree "PMC (Power Management Controller)"
|
|
base ad:0x400E0400
|
|
width 12.
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "PMC_SCSR,PMC System Clock Status Register"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " PCK2_set/clr ,Programmable Clock 2 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " PCK1_set/clr ,Programmable Clock 1 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " PCK0_set/clr ,Programmable Clock 0 Output Status" "Disabled,Enabled"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " UOTGCLK_set/clr ,USB OTG Clock" "Disabled,Enabled"
|
|
elif (cpuis("ATSAM4E*"))
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " UDP_set/clr ,USB Device Port Clock" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " UOTGCLK_set/clr ,USB OTG Clock" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PMC_PCSR,PMC Peripheral Clock Status Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " TC4_set/clr ,Timer Counter 4 (Peripheral ID 31) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " TC3_set/clr ,Timer Counter 3 (Peripheral ID 30)Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " TC2_set/clr ,Timer Counter 2 (Peripheral ID 29) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " TC1_set/clr ,Timer Counter 1 (Peripheral ID 28)Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " TC0_set/clr ,Timer Counter 0 (Peripheral ID 27) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " SSC_set/clr ,Synchronous Serial Controller (Peripheral ID 26) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " SPI1_set/clr ,Serial Peripheral Interface (Peripheral ID 25) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " SPI0_set/clr ,Serial Peripheral Interface (Peripheral ID 24) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 23. " TWI1_set/clr ,Two-Wire Interface 1 (Peripheral ID 24) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " TWI0_set/clr ,Two-Wire Interface 0 (Peripheral ID 22) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " HSMCI_set/clr ,High Speed Multimedia Card Interface (Peripheral ID 21) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " USART3_set/clr ,USART 3 (Peripheral ID 20) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " USART2_set/clr ,USART 2 (Peripheral ID 19) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " USART1_set/clr ,USART 1 (Peripheral ID 18) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " USART0_set/clr ,USART 0 (Peripheral ID 17) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " PIOF_set/clr ,Parallel I/O Controller F (Peripheral ID 16) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " PIOE_set/clr ,Parallel I/O Controller E (Peripheral ID 15) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " PIOD_set/clr ,Parallel I/O Controller D (Peripheral ID 14) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " PIOC_set/clr ,Parallel I/O Controller C (Peripheral ID 13) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " PIOB_set/clr ,Parallel I/O Controller B (Peripheral ID 12) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " PIOA_set/clr ,Parallel I/O Controller A (Peripheral ID 11) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " SMC_SDRAMC_set/clr ,Static Memory Controller/Synchronous Dynamic RAM Controller (Peripheral ID 9) Clock Status" "Disabled,Enabled"
|
|
elif (cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " AFEC1_set/clr ,Analog Front End 1 (Peripheral ID 31) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " AFEC0_set/clr ,Analog Front End 0 (Peripheral ID 30) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " TC8_set/clr ,Timer/Counter 8 (Peripheral ID 29)Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " TC7_set/clr ,Timer Counter 7 Controller (Peripheral ID 28) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " TC6_set/clr ,Timer Counter 6 Controller (Peripheral ID 27) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " TC5_set/clr ,Timer Counter 5 Controller (Peripheral ID 26) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " TC4_set/clr ,Timer Counter 4 (Peripheral ID 25) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " TC3_set/clr ,Timer Counter 3 (Peripheral ID 24) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " TC2_set/clr ,Timer Counter 2 (Peripheral ID 23) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " TC1_set/clr ,Timer Counter 1 (Peripheral ID 22) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " TC0_set/clr ,Timer Counter 0 (Peripheral ID 21) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " DMAC_set/clr ,DMAC (Peripheral ID 20) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " SPI_set/clr ,Serial Peripheral Interface (Peripheral ID 19) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " TWI1_set/clr ,Two-wire Interface 1 (Peripheral ID 18) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " TWI0_set/clr ,Two-wire Interface 0 Peripheral ID 15) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " HSMCI_set/clr ,Multimedia Card Interface (Peripheral ID 14) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " USART1_set/clr ,USART 1 (Peripheral ID 15) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " USART0_set/clr ,USART 0 (Peripheral ID 14) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="ATSAM4E16C"&&cpu()!="ATSAM4E8C")
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " PIOE_set/clr ,Parallel I/O Controller E (Peripheral ID 13) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " PIOD_set/clr ,Parallel I/O Controller D (Peripheral ID 12) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " PIOC_set/clr ,Parallel I/O Controller C (Peripheral ID 11) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " PIOB_set/clr ,Parallel I/O Controller B (Peripheral ID 10) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " PIOA_set/clr ,Parallel I/O Controller A (Peripheral ID 9) Clock Status" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " UDPHS_set/clr ,USB Device High Speed (Peripheral ID 29) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " DMAC_set/clr ,DMA Controller (Peripheral ID 28)Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " ADC_set/clr ,10-bit ADC Controller (Peripheral ID 27) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " ADC12B_set/clr ,12-bit ADC Controller (Peripheral ID 26) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " PWM_set/clr ,Pulse Width Modulation Controller (Peripheral ID 25) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " TC2_set/clr ,Timer Counter 2 (Peripheral ID 24) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 23. " TC1_set/clr ,Timer Counter 1 (Peripheral ID 24) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " TC0_set/clr ,Timer Counter 0 (Peripheral ID 22) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " SSC_set/clr ,Synchronous Serial Controller (Peripheral ID 21) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " SPI_set/clr ,Serial Peripheral Interface (Peripheral ID 20) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " TWI1_set/clr ,Two-Wire Interface 1 (Peripheral ID 19) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " TWI0_set/clr ,Two-Wire Interface 0 (Peripheral ID 18) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " HSMCI_set/clr ,High Speed Multimedia Card Interface (Peripheral ID 17) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " USART3_set/clr ,USART 3 (Peripheral ID 16) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " USART2_set/clr ,USART 2 (Peripheral ID 15) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " USART1_set/clr ,USART 1 (Peripheral ID 14) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " USART0_set/clr ,USART 0 (Peripheral ID 13) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " PIOC_set/clr ,Parallel I/O Controller C (Peripheral ID 12) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " PIOB_set/clr ,Parallel I/O Controller B (Peripheral ID 11) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " PIOA_set/clr ,Parallel I/O Controller A (Peripheral ID 10) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " SMC_set/clr ,Static Memory Controller (Peripheral ID 9) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " UART_set/clr ,Universal Asynchronous Receiver Transmitter (Peripheral ID 8) Clock Status" "Disabled,Enabled"
|
|
endif
|
|
sif (!cpuis("ATSAM4E*"))
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "CKGR_UCKR,PMC UTMI Clock Configuration Register"
|
|
bitfld.long 0x00 20.--23. " UPLLCOUNT , UTMI PLL Start-up Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " UPLLEN , UTMI PLL Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "CKGR_MOR,PMC Clock Generator Main Oscillator Register"
|
|
bitfld.long 0x00 25. " CFDEN ,Clock Failure Detector Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " MOSCSEL ,Main Oscillator Selection" "Main On-Chip RC,Main Crystal"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " KEY ,Password"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MOSCXTST ,Main Crystal Oscillator Start-up Time"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " MOSCRCF ,Main On-Chip RC Oscillator Frequency Selection" "4 MHz,8 MHz,12 MHz,?..."
|
|
bitfld.long 0x00 3. " MOSCRCEN ,Main On-Chip RC Oscillator Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("AT91SAM3A*")&&!cpuis("AT91SAM3X4C")&&!cpuis("AT91SAM3X4E")&&!cpuis("AT91SAM3X8C")&&!cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 2. " WAITMODE ,Wait Mode Command" "No effect,Wait"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " MOSCXTBY ,Main Crystal Oscillator Bypass" "No effect,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MOSCXTEN ,Main Crystal Oscillator Enable" "Disabled,Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CKGR_MCFR,PMC Clock Generator Main Clock Frequency Register"
|
|
sif (cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 20. " RCMEAS ,RC Oscillator Frequency Measure" "No effect,Restart"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " MAINRDY ,Main Clock Ready" "Not ready,Ready"
|
|
hexmask.long.word 0x00 0.--15. 1. " MAINF ,Main Clock Frequency"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "CKGR_PLLAR,PMC Clock Generator PLL A Register"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 29. " ONE ,Must Be Set to 1" "0,1"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x00 16.--26. 1. " MULA ,PLL A Multiplier"
|
|
textline " "
|
|
sif (!cpuis("AT91SAM3A*")&&!cpuis("AT91SAM3X4C")&&!cpuis("AT91SAM3X4E")&&!cpuis("AT91SAM3X8C")&&!cpuis("AT91SAM3X8E")&&!cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 14.--15. " STMODE ,Start Mode" "Fast Startup,,Normal Startup,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 8.--13. 1. " PLLACOUNT ,PLL A Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIVA ,Divider A"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "PMC_MCKR,PMC Master Clock Register"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x0 12. " PLLADIV2 ,PLLA Divisor by 2" "Clock,Clock/2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 4.--6. " PRES ,Processor Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,Clock/3"
|
|
bitfld.long 0x0 0.--1. " CSS ,Master Clock Source Selection" "Slow,Main,PLL A,UPLL"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4E*"))
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "PMC_USB,PMC USB Clock Register"
|
|
bitfld.long 0x00 8.--11. " USBDIV ,Divider for USB Clock" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
sif (!cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0. " USBS ,USB Input Clock Selection" "PLLA,PLLB"
|
|
endif
|
|
endif
|
|
sif (cpuis("ATSAM4E*"))
|
|
group.long 0x40++0xF
|
|
line.long 0x0 "PMC_PCK0,PMC Programmable Clock 0 Register"
|
|
bitfld.long 0x0 4.--6. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x0 0.--2. " CSS ,Master Clock Selection" "Slow,Main,PLL A,,Master,?..."
|
|
line.long 0x4 "PMC_PCK1,PMC Programmable Clock 1 Register"
|
|
bitfld.long 0x4 4.--6. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x4 0.--2. " CSS ,Master Clock Selection" "Slow,Main,PLL A,,Master,?..."
|
|
line.long 0x8 "PMC_PCK2,PMC Programmable Clock 2 Register"
|
|
bitfld.long 0x8 4.--6. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x8 0.--2. " CSS ,Master Clock Selection" "Slow,Main,PLL A,,Master,?..."
|
|
line.long 0xC "PMC_PCK3,PMC Programmable Clock 3 Register"
|
|
bitfld.long 0xC 4.--6. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0xC 0.--2. " CSS ,Master Clock Selection" "Slow,Main,PLL A,,Master,?..."
|
|
else
|
|
group.long 0x40++0xF
|
|
line.long 0x0 "PMC_PCK0,PMC Programmable Clock 0 Register"
|
|
bitfld.long 0x0 4.--6. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x0 0.--2. " CSS ,Master Clock Selection" "Slow,Main,PLL A,UPLL,Master,Master,Master,Master"
|
|
line.long 0x4 "PMC_PCK1,PMC Programmable Clock 1 Register"
|
|
bitfld.long 0x4 4.--6. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x4 0.--2. " CSS ,Master Clock Selection" "Slow,Main,PLL A,UPLL,Master,Master,Master,Master"
|
|
line.long 0x8 "PMC_PCK2,PMC Programmable Clock 2 Register"
|
|
bitfld.long 0x8 4.--6. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x8 0.--2. " CSS ,Master Clock Selection" "Slow,Main,PLL A,UPLL,Master,Master,Master,Master"
|
|
line.long 0xC "PMC_PCK3,PMC Programmable Clock 3 Register"
|
|
bitfld.long 0xC 4.--6. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0xC 0.--2. " CSS ,Master Clock Selection" "Slow,Main,PLL A,UPLL,Master,Master,Master,Master"
|
|
endif
|
|
group.long 0x6c++3
|
|
line.long 0x00 "PMC_IMR,Interrupt Enable\Mask Register"
|
|
setclrfld.long 0x00 18. -0xc 18. -0x8 18. " CFDEV_set/clr ,Clock Failure Detector Event" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0xc 17. -0x8 17. " MOSCRCS_set/clr ,Main On-Chip RC Oscillator Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0xc 16. -0x8 16. " MOSCSELS_set/clr ,Main Oscillator Selection Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0xc 10. -0x8 10. " PCKRDY2_set/clr ,Programmable Clock Ready 2 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0xc 9. -0x8 9. " PCKRDY1_set/clr ,Programmable Clock Ready 1 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0xc 8. -0x8 8. " PCKRDY0_set/clr ,Programmable Clock Ready 0 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("AT91SAM3A*")&&!cpuis("AT91SAM3X4C")&&!cpuis("AT91SAM3X4E")&&!cpuis("AT91SAM3X8C")&&!cpuis("AT91SAM3X8E")&&!cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x00 7. -0xc 7. -0x8 7. " OSCSELS_set/clr ,Slow Clock Oscillator Selection" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x00 6. -0xc 6. -0x8 6. " LOCKU_set/clr ,UTMI PLL Lock Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 3. -0xc 3. -0x8 3. " MCKRDY_set/clr ,Master Clock Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0xc 1. -0x8 1. " LOCKA_set/clr ,PLL A Lock Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0xc 0. -0x8 0. " MOSCXTS_set/clr ,Main Oscillator Status Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x68++0x3
|
|
hide.long 0x00 "PMC_SR,PMC Status Register"
|
|
in
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "PMC_FSMR,PMC Fast Startup Mode Register"
|
|
sif (cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 21.--22. " FLPM ,Flash Low Power Mode" "FLASH_STANDBY,FLASH_DEEP_POWERDOWN,FLASH_IDLE,?..."
|
|
bitfld.long 0x00 20. " LPM ,Low Power Mode" "Idle,Wait"
|
|
else
|
|
bitfld.long 0x00 20. " LPM ,Low Power Mode" "Idle,Wait"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18. " USBAL ,USB Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RTCAL ,RTC Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RTTAL ,RTT Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " FSTT15 ,Fast Startup Input Enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FSTT14 ,Fast Startup Input Enable 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FSTT13 ,Fast Startup Input Enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " FSTT12 ,Fast Startup Input Enable 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " FSTT11 ,Fast Startup Input Enable 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSTT10 ,Fast Startup Input Enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " FSTT9 ,Fast Startup Input Enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FSTT8 ,Fast Startup Input Enable 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FSTT7 ,Fast Startup Input Enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FSTT6 ,Fast Startup Input Enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FSTT5 ,Fast Startup Input Enable 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FSTT4 ,Fast Startup Input Enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FSTT3 ,Fast Startup Input Enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FSTT2 ,Fast Startup Input Enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FSTT1 ,Fast Startup Input Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FSTT0 ,Fast Startup Input Enable 0" "Disabled,Enabled"
|
|
group.long 0x74++0x3
|
|
line.long 0x00 "PMC_FSPR,PMC Fast Startup Polarity Register"
|
|
bitfld.long 0x00 15. " FSTP15 ,Fast Startup Input Polarity 15" "Low,High"
|
|
bitfld.long 0x00 14. " FSTP14 ,Fast Startup Input Polarity 14" "Low,High"
|
|
bitfld.long 0x00 13. " FSTP13 ,Fast Startup Input Polarity 13" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSTP12 ,Fast Startup Input Polarity 12" "Low,High"
|
|
bitfld.long 0x00 11. " FSTP11 ,Fast Startup Input Polarity 11" "Low,High"
|
|
bitfld.long 0x00 10. " FSTP10 ,Fast Startup Input Polarity 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FSTP9 ,Fast Startup Input Polarity 9" "Low,High"
|
|
bitfld.long 0x00 8. " FSTP8 ,Fast Startup Input Polarity 8" "Low,High"
|
|
bitfld.long 0x00 7. " FSTP7 ,Fast Startup Input Polarity 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FSTP6 ,Fast Startup Input Polarity 6" "Low,High"
|
|
bitfld.long 0x00 5. " FSTP5 ,Fast Startup Input Polarity 5" "Low,High"
|
|
bitfld.long 0x00 4. " FSTP4 ,Fast Startup Input Polarity 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FSTP3 ,Fast Startup Input Polarity 3" "Low,High"
|
|
bitfld.long 0x00 2. " FSTP2 ,Fast Startup Input Polarity 2" "Low,High"
|
|
bitfld.long 0x00 1. " FSTP1 ,Fast Startup Input Polarity 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSTP0 ,Fast Startup Input Polarity 0" "Low,High"
|
|
wgroup.long 0x78++0x3
|
|
line.long 0x00 "PMC_FOCR,PMC Fault Output Clear Register"
|
|
bitfld.long 0x00 0. " FOCLR ,Fault Output Clear" "No effect,Clear"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PMC_WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PMC_WPSR,Write Protect Status Register"
|
|
in
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4E*"))
|
|
group.long 0x108++0x3
|
|
line.long 0x00 "PMC_PCSR1,PMC Peripheral Clock Status Register 1"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " CAN1_set/clr ,CAN Controller 1(Peripheral 44)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " CAN0_set/clr ,CAN Controller 0(Peripheral 43)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " EMAC_set/clr ,Ethernet MAC(Peripheral 42)" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TRNG_set/clr ,True Random Number Generator(Peripheral 41)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " UOTGHS_set/clr ,USB OTG High Speed(Peripheral 40)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " DMAC_set/clr ,DMA Controller(Peripheral 39)" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " DACC_set/clr ,DAC Controller(Peripheral 38)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " ADC_set/clr ,ADC Controller(Peripheral 37)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " PWM_set/clr ,Pulse Width Modulation Controller(Peripheral 36)" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " TC8_set/clr ,Timer Counter 8 (Peripheral 35)" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " TC7_set/clr ,Timer Counter 7 (Peripheral 34)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TC6_set/clr ,Timer Counter 6 (Peripheral 33)" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " TC5_set/clr ,Timer Counter 5 (Peripheral 32)" "Disabled,Enabled"
|
|
elif (cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " UART1_set/clr ,UART1 (Peripheral 45)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " EMAC_set/clr ,EMAC(Peripheral 44)" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " AES_set/clr ,AES(Peripheral 39)" "Disabled,Enabled"
|
|
sif (cpu()=="ATSAM4E8E"||cpu()=="ATSAM4E16E")
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " CAN1_set/clr ,CAN1(Peripheral 38)" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " CAN0_set/clr ,CAN0(Peripheral 37)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " PWM_set/clr ,Pulse Width Modulation Controller(Peripheral 36)" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " UDP_set/clr ,USB DEVICE (Peripheral 35)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " ARM_set/clr ,FPU signals: FPIXC FPOFC FPUFC FPIOC FPDZC FPIDC FPIXC (Peripheral 34)" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " ACC_set/clr ,Analog Comparator (Peripheral 33)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DACC_set/clr ,Digital to Analog Converter (Peripheral 32)" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " UDP_set/clr ,USB Device Port (Peripheral 34)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " ACC_set/clr ,Analog Comparator (Peripheral 33)" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " CRCCU_set/clr ,CRC Calculation Unit (Peripheral 32)" "Disabled,Enabled"
|
|
endif
|
|
sif (!cpuis("ATSAM4E*"))
|
|
group.long 0x10C++0x3
|
|
line.long 0x00 "PMC_PCR,PMC Peripheral Control Register"
|
|
bitfld.long 0x00 28. " EN ,Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " DIV ,Divisor Value" "MCK,MCK/2,MCK/4,?..."
|
|
bitfld.long 0x00 12. " CMD ,Command" "Read mode,Write mode"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " PID ,Peripheral ID"
|
|
endif
|
|
endif
|
|
sif (cpuis("ATSAM4E*"))
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "PMC_OCR,PMC Oscillator Calibration Register"
|
|
bitfld.long 0x00 23. " SEL12 ,Selection of RC Oscillator Calibration bits for 12 Mhz" "Flash memory,Written in CAL12"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CAL12 ,RC Oscillator Calibration bits for 12 Mhz"
|
|
bitfld.long 0x00 15. " SEL8 ,Selection of RC Oscillator Calibration bits for 8 Mhz" "Flash memory,Written in CAL8"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " CAL8 ,RC Oscillator Calibration bits for 8 Mhz"
|
|
bitfld.long 0x00 7. " SEL4 ,Selection of RC Oscillator Calibration bits for 4 Mhz" "Flash memory,Written in CAL4"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CAL4 ,RC Oscillator Calibration bits for 4 Mhz"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "AES (Advanced Encryption Standard)"
|
|
base ad:0x40004000
|
|
width 14.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "AES_CR,AES Control Register"
|
|
bitfld.long 0x00 8. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " START ,Start Processing" "No effect,Start"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "AES_MR,AES Mode Register"
|
|
bitfld.long 0x00 20.--23. " CKEY ,Key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--18. " CFBS ,Cipher Feedback Data Size" "128-bit,64-bit,32-bit,16-bit,8-bit,,,"
|
|
textline " "
|
|
bitfld.long 0x00 15. " LOD ,Last Output Data Mode" "No effect,Set"
|
|
bitfld.long 0x00 12.--14. " OPMOD ,Operation Mode" "ECB,CBC,OFB,CFB,CTR,,,"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " KEYSIZE ,Key Size" "128 bits,192 bits,256 bits,"
|
|
bitfld.long 0x00 8.--9. " SMOD ,Start Mode" "Manual,Auto,AES_IDATAR0 access only,"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PROCDLY ,Processing Delay" "12 cycles,24 cycles,36 cycles,48 cycles,60 cycles,72 cycles,84 cycles,96 cycles,108 cycles,120 cycles,132 cycles,144 cycles,156 cycles,168 cycles,180 cycles,192 cycles"
|
|
bitfld.long 0x00 3. " DUALBUFF ,Dual Input BUFFer" "Inactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CIPHER ,Processing Mode" "Decrypt,Encrypt"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "AES_IMR,AES Interrupt Mask Register"
|
|
bitfld.long 0x00 8. " URAD ,Unspecified Register Access Detection Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " TXBUFE ,Transmit Buffer Empty Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RXBUFF ,Receive Buffer Full Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " ENDTX ,End of Transmit Buffer Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENDRX ,End of Receive Buffer Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " DATRDY ,Data Ready Interrupt Mask" "Masked,Not masked"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "AES_ISR,AES Interrupt Status Register"
|
|
rbitfld.long 0x00 12.--15. " URAT ,Unspecified Register Access" "IDR_WR_PROCESSING,ODR_RD_PROCESSING,MR_WR_PROCESSING,ODR_RD_SUBKGEN,MR_WR_SUBKGEN,WOR_RD_ACCESS,,,,,,,,,,"
|
|
setclrfld.long 0x00 8. -0x0C 8. -0x08 8. " URAD_SET/CLR ,Unspecified Register Access Detection Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x0C 4. -0x08 4. " TXBUFE_SET/CLR ,TX Buffer Empty" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. -0x0C 3. -0x08 3. " RXBUFF_SET/CLR ,RX Buffer Full" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x0C 2. -0x08 2. " ENDTX_SET/CLR ,End of TX Buffer" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. -0x0C 1. -0x08 1. " ENDRX_SET/CLR ,End of RX Buffer" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x0C 0. -0x08 0. " DATRDY_SET/CLR ,Data Ready" "No interrupt,Interrupt"
|
|
wgroup.long 0x20++0x1F
|
|
line.long 0x0 "AES_KEYWR0,Key Word Register 0"
|
|
line.long 0x4 "AES_KEYWR1,Key Word Register 1"
|
|
line.long 0x8 "AES_KEYWR2,Key Word Register 2"
|
|
line.long 0xC "AES_KEYWR3,Key Word Register 3"
|
|
line.long 0x10 "AES_KEYWR4,Key Word Register 4"
|
|
line.long 0x14 "AES_KEYWR5,Key Word Register 5"
|
|
line.long 0x18 "AES_KEYWR6,Key Word Register 6"
|
|
line.long 0x1C "AES_KEYWR7,Key Word Register 7"
|
|
wgroup.long 0x40++0x0F
|
|
line.long 0x0 "AES_IDATAR0,AES Input Data Register 0"
|
|
line.long 0x4 "AES_IDATAR1,AES Input Data Register 1"
|
|
line.long 0x8 "AES_IDATAR2,AES Input Data Register 2"
|
|
line.long 0xC "AES_IDATAR3,AES Input Data Register 3"
|
|
rgroup.long 0x50++0x0F
|
|
line.long 0x0 "AES_ODATAR0,AES Output Data Register 0"
|
|
line.long 0x4 "AES_ODATAR1,AES Output Data Register 1"
|
|
line.long 0x8 "AES_ODATAR2,AES Output Data Register 2"
|
|
line.long 0xC "AES_ODATAR3,AES Output Data Register 3"
|
|
wgroup.long 0x60++0x0F
|
|
line.long 0x0 "AES_IVR0,AES Initialization Vector Register 0"
|
|
line.long 0x4 "AES_IVR1,AES Initialization Vector Register 1"
|
|
line.long 0x8 "AES_IVR2,AES Initialization Vector Register 2"
|
|
line.long 0xC "AES_IVR3,AES Initialization Vector Register 3"
|
|
width 0x0b
|
|
tree "AES PDC (Peripheral DMA Controller)"
|
|
width 9.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "AES_RPR,Receive Pointer Register"
|
|
line.long 0x04 "AES_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "AES_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "AES_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "AES_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "AES_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "AES_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "AES_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "AES_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "AES_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "CAN (Controller Area Network)"
|
|
tree "CAN0"
|
|
base ad:0x40010000
|
|
width 13.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "CAN_MR,CAN Mode Register"
|
|
bitfld.long 0x00 7. " DRPT ,Disable Repeat" "No,Yes"
|
|
bitfld.long 0x00 6. " TIMFRZ ,Enable Timer Freeze" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TTM ,Disable/Enable Time Triggered Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TEOF ,Timestamp messages at each end of Frame" "Start Of Frame,End Of Frame"
|
|
bitfld.long 0x00 3. " OVL ,Disable/Enable Overload Frame" "Not generated,Generated"
|
|
bitfld.long 0x00 2. " ABM ,Disable/Enable Autobaud/Listen mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LPM ,Disable/Enable Low Power Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CANEN ,CAN Controller Enable" "Disabled,Enabled"
|
|
group.long 0xc++0x3
|
|
line.long 0x00 "CAN_IMR,CAN Interrupt Mask Register"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x4 28. " BERR_set/clr ,Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x4 27. " FERR_set/clr ,Form Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x4 26. " AERR_set/clr ,Acknowledgment Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x4 25. " SERR_set/clr ,Stuffing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x4 24. " CERR_set/clr ,CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x4 23. " TSTP_set/clr ,Timestamp Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x4 22. " TOVF_set/clr ,Timer Overflow Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x4 21. " WAKEUP_set/clr ,Wakeup Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x4 20. " SLEEP_set/clr ,Sleep Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x4 19. " BOFF_set/clr ,Bus Off Mode Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x4 18. " ERRP_set/clr ,Error Passive Mode Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x4 17. " WARN_set/clr ,Warning Limit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x4 16. " ERRA_set/clr ,Error Active Mode Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x4 7. " MB7_set/clr ,Mailbox 7 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x4 6. " MB6_set/clr ,Mailbox 6 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x4 5. " MB5_set/clr ,Mailbox 5 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x4 4. " MB4_set/clr ,Mailbox 4 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x4 3. " MB3_set/clr ,Mailbox 3 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x4 2. " MB2_set/clr ,Mailbox 2 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x4 1. " MB1_set/clr ,Mailbox 1 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x4 0. " MB0_set/clr ,Mailbox 0 Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x10++0x3
|
|
hide.long 0x00 "CAN_SR,CAN Status Register"
|
|
in
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "CAN_BR,CAN Baudrate Register"
|
|
bitfld.long 0x00 24. " SMP ,Sampling Mode" "Sampled once,Sampled three times"
|
|
hexmask.long.byte 0x00 16.--22. 1. " BRP ,Baudrate Prescaler"
|
|
bitfld.long 0x00 12.--13. " SJW ,Re-synchronization jump width" "1,2,3,4"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PROPAG ,Programming time segment" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 4.--6. " PHASE1 ,Phase 1 segment" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 0.--2. " PHASE2 ,Phase 2 segment" "1,2,3,4,5,6,7,8"
|
|
rgroup.long 0x18++0xB
|
|
line.long 0x00 "CAN_TIM,CAN Timer Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMER ,Timer"
|
|
line.long 0x04 "CAN_TIMESTP,CAN Timestamp Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " MTIMESTAMP ,Timestamp"
|
|
line.long 0x08 "CAN_ECR,CAN Error Counter Register"
|
|
hexmask.long.word 0x08 16.--24. 1. " TEC ,Transmit Error Counter"
|
|
hexmask.long.byte 0x08 0.--7. 1. " REC ,Receive Error Counter"
|
|
wgroup.long 0x24++0x7
|
|
line.long 0x00 "CAN_TCR,CAN Transfer Command Register"
|
|
bitfld.long 0x00 31. " TIMRST ,Timer Reset" "No reset,Reset"
|
|
bitfld.long 0x00 7. " MB7 ,Transfer Request for Mailbox 7" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " MB6 ,Transfer Request for Mailbox 6" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MB5 ,Transfer Request for Mailbox 5" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " MB4 ,Transfer Request for Mailbox 4" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " MB3 ,Transfer Request for Mailbox 3" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MB2 ,Transfer Request for Mailbox 2" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " MB1 ,Transfer Request for Mailbox 1" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " MB0 ,Transfer Request for Mailbox 0" "Not requested,Requested"
|
|
line.long 0x04 "CAN_ACR,CAN Abort Command Register"
|
|
bitfld.long 0x04 7. " MB7 ,Abort Request for Mailbox 7" "Not aborted,Aborted"
|
|
bitfld.long 0x04 6. " MB6 ,Abort Request for Mailbox 6" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x04 5. " MB5 ,Abort Request for Mailbox 5" "Not aborted,Aborted"
|
|
bitfld.long 0x04 4. " MB4 ,Abort Request for Mailbox 4" "Not aborted,Aborted"
|
|
bitfld.long 0x04 3. " MB3 ,Abort Request for Mailbox 3" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x04 2. " MB2 ,Abort Request for Mailbox 2" "Not aborted,Aborted"
|
|
bitfld.long 0x04 1. " MB1 ,Abort Request for Mailbox 1" "Not aborted,Aborted"
|
|
bitfld.long 0x04 0. " MB0 ,Abort Request for Mailbox 0" "Not aborted,Aborted"
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "CAN_WPMR,CAN Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,SPI Write Protection Key Password"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x00 "CAN_WPSR,CAN Write Protection Status Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " WPVSRC ,Write Protection Violation Source"
|
|
bitfld.long 0x00 0. " WPVS ,Write Protection Violation Status" "Not occurred,Occurred"
|
|
width 12.
|
|
tree "Mailbox 0"
|
|
group.long 0x200++0xB
|
|
line.long 0x00 "CAN_MMR0,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "MB_DISABLED,MB_RX,MB_RX_OVERWRITE,MB_TX,MB_CONSUMER,MB_PRODUCER,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM0,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID0,Compared IDvA and IDvB with CAN_MID0"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID0,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x200+0x0C)++0x7
|
|
line.long 0x0 "CAN_MFID0,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
line.long 0x04 "CAN_MSR0,CAN Message Status Register"
|
|
bitfld.long 0x04 24. " MMI ,Mailbox Message Ignored" "Not ignored,Ignored"
|
|
bitfld.long 0x04 23. " MRDY ,Mailbox Ready" "Can not R/W by software,Can R/W by software"
|
|
bitfld.long 0x04 22. " MABT ,Mailbox Message Abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x04 20. " MRTR ,Mailbox Remote Transmission Request" "Not occurred,Occurred"
|
|
bitfld.long 0x04 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--15. 1. " MTIMESTAMP ,Timer value"
|
|
group.long (0x200+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL0,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH0,CAN Message Data High Register"
|
|
wgroup.long (0x200+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR0,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 0" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Mailbox 1"
|
|
group.long 0x220++0xB
|
|
line.long 0x00 "CAN_MMR1,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "MB_DISABLED,MB_RX,MB_RX_OVERWRITE,MB_TX,MB_CONSUMER,MB_PRODUCER,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM1,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID1,Compared IDvA and IDvB with CAN_MID1"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID1,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x220+0x0C)++0x7
|
|
line.long 0x0 "CAN_MFID1,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
line.long 0x04 "CAN_MSR1,CAN Message Status Register"
|
|
bitfld.long 0x04 24. " MMI ,Mailbox Message Ignored" "Not ignored,Ignored"
|
|
bitfld.long 0x04 23. " MRDY ,Mailbox Ready" "Can not R/W by software,Can R/W by software"
|
|
bitfld.long 0x04 22. " MABT ,Mailbox Message Abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x04 20. " MRTR ,Mailbox Remote Transmission Request" "Not occurred,Occurred"
|
|
bitfld.long 0x04 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--15. 1. " MTIMESTAMP ,Timer value"
|
|
group.long (0x220+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL1,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH1,CAN Message Data High Register"
|
|
wgroup.long (0x220+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR1,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 1" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Mailbox 2"
|
|
group.long 0x240++0xB
|
|
line.long 0x00 "CAN_MMR2,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "MB_DISABLED,MB_RX,MB_RX_OVERWRITE,MB_TX,MB_CONSUMER,MB_PRODUCER,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM2,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID2,Compared IDvA and IDvB with CAN_MID2"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID2,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x240+0x0C)++0x7
|
|
line.long 0x0 "CAN_MFID2,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
line.long 0x04 "CAN_MSR2,CAN Message Status Register"
|
|
bitfld.long 0x04 24. " MMI ,Mailbox Message Ignored" "Not ignored,Ignored"
|
|
bitfld.long 0x04 23. " MRDY ,Mailbox Ready" "Can not R/W by software,Can R/W by software"
|
|
bitfld.long 0x04 22. " MABT ,Mailbox Message Abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x04 20. " MRTR ,Mailbox Remote Transmission Request" "Not occurred,Occurred"
|
|
bitfld.long 0x04 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--15. 1. " MTIMESTAMP ,Timer value"
|
|
group.long (0x240+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL2,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH2,CAN Message Data High Register"
|
|
wgroup.long (0x240+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR2,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 2" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Mailbox 3"
|
|
group.long 0x260++0xB
|
|
line.long 0x00 "CAN_MMR3,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "MB_DISABLED,MB_RX,MB_RX_OVERWRITE,MB_TX,MB_CONSUMER,MB_PRODUCER,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM3,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID3,Compared IDvA and IDvB with CAN_MID3"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID3,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x260+0x0C)++0x7
|
|
line.long 0x0 "CAN_MFID3,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
line.long 0x04 "CAN_MSR3,CAN Message Status Register"
|
|
bitfld.long 0x04 24. " MMI ,Mailbox Message Ignored" "Not ignored,Ignored"
|
|
bitfld.long 0x04 23. " MRDY ,Mailbox Ready" "Can not R/W by software,Can R/W by software"
|
|
bitfld.long 0x04 22. " MABT ,Mailbox Message Abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x04 20. " MRTR ,Mailbox Remote Transmission Request" "Not occurred,Occurred"
|
|
bitfld.long 0x04 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--15. 1. " MTIMESTAMP ,Timer value"
|
|
group.long (0x260+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL3,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH3,CAN Message Data High Register"
|
|
wgroup.long (0x260+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR3,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 3" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Mailbox 4"
|
|
group.long 0x280++0xB
|
|
line.long 0x00 "CAN_MMR4,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "MB_DISABLED,MB_RX,MB_RX_OVERWRITE,MB_TX,MB_CONSUMER,MB_PRODUCER,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM4,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID4,Compared IDvA and IDvB with CAN_MID4"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID4,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x280+0x0C)++0x7
|
|
line.long 0x0 "CAN_MFID4,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
line.long 0x04 "CAN_MSR4,CAN Message Status Register"
|
|
bitfld.long 0x04 24. " MMI ,Mailbox Message Ignored" "Not ignored,Ignored"
|
|
bitfld.long 0x04 23. " MRDY ,Mailbox Ready" "Can not R/W by software,Can R/W by software"
|
|
bitfld.long 0x04 22. " MABT ,Mailbox Message Abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x04 20. " MRTR ,Mailbox Remote Transmission Request" "Not occurred,Occurred"
|
|
bitfld.long 0x04 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--15. 1. " MTIMESTAMP ,Timer value"
|
|
group.long (0x280+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL4,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH4,CAN Message Data High Register"
|
|
wgroup.long (0x280+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR4,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 4" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Mailbox 5"
|
|
group.long 0x2A0++0xB
|
|
line.long 0x00 "CAN_MMR5,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "MB_DISABLED,MB_RX,MB_RX_OVERWRITE,MB_TX,MB_CONSUMER,MB_PRODUCER,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM5,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID5,Compared IDvA and IDvB with CAN_MID5"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID5,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x2A0+0x0C)++0x7
|
|
line.long 0x0 "CAN_MFID5,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
line.long 0x04 "CAN_MSR5,CAN Message Status Register"
|
|
bitfld.long 0x04 24. " MMI ,Mailbox Message Ignored" "Not ignored,Ignored"
|
|
bitfld.long 0x04 23. " MRDY ,Mailbox Ready" "Can not R/W by software,Can R/W by software"
|
|
bitfld.long 0x04 22. " MABT ,Mailbox Message Abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x04 20. " MRTR ,Mailbox Remote Transmission Request" "Not occurred,Occurred"
|
|
bitfld.long 0x04 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--15. 1. " MTIMESTAMP ,Timer value"
|
|
group.long (0x2A0+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL5,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH5,CAN Message Data High Register"
|
|
wgroup.long (0x2A0+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR5,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 5" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Mailbox 6"
|
|
group.long 0x2C0++0xB
|
|
line.long 0x00 "CAN_MMR6,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "MB_DISABLED,MB_RX,MB_RX_OVERWRITE,MB_TX,MB_CONSUMER,MB_PRODUCER,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM6,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID6,Compared IDvA and IDvB with CAN_MID6"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID6,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x2C0+0x0C)++0x7
|
|
line.long 0x0 "CAN_MFID6,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
line.long 0x04 "CAN_MSR6,CAN Message Status Register"
|
|
bitfld.long 0x04 24. " MMI ,Mailbox Message Ignored" "Not ignored,Ignored"
|
|
bitfld.long 0x04 23. " MRDY ,Mailbox Ready" "Can not R/W by software,Can R/W by software"
|
|
bitfld.long 0x04 22. " MABT ,Mailbox Message Abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x04 20. " MRTR ,Mailbox Remote Transmission Request" "Not occurred,Occurred"
|
|
bitfld.long 0x04 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--15. 1. " MTIMESTAMP ,Timer value"
|
|
group.long (0x2C0+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL6,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH6,CAN Message Data High Register"
|
|
wgroup.long (0x2C0+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR6,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 6" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Mailbox 7"
|
|
group.long 0x2E0++0xB
|
|
line.long 0x00 "CAN_MMR7,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "MB_DISABLED,MB_RX,MB_RX_OVERWRITE,MB_TX,MB_CONSUMER,MB_PRODUCER,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM7,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID7,Compared IDvA and IDvB with CAN_MID7"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID7,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x2E0+0x0C)++0x7
|
|
line.long 0x0 "CAN_MFID7,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
line.long 0x04 "CAN_MSR7,CAN Message Status Register"
|
|
bitfld.long 0x04 24. " MMI ,Mailbox Message Ignored" "Not ignored,Ignored"
|
|
bitfld.long 0x04 23. " MRDY ,Mailbox Ready" "Can not R/W by software,Can R/W by software"
|
|
bitfld.long 0x04 22. " MABT ,Mailbox Message Abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x04 20. " MRTR ,Mailbox Remote Transmission Request" "Not occurred,Occurred"
|
|
bitfld.long 0x04 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--15. 1. " MTIMESTAMP ,Timer value"
|
|
group.long (0x2E0+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL7,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH7,CAN Message Data High Register"
|
|
wgroup.long (0x2E0+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR7,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 7" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
sif (cpu()=="ATSAM4E8E"||cpu()=="ATSAM4E16E")
|
|
tree "CAN1"
|
|
base ad:0x40014000
|
|
width 13.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "CAN_MR,CAN Mode Register"
|
|
bitfld.long 0x00 7. " DRPT ,Disable Repeat" "No,Yes"
|
|
bitfld.long 0x00 6. " TIMFRZ ,Enable Timer Freeze" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TTM ,Disable/Enable Time Triggered Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TEOF ,Timestamp messages at each end of Frame" "Start Of Frame,End Of Frame"
|
|
bitfld.long 0x00 3. " OVL ,Disable/Enable Overload Frame" "Not generated,Generated"
|
|
bitfld.long 0x00 2. " ABM ,Disable/Enable Autobaud/Listen mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LPM ,Disable/Enable Low Power Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CANEN ,CAN Controller Enable" "Disabled,Enabled"
|
|
group.long 0xc++0x3
|
|
line.long 0x00 "CAN_IMR,CAN Interrupt Mask Register"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x4 28. " BERR_set/clr ,Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x4 27. " FERR_set/clr ,Form Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x4 26. " AERR_set/clr ,Acknowledgment Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x4 25. " SERR_set/clr ,Stuffing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x4 24. " CERR_set/clr ,CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x4 23. " TSTP_set/clr ,Timestamp Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x4 22. " TOVF_set/clr ,Timer Overflow Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x4 21. " WAKEUP_set/clr ,Wakeup Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x4 20. " SLEEP_set/clr ,Sleep Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x4 19. " BOFF_set/clr ,Bus Off Mode Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x4 18. " ERRP_set/clr ,Error Passive Mode Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x4 17. " WARN_set/clr ,Warning Limit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x4 16. " ERRA_set/clr ,Error Active Mode Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x4 7. " MB7_set/clr ,Mailbox 7 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x4 6. " MB6_set/clr ,Mailbox 6 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x4 5. " MB5_set/clr ,Mailbox 5 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x4 4. " MB4_set/clr ,Mailbox 4 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x4 3. " MB3_set/clr ,Mailbox 3 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x4 2. " MB2_set/clr ,Mailbox 2 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x4 1. " MB1_set/clr ,Mailbox 1 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x4 0. " MB0_set/clr ,Mailbox 0 Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x10++0x3
|
|
hide.long 0x00 "CAN_SR,CAN Status Register"
|
|
in
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "CAN_BR,CAN Baudrate Register"
|
|
bitfld.long 0x00 24. " SMP ,Sampling Mode" "Sampled once,Sampled three times"
|
|
hexmask.long.byte 0x00 16.--22. 1. " BRP ,Baudrate Prescaler"
|
|
bitfld.long 0x00 12.--13. " SJW ,Re-synchronization jump width" "1,2,3,4"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PROPAG ,Programming time segment" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 4.--6. " PHASE1 ,Phase 1 segment" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 0.--2. " PHASE2 ,Phase 2 segment" "1,2,3,4,5,6,7,8"
|
|
rgroup.long 0x18++0xB
|
|
line.long 0x00 "CAN_TIM,CAN Timer Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMER ,Timer"
|
|
line.long 0x04 "CAN_TIMESTP,CAN Timestamp Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " MTIMESTAMP ,Timestamp"
|
|
line.long 0x08 "CAN_ECR,CAN Error Counter Register"
|
|
hexmask.long.word 0x08 16.--24. 1. " TEC ,Transmit Error Counter"
|
|
hexmask.long.byte 0x08 0.--7. 1. " REC ,Receive Error Counter"
|
|
wgroup.long 0x24++0x7
|
|
line.long 0x00 "CAN_TCR,CAN Transfer Command Register"
|
|
bitfld.long 0x00 31. " TIMRST ,Timer Reset" "No reset,Reset"
|
|
bitfld.long 0x00 7. " MB7 ,Transfer Request for Mailbox 7" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " MB6 ,Transfer Request for Mailbox 6" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MB5 ,Transfer Request for Mailbox 5" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " MB4 ,Transfer Request for Mailbox 4" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " MB3 ,Transfer Request for Mailbox 3" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MB2 ,Transfer Request for Mailbox 2" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " MB1 ,Transfer Request for Mailbox 1" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " MB0 ,Transfer Request for Mailbox 0" "Not requested,Requested"
|
|
line.long 0x04 "CAN_ACR,CAN Abort Command Register"
|
|
bitfld.long 0x04 7. " MB7 ,Abort Request for Mailbox 7" "Not aborted,Aborted"
|
|
bitfld.long 0x04 6. " MB6 ,Abort Request for Mailbox 6" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x04 5. " MB5 ,Abort Request for Mailbox 5" "Not aborted,Aborted"
|
|
bitfld.long 0x04 4. " MB4 ,Abort Request for Mailbox 4" "Not aborted,Aborted"
|
|
bitfld.long 0x04 3. " MB3 ,Abort Request for Mailbox 3" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x04 2. " MB2 ,Abort Request for Mailbox 2" "Not aborted,Aborted"
|
|
bitfld.long 0x04 1. " MB1 ,Abort Request for Mailbox 1" "Not aborted,Aborted"
|
|
bitfld.long 0x04 0. " MB0 ,Abort Request for Mailbox 0" "Not aborted,Aborted"
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "CAN_WPMR,CAN Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,SPI Write Protection Key Password"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x00 "CAN_WPSR,CAN Write Protection Status Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " WPVSRC ,Write Protection Violation Source"
|
|
bitfld.long 0x00 0. " WPVS ,Write Protection Violation Status" "Not occurred,Occurred"
|
|
width 12.
|
|
tree "Mailbox 0"
|
|
group.long 0x200++0xB
|
|
line.long 0x00 "CAN_MMR0,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "MB_DISABLED,MB_RX,MB_RX_OVERWRITE,MB_TX,MB_CONSUMER,MB_PRODUCER,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM0,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID0,Compared IDvA and IDvB with CAN_MID0"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID0,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x200+0x0C)++0x7
|
|
line.long 0x0 "CAN_MFID0,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
line.long 0x04 "CAN_MSR0,CAN Message Status Register"
|
|
bitfld.long 0x04 24. " MMI ,Mailbox Message Ignored" "Not ignored,Ignored"
|
|
bitfld.long 0x04 23. " MRDY ,Mailbox Ready" "Can not R/W by software,Can R/W by software"
|
|
bitfld.long 0x04 22. " MABT ,Mailbox Message Abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x04 20. " MRTR ,Mailbox Remote Transmission Request" "Not occurred,Occurred"
|
|
bitfld.long 0x04 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--15. 1. " MTIMESTAMP ,Timer value"
|
|
group.long (0x200+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL0,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH0,CAN Message Data High Register"
|
|
wgroup.long (0x200+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR0,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 0" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Mailbox 1"
|
|
group.long 0x220++0xB
|
|
line.long 0x00 "CAN_MMR1,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "MB_DISABLED,MB_RX,MB_RX_OVERWRITE,MB_TX,MB_CONSUMER,MB_PRODUCER,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM1,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID1,Compared IDvA and IDvB with CAN_MID1"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID1,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x220+0x0C)++0x7
|
|
line.long 0x0 "CAN_MFID1,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
line.long 0x04 "CAN_MSR1,CAN Message Status Register"
|
|
bitfld.long 0x04 24. " MMI ,Mailbox Message Ignored" "Not ignored,Ignored"
|
|
bitfld.long 0x04 23. " MRDY ,Mailbox Ready" "Can not R/W by software,Can R/W by software"
|
|
bitfld.long 0x04 22. " MABT ,Mailbox Message Abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x04 20. " MRTR ,Mailbox Remote Transmission Request" "Not occurred,Occurred"
|
|
bitfld.long 0x04 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--15. 1. " MTIMESTAMP ,Timer value"
|
|
group.long (0x220+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL1,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH1,CAN Message Data High Register"
|
|
wgroup.long (0x220+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR1,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 1" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Mailbox 2"
|
|
group.long 0x240++0xB
|
|
line.long 0x00 "CAN_MMR2,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "MB_DISABLED,MB_RX,MB_RX_OVERWRITE,MB_TX,MB_CONSUMER,MB_PRODUCER,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM2,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID2,Compared IDvA and IDvB with CAN_MID2"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID2,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x240+0x0C)++0x7
|
|
line.long 0x0 "CAN_MFID2,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
line.long 0x04 "CAN_MSR2,CAN Message Status Register"
|
|
bitfld.long 0x04 24. " MMI ,Mailbox Message Ignored" "Not ignored,Ignored"
|
|
bitfld.long 0x04 23. " MRDY ,Mailbox Ready" "Can not R/W by software,Can R/W by software"
|
|
bitfld.long 0x04 22. " MABT ,Mailbox Message Abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x04 20. " MRTR ,Mailbox Remote Transmission Request" "Not occurred,Occurred"
|
|
bitfld.long 0x04 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--15. 1. " MTIMESTAMP ,Timer value"
|
|
group.long (0x240+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL2,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH2,CAN Message Data High Register"
|
|
wgroup.long (0x240+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR2,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 2" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Mailbox 3"
|
|
group.long 0x260++0xB
|
|
line.long 0x00 "CAN_MMR3,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "MB_DISABLED,MB_RX,MB_RX_OVERWRITE,MB_TX,MB_CONSUMER,MB_PRODUCER,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM3,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID3,Compared IDvA and IDvB with CAN_MID3"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID3,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x260+0x0C)++0x7
|
|
line.long 0x0 "CAN_MFID3,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
line.long 0x04 "CAN_MSR3,CAN Message Status Register"
|
|
bitfld.long 0x04 24. " MMI ,Mailbox Message Ignored" "Not ignored,Ignored"
|
|
bitfld.long 0x04 23. " MRDY ,Mailbox Ready" "Can not R/W by software,Can R/W by software"
|
|
bitfld.long 0x04 22. " MABT ,Mailbox Message Abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x04 20. " MRTR ,Mailbox Remote Transmission Request" "Not occurred,Occurred"
|
|
bitfld.long 0x04 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--15. 1. " MTIMESTAMP ,Timer value"
|
|
group.long (0x260+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL3,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH3,CAN Message Data High Register"
|
|
wgroup.long (0x260+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR3,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 3" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Mailbox 4"
|
|
group.long 0x280++0xB
|
|
line.long 0x00 "CAN_MMR4,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "MB_DISABLED,MB_RX,MB_RX_OVERWRITE,MB_TX,MB_CONSUMER,MB_PRODUCER,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM4,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID4,Compared IDvA and IDvB with CAN_MID4"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID4,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x280+0x0C)++0x7
|
|
line.long 0x0 "CAN_MFID4,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
line.long 0x04 "CAN_MSR4,CAN Message Status Register"
|
|
bitfld.long 0x04 24. " MMI ,Mailbox Message Ignored" "Not ignored,Ignored"
|
|
bitfld.long 0x04 23. " MRDY ,Mailbox Ready" "Can not R/W by software,Can R/W by software"
|
|
bitfld.long 0x04 22. " MABT ,Mailbox Message Abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x04 20. " MRTR ,Mailbox Remote Transmission Request" "Not occurred,Occurred"
|
|
bitfld.long 0x04 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--15. 1. " MTIMESTAMP ,Timer value"
|
|
group.long (0x280+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL4,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH4,CAN Message Data High Register"
|
|
wgroup.long (0x280+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR4,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 4" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Mailbox 5"
|
|
group.long 0x2A0++0xB
|
|
line.long 0x00 "CAN_MMR5,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "MB_DISABLED,MB_RX,MB_RX_OVERWRITE,MB_TX,MB_CONSUMER,MB_PRODUCER,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM5,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID5,Compared IDvA and IDvB with CAN_MID5"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID5,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x2A0+0x0C)++0x7
|
|
line.long 0x0 "CAN_MFID5,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
line.long 0x04 "CAN_MSR5,CAN Message Status Register"
|
|
bitfld.long 0x04 24. " MMI ,Mailbox Message Ignored" "Not ignored,Ignored"
|
|
bitfld.long 0x04 23. " MRDY ,Mailbox Ready" "Can not R/W by software,Can R/W by software"
|
|
bitfld.long 0x04 22. " MABT ,Mailbox Message Abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x04 20. " MRTR ,Mailbox Remote Transmission Request" "Not occurred,Occurred"
|
|
bitfld.long 0x04 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--15. 1. " MTIMESTAMP ,Timer value"
|
|
group.long (0x2A0+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL5,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH5,CAN Message Data High Register"
|
|
wgroup.long (0x2A0+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR5,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 5" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Mailbox 6"
|
|
group.long 0x2C0++0xB
|
|
line.long 0x00 "CAN_MMR6,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "MB_DISABLED,MB_RX,MB_RX_OVERWRITE,MB_TX,MB_CONSUMER,MB_PRODUCER,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM6,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID6,Compared IDvA and IDvB with CAN_MID6"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID6,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x2C0+0x0C)++0x7
|
|
line.long 0x0 "CAN_MFID6,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
line.long 0x04 "CAN_MSR6,CAN Message Status Register"
|
|
bitfld.long 0x04 24. " MMI ,Mailbox Message Ignored" "Not ignored,Ignored"
|
|
bitfld.long 0x04 23. " MRDY ,Mailbox Ready" "Can not R/W by software,Can R/W by software"
|
|
bitfld.long 0x04 22. " MABT ,Mailbox Message Abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x04 20. " MRTR ,Mailbox Remote Transmission Request" "Not occurred,Occurred"
|
|
bitfld.long 0x04 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--15. 1. " MTIMESTAMP ,Timer value"
|
|
group.long (0x2C0+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL6,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH6,CAN Message Data High Register"
|
|
wgroup.long (0x2C0+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR6,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 6" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Mailbox 7"
|
|
group.long 0x2E0++0xB
|
|
line.long 0x00 "CAN_MMR7,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "MB_DISABLED,MB_RX,MB_RX_OVERWRITE,MB_TX,MB_CONSUMER,MB_PRODUCER,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM7,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID7,Compared IDvA and IDvB with CAN_MID7"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID7,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDVA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDVB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x2E0+0x0C)++0x7
|
|
line.long 0x0 "CAN_MFID7,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
line.long 0x04 "CAN_MSR7,CAN Message Status Register"
|
|
bitfld.long 0x04 24. " MMI ,Mailbox Message Ignored" "Not ignored,Ignored"
|
|
bitfld.long 0x04 23. " MRDY ,Mailbox Ready" "Can not R/W by software,Can R/W by software"
|
|
bitfld.long 0x04 22. " MABT ,Mailbox Message Abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x04 20. " MRTR ,Mailbox Remote Transmission Request" "Not occurred,Occurred"
|
|
bitfld.long 0x04 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--15. 1. " MTIMESTAMP ,Timer value"
|
|
group.long (0x2E0+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL7,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH7,CAN Message Data High Register"
|
|
wgroup.long (0x2E0+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR7,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 7" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree.open "PIO (Parallel Input/Output Controller)"
|
|
tree "PIO A"
|
|
base ad:0x400E0E00
|
|
width 13.
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PIO_PSR,PIO Status Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO Status 20" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,PIO Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,PIO Status 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,PIO Status 29" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,PIO Status 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,PIO Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,PIO Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,PIO Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,PIO Status 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,PIO Status 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,PIO Status 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,PIO Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO Status 20" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO Status 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO Status 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO Status 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO Status 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO Status 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO Status 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO Status 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO Status 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO Status 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO Status 0" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PIO_OSR,PIO Output Status Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Status pin 20" "Input,Output"
|
|
else
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Status pin 31" "Input,Output"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Status pin 30" "Input,Output"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Status pin 29" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Status pin 28" "Input,Output"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Status pin 27" "Input,Output"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Status pin 26" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Status pin 25" "Input,Output"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Status pin 24" "Input,Output"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Status pin 23" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Status pin 22" "Input,Output"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Status pin 21" "Input,Output"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Status pin 20" "Input,Output"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Status pin 19" "Input,Output"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Status pin 18" "Input,Output"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Status pin 17" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Status pin 16" "Input,Output"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Status pin 15" "Input,Output"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Status pin 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Status pin 13" "Input,Output"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Status pin 12" "Input,Output"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Status pin 11" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Status pin 10" "Input,Output"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Status pin 9" "Input,Output"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Status pin 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Status pin 7" "Input,Output"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Status pin 6" "Input,Output"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Status pin 5" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Status pin 4" "Input,Output"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Status pin 3" "Input,Output"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Status pin 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Status pin 1" "Input,Output"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Status pin 0" "Input,Output"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PIO_IFSR,PIO Input Filter Status Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Input Filer Status pin 20" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Input Filer Status pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Input Filer Status pin 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Input Filer Status pin 29" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Input Filer Status pin 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Input Filer Status pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Input Filer Status pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Input Filer Status pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Input Filer Status pin 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Input Filer Status pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Input Filer Status pin 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Input Filer Status pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Input Filer Status pin 20" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Input Filer Status pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Input Filer Status pin 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Input Filer Status pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Input Filer Status pin 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Input Filer Status pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Filer Status pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Filer Status pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Filer Status pin 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Filer Status pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Filer Status pin 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Filer Status pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Filer Status pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Filer Status pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Filer Status pin 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Filer Status pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Filer Status pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Filer Status pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Filer Status pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Filer Status pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Filer Status pin 0" "Disabled,Enabled"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PIO_ODSR,PIO Output Data Status Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Data Status pin 20" "0,1"
|
|
else
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Data Status pin 31" "0,1"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Data Status pin 30" "0,1"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Data Status pin 29" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Data Status pin 28" "0,1"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Data Status pin 27" "0,1"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Data Status pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Data Status pin 25" "0,1"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Data Status pin 24" "0,1"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Data Status pin 23" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Data Status pin 22" "0,1"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Data Status pin 21" "0,1"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Data Status pin 20" "0,1"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Data Status pin 19" "0,1"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Data Status pin 18" "0,1"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Data Status pin 17" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Data Status pin 16" "0,1"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Data Status pin 15" "0,1"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Data Status pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Data Status pin 13" "0,1"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Data Status pin 12" "0,1"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Data Status pin 11" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Data Status pin 10" "0,1"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Data Status pin 9" "0,1"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Data Status pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Data Status pin 7" "0,1"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Data Status pin 6" "0,1"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Data Status pin 5" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Data Status pin 4" "0,1"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Data Status pin 3" "0,1"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Data Status pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Data Status pin 1" "0,1"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Data Status pin 0" "0,1"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "PIO_PDSR,PIO Pin Data Status Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
bitfld.long 0x00 20. " P20 ,Output Data Status pin 20" "Level 0,Level 1"
|
|
else
|
|
bitfld.long 0x00 31. " P31 ,Output Data Status pin 31" "Level 0,Level 1"
|
|
bitfld.long 0x00 30. " P30 ,Output Data Status pin 30" "Level 0,Level 1"
|
|
bitfld.long 0x00 29. " P29 ,Output Data Status pin 29" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " P28 ,Output Data Status pin 28" "Level 0,Level 1"
|
|
bitfld.long 0x00 27. " P27 ,Output Data Status pin 27" "Level 0,Level 1"
|
|
bitfld.long 0x00 26. " P26 ,Output Data Status pin 26" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Data Status pin 25" "Level 0,Level 1"
|
|
bitfld.long 0x00 24. " P24 ,Output Data Status pin 24" "Level 0,Level 1"
|
|
bitfld.long 0x00 23. " P23 ,Output Data Status pin 23" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Output Data Status pin 22" "Level 0,Level 1"
|
|
bitfld.long 0x00 21. " P21 ,Output Data Status pin 21" "Level 0,Level 1"
|
|
bitfld.long 0x00 20. " P20 ,Output Data Status pin 20" "Level 0,Level 1"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Data Status pin 19" "Level 0,Level 1"
|
|
bitfld.long 0x00 18. " P18 ,Output Data Status pin 18" "Level 0,Level 1"
|
|
bitfld.long 0x00 17. " P17 ,Output Data Status pin 17" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Output Data Status pin 16" "Level 0,Level 1"
|
|
bitfld.long 0x00 15. " P15 ,Output Data Status pin 15" "Level 0,Level 1"
|
|
bitfld.long 0x00 14. " P14 ,Output Data Status pin 14" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Data Status pin 13" "Level 0,Level 1"
|
|
bitfld.long 0x00 12. " P12 ,Output Data Status pin 12" "Level 0,Level 1"
|
|
bitfld.long 0x00 11. " P11 ,Output Data Status pin 11" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Output Data Status pin 10" "Level 0,Level 1"
|
|
bitfld.long 0x00 9. " P9 ,Output Data Status pin 9" "Level 0,Level 1"
|
|
bitfld.long 0x00 8. " P8 ,Output Data Status pin 8" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Data Status pin 7" "Level 0,Level 1"
|
|
bitfld.long 0x00 6. " P6 ,Output Data Status pin 6" "Level 0,Level 1"
|
|
bitfld.long 0x00 5. " P5 ,Output Data Status pin 5" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Output Data Status pin 4" "Level 0,Level 1"
|
|
bitfld.long 0x00 3. " P3 ,Output Data Status pin 3" "Level 0,Level 1"
|
|
bitfld.long 0x00 2. " P2 ,Output Data Status pin 2" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Data Status pin 1" "Level 0,Level 1"
|
|
bitfld.long 0x00 0. " P0 ,Output Data Status pin 0" "Level 0,Level 1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PIO_IMR,PIO Interrupt Status Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Input Change Interrupt Mask pin 20" "No interrupt,Interrupt"
|
|
else
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Input Change Interrupt Mask pin 31" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Input Change Interrupt Mask pin 30" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Input Change Interrupt Mask pin 29" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Input Change Interrupt Mask pin 28" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Input Change Interrupt Mask pin 27" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Input Change Interrupt Mask pin 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Input Change Interrupt Mask pin 25" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Input Change Interrupt Mask pin 24" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Input Change Interrupt Mask pin 23" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Input Change Interrupt Mask pin 22" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Input Change Interrupt Mask pin 21" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Input Change Interrupt Mask pin 20" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Input Change Interrupt Mask pin 19" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Input Change Interrupt Mask pin 18" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Input Change Interrupt Mask pin 17" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Input Change Interrupt Mask pin 16" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Input Change Interrupt Mask pin 15" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Change Interrupt Mask pin 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Change Interrupt Mask pin 13" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Change Interrupt Mask pin 12" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Change Interrupt Mask pin 11" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Change Interrupt Mask pin 10" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Change Interrupt Mask pin 9" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Change Interrupt Mask pin 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Change Interrupt Mask pin 7" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Change Interrupt Mask pin 6" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Change Interrupt Mask pin 5" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Change Interrupt Mask pin 4" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Change Interrupt Mask pin 3" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Change Interrupt Mask pin 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Change Interrupt Mask pin 1" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Change Interrupt Mask pin 0" "No interrupt,Interrupt"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "PIO_ISR,PIO Interrupt Status Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
bitfld.long 0x00 20. " P20 ,Input Change Interrupt Status pin 20" "Not detected,Detected"
|
|
else
|
|
bitfld.long 0x00 31. " P31 ,Input Change Interrupt Status pin 31" "Not detected,Detected"
|
|
bitfld.long 0x00 30. " P30 ,Input Change Interrupt Status pin 30" "Not detected,Detected"
|
|
bitfld.long 0x00 29. " P29 ,Input Change Interrupt Status pin 29" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 28. " P28 ,Input Change Interrupt Status pin 28" "Not detected,Detected"
|
|
bitfld.long 0x00 27. " P27 ,Input Change Interrupt Status pin 27" "Not detected,Detected"
|
|
bitfld.long 0x00 26. " P26 ,Input Change Interrupt Status pin 26" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Input Change Interrupt Status pin 25" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " P24 ,Input Change Interrupt Status pin 24" "Not detected,Detected"
|
|
bitfld.long 0x00 23. " P23 ,Input Change Interrupt Status pin 23" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Input Change Interrupt Status pin 22" "Not detected,Detected"
|
|
bitfld.long 0x00 21. " P21 ,Input Change Interrupt Status pin 21" "Not detected,Detected"
|
|
bitfld.long 0x00 20. " P20 ,Input Change Interrupt Status pin 20" "Not detected,Detected"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Input Change Interrupt Status pin 19" "Not detected,Detected"
|
|
bitfld.long 0x00 18. " P18 ,Input Change Interrupt Status pin 18" "Not detected,Detected"
|
|
bitfld.long 0x00 17. " P17 ,Input Change Interrupt Status pin 17" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Input Change Interrupt Status pin 16" "Not detected,Detected"
|
|
bitfld.long 0x00 15. " P15 ,Input Change Interrupt Status pin 15" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " P14 ,Input Change Interrupt Status pin 14" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Input Change Interrupt Status pin 13" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " P12 ,Input Change Interrupt Status pin 12" "Not detected,Detected"
|
|
bitfld.long 0x00 11. " P11 ,Input Change Interrupt Status pin 11" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Input Change Interrupt Status pin 10" "Not detected,Detected"
|
|
bitfld.long 0x00 9. " P9 ,Input Change Interrupt Status pin 9" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " P8 ,Input Change Interrupt Status pin 8" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Input Change Interrupt Status pin 7" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " P6 ,Input Change Interrupt Status pin 6" "Not detected,Detected"
|
|
bitfld.long 0x00 5. " P5 ,Input Change Interrupt Status pin 5" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Input Change Interrupt Status pin 4" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " P3 ,Input Change Interrupt Status pin 3" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " P2 ,Input Change Interrupt Status pin 2" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Input Change Interrupt Status pin 1" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " P0 ,Input Change Interrupt Status pin 0" "Not detected,Detected"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PIO_MDSR,PIO Multi-driver Status Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Multi Drive Status/Drive pin 20" "Low,High"
|
|
else
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Multi Drive Status/Drive pin 31" "Low,High"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Multi Drive Status/Drive pin 30" "Low,High"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Multi Drive Status/Drive pin 29" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Multi Drive Status/Drive pin 28" "Low,High"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Multi Drive Status/Drive pin 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Multi Drive Status/Drive pin 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Multi Drive Status/Drive pin 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Multi Drive Status/Drive pin 24" "Low,High"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Multi Drive Status/Drive pin 23" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Multi Drive Status/Drive pin 22" "Low,High"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Multi Drive Status/Drive pin 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Multi Drive Status/Drive pin 20" "Low,High"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Multi Drive Status/Drive pin 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Multi Drive Status/Drive pin 18" "Low,High"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Multi Drive Status/Drive pin 17" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Multi Drive Status/Drive pin 16" "Low,High"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Multi Drive Status/Drive pin 15" "Low,High"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Multi Drive Status/Drive pin 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Multi Drive Status/Drive pin 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Multi Drive Status/Drive pin 12" "Low,High"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Multi Drive Status/Drive pin 11" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Multi Drive Status/Drive pin 10" "Low,High"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Multi Drive Status/Drive pin 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Multi Drive Status/Drive pin 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Multi Drive Status/Drive pin 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Multi Drive Status/Drive pin 6" "Low,High"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Multi Drive Status/Drive pin 5" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Multi Drive Status/Drive pin 4" "Low,High"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Multi Drive Status/Drive pin 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Multi Drive Status/Drive pin 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Multi Drive Status/Drive pin 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Multi Drive Status/Drive pin 0" "Low,High"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PIO_PUSR,PIO Pull Up Status Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Pull Up Status pin 20" "Enabled,Disabled"
|
|
else
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31_set/clr ,Pull Up Status pin 31" "Enabled,Disabled"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30_set/clr ,Pull Up Status pin 30" "Enabled,Disabled"
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29_set/clr ,Pull Up Status pin 29" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28_set/clr ,Pull Up Status pin 28" "Enabled,Disabled"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27_set/clr ,Pull Up Status pin 27" "Enabled,Disabled"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26_set/clr ,Pull Up Status pin 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25_set/clr ,Pull Up Status pin 25" "Enabled,Disabled"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24_set/clr ,Pull Up Status pin 24" "Enabled,Disabled"
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_set/clr ,Pull Up Status pin 23" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_set/clr ,Pull Up Status pin 22" "Enabled,Disabled"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_set/clr ,Pull Up Status pin 21" "Enabled,Disabled"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Pull Up Status pin 20" "Enabled,Disabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_set/clr ,Pull Up Status pin 19" "Enabled,Disabled"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_set/clr ,Pull Up Status pin 18" "Enabled,Disabled"
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_set/clr ,Pull Up Status pin 17" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_set/clr ,Pull Up Status pin 16" "Enabled,Disabled"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Pull Up Status pin 15" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Pull Up Status pin 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Pull Up Status pin 13" "Enabled,Disabled"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Pull Up Status pin 12" "Enabled,Disabled"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Pull Up Status pin 11" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Pull Up Status pin 10" "Enabled,Disabled"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Pull Up Status pin 9" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Pull Up Status pin 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Pull Up Status pin 7" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Pull Up Status pin 6" "Enabled,Disabled"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Pull Up Status pin 5" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Pull Up Status pin 4" "Enabled,Disabled"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Pull Up Status pin 3" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Pull Up Status pin 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr ,Pull Up Status pin 1" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Pull Up Status pin 0" "Enabled,Disabled"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "PIO_ABCDSR1,Peripheral Select Register 1"
|
|
sif cpuis("ATSAM4N*")
|
|
sif cpuis("ATSAM4N8A")
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Select pin 20 - A/C B/D" "A/C,B/D"
|
|
else
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Select pin 31 - A/C B/D" "NPCS1/C,PCK2/D"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Select pin 30 - A/C B/D" "A/C,NPCS2/D"
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Select pin 29 - A/C B/D" "A/C,TCLK2/D"
|
|
textline " "
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Select pin 28 - A/C B/D" "A/C,TCLK1/D"
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Select pin 27 - A/C B/D" "A/C,TIOB2/D"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Select pin 26 - A/C B/D" "A/C,TIOA2/D"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Select pin 25 - A/C B/D" "CTS1/C,PWM2/D"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Select pin 24 - A/C B/D" "RTS1/C,PWM1/D"
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Select pin 23 - A/C B/D" "SCK1/C,PWM0/D"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Select pin 22 - A/C B/D" "TXD1/C,NPCS3/D"
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Select pin 21 - A/C B/D" "RXD1/C,PCK1/D"
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Select pin 20 - A/C B/D" "A/C,B/D"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Select pin 19 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Select pin 18 - A/C B/D" "A/C,PCK2/D"
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Select pin 17 - A/C B/D" "A/C,PCK1/D"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Select pin 16 - A/C B/D" "URXD2/C,TIOB1/D"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select pin 15 - A/C B/D" "UTXD2/C,TIOA1/D"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select pin 14 - A/C B/D" "SPCK/C,PWM3/D"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select pin 13 - A/C B/D" "MOSI/C,PWM2/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select pin 12 - A/C B/D" "MISO/C,PWM1/D"
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select pin 11 - A/C B/D" "NPCS0/C,PWM0/D"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select pin 10 - A/C B/D" "UTXD0/C,NPCS2/D"
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select pin 9 - A/C B/D" "URXD0/C,NPCS1/D"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select pin 8 - A/C B/D" "CTS0/C,ADTRG/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select pin 7 - A/C B/D" "RTS0/C,PWM3/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select pin 6 - A/C B/D" "TXD0/C,PCK0/D"
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select pin 5 - A/C B/D" "RXD0/C,NPCS3/D"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select pin 4 - A/C B/D" "TWCK0/C,TCLK0/D"
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select pin 3 - A/C B/D" "TWD0/C,NPCS3/D"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select pin 2 - A/C B/D" "PWM2/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select pin 1 - A/C B/D" "PWM1/C,TIOB0/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select pin 0 - A/C B/D" "PWM0/C,TIOA0/D "
|
|
else
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Select pin 31 - A/C B/D" "NPCS1/MCDA1,PCK2/D"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Select pin 30 - A/C B/D" "PWML2/MCDA0,NPCS2/D"
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Select pin 29 - A/C B/D" "RI1/MCCK,TCLK2/D"
|
|
textline " "
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Select pin 28 - A/C B/D" "DSR1/MCCDA,TCLK1/D"
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Select pin 27 - A/C B/D" "DTR1/MCDA3,TIOB2/D"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Select pin 26 - A/C B/D" "DCD1/MCDA2,TIOA2/D"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Select pin 25 - A/C B/D" "CTS1/A23,PWMH2/D"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Select pin 24 - A/C B/D" "RTS1/A20,PWMH1/D"
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Select pin 23 - A/C B/D" "SCK1/A19,PWMH0/D"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Select pin 22 - A/C B/D" "TXD1/NCS2,NPCS3/D"
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Select pin 21 - A/C B/D" "RXD1/C,PCK1/D"
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Select pin 20 - A/C B/D" "A/A16,PWML1/D"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Select pin 19 - A/C B/D" "A/A15,PWML0/D"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Select pin 18 - A/C B/D" "A/A14,PCK2/D"
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Select pin 17 - A/C B/D" "A/PWMH3,PCK1/D"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Select pin 16 - A/C B/D" "A/PWML2,TIOB1/D"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select pin 15 - A/C B/D" "A/PWML3,TIOA1/D"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select pin 14 - A/C B/D" "SPCK/C,PWMH3/D"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select pin 13 - A/C B/D" "MOSI/C,PWMH2/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select pin 12 - A/C B/D" "MISO/C,PWMH1/D"
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select pin 11 - A/C B/D" "NPCS0/C,PWMH0/D"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select pin 10 - A/C B/D" "UTXD0/C,NPCS2/D"
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select pin 9 - A/C B/D" "URXD0/PWMFI0,NPCS1/D"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select pin 8 - A/C B/D" "A/C,AFE0_ADTRG/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select pin 7 - A/C B/D" "A/C,PWMH3/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select pin 6 - A/C B/D" "A/UTXD1,PCK0/D"
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select pin 5 - A/C B/D" "A/URXD1,NPCS3/D"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select pin 4 - A/C B/D" "TWCK0/C,TCLK0/D"
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select pin 3 - A/C B/D" "TWD0/C,NPCS3/D"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select pin 2 - A/C B/D" "PWMH2/DATRG,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select pin 1 - A/C B/D" "PWMH1/A18,TIOB0/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select pin 0 - A/C B/D" "PWMH0/A17,TIOA0/D "
|
|
endif
|
|
line.long 0x04 "PIO_ABCDSR2,Peripheral Select Register 2"
|
|
sif cpuis("ATSAM4N*")
|
|
sif cpuis("ATSAM4N8A")
|
|
bitfld.long 0x04 20. " P20 ,Peripheral Select pin 20 - A/B C/D" "A/B,C/D"
|
|
else
|
|
bitfld.long 0x04 31. " P31 ,Peripheral Select pin 31 - A/B C/D" "NPCS1/PCK2,C/D"
|
|
bitfld.long 0x04 30. " P30 ,Peripheral Select pin 30 - A/B C/D" "A/NPCS2,C/D"
|
|
bitfld.long 0x04 29. " P29 ,Peripheral Select pin 29 - A/B C/D" "A/TCLK2,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 28. " P28 ,Peripheral Select pin 28 - A/B C/D" "A/TCLK1,C/D"
|
|
bitfld.long 0x04 27. " P27 ,Peripheral Select pin 27 - A/B C/D" "A/TIOB2,C/D"
|
|
bitfld.long 0x04 26. " P26 ,Peripheral Select pin 26 - A/B C/D" "A/TIOA2,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 25. " P25 ,Peripheral Select pin 25 - A/B C/D" "CTS1/PWM2,C/D"
|
|
bitfld.long 0x04 24. " P24 ,Peripheral Select pin 24 - A/B C/D" "RTS1/PWM1,C/D"
|
|
bitfld.long 0x04 23. " P23 ,Peripheral Select pin 23 - A/B C/D" "SCK1/PWM0,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 22. " P22 ,Peripheral Select pin 22 - A/B C/D" "TXD1/NPCS3,C/D"
|
|
bitfld.long 0x04 21. " P21 ,Peripheral Select pin 21 - A/B C/D" "RXD1/PCK1,C/D"
|
|
bitfld.long 0x04 20. " P20 ,Peripheral Select pin 20 - A/B C/D" "A/B,C/D"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 19. " P19 ,Peripheral Select pin 19 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 18. " P18 ,Peripheral Select pin 18 - A/B C/D" "A/PCK2,C/D"
|
|
bitfld.long 0x04 17. " P17 ,Peripheral Select pin 17 - A/B C/D" "A/PCK1,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 16. " P16 ,Peripheral Select pin 16 - A/B C/D" "URXD2/TIOB1,C/D"
|
|
bitfld.long 0x04 15. " P15 ,Peripheral Select pin 15 - A/B C/D" "UTXD2/TIOA1,C/D"
|
|
bitfld.long 0x04 14. " P14 ,Peripheral Select pin 14 - A/B C/D" "SPCK/PWM3,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 13. " P13 ,Peripheral Select pin 13 - A/B C/D" "MOSI/PWM2,C/D"
|
|
bitfld.long 0x04 12. " P12 ,Peripheral Select pin 12 - A/B C/D" "MISO/PWM1,C/D"
|
|
bitfld.long 0x04 11. " P11 ,Peripheral Select pin 11 - A/B C/D" "NPCS0/PWM0,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 10. " P10 ,Peripheral Select pin 10 - A/B C/D" "UTXD0/NPCS2,C/D"
|
|
bitfld.long 0x04 9. " P9 ,Peripheral Select pin 9 - A/B C/D" "URXD0/NPCS1,C/D"
|
|
bitfld.long 0x04 8. " P8 ,Peripheral Select pin 8 - A/B C/D" "CTS0/ADTRG,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 7. " P7 ,Peripheral Select pin 7 - A/B C/D" "RTS0/PWM3,C/D"
|
|
bitfld.long 0x04 6. " P6 ,Peripheral Select pin 6 - A/B C/D" "TXD0/PCK0,C/D"
|
|
bitfld.long 0x04 5. " P5 ,Peripheral Select pin 5 - A/B C/D" "RXD0/NPCS3,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 4. " P4 ,Peripheral Select pin 4 - A/B C/D" "TWCK0/TCLK0,C/D"
|
|
bitfld.long 0x04 3. " P3 ,Peripheral Select pin 3 - A/B C/D" "TWD0/NPCS3,C/D"
|
|
bitfld.long 0x04 2. " P2 ,Peripheral Select pin 2 - A/B C/D" "PWM2/SCK0,DATRG/D"
|
|
textline " "
|
|
bitfld.long 0x04 1. " P1 ,Peripheral Select pin 1 - A/B C/D" "PWM1/TIOB0,C/D"
|
|
bitfld.long 0x04 0. " P0 ,Peripheral Select pin 0 - A/B C/D" "PWM0/TIOA0,C/D"
|
|
else
|
|
bitfld.long 0x04 31. " P31 ,Peripheral Select pin 31 - A/B C/D" "NPCS1/PCK2,MCDA1/D"
|
|
bitfld.long 0x04 30. " P30 ,Peripheral Select pin 30 - A/B C/D" "PWML2/NPCS2,MCDA0/D"
|
|
bitfld.long 0x04 29. " P29 ,Peripheral Select pin 29 - A/B C/D" "RI1/TCLK2,MCCK/D"
|
|
textline " "
|
|
bitfld.long 0x04 28. " P28 ,Peripheral Select pin 28 - A/B C/D" "DSR1/TCLK1,MCCDA/D"
|
|
bitfld.long 0x04 27. " P27 ,Peripheral Select pin 27 - A/B C/D" "DTR1/TIOB2,MCDA3/D"
|
|
bitfld.long 0x04 26. " P26 ,Peripheral Select pin 26 - A/B C/D" "DCD1/TIOA2,MCDA2/D"
|
|
textline " "
|
|
bitfld.long 0x04 25. " P25 ,Peripheral Select pin 25 - A/B C/D" "CTS1/PWMH2,A23/D"
|
|
bitfld.long 0x04 24. " P24 ,Peripheral Select pin 24 - A/B C/D" "RTS1/PWMH1,A20/D"
|
|
bitfld.long 0x04 23. " P23 ,Peripheral Select pin 23 - A/B C/D" "SCK1/PWMH0,A19/D"
|
|
textline " "
|
|
bitfld.long 0x04 22. " P22 ,Peripheral Select pin 22 - A/B C/D" "TXD1/NPCS3,NCS2/D"
|
|
bitfld.long 0x04 21. " P21 ,Peripheral Select pin 21 - A/B C/D" "RXD1/PCK1,C/D"
|
|
bitfld.long 0x04 20. " P20 ,Peripheral Select pin 20 - A/B C/D" "A/PWML1,A16/D"
|
|
textline " "
|
|
bitfld.long 0x04 19. " P19 ,Peripheral Select pin 19 - A/B C/D" "A/PWML0,A15/D"
|
|
bitfld.long 0x04 18. " P18 ,Peripheral Select pin 18 - A/B C/D" "A/PCK2,A14/D"
|
|
bitfld.long 0x04 17. " P17 ,Peripheral Select pin 17 - A/B C/D" "A/PCK1,PWMH3/D"
|
|
textline " "
|
|
bitfld.long 0x04 16. " P16 ,Peripheral Select pin 16 - A/B C/D" "A/TIOB1,PWML2/D"
|
|
bitfld.long 0x04 15. " P15 ,Peripheral Select pin 15 - A/B C/D" "A/TIOA1,PWML3/D"
|
|
bitfld.long 0x04 14. " P14 ,Peripheral Select pin 14 - A/B C/D" "SPCK/PWMH3,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 13. " P13 ,Peripheral Select pin 13 - A/B C/D" "MOSI/PWMH2,C/D"
|
|
bitfld.long 0x04 12. " P12 ,Peripheral Select pin 12 - A/B C/D" "MISO/PWMH1,C/D"
|
|
bitfld.long 0x04 11. " P11 ,Peripheral Select pin 11 - A/B C/D" "NPCS0/PWMH0,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 10. " P10 ,Peripheral Select pin 10 - A/B C/D" "UTXD0/NPCS2,C/D"
|
|
bitfld.long 0x04 9. " P9 ,Peripheral Select pin 9 - A/B C/D" "URXD0/NPCS1,PWMFI0/D"
|
|
bitfld.long 0x04 8. " P8 ,Peripheral Select pin 8 - A/B C/D" "A/AFE0_ADTRG,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 7. " P7 ,Peripheral Select pin 7 - A/B C/D" "A/PWMH3,C/D"
|
|
bitfld.long 0x04 6. " P6 ,Peripheral Select pin 6 - A/B C/D" "A/PCK0,UTXD1/D"
|
|
bitfld.long 0x04 5. " P5 ,Peripheral Select pin 5 - A/B C/D" "A/NPCS3,URXD1/D"
|
|
textline " "
|
|
bitfld.long 0x04 4. " P4 ,Peripheral Select pin 4 - A/B C/D" "TWCK0/TCLK0,C/D"
|
|
bitfld.long 0x04 3. " P3 ,Peripheral Select pin 3 - A/B C/D" "TWD0/NPCS3,C/D"
|
|
bitfld.long 0x04 2. " P2 ,Peripheral Select pin 2 - A/B C/D" "PWMH2/B,DATRG/D"
|
|
textline " "
|
|
bitfld.long 0x04 1. " P1 ,Peripheral Select pin 1 - A/B C/D" "PWMH1/TIOB0,A18/D"
|
|
bitfld.long 0x04 0. " P0 ,Peripheral Select pin 0 - A/B C/D" "PWMH0/TIOA0,A17/D"
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PIO_IFSCSR,PIO Input Filter Slow Clock Status Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Glitch or Debouncing Filter Selection Status pin 20" "Glitch,Debouncing"
|
|
else
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31_set/clr ,Glitch or Debouncing Filter Selection Status pin 31" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30_set/clr ,Glitch or Debouncing Filter Selection Status pin 30" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29_set/clr ,Glitch or Debouncing Filter Selection Status pin 29" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28_set/clr ,Glitch or Debouncing Filter Selection Status pin 28" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27_set/clr ,Glitch or Debouncing Filter Selection Status pin 27" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26_set/clr ,Glitch or Debouncing Filter Selection Status pin 26" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25_set/clr ,Glitch or Debouncing Filter Selection Status pin 25" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24_set/clr ,Glitch or Debouncing Filter Selection Status pin 24" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_set/clr ,Glitch or Debouncing Filter Selection Status pin 23" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_set/clr ,Glitch or Debouncing Filter Selection Status pin 22" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_set/clr ,Glitch or Debouncing Filter Selection Status pin 21" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Glitch or Debouncing Filter Selection Status pin 20" "Glitch,Debouncing"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_set/clr ,Glitch or Debouncing Filter Selection Status pin 19" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_set/clr ,Glitch or Debouncing Filter Selection Status pin 18" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_set/clr ,Glitch or Debouncing Filter Selection Status pin 17" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_set/clr ,Glitch or Debouncing Filter Selection Status pin 16" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Glitch or Debouncing Filter Selection Status pin 15" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status pin 14" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status pin 13" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status pin 12" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status pin 11" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status pin 10" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status pin 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status pin 8" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status pin 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status pin 6" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status pin 5" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status pin 4" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status pin 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status pin 2" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr ,Glitch or Debouncing Filter Selection Status pin 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status pin 0" "Glitch,Debouncing"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PIO_SCDR,PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow Clock Divider Selection for Debouncing - Tdiv_slclk = 2*(DIV+1)*Tslow_clock"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PIO_PPDSR,PIO Pad Pull Down Status Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20 ,Pull Down Status pin 20" "Enabled,Disabled"
|
|
else
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31 ,Pull Down Status pin 31" "Enabled,Disabled"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30 ,Pull Down Status pin 30" "Enabled,Disabled"
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29 ,Pull Down Status pin 29" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28 ,Pull Down Status pin 28" "Enabled,Disabled"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27 ,Pull Down Status pin 27" "Enabled,Disabled"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26 ,Pull Down Status pin 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25 ,Pull Down Status pin 25" "Enabled,Disabled"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24 ,Pull Down Status pin 24" "Enabled,Disabled"
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23 ,Pull Down Status pin 23" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22 ,Pull Down Status pin 22" "Enabled,Disabled"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21 ,Pull Down Status pin 21" "Enabled,Disabled"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20 ,Pull Down Status pin 20" "Enabled,Disabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19 ,Pull Down Status pin 19" "Enabled,Disabled"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18 ,Pull Down Status pin 18" "Enabled,Disabled"
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17 ,Pull Down Status pin 17" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16 ,Pull Down Status pin 16" "Enabled,Disabled"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15 ,Pull Down Status pin 15" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14 ,Pull Down Status pin 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13 ,Pull Down Status pin 13" "Enabled,Disabled"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12 ,Pull Down Status pin 12" "Enabled,Disabled"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11 ,Pull Down Status pin 11" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10 ,Pull Down Status pin 10" "Enabled,Disabled"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9 ,Pull Down Status pin 9" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8 ,Pull Down Status pin 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7 ,Pull Down Status pin 7" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6 ,Pull Down Status pin 6" "Enabled,Disabled"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5 ,Pull Down Status pin 5" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4 ,Pull Down Status pin 4" "Enabled,Disabled"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3 ,Pull Down Status pin 3" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2 ,Pull Down Status pin 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1 ,Pull Down Status pin 1" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0 ,Pull Down Status pin 0" "Enabled,Disabled"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PIO_OWSR,PIO Output Write Status Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Write Status pin 20" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Write Status pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Write Status pin 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Write Status pin 29" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Write Status pin 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Write Status pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Write Status pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Write Status pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Write Status pin 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Write Status pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Write Status pin 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Write Status pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Write Status pin 20" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Write Status pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Write Status pin 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Write Status pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Write Status pin 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Write Status pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Write Status pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Write Status pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Write Status pin 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Write Status pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Write Status pin 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Write Status pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Write Status pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Write Status pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Write Status pin 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Write Status pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Write Status pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Write Status pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Write Status pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Write Status pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Write Status pin 0" "Disabled,Enabled"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "PIO_AIMMR,PIO Additional Interrupt Modes Mask Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Peripheral CD Status pin 20" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
else
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Peripheral CD Status pin 31" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Peripheral CD Status pin 30" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Peripheral CD Status pin 29" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Peripheral CD Status pin 28" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Peripheral CD Status pin 27" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Peripheral CD Status pin 26" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Peripheral CD Status pin 25" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Peripheral CD Status pin 24" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Peripheral CD Status pin 23" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Peripheral CD Status pin 22" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Peripheral CD Status pin 21" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Peripheral CD Status pin 20" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Peripheral CD Status pin 19" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Peripheral CD Status pin 18" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Peripheral CD Status pin 17" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Peripheral CD Status pin 16" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Peripheral CD Status pin 15" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Peripheral CD Status pin 14" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Peripheral CD Status pin 13" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Peripheral CD Status pin 12" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Peripheral CD Status pin 11" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Peripheral CD Status pin 10" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Peripheral CD Status pin 9" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Peripheral CD Status pin 8" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Peripheral CD Status pin 7" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Peripheral CD Status pin 6" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Peripheral CD Status pin 5" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Peripheral CD Status pin 4" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Peripheral CD Status pin 3" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Peripheral CD Status pin 2" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Peripheral CD Status pin 1" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Peripheral CD Status pin 0" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "PIO_ELSR,PIO Edge/Level Status Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Edge/Level Interrupt source selection pin 20" "Edge,Level"
|
|
else
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Edge/Level Interrupt source selection pin 31" "Edge,Level"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Edge/Level Interrupt source selection pin 30" "Edge,Level"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Edge/Level Interrupt source selection pin 29" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Edge/Level Interrupt source selection pin 28" "Edge,Level"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Edge/Level Interrupt source selection pin 27" "Edge,Level"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Edge/Level Interrupt source selection pin 26" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Edge/Level Interrupt source selection pin 25" "Edge,Level"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Edge/Level Interrupt source selection pin 24" "Edge,Level"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Edge/Level Interrupt source selection pin 23" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Edge/Level Interrupt source selection pin 22" "Edge,Level"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Edge/Level Interrupt source selection pin 21" "Edge,Level"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Edge/Level Interrupt source selection pin 20" "Edge,Level"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Edge/Level Interrupt source selection pin 19" "Edge,Level"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Edge/Level Interrupt source selection pin 18" "Edge,Level"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Edge/Level Interrupt source selection pin 17" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Edge/Level Interrupt source selection pin 16" "Edge,Level"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Edge/Level Interrupt source selection pin 15" "Edge,Level"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection pin 14" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection pin 13" "Edge,Level"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection pin 12" "Edge,Level"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection pin 11" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection pin 10" "Edge,Level"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection pin 9" "Edge,Level"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection pin 8" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection pin 7" "Edge,Level"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection pin 6" "Edge,Level"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection pin 5" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection pin 4" "Edge,Level"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection pin 3" "Edge,Level"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection pin 2" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Edge/Level Interrupt source selection pin 1" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection pin 0" "Edge,Level"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "PIO_FRLHSR,PIO Fall/Rise - Low/High Status Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Edge /Level Interrupt Source Selection pin 20" "Falling/Low,Rising/High"
|
|
else
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31_set/clr ,Edge /Level Interrupt Source Selection pin 31" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30_set/clr ,Edge /Level Interrupt Source Selection pin 30" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29_set/clr ,Edge /Level Interrupt Source Selection pin 29" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28_set/clr ,Edge /Level Interrupt Source Selection pin 28" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27_set/clr ,Edge /Level Interrupt Source Selection pin 27" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26_set/clr ,Edge /Level Interrupt Source Selection pin 26" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25_set/clr ,Edge /Level Interrupt Source Selection pin 25" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24_set/clr ,Edge /Level Interrupt Source Selection pin 24" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_set/clr ,Edge /Level Interrupt Source Selection pin 23" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_set/clr ,Edge /Level Interrupt Source Selection pin 22" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_set/clr ,Edge /Level Interrupt Source Selection pin 21" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Edge /Level Interrupt Source Selection pin 20" "Falling/Low,Rising/High"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_set/clr ,Edge /Level Interrupt Source Selection pin 19" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_set/clr ,Edge /Level Interrupt Source Selection pin 18" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_set/clr ,Edge /Level Interrupt Source Selection pin 17" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_set/clr ,Edge /Level Interrupt Source Selection pin 16" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Edge /Level Interrupt Source Selection pin 15" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Edge /Level Interrupt Source Selection pin 14" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Edge /Level Interrupt Source Selection pin 13" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Edge /Level Interrupt Source Selection pin 12" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Edge /Level Interrupt Source Selection pin 11" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Edge /Level Interrupt Source Selection pin 10" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Edge /Level Interrupt Source Selection pin 9" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Edge /Level Interrupt Source Selection pin 8" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Edge /Level Interrupt Source Selection pin 7" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Edge /Level Interrupt Source Selection pin 6" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Edge /Level Interrupt Source Selection pin 5" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Edge /Level Interrupt Source Selection pin 4" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Edge /Level Interrupt Source Selection pin 3" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Edge /Level Interrupt Source Selection pin 2" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr ,Edge /Level Interrupt Source Selection pin 1" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Edge /Level Interrupt Source Selection pin 0" "Falling/Low,Rising/High"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "PIO_LOCKSR,PIO Lock Status Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
bitfld.long 0x00 20. " P20 ,Lock Status pin 20" "Not locked,Locked"
|
|
else
|
|
bitfld.long 0x00 31. " P31 ,Lock Status pin 31" "Not locked,Locked"
|
|
bitfld.long 0x00 30. " P30 ,Lock Status pin 30" "Not locked,Locked"
|
|
bitfld.long 0x00 29. " P29 ,Lock Status pin 29" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " P28 ,Lock Status pin 28" "Not locked,Locked"
|
|
bitfld.long 0x00 27. " P27 ,Lock Status pin 27" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " P26 ,Lock Status pin 26" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Lock Status pin 25" "Not locked,Locked"
|
|
bitfld.long 0x00 24. " P24 ,Lock Status pin 24" "Not locked,Locked"
|
|
bitfld.long 0x00 23. " P23 ,Lock Status pin 23" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Lock Status pin 22" "Not locked,Locked"
|
|
bitfld.long 0x00 21. " P21 ,Lock Status pin 21" "Not locked,Locked"
|
|
bitfld.long 0x00 20. " P20 ,Lock Status pin 20" "Not locked,Locked"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Lock Status pin 19" "Not locked,Locked"
|
|
bitfld.long 0x00 18. " P18 ,Lock Status pin 18" "Not locked,Locked"
|
|
bitfld.long 0x00 17. " P17 ,Lock Status pin 17" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Lock Status pin 16" "Not locked,Locked"
|
|
bitfld.long 0x00 15. " P15 ,Lock Status pin 15" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " P14 ,Lock Status pin 14" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Lock Status pin 13" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " P12 ,Lock Status pin 12" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " P11 ,Lock Status pin 11" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Lock Status pin 10" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " P9 ,Lock Status pin 9" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " P8 ,Lock Status pin 8" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Lock Status pin 7" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,Lock Status pin 6" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " P5 ,Lock Status pin 5" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Lock Status pin 4" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " P3 ,Lock Status pin 3" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " P2 ,Lock Status pin 2" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Lock Status pin 1" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,Lock Status pin 0" "Not locked,Locked"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in.
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PIO_SCHMITT,PIO Schmitt Trigger Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
bitfld.long 0x00 20. " SCHMITT20 ,Schmitt Trigger 20 Disabled" "No,Yes"
|
|
else
|
|
bitfld.long 0x00 31. " SCHMITT31 ,Schmitt Trigger 31 Disabled" "No,Yes"
|
|
bitfld.long 0x00 30. " SCHMITT30 ,Schmitt Trigger 30 Disabled" "No,Yes"
|
|
bitfld.long 0x00 29. " SCHMITT29 ,Schmitt Trigger 29 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SCHMITT28 ,Schmitt Trigger 28 Disabled" "No,Yes"
|
|
bitfld.long 0x00 27. " SCHMITT27 ,Schmitt Trigger 27 Disabled" "No,Yes"
|
|
bitfld.long 0x00 26. " SCHMITT26 ,Schmitt Trigger 26 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SCHMITT25 ,Schmitt Trigger 25 Disabled" "No,Yes"
|
|
bitfld.long 0x00 24. " SCHMITT24 ,Schmitt Trigger 24 Disabled" "No,Yes"
|
|
bitfld.long 0x00 23. " SCHMITT23 ,Schmitt Trigger 23 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCHMITT22 ,Schmitt Trigger 22 Disabled" "No,Yes"
|
|
bitfld.long 0x00 21. " SCHMITT21 ,Schmitt Trigger 21 Disabled" "No,Yes"
|
|
bitfld.long 0x00 20. " SCHMITT20 ,Schmitt Trigger 20 Disabled" "No,Yes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " SCHMITT19 ,Schmitt Trigger 19 Disabled" "No,Yes"
|
|
bitfld.long 0x00 18. " SCHMITT18 ,Schmitt Trigger 18 Disabled" "No,Yes"
|
|
bitfld.long 0x00 17. " SCHMITT17 ,Schmitt Trigger 17 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SCHMITT16 ,Schmitt Trigger 16 Disabled" "No,Yes"
|
|
bitfld.long 0x00 15. " SCHMITT15 ,Schmitt Trigger 15 Disabled" "No,Yes"
|
|
bitfld.long 0x00 14. " SCHMITT14 ,Schmitt Trigger 14 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCHMITT13 ,Schmitt Trigger 13 Disabled" "No,Yes"
|
|
bitfld.long 0x00 12. " SCHMITT12 ,Schmitt Trigger 12 Disabled" "No,Yes"
|
|
bitfld.long 0x00 11. " SCHMITT11 ,Schmitt Trigger 11 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SCHMITT10 ,Schmitt Trigger 10 Disabled" "No,Yes"
|
|
bitfld.long 0x00 9. " SCHMITT9 ,Schmitt Trigger 9 Disabled" "No,Yes"
|
|
bitfld.long 0x00 8. " SCHMITT8 ,Schmitt Trigger 8 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCHMITT7 ,Schmitt Trigger 7 Disabled" "No,Yes"
|
|
bitfld.long 0x00 6. " SCHMITT6 ,Schmitt Trigger 6 Disabled" "No,Yes"
|
|
bitfld.long 0x00 5. " SCHMITT5 ,Schmitt Trigger 5 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SCHMITT4 ,Schmitt Trigger 4 Disabled" "No,Yes"
|
|
bitfld.long 0x00 3. " SCHMITT3 ,Schmitt Trigger 3 Disabled" "No,Yes"
|
|
bitfld.long 0x00 2. " SCHMITT2 ,Schmitt Trigger 2 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCHMITT1 ,Schmitt Trigger 1 Disabled" "No,Yes"
|
|
bitfld.long 0x00 0. " SCHMITT0 ,Schmitt Trigger 0 Disabled" "No,Yes"
|
|
sif !cpuis("ATSAM4N*")
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "PIO_DELAYR,PIO I/O Delay Register"
|
|
bitfld.long 0x00 28.--31. " DELAY7 ,Gives the number of elements in the delay line associated to pad 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " DELAY6 ,Gives the number of elements in the delay line associated to pad 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " DELAY5 ,Gives the number of elements in the delay line associated to pad 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DELAY4 ,Gives the number of elements in the delay line associated to pad 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DELAY3 ,Gives the number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DELAY2 ,Gives the number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DELAY1 ,Gives the number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DELAY0 ,Gives the number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "PIO_PCMR,PIO Parallel Capture Mode Register"
|
|
bitfld.long 0x00 11. " FRSTS ,Parallel Capture Mode First Sample" "Even index,Odd index"
|
|
bitfld.long 0x00 10. " HALFS ,Parallel Capture Mode Half" "All data,One time out of two"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ALWYS ,Parallel Capture Mode Always Sampling" "No,Yes"
|
|
bitfld.long 0x00 4.--5. " DSIZE ,Parallel Capture Mode Data Size" "BYTE,HALF-WORD,WORD,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " PCEN ,Parallel Capture Mode Enable" "Disabled,Enabled"
|
|
rgroup.long 0x15C++0x03
|
|
line.long 0x00 "PIO_PCIMR,PIO Parallel Capture Interrupt Mask Register"
|
|
bitfld.long 0x00 3. " RXBUFF ,Reception Buffer Full Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " ENDRX ,End of Reception Transfer Interrupt Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OVRE ,Parallel Capture Mode Overrun Error Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " DRDY ,Parallel Capture Mode Data Ready Interrupt Mask" "Not masked,Masked"
|
|
group.long 0x160++0x3
|
|
line.long 0x00 "PIO_PCISR,PIO Parallel Capture Interrupt Status Register"
|
|
setclrfld.long 0x00 3. -0x0C 3. -0x08 3. " RXBUFF_set/clr ,Reception Buffer Full Interrupt Status" "Inactive,Active"
|
|
setclrfld.long 0x00 2. -0x0C 2. -0x08 2. " ENDRX_set/clr ,End of Reception Transfer Interrupt Status" "Inactive,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x0C 1. -0x08 1. " OVRE_set/clr ,Parallel Capture Mode Overrun Error Interrupt Status" "No error,Error"
|
|
setclrfld.long 0x00 0. -0x0C 0. -0x08 0. " DRDY_set/clr ,Parallel Capture Mode Data Ready Interrupt Status" "Not ready,Ready"
|
|
if ((d.l(ad:0x400E0E00+0x150)&0x30)==0x00)
|
|
rgroup.long 0x164++0x3
|
|
line.long 0x00 "PIO_PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " RDATA ,Parallel Capture Mode Reception Data"
|
|
elif ((d.l(ad:0x400E0E00+0x150)&0x30)==0x10)
|
|
rgroup.long 0x164++0x3
|
|
line.long 0x00 "PIO_PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " RDATA ,Parallel Capture Mode Reception Data"
|
|
else
|
|
rgroup.long 0xF64++0x3
|
|
line.long 0x00 "PIO_PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
endif
|
|
endif
|
|
width 0xB
|
|
tree "PIOA PDC (Peripheral DMA Controller)"
|
|
base ad:0x400E0E68
|
|
width 10.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "PIOA_RPR,Receive Pointer Register"
|
|
line.long 0x04 "PIOA_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "PIOA_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "PIOA_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "PIOA_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "PIOA_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "PIOA_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "PIOA_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "PIOA_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "PIOA_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "PIO B"
|
|
base ad:0x400E1000
|
|
width 13.
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PIO_PSR,PIO Status Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO Status 12" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO Status 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO Status 12" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO Status 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO Status 9" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO Status 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO Status 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO Status 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO Status 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO Status 0" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PIO_OSR,PIO Output Status Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Status pin 12" "Input,Output"
|
|
else
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Status pin 14" "Input,Output"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Status pin 13" "Input,Output"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Status pin 12" "Input,Output"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Status pin 11" "Input,Output"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Status pin 10" "Input,Output"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Status pin 9" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Status pin 8" "Input,Output"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Status pin 7" "Input,Output"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Status pin 6" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Status pin 5" "Input,Output"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Status pin 4" "Input,Output"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Status pin 3" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Status pin 2" "Input,Output"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Status pin 1" "Input,Output"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Status pin 0" "Input,Output"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PIO_IFSR,PIO Input Filter Status Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Filer Status pin 12" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Filer Status pin 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Filer Status pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Filer Status pin 12" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Filer Status pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Filer Status pin 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Filer Status pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Filer Status pin 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Filer Status pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Filer Status pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Filer Status pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Filer Status pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Filer Status pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Filer Status pin 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Filer Status pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Filer Status pin 0" "Disabled,Enabled"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PIO_ODSR,PIO Output Data Status Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Data Status pin 12" "0,1"
|
|
else
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Data Status pin 14" "0,1"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Data Status pin 13" "0,1"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Data Status pin 12" "0,1"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Data Status pin 11" "0,1"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Data Status pin 10" "0,1"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Data Status pin 9" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Data Status pin 8" "0,1"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Data Status pin 7" "0,1"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Data Status pin 6" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Data Status pin 5" "0,1"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Data Status pin 4" "0,1"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Data Status pin 3" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Data Status pin 2" "0,1"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Data Status pin 1" "0,1"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Data Status pin 0" "0,1"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "PIO_PDSR,PIO Pin Data Status Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
bitfld.long 0x00 12. " P12 ,Output Data Status pin 12" "Level 0,Level 1"
|
|
else
|
|
bitfld.long 0x00 14. " P14 ,Output Data Status pin 14" "Level 0,Level 1"
|
|
bitfld.long 0x00 13. " P13 ,Output Data Status pin 13" "Level 0,Level 1"
|
|
bitfld.long 0x00 12. " P12 ,Output Data Status pin 12" "Level 0,Level 1"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Data Status pin 11" "Level 0,Level 1"
|
|
bitfld.long 0x00 10. " P10 ,Output Data Status pin 10" "Level 0,Level 1"
|
|
bitfld.long 0x00 9. " P9 ,Output Data Status pin 9" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Output Data Status pin 8" "Level 0,Level 1"
|
|
bitfld.long 0x00 7. " P7 ,Output Data Status pin 7" "Level 0,Level 1"
|
|
bitfld.long 0x00 6. " P6 ,Output Data Status pin 6" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Data Status pin 5" "Level 0,Level 1"
|
|
bitfld.long 0x00 4. " P4 ,Output Data Status pin 4" "Level 0,Level 1"
|
|
bitfld.long 0x00 3. " P3 ,Output Data Status pin 3" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Output Data Status pin 2" "Level 0,Level 1"
|
|
bitfld.long 0x00 1. " P1 ,Output Data Status pin 1" "Level 0,Level 1"
|
|
bitfld.long 0x00 0. " P0 ,Output Data Status pin 0" "Level 0,Level 1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PIO_IMR,PIO Interrupt Status Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Change Interrupt Mask pin 12" "No interrupt,Interrupt"
|
|
else
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Change Interrupt Mask pin 14" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Change Interrupt Mask pin 13" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Change Interrupt Mask pin 12" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Change Interrupt Mask pin 11" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Change Interrupt Mask pin 10" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Change Interrupt Mask pin 9" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Change Interrupt Mask pin 8" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Change Interrupt Mask pin 7" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Change Interrupt Mask pin 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Change Interrupt Mask pin 5" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Change Interrupt Mask pin 4" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Change Interrupt Mask pin 3" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Change Interrupt Mask pin 2" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Change Interrupt Mask pin 1" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Change Interrupt Mask pin 0" "No interrupt,Interrupt"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "PIO_ISR,PIO Interrupt Status Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
bitfld.long 0x00 12. " P12 ,Input Change Interrupt Status pin 12" "Not detected,Detected"
|
|
else
|
|
bitfld.long 0x00 14. " P14 ,Input Change Interrupt Status pin 14" "Not detected,Detected"
|
|
bitfld.long 0x00 13. " P13 ,Input Change Interrupt Status pin 13" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " P12 ,Input Change Interrupt Status pin 12" "Not detected,Detected"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Input Change Interrupt Status pin 11" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " P10 ,Input Change Interrupt Status pin 10" "Not detected,Detected"
|
|
bitfld.long 0x00 9. " P9 ,Input Change Interrupt Status pin 9" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Input Change Interrupt Status pin 8" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " P7 ,Input Change Interrupt Status pin 7" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " P6 ,Input Change Interrupt Status pin 6" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Input Change Interrupt Status pin 5" "Not detected,Detected"
|
|
bitfld.long 0x00 4. " P4 ,Input Change Interrupt Status pin 4" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " P3 ,Input Change Interrupt Status pin 3" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Input Change Interrupt Status pin 2" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " P1 ,Input Change Interrupt Status pin 1" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " P0 ,Input Change Interrupt Status pin 0" "Not detected,Detected"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PIO_MDSR,PIO Multi-driver Status Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Multi Drive Status/Drive pin 12" "Low,High"
|
|
else
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Multi Drive Status/Drive pin 14" "Low,High"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Multi Drive Status/Drive pin 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Multi Drive Status/Drive pin 12" "Low,High"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Multi Drive Status/Drive pin 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Multi Drive Status/Drive pin 10" "Low,High"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Multi Drive Status/Drive pin 9" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Multi Drive Status/Drive pin 8" "Low,High"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Multi Drive Status/Drive pin 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Multi Drive Status/Drive pin 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Multi Drive Status/Drive pin 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Multi Drive Status/Drive pin 4" "Low,High"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Multi Drive Status/Drive pin 3" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Multi Drive Status/Drive pin 2" "Low,High"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Multi Drive Status/Drive pin 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Multi Drive Status/Drive pin 0" "Low,High"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PIO_PUSR,PIO Pull Up Status Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Pull Up Status pin 12" "Enabled,Disabled"
|
|
else
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Pull Up Status pin 14" "Enabled,Disabled"
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Pull Up Status pin 13" "Enabled,Disabled"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Pull Up Status pin 12" "Enabled,Disabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Pull Up Status pin 11" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Pull Up Status pin 10" "Enabled,Disabled"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Pull Up Status pin 9" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Pull Up Status pin 8" "Enabled,Disabled"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Pull Up Status pin 7" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Pull Up Status pin 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Pull Up Status pin 5" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Pull Up Status pin 4" "Enabled,Disabled"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Pull Up Status pin 3" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Pull Up Status pin 2" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr ,Pull Up Status pin 1" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Pull Up Status pin 0" "Enabled,Disabled"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "PIO_ABCDSR1,Peripheral Select Register 1"
|
|
sif cpuis("ATSAM4N*")
|
|
sif cpuis("ATSAM4N8A")
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select pin 12 - A/C B/D" "A/C,B/D"
|
|
else
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select pin 14 - A/C B/D" "NPCS1/C,PWM3/D"
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select pin 13 - A/C B/D" "A/C,PCK0/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select pin 12 - A/C B/D" "A/C,B/D"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select pin 11 - A/C B/D" "A/C,UTXD3/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select pin 10 - A/C B/D" "A/C,URXD3/D"
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select pin 9 - A/C B/D" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select pin 8 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select pin 7 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select pin 6 - A/C B/D" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select pin 5 - A/C B/D" "TWCK1/C,B/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select pin 4 - A/C B/D" "TWD1/C,PWM2/D"
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select pin 3 - A/C B/D" "UTXD1/C,PCK2/D"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select pin 2 - A/C B/D" "URXD1/C,NPCS2/D"
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select pin 1 - A/C B/D" "PWM1/C,TWCK2/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select pin 0 - A/C B/D" "PWM0/C,TWD2/D"
|
|
else
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select pin 14 - A/C B/D" "NPCS1/C,PWMH3/D"
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select pin 13 - A/C B/D" "PWML2/SCK0,PCK0/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select pin 12 - A/C B/D" "PWML1/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select pin 11 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select pin 10 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select pin 9 - A/C B/D" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select pin 8 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select pin 7 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select pin 6 - A/C B/D" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select pin 5 - A/C B/D" "TWCK1/C,PWML0/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select pin 4 - A/C B/D" "TWD1/C,PWMH2/D"
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select pin 3 - A/C B/D" "CANRX0/RTS0,PCK2/D"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select pin 2 - A/C B/D" "CANTX0/CTS0,NPCS2/D"
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select pin 1 - A/C B/D" "PWMH1/TXD0,B/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select pin 0 - A/C B/D" "PWMH0/RXD0,B/D"
|
|
endif
|
|
line.long 0x04 "PIO_ABCDSR2,Peripheral Select Register 2"
|
|
sif cpuis("ATSAM4N*")
|
|
sif cpuis("ATSAM4N8A")
|
|
bitfld.long 0x04 12. " P12 ,Peripheral Select pin 12 - A/B C/D" "A/B,C/D"
|
|
else
|
|
bitfld.long 0x04 14. " P14 ,Peripheral Select pin 14 - A/B C/D" "NPCS1/PWMH3,C/D"
|
|
bitfld.long 0x04 13. " P13 ,Peripheral Select pin 13 - A/B C/D" "A/PCK0,PCK0/D"
|
|
bitfld.long 0x04 12. " P12 ,Peripheral Select pin 12 - A/B C/D" "A/B,C/D"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 11. " P11 ,Peripheral Select pin 11 - A/B C/D" "A/UTXD3,C/D"
|
|
bitfld.long 0x04 10. " P10 ,Peripheral Select pin 10 - A/B C/D" "A/URXD3,C/D"
|
|
bitfld.long 0x04 9. " P9 ,Peripheral Select pin 9 - A/B C/D" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 8. " P8 ,Peripheral Select pin 8 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 7. " P7 ,Peripheral Select pin 7 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 6. " P6 ,Peripheral Select pin 6 - A/B C/D" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 5. " P5 ,Peripheral Select pin 5 - A/B C/D" "TWCK1/B,C/D"
|
|
bitfld.long 0x04 4. " P4 ,Peripheral Select pin 4 - A/B C/D" "TWD1/PWM2,C/D"
|
|
bitfld.long 0x04 3. " P3 ,Peripheral Select pin 3 - A/B C/D" "UTXD1/PCK2,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 2. " P2 ,Peripheral Select pin 2 - A/B C/D" "URXD1/NPCS2,C/D"
|
|
bitfld.long 0x04 1. " P1 ,Peripheral Select pin 1 - A/B C/D" "PWM1/TWCK2,C/D"
|
|
bitfld.long 0x04 0. " P0 ,Peripheral Select pin 0 - A/B C/D" "PWM0/TWD2,C/D"
|
|
else
|
|
bitfld.long 0x04 14. " P14 ,Peripheral Select pin 14 - A/B C/D" "NPCS1/PWMH3,C/D"
|
|
bitfld.long 0x04 13. " P13 ,Peripheral Select pin 13 - A/B C/D" "PWML2/PCK0,PCK0/D"
|
|
bitfld.long 0x04 12. " P12 ,Peripheral Select pin 12 - A/B C/D" "PWML1/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 11. " P11 ,Peripheral Select pin 11 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 10. " P10 ,Peripheral Select pin 10 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 9. " P9 ,Peripheral Select pin 9 - A/B C/D" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 8. " P8 ,Peripheral Select pin 8 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 7. " P7 ,Peripheral Select pin 7 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 6. " P6 ,Peripheral Select pin 6 - A/B C/D" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 5. " P5 ,Peripheral Select pin 5 - A/B C/D" "TWCK1/PWML0,C/D"
|
|
bitfld.long 0x04 4. " P4 ,Peripheral Select pin 4 - A/B C/D" "TWD1/PWMH2,C/D"
|
|
bitfld.long 0x04 3. " P3 ,Peripheral Select pin 3 - A/B C/D" "CANRX0/PCK2,RTS0/D"
|
|
textline " "
|
|
bitfld.long 0x04 2. " P2 ,Peripheral Select pin 2 - A/B C/D" "CANTX0/NPCS2,CTS0/D"
|
|
bitfld.long 0x04 1. " P1 ,Peripheral Select pin 1 - A/B C/D" "PWMH1/B,TXD0/D"
|
|
bitfld.long 0x04 0. " P0 ,Peripheral Select pin 0 - A/B C/D" "PWMH0/B,RXD0/D"
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PIO_IFSCSR,PIO Input Filter Slow Clock Status Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status pin 12" "Glitch,Debouncing"
|
|
else
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status pin 14" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status pin 13" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status pin 12" "Glitch,Debouncing"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status pin 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status pin 10" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status pin 9" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status pin 8" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status pin 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status pin 6" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status pin 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status pin 4" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status pin 3" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status pin 2" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr ,Glitch or Debouncing Filter Selection Status pin 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status pin 0" "Glitch,Debouncing"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PIO_SCDR,PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow Clock Divider Selection for Debouncing - Tdiv_slclk = 2*(DIV+1)*Tslow_clock"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PIO_PPDSR,PIO Pad Pull Down Status Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12 ,Pull Down Status pin 12" "Enabled,Disabled"
|
|
else
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14 ,Pull Down Status pin 14" "Enabled,Disabled"
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13 ,Pull Down Status pin 13" "Enabled,Disabled"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12 ,Pull Down Status pin 12" "Enabled,Disabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11 ,Pull Down Status pin 11" "Enabled,Disabled"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10 ,Pull Down Status pin 10" "Enabled,Disabled"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9 ,Pull Down Status pin 9" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8 ,Pull Down Status pin 8" "Enabled,Disabled"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7 ,Pull Down Status pin 7" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6 ,Pull Down Status pin 6" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5 ,Pull Down Status pin 5" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4 ,Pull Down Status pin 4" "Enabled,Disabled"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3 ,Pull Down Status pin 3" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2 ,Pull Down Status pin 2" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1 ,Pull Down Status pin 1" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0 ,Pull Down Status pin 0" "Enabled,Disabled"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PIO_OWSR,PIO Output Write Status Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Write Status pin 12" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Write Status pin 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Write Status pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Write Status pin 12" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Write Status pin 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Write Status pin 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Write Status pin 9" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Write Status pin 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Write Status pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Write Status pin 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Write Status pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Write Status pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Write Status pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Write Status pin 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Write Status pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Write Status pin 0" "Disabled,Enabled"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "PIO_AIMMR,PIO Additional Interrupt Modes Mask Register"
|
|
sif !cpuis("ATSAM4N8A")
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Peripheral CD Status pin 14" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Peripheral CD Status pin 13" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Peripheral CD Status pin 12" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Peripheral CD Status pin 11" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Peripheral CD Status pin 10" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Peripheral CD Status pin 9" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Peripheral CD Status pin 8" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Peripheral CD Status pin 7" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Peripheral CD Status pin 6" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Peripheral CD Status pin 5" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Peripheral CD Status pin 4" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Peripheral CD Status pin 3" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Peripheral CD Status pin 2" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Peripheral CD Status pin 1" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Peripheral CD Status pin 0" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "PIO_ELSR,PIO Edge/Level Status Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection pin 12" "Edge,Level"
|
|
else
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection pin 14" "Edge,Level"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection pin 13" "Edge,Level"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection pin 12" "Edge,Level"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection pin 11" "Edge,Level"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection pin 10" "Edge,Level"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection pin 9" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection pin 8" "Edge,Level"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection pin 7" "Edge,Level"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection pin 6" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection pin 5" "Edge,Level"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection pin 4" "Edge,Level"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection pin 3" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection pin 2" "Edge,Level"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Edge/Level Interrupt source selection pin 1" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection pin 0" "Edge,Level"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "PIO_FRLHSR,PIO Fall/Rise - Low/High Status Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Edge /Level Interrupt Source Selection pin 12" "Falling/Low,Rising/High"
|
|
else
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Edge /Level Interrupt Source Selection pin 14" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Edge /Level Interrupt Source Selection pin 13" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Edge /Level Interrupt Source Selection pin 12" "Falling/Low,Rising/High"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Edge /Level Interrupt Source Selection pin 11" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Edge /Level Interrupt Source Selection pin 10" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Edge /Level Interrupt Source Selection pin 9" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Edge /Level Interrupt Source Selection pin 8" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Edge /Level Interrupt Source Selection pin 7" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Edge /Level Interrupt Source Selection pin 6" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Edge /Level Interrupt Source Selection pin 5" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Edge /Level Interrupt Source Selection pin 4" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Edge /Level Interrupt Source Selection pin 3" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Edge /Level Interrupt Source Selection pin 2" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr ,Edge /Level Interrupt Source Selection pin 1" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Edge /Level Interrupt Source Selection pin 0" "Falling/Low,Rising/High"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "PIO_LOCKSR,PIO Lock Status Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
bitfld.long 0x00 12. " P12 ,Lock Status pin 12" "Not locked,Locked"
|
|
else
|
|
bitfld.long 0x00 14. " P14 ,Lock Status pin 14" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " P13 ,Lock Status pin 13" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " P12 ,Lock Status pin 12" "Not locked,Locked"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Lock Status pin 11" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " P10 ,Lock Status pin 10" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " P9 ,Lock Status pin 9" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " P8 ,Lock Status pin 8" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " P7 ,Lock Status pin 7" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,Lock Status pin 6" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Lock Status pin 5" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " P4 ,Lock Status pin 4" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " P3 ,Lock Status pin 3" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Lock Status pin 2" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " P1 ,Lock Status pin 1" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,Lock Status pin 0" "Not locked,Locked"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in.
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PIO_SCHMITT,PIO Schmitt Trigger Register"
|
|
sif cpuis("ATSAM4N8A")
|
|
bitfld.long 0x00 12. " SCHMITT12 ,Schmitt Trigger pin 12 Disabled" "No,Yes"
|
|
else
|
|
bitfld.long 0x00 14. " SCHMITT14 ,Schmitt Trigger pin 14 Disabled" "No,Yes"
|
|
bitfld.long 0x00 13. " SCHMITT13 ,Schmitt Trigger pin 13 Disabled" "No,Yes"
|
|
bitfld.long 0x00 12. " SCHMITT12 ,Schmitt Trigger pin 12 Disabled" "No,Yes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 11. " SCHMITT11 ,Schmitt Trigger pin 11 Disabled" "No,Yes"
|
|
bitfld.long 0x00 10. " SCHMITT10 ,Schmitt Trigger pin 10 Disabled" "No,Yes"
|
|
bitfld.long 0x00 9. " SCHMITT9 ,Schmitt Trigger pin 9 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SCHMITT8 ,Schmitt Trigger pin 8 Disabled" "No,Yes"
|
|
bitfld.long 0x00 7. " SCHMITT7 ,Schmitt Trigger pin 7 Disabled" "No,Yes"
|
|
bitfld.long 0x00 6. " SCHMITT6 ,Schmitt Trigger pin 6 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCHMITT5 ,Schmitt Trigger pin 5 Disabled" "No,Yes"
|
|
bitfld.long 0x00 4. " SCHMITT4 ,Schmitt Trigger pin 4 Disabled" "No,Yes"
|
|
bitfld.long 0x00 3. " SCHMITT3 ,Schmitt Trigger pin 3 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SCHMITT2 ,Schmitt Trigger pin 2 Disabled" "No,Yes"
|
|
bitfld.long 0x00 1. " SCHMITT1 ,Schmitt Trigger pin 1 Disabled" "No,Yes"
|
|
bitfld.long 0x00 0. " SCHMITT0 ,Schmitt Trigger pin 0 Disabled" "No,Yes"
|
|
sif !cpuis("ATSAM4N*")
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "PIO_DELAYR,PIO I/O Delay Register"
|
|
bitfld.long 0x00 28.--31. " DELAY7 ,Gives the number of elements in the delay line associated to pad 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " DELAY6 ,Gives the number of elements in the delay line associated to pad 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " DELAY5 ,Gives the number of elements in the delay line associated to pad 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DELAY4 ,Gives the number of elements in the delay line associated to pad 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DELAY3 ,Gives the number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DELAY2 ,Gives the number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DELAY1 ,Gives the number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DELAY0 ,Gives the number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "PIO_PCMR,PIO Parallel Capture Mode Register"
|
|
bitfld.long 0x00 11. " FRSTS ,Parallel Capture Mode First Sample" "Even index,Odd index"
|
|
bitfld.long 0x00 10. " HALFS ,Parallel Capture Mode Half" "All data,One time out of two"
|
|
bitfld.long 0x00 9. " ALWYS ,Parallel Capture Mode Always Sampling" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " DSIZE ,Parallel Capture Mode Data Size" "BYTE,HALF-WORD,WORD,?..."
|
|
bitfld.long 0x00 0. " PCEN ,Parallel Capture Mode Enable" "Disabled,Enabled"
|
|
rgroup.long 0x15C++0x03
|
|
line.long 0x00 "PIO_PCIMR,PIO Parallel Capture Interrupt Mask Register"
|
|
bitfld.long 0x00 3. " RXBUFF ,Reception Buffer Full Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " ENDRX ,End of Reception Transfer Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " OVRE ,Parallel Capture Mode Overrun Error Interrupt Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DRDY ,Parallel Capture Mode Data Ready Interrupt Mask" "Not masked,Masked"
|
|
group.long 0x160++0x3
|
|
line.long 0x00 "PIO_PCISR,PIO Parallel Capture Interrupt Status Register"
|
|
setclrfld.long 0x00 3. -0x0C 3. -0x08 3. " RXBUFF_set/clr ,Reception Buffer Full Interrupt Status" "Inactive,Active"
|
|
setclrfld.long 0x00 2. -0x0C 2. -0x08 2. " ENDRX_set/clr ,End of Reception Transfer Interrupt Status" "Inactive,Active"
|
|
setclrfld.long 0x00 1. -0x0C 1. -0x08 1. " OVRE_set/clr ,Parallel Capture Mode Overrun Error Interrupt Status" "No error,Error"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x0C 0. -0x08 0. " DRDY_set/clr ,Parallel Capture Mode Data Ready Interrupt Status" "Not ready,Ready"
|
|
if ((d.l(ad:0x400E1000+0x150)&0x30)==0x00)
|
|
rgroup.long 0x164++0x3
|
|
line.long 0x00 "PIO_PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.byte 0x00 0.--8. 1. " RDATA ,Parallel Capture Mode Reception Data"
|
|
elif ((d.l(ad:0x400E1000+0x150)&0x30)==0x10)
|
|
rgroup.long 0x164++0x3
|
|
line.long 0x00 "PIO_PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.word 0x00 0.--16. 1. " RDATA ,Parallel Capture Mode Reception Data"
|
|
else
|
|
rgroup.long 0xF64++0x3
|
|
line.long 0x00 "PIO_PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
endif
|
|
endif
|
|
width 0xB
|
|
tree "PIOB PDC (Peripheral DMA Controller)"
|
|
base ad:0x400E1068
|
|
width 10.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "PIOB_RPR,Receive Pointer Register"
|
|
line.long 0x04 "PIOB_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "PIOB_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "PIOB_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "PIOB_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "PIOB_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "PIOB_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "PIOB_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "PIOB_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "PIOB_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "PIO C"
|
|
base ad:0x400E1200
|
|
width 13.
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PIO_PSR,PIO Status Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,PIO Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,PIO Status 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,PIO Status 29" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,PIO Status 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,PIO Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,PIO Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,PIO Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,PIO Status 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,PIO Status 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,PIO Status 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,PIO Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO Status 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO Status 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO Status 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO Status 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO Status 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO Status 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO Status 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO Status 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO Status 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO Status 0" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PIO_OSR,PIO Output Status Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Status pin 31" "Input,Output"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Status pin 30" "Input,Output"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Status pin 29" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Status pin 28" "Input,Output"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Status pin 27" "Input,Output"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Status pin 26" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Status pin 25" "Input,Output"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Status pin 24" "Input,Output"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Status pin 23" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Status pin 22" "Input,Output"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Status pin 21" "Input,Output"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Status pin 20" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Status pin 19" "Input,Output"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Status pin 18" "Input,Output"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Status pin 17" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Status pin 16" "Input,Output"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Status pin 15" "Input,Output"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Status pin 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Status pin 13" "Input,Output"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Status pin 12" "Input,Output"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Status pin 11" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Status pin 10" "Input,Output"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Status pin 9" "Input,Output"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Status pin 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Status pin 7" "Input,Output"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Status pin 6" "Input,Output"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Status pin 5" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Status pin 4" "Input,Output"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Status pin 3" "Input,Output"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Status pin 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Status pin 1" "Input,Output"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Status pin 0" "Input,Output"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PIO_IFSR,PIO Input Filter Status Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Input Filer Status pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Input Filer Status pin 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Input Filer Status pin 29" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Input Filer Status pin 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Input Filer Status pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Input Filer Status pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Input Filer Status pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Input Filer Status pin 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Input Filer Status pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Input Filer Status pin 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Input Filer Status pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Input Filer Status pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Input Filer Status pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Input Filer Status pin 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Input Filer Status pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Input Filer Status pin 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Input Filer Status pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Filer Status pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Filer Status pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Filer Status pin 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Filer Status pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Filer Status pin 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Filer Status pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Filer Status pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Filer Status pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Filer Status pin 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Filer Status pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Filer Status pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Filer Status pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Filer Status pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Filer Status pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Filer Status pin 0" "Disabled,Enabled"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PIO_ODSR,PIO Output Data Status Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Data Status pin 31" "0,1"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Data Status pin 30" "0,1"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Data Status pin 29" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Data Status pin 28" "0,1"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Data Status pin 27" "0,1"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Data Status pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Data Status pin 25" "0,1"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Data Status pin 24" "0,1"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Data Status pin 23" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Data Status pin 22" "0,1"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Data Status pin 21" "0,1"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Data Status pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Data Status pin 19" "0,1"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Data Status pin 18" "0,1"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Data Status pin 17" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Data Status pin 16" "0,1"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Data Status pin 15" "0,1"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Data Status pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Data Status pin 13" "0,1"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Data Status pin 12" "0,1"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Data Status pin 11" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Data Status pin 10" "0,1"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Data Status pin 9" "0,1"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Data Status pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Data Status pin 7" "0,1"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Data Status pin 6" "0,1"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Data Status pin 5" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Data Status pin 4" "0,1"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Data Status pin 3" "0,1"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Data Status pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Data Status pin 1" "0,1"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Data Status pin 0" "0,1"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "PIO_PDSR,PIO Pin Data Status Register"
|
|
bitfld.long 0x00 31. " P31 ,Output Data Status pin 31" "Level 0,Level 1"
|
|
bitfld.long 0x00 30. " P30 ,Output Data Status pin 30" "Level 0,Level 1"
|
|
bitfld.long 0x00 29. " P29 ,Output Data Status pin 29" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " P28 ,Output Data Status pin 28" "Level 0,Level 1"
|
|
bitfld.long 0x00 27. " P27 ,Output Data Status pin 27" "Level 0,Level 1"
|
|
bitfld.long 0x00 26. " P26 ,Output Data Status pin 26" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Data Status pin 25" "Level 0,Level 1"
|
|
bitfld.long 0x00 24. " P24 ,Output Data Status pin 24" "Level 0,Level 1"
|
|
bitfld.long 0x00 23. " P23 ,Output Data Status pin 23" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Output Data Status pin 22" "Level 0,Level 1"
|
|
bitfld.long 0x00 21. " P21 ,Output Data Status pin 21" "Level 0,Level 1"
|
|
bitfld.long 0x00 20. " P20 ,Output Data Status pin 20" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Data Status pin 19" "Level 0,Level 1"
|
|
bitfld.long 0x00 18. " P18 ,Output Data Status pin 18" "Level 0,Level 1"
|
|
bitfld.long 0x00 17. " P17 ,Output Data Status pin 17" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Output Data Status pin 16" "Level 0,Level 1"
|
|
bitfld.long 0x00 15. " P15 ,Output Data Status pin 15" "Level 0,Level 1"
|
|
bitfld.long 0x00 14. " P14 ,Output Data Status pin 14" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Data Status pin 13" "Level 0,Level 1"
|
|
bitfld.long 0x00 12. " P12 ,Output Data Status pin 12" "Level 0,Level 1"
|
|
bitfld.long 0x00 11. " P11 ,Output Data Status pin 11" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Output Data Status pin 10" "Level 0,Level 1"
|
|
bitfld.long 0x00 9. " P9 ,Output Data Status pin 9" "Level 0,Level 1"
|
|
bitfld.long 0x00 8. " P8 ,Output Data Status pin 8" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Data Status pin 7" "Level 0,Level 1"
|
|
bitfld.long 0x00 6. " P6 ,Output Data Status pin 6" "Level 0,Level 1"
|
|
bitfld.long 0x00 5. " P5 ,Output Data Status pin 5" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Output Data Status pin 4" "Level 0,Level 1"
|
|
bitfld.long 0x00 3. " P3 ,Output Data Status pin 3" "Level 0,Level 1"
|
|
bitfld.long 0x00 2. " P2 ,Output Data Status pin 2" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Data Status pin 1" "Level 0,Level 1"
|
|
bitfld.long 0x00 0. " P0 ,Output Data Status pin 0" "Level 0,Level 1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PIO_IMR,PIO Interrupt Status Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Input Change Interrupt Mask pin 31" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Input Change Interrupt Mask pin 30" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Input Change Interrupt Mask pin 29" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Input Change Interrupt Mask pin 28" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Input Change Interrupt Mask pin 27" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Input Change Interrupt Mask pin 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Input Change Interrupt Mask pin 25" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Input Change Interrupt Mask pin 24" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Input Change Interrupt Mask pin 23" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Input Change Interrupt Mask pin 22" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Input Change Interrupt Mask pin 21" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Input Change Interrupt Mask pin 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Input Change Interrupt Mask pin 19" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Input Change Interrupt Mask pin 18" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Input Change Interrupt Mask pin 17" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Input Change Interrupt Mask pin 16" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Input Change Interrupt Mask pin 15" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Change Interrupt Mask pin 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Change Interrupt Mask pin 13" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Change Interrupt Mask pin 12" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Change Interrupt Mask pin 11" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Change Interrupt Mask pin 10" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Change Interrupt Mask pin 9" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Change Interrupt Mask pin 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Change Interrupt Mask pin 7" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Change Interrupt Mask pin 6" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Change Interrupt Mask pin 5" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Change Interrupt Mask pin 4" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Change Interrupt Mask pin 3" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Change Interrupt Mask pin 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Change Interrupt Mask pin 1" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Change Interrupt Mask pin 0" "No interrupt,Interrupt"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "PIO_ISR,PIO Interrupt Status Register"
|
|
bitfld.long 0x00 31. " P31 ,Input Change Interrupt Status pin 31" "Not detected,Detected"
|
|
bitfld.long 0x00 30. " P30 ,Input Change Interrupt Status pin 30" "Not detected,Detected"
|
|
bitfld.long 0x00 29. " P29 ,Input Change Interrupt Status pin 29" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 28. " P28 ,Input Change Interrupt Status pin 28" "Not detected,Detected"
|
|
bitfld.long 0x00 27. " P27 ,Input Change Interrupt Status pin 27" "Not detected,Detected"
|
|
bitfld.long 0x00 26. " P26 ,Input Change Interrupt Status pin 26" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Input Change Interrupt Status pin 25" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " P24 ,Input Change Interrupt Status pin 24" "Not detected,Detected"
|
|
bitfld.long 0x00 23. " P23 ,Input Change Interrupt Status pin 23" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Input Change Interrupt Status pin 22" "Not detected,Detected"
|
|
bitfld.long 0x00 21. " P21 ,Input Change Interrupt Status pin 21" "Not detected,Detected"
|
|
bitfld.long 0x00 20. " P20 ,Input Change Interrupt Status pin 20" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Input Change Interrupt Status pin 19" "Not detected,Detected"
|
|
bitfld.long 0x00 18. " P18 ,Input Change Interrupt Status pin 18" "Not detected,Detected"
|
|
bitfld.long 0x00 17. " P17 ,Input Change Interrupt Status pin 17" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Input Change Interrupt Status pin 16" "Not detected,Detected"
|
|
bitfld.long 0x00 15. " P15 ,Input Change Interrupt Status pin 15" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " P14 ,Input Change Interrupt Status pin 14" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Input Change Interrupt Status pin 13" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " P12 ,Input Change Interrupt Status pin 12" "Not detected,Detected"
|
|
bitfld.long 0x00 11. " P11 ,Input Change Interrupt Status pin 11" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Input Change Interrupt Status pin 10" "Not detected,Detected"
|
|
bitfld.long 0x00 9. " P9 ,Input Change Interrupt Status pin 9" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " P8 ,Input Change Interrupt Status pin 8" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Input Change Interrupt Status pin 7" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " P6 ,Input Change Interrupt Status pin 6" "Not detected,Detected"
|
|
bitfld.long 0x00 5. " P5 ,Input Change Interrupt Status pin 5" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Input Change Interrupt Status pin 4" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " P3 ,Input Change Interrupt Status pin 3" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " P2 ,Input Change Interrupt Status pin 2" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Input Change Interrupt Status pin 1" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " P0 ,Input Change Interrupt Status pin 0" "Not detected,Detected"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PIO_MDSR,PIO Multi-driver Status Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Multi Drive Status/Drive pin 31" "Low,High"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Multi Drive Status/Drive pin 30" "Low,High"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Multi Drive Status/Drive pin 29" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Multi Drive Status/Drive pin 28" "Low,High"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Multi Drive Status/Drive pin 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Multi Drive Status/Drive pin 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Multi Drive Status/Drive pin 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Multi Drive Status/Drive pin 24" "Low,High"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Multi Drive Status/Drive pin 23" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Multi Drive Status/Drive pin 22" "Low,High"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Multi Drive Status/Drive pin 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Multi Drive Status/Drive pin 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Multi Drive Status/Drive pin 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Multi Drive Status/Drive pin 18" "Low,High"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Multi Drive Status/Drive pin 17" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Multi Drive Status/Drive pin 16" "Low,High"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Multi Drive Status/Drive pin 15" "Low,High"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Multi Drive Status/Drive pin 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Multi Drive Status/Drive pin 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Multi Drive Status/Drive pin 12" "Low,High"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Multi Drive Status/Drive pin 11" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Multi Drive Status/Drive pin 10" "Low,High"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Multi Drive Status/Drive pin 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Multi Drive Status/Drive pin 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Multi Drive Status/Drive pin 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Multi Drive Status/Drive pin 6" "Low,High"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Multi Drive Status/Drive pin 5" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Multi Drive Status/Drive pin 4" "Low,High"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Multi Drive Status/Drive pin 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Multi Drive Status/Drive pin 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Multi Drive Status/Drive pin 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Multi Drive Status/Drive pin 0" "Low,High"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PIO_PUSR,PIO Pull Up Status Register"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31_set/clr ,Pull Up Status pin 31" "Enabled,Disabled"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30_set/clr ,Pull Up Status pin 30" "Enabled,Disabled"
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29_set/clr ,Pull Up Status pin 29" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28_set/clr ,Pull Up Status pin 28" "Enabled,Disabled"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27_set/clr ,Pull Up Status pin 27" "Enabled,Disabled"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26_set/clr ,Pull Up Status pin 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25_set/clr ,Pull Up Status pin 25" "Enabled,Disabled"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24_set/clr ,Pull Up Status pin 24" "Enabled,Disabled"
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_set/clr ,Pull Up Status pin 23" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_set/clr ,Pull Up Status pin 22" "Enabled,Disabled"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_set/clr ,Pull Up Status pin 21" "Enabled,Disabled"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Pull Up Status pin 20" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_set/clr ,Pull Up Status pin 19" "Enabled,Disabled"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_set/clr ,Pull Up Status pin 18" "Enabled,Disabled"
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_set/clr ,Pull Up Status pin 17" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_set/clr ,Pull Up Status pin 16" "Enabled,Disabled"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Pull Up Status pin 15" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Pull Up Status pin 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Pull Up Status pin 13" "Enabled,Disabled"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Pull Up Status pin 12" "Enabled,Disabled"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Pull Up Status pin 11" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Pull Up Status pin 10" "Enabled,Disabled"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Pull Up Status pin 9" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Pull Up Status pin 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Pull Up Status pin 7" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Pull Up Status pin 6" "Enabled,Disabled"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Pull Up Status pin 5" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Pull Up Status pin 4" "Enabled,Disabled"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Pull Up Status pin 3" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Pull Up Status pin 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr ,Pull Up Status pin 1" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Pull Up Status pin 0" "Enabled,Disabled"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "PIO_ABCDSR1,Peripheral Select Register 1"
|
|
sif cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Select pin 31 - A/C B/D" "A/C,TCLK5/D"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Select pin 30 - A/C B/D" "A/C,TIOB5/D"
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Select pin 29 - A/C B/D" "A/C,TIOA5/D"
|
|
textline " "
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Select pin 28 - A/C B/D" "A/C,TCLK4/D"
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Select pin 27 - A/C B/D" "A/C,TIOB4/D"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Select pin 26 - A/C B/D" "A/C,TIOA4/D"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Select pin 25 - A/C B/D" "A/C,TCLK3/D"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Select pin 24 - A/C B/D" "A/C,TIOB3/D"
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Select pin 23 - A/C B/D" "A/C,TIOA3/D"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Select pin 22 - A/C B/D" "A/C,PWM0/D"
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Select pin 21 - A/C B/D" "A/C,PWM3/D"
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Select pin 20 - A/C B/D" "A/C,PWM2/D"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Select pin 19 - A/C B/D" "A/C,PWM1/D"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Select pin 18 - A/C B/D" "A/C,PWM0/D"
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Select pin 17 - A/C B/D" "CTS2/C,PCK1/D"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Select pin 16 - A/C B/D" "RTS2/C,PCK0/D"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select pin 15 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select pin 14 - A/C B/D" "SCK2/C,PCK2/D"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select pin 13 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select pin 12 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select pin 11 - A/C B/D" "A/C,PWM3/D"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select pin 10 - A/C B/D" "TXD2/C,PWM2/D"
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select pin 9 - A/C B/D" "RXD2/C,PWM1/D"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select pin 8 - A/C B/D" "A/C,PWM0/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select pin 7 - A/C B/D" "A/C,NPCS2/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select pin 6 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select pin 5 - A/C B/D" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select pin 4 - A/C B/D" "A/C,NPCS1/D"
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select pin 3 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select pin 2 - A/C B/D" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select pin 1 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select pin 0 - A/C B/D" "A/C,B/D"
|
|
else
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Select pin 31 - A/C B/D" "A13/C,TCLK5/D"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Select pin 30 - A/C B/D" "A12/C,TIOB5/D"
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Select pin 29 - A/C B/D" "A11/C,TIOA5/D"
|
|
textline " "
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Select pin 28 - A/C B/D" "A10/C,TCLK4/D"
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Select pin 27 - A/C B/D" "A9/C,TIOB4/D"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Select pin 26 - A/C B/D" "A8/C,TIOA4/D"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Select pin 25 - A/C B/D" "A7/C,TCLK3/D"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Select pin 24 - A/C B/D" "A6/C,TIOB3/D"
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Select pin 23 - A/C B/D" "A5/C,TIOA3/D"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Select pin 22 - A/C B/D" "A4/C,PWML3/D"
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Select pin 21 - A/C B/D" "A3/C,PWMH3/D"
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Select pin 20 - A/C B/D" "A2/C,PWMH2/D"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Select pin 19 - A/C B/D" "A1/C,PWMH1/D"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Select pin 18 - A/C B/D" "A0/C,PWMH0/D"
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Select pin 17 - A/C B/D" "A21|NANDALE/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Select pin 16 - A/C B/D" "A21|NANDALE/C,B/D"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select pin 15 - A/C B/D" "NCS1/CANTX1,PWML1/D"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select pin 14 - A/C B/D" "NCS0/C,TCLK8/D"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select pin 13 - A/C B/D" "NWAIT/C,PWML0/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select pin 12 - A/C B/D" "NCS3/CANRX1,TIOB8/D"
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select pin 11 - A/C B/D" "NRD/C,TIOA8/D"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select pin 10 - A/C B/D" "NANDWE/C,TCLK7/D"
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select pin 9 - A/C B/D" "NANDOE/C,TIOB7/D"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select pin 8 - A/C B/D" "NWE/C,TIOA7/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select pin 7 - A/C B/D" "D7/C,TCLK6/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select pin 6 - A/C B/D" "D6/C,TIOB6/D"
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select pin 5 - A/C B/D" "D5/C,TIOA6/D"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select pin 4 - A/C B/D" "D4/C,NPCS1/D"
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select pin 3 - A/C B/D" "D3/C,PWML3/D"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select pin 2 - A/C B/D" "D2/C,PWML2/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select pin 1 - A/C B/D" "D1/C,PWML1/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select pin 0 - A/C B/D" "D0/C,PWML0/D"
|
|
endif
|
|
line.long 0x04 "PIO_ABCDSR2,Peripheral Select Register 2"
|
|
sif cpuis("ATSAM4N*")
|
|
bitfld.long 0x04 31. " P31 ,Peripheral Select pin 31 - A/B C/D" "A/TCLK5,C/D"
|
|
bitfld.long 0x04 30. " P30 ,Peripheral Select pin 30 - A/B C/D" "A/TIOB5,C/D"
|
|
bitfld.long 0x04 29. " P29 ,Peripheral Select pin 29 - A/B C/D" "A/TIOA5,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 28. " P28 ,Peripheral Select pin 28 - A/B C/D" "A/TCLK4,C/D"
|
|
bitfld.long 0x04 27. " P27 ,Peripheral Select pin 27 - A/B C/D" "A/TIOB4,C/D"
|
|
bitfld.long 0x04 26. " P26 ,Peripheral Select pin 26 - A/B C/D" "A/TIOA4,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 25. " P25 ,Peripheral Select pin 25 - A/B C/D" "A/TCLK3,C/D"
|
|
bitfld.long 0x04 24. " P24 ,Peripheral Select pin 24 - A/B C/D" "A/TIOB3,C/D"
|
|
bitfld.long 0x04 23. " P23 ,Peripheral Select pin 23 - A/B C/D" "A/TIOA3,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 22. " P22 ,Peripheral Select pin 22 - A/B C/D" "A/PWM0,C/D"
|
|
bitfld.long 0x04 21. " P21 ,Peripheral Select pin 21 - A/B C/D" "A/PWM3,C/D"
|
|
bitfld.long 0x04 20. " P20 ,Peripheral Select pin 20 - A/B C/D" "A/PWM2,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 19. " P19 ,Peripheral Select pin 19 - A/B C/D" "A/PWM1,C/D"
|
|
bitfld.long 0x04 18. " P18 ,Peripheral Select pin 18 - A/B C/D" "A/PWM0,C/D"
|
|
bitfld.long 0x04 17. " P17 ,Peripheral Select pin 17 - A/B C/D" "CTS2/PCK1,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 16. " P16 ,Peripheral Select pin 16 - A/B C/D" "RTS2/PCK0,C/D"
|
|
bitfld.long 0x04 15. " P15 ,Peripheral Select pin 15 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 14. " P14 ,Peripheral Select pin 14 - A/B C/D" "SCK2/PCK2,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 13. " P13 ,Peripheral Select pin 13 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 12. " P12 ,Peripheral Select pin 12 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 11. " P11 ,Peripheral Select pin 11 - A/B C/D" "A/PWM3,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 10. " P10 ,Peripheral Select pin 10 - A/B C/D" "TXD2/PWM2,C/D"
|
|
bitfld.long 0x04 9. " P9 ,Peripheral Select pin 9 - A/B C/D" "RXD2/PWM1,C/D"
|
|
bitfld.long 0x04 8. " P8 ,Peripheral Select pin 8 - A/B C/D" "A/PWM0,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 7. " P7 ,Peripheral Select pin 7 - A/B C/D" "A/NPCS2,C/D"
|
|
bitfld.long 0x04 6. " P6 ,Peripheral Select pin 6 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 5. " P5 ,Peripheral Select pin 5 - A/B C/D" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 4. " P4 ,Peripheral Select pin 4 - A/B C/D" "A/NPCS1,C/D"
|
|
bitfld.long 0x04 3. " P3 ,Peripheral Select pin 3 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 2. " P2 ,Peripheral Select pin 2 - A/B C/D" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 1. " P1 ,Peripheral Select pin 1 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 0. " P0 ,Peripheral Select pin 0 - A/B C/D" "A/B,C/D"
|
|
else
|
|
bitfld.long 0x04 31. " P31 ,Peripheral Select pin 31 - A/B C/D" "A13/TCLK5,C/D"
|
|
bitfld.long 0x04 30. " P30 ,Peripheral Select pin 30 - A/B C/D" "A12/TIOB5,C/D"
|
|
bitfld.long 0x04 29. " P29 ,Peripheral Select pin 29 - A/B C/D" "A11/TIOA5,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 28. " P28 ,Peripheral Select pin 28 - A/B C/D" "A10/TCLK4,C/D"
|
|
bitfld.long 0x04 27. " P27 ,Peripheral Select pin 27 - A/B C/D" "A9/TIOB4,C/D"
|
|
bitfld.long 0x04 26. " P26 ,Peripheral Select pin 26 - A/B C/D" "A8/TIOA4,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 25. " P25 ,Peripheral Select pin 25 - A/B C/D" "A7/TCLK3,C/D"
|
|
bitfld.long 0x04 24. " P24 ,Peripheral Select pin 24 - A/B C/D" "A6/TIOB3,C/D"
|
|
bitfld.long 0x04 23. " P23 ,Peripheral Select pin 23 - A/B C/D" "A5/TIOA3,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 22. " P22 ,Peripheral Select pin 22 - A/B C/D" "A4/PWML3,C/D"
|
|
bitfld.long 0x04 21. " P21 ,Peripheral Select pin 21 - A/B C/D" "A3/PWMH3,C/D"
|
|
bitfld.long 0x04 20. " P20 ,Peripheral Select pin 20 - A/B C/D" "A2/PWMH2,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 19. " P19 ,Peripheral Select pin 19 - A/B C/D" "A1/PWMH1,C/D"
|
|
bitfld.long 0x04 18. " P18 ,Peripheral Select pin 18 - A/B C/D" "A0/PWMH0,C/D"
|
|
bitfld.long 0x04 17. " P17 ,Peripheral Select pin 17 - A/B C/D" "A22|NANDCLE/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 16. " P16 ,Peripheral Select pin 16 - A/B C/D" "A21|NANDALE/B,C/D"
|
|
bitfld.long 0x04 15. " P15 ,Peripheral Select pin 15 - A/B C/D" "NCS1/PWML1,CANTX1/D"
|
|
bitfld.long 0x04 14. " P14 ,Peripheral Select pin 14 - A/B C/D" "NCS0/TCLK8,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 13. " P13 ,Peripheral Select pin 13 - A/B C/D" "NWAIT/PWML0,C/D"
|
|
bitfld.long 0x04 12. " P12 ,Peripheral Select pin 12 - A/B C/D" "NCS3/TIOB8,CANRX1/D"
|
|
bitfld.long 0x04 11. " P11 ,Peripheral Select pin 11 - A/B C/D" "NRD/TIOA8,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 10. " P10 ,Peripheral Select pin 10 - A/B C/D" "NANDWE/TCLK7,C/D"
|
|
bitfld.long 0x04 9. " P9 ,Peripheral Select pin 9 - A/B C/D" "NANDOE/TIOB7,C/D"
|
|
bitfld.long 0x04 8. " P8 ,Peripheral Select pin 8 - A/B C/D" "NWE/TIOA7,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 7. " P7 ,Peripheral Select pin 7 - A/B C/D" "D7/TCLK6,C/D"
|
|
bitfld.long 0x04 6. " P6 ,Peripheral Select pin 6 - A/B C/D" "D6/TIOB6,C/D"
|
|
bitfld.long 0x04 5. " P5 ,Peripheral Select pin 5 - A/B C/D" "D5/TIOA6,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 4. " P4 ,Peripheral Select pin 4 - A/B C/D" "D4/NPCS1,C/D"
|
|
bitfld.long 0x04 3. " P3 ,Peripheral Select pin 3 - A/B C/D" "D3/PWML3,C/D"
|
|
bitfld.long 0x04 2. " P2 ,Peripheral Select pin 2 - A/B C/D" "D2/PWML2,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 1. " P1 ,Peripheral Select pin 1 - A/B C/D" "D1/PWML1,C/D"
|
|
bitfld.long 0x04 0. " P0 ,Peripheral Select pin 0 - A/B C/D" "D0/PWML0,C/D"
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PIO_IFSCSR,PIO Input Filter Slow Clock Status Register"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31_set/clr ,Glitch or Debouncing Filter Selection Status pin 31" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30_set/clr ,Glitch or Debouncing Filter Selection Status pin 30" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29_set/clr ,Glitch or Debouncing Filter Selection Status pin 29" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28_set/clr ,Glitch or Debouncing Filter Selection Status pin 28" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27_set/clr ,Glitch or Debouncing Filter Selection Status pin 27" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26_set/clr ,Glitch or Debouncing Filter Selection Status pin 26" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25_set/clr ,Glitch or Debouncing Filter Selection Status pin 25" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24_set/clr ,Glitch or Debouncing Filter Selection Status pin 24" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_set/clr ,Glitch or Debouncing Filter Selection Status pin 23" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_set/clr ,Glitch or Debouncing Filter Selection Status pin 22" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_set/clr ,Glitch or Debouncing Filter Selection Status pin 21" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Glitch or Debouncing Filter Selection Status pin 20" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_set/clr ,Glitch or Debouncing Filter Selection Status pin 19" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_set/clr ,Glitch or Debouncing Filter Selection Status pin 18" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_set/clr ,Glitch or Debouncing Filter Selection Status pin 17" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_set/clr ,Glitch or Debouncing Filter Selection Status pin 16" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Glitch or Debouncing Filter Selection Status pin 15" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status pin 14" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status pin 13" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status pin 12" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status pin 11" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status pin 10" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status pin 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status pin 8" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status pin 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status pin 6" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status pin 5" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status pin 4" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status pin 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status pin 2" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr ,Glitch or Debouncing Filter Selection Status pin 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status pin 0" "Glitch,Debouncing"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PIO_SCDR,PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow Clock Divider Selection for Debouncing - Tdiv_slclk = 2*(DIV+1)*Tslow_clock"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PIO_PPDSR,PIO Pad Pull Down Status Register"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31 ,Pull Down Status pin 31" "Enabled,Disabled"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30 ,Pull Down Status pin 30" "Enabled,Disabled"
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29 ,Pull Down Status pin 29" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28 ,Pull Down Status pin 28" "Enabled,Disabled"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27 ,Pull Down Status pin 27" "Enabled,Disabled"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26 ,Pull Down Status pin 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25 ,Pull Down Status pin 25" "Enabled,Disabled"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24 ,Pull Down Status pin 24" "Enabled,Disabled"
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23 ,Pull Down Status pin 23" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22 ,Pull Down Status pin 22" "Enabled,Disabled"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21 ,Pull Down Status pin 21" "Enabled,Disabled"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20 ,Pull Down Status pin 20" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19 ,Pull Down Status pin 19" "Enabled,Disabled"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18 ,Pull Down Status pin 18" "Enabled,Disabled"
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17 ,Pull Down Status pin 17" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16 ,Pull Down Status pin 16" "Enabled,Disabled"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15 ,Pull Down Status pin 15" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14 ,Pull Down Status pin 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13 ,Pull Down Status pin 13" "Enabled,Disabled"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12 ,Pull Down Status pin 12" "Enabled,Disabled"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11 ,Pull Down Status pin 11" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10 ,Pull Down Status pin 10" "Enabled,Disabled"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9 ,Pull Down Status pin 9" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8 ,Pull Down Status pin 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7 ,Pull Down Status pin 7" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6 ,Pull Down Status pin 6" "Enabled,Disabled"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5 ,Pull Down Status pin 5" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4 ,Pull Down Status pin 4" "Enabled,Disabled"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3 ,Pull Down Status pin 3" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2 ,Pull Down Status pin 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1 ,Pull Down Status pin 1" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0 ,Pull Down Status pin 0" "Enabled,Disabled"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PIO_OWSR,PIO Output Write Status Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Write Status pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Write Status pin 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Write Status pin 29" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Write Status pin 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Write Status pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Write Status pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Write Status pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Write Status pin 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Write Status pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Write Status pin 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Write Status pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Write Status pin 20" "Disabled,Enabled"
|
|
textline " "
|
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setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Write Status pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Write Status pin 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Write Status pin 17" "Disabled,Enabled"
|
|
textline " "
|
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setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Write Status pin 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Write Status pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Write Status pin 14" "Disabled,Enabled"
|
|
textline " "
|
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setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Write Status pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Write Status pin 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Write Status pin 11" "Disabled,Enabled"
|
|
textline " "
|
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setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Write Status pin 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Write Status pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Write Status pin 8" "Disabled,Enabled"
|
|
textline " "
|
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setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Write Status pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Write Status pin 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Write Status pin 5" "Disabled,Enabled"
|
|
textline " "
|
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setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Write Status pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Write Status pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Write Status pin 2" "Disabled,Enabled"
|
|
textline " "
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setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Write Status pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Write Status pin 0" "Disabled,Enabled"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "PIO_AIMMR,PIO Additional Interrupt Modes Mask Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Peripheral CD Status pin 31" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
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setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Peripheral CD Status pin 30" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Peripheral CD Status pin 29" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
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setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Peripheral CD Status pin 28" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Peripheral CD Status pin 27" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
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setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Peripheral CD Status pin 26" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Peripheral CD Status pin 25" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
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setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Peripheral CD Status pin 24" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Peripheral CD Status pin 23" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
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setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Peripheral CD Status pin 22" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
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textline " "
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setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Peripheral CD Status pin 21" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
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setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Peripheral CD Status pin 20" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
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textline " "
|
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setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Peripheral CD Status pin 19" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
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setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Peripheral CD Status pin 18" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Peripheral CD Status pin 17" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
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setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Peripheral CD Status pin 16" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
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textline " "
|
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setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Peripheral CD Status pin 15" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
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setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Peripheral CD Status pin 14" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Peripheral CD Status pin 13" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
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setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Peripheral CD Status pin 12" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
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textline " "
|
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setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Peripheral CD Status pin 11" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
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setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Peripheral CD Status pin 10" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Peripheral CD Status pin 9" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Peripheral CD Status pin 8" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Peripheral CD Status pin 7" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Peripheral CD Status pin 6" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Peripheral CD Status pin 5" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
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setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Peripheral CD Status pin 4" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Peripheral CD Status pin 3" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
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setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Peripheral CD Status pin 2" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Peripheral CD Status pin 1" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Peripheral CD Status pin 0" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "PIO_ELSR,PIO Edge/Level Status Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Edge/Level Interrupt source selection pin 31" "Edge,Level"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Edge/Level Interrupt source selection pin 30" "Edge,Level"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Edge/Level Interrupt source selection pin 29" "Edge,Level"
|
|
textline " "
|
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setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Edge/Level Interrupt source selection pin 28" "Edge,Level"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Edge/Level Interrupt source selection pin 27" "Edge,Level"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Edge/Level Interrupt source selection pin 26" "Edge,Level"
|
|
textline " "
|
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setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Edge/Level Interrupt source selection pin 25" "Edge,Level"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Edge/Level Interrupt source selection pin 24" "Edge,Level"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Edge/Level Interrupt source selection pin 23" "Edge,Level"
|
|
textline " "
|
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setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Edge/Level Interrupt source selection pin 22" "Edge,Level"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Edge/Level Interrupt source selection pin 21" "Edge,Level"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Edge/Level Interrupt source selection pin 20" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Edge/Level Interrupt source selection pin 19" "Edge,Level"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Edge/Level Interrupt source selection pin 18" "Edge,Level"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Edge/Level Interrupt source selection pin 17" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Edge/Level Interrupt source selection pin 16" "Edge,Level"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Edge/Level Interrupt source selection pin 15" "Edge,Level"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection pin 14" "Edge,Level"
|
|
textline " "
|
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setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection pin 13" "Edge,Level"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection pin 12" "Edge,Level"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection pin 11" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection pin 10" "Edge,Level"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection pin 9" "Edge,Level"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection pin 8" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection pin 7" "Edge,Level"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection pin 6" "Edge,Level"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection pin 5" "Edge,Level"
|
|
textline " "
|
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setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection pin 4" "Edge,Level"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection pin 3" "Edge,Level"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection pin 2" "Edge,Level"
|
|
textline " "
|
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setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Edge/Level Interrupt source selection pin 1" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection pin 0" "Edge,Level"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "PIO_FRLHSR,PIO Fall/Rise - Low/High Status Register"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31_set/clr ,Edge /Level Interrupt Source Selection pin 31" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30_set/clr ,Edge /Level Interrupt Source Selection pin 30" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29_set/clr ,Edge /Level Interrupt Source Selection pin 29" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28_set/clr ,Edge /Level Interrupt Source Selection pin 28" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27_set/clr ,Edge /Level Interrupt Source Selection pin 27" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26_set/clr ,Edge /Level Interrupt Source Selection pin 26" "Falling/Low,Rising/High"
|
|
textline " "
|
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setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25_set/clr ,Edge /Level Interrupt Source Selection pin 25" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24_set/clr ,Edge /Level Interrupt Source Selection pin 24" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_set/clr ,Edge /Level Interrupt Source Selection pin 23" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_set/clr ,Edge /Level Interrupt Source Selection pin 22" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_set/clr ,Edge /Level Interrupt Source Selection pin 21" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Edge /Level Interrupt Source Selection pin 20" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_set/clr ,Edge /Level Interrupt Source Selection pin 19" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_set/clr ,Edge /Level Interrupt Source Selection pin 18" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_set/clr ,Edge /Level Interrupt Source Selection pin 17" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_set/clr ,Edge /Level Interrupt Source Selection pin 16" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Edge /Level Interrupt Source Selection pin 15" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Edge /Level Interrupt Source Selection pin 14" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Edge /Level Interrupt Source Selection pin 13" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Edge /Level Interrupt Source Selection pin 12" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Edge /Level Interrupt Source Selection pin 11" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Edge /Level Interrupt Source Selection pin 10" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Edge /Level Interrupt Source Selection pin 9" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Edge /Level Interrupt Source Selection pin 8" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Edge /Level Interrupt Source Selection pin 7" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Edge /Level Interrupt Source Selection pin 6" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Edge /Level Interrupt Source Selection pin 5" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Edge /Level Interrupt Source Selection pin 4" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Edge /Level Interrupt Source Selection pin 3" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Edge /Level Interrupt Source Selection pin 2" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr ,Edge /Level Interrupt Source Selection pin 1" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Edge /Level Interrupt Source Selection pin 0" "Falling/Low,Rising/High"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "PIO_LOCKSR,PIO Lock Status Register"
|
|
bitfld.long 0x00 31. " P31 ,Lock Status pin 31" "Not locked,Locked"
|
|
bitfld.long 0x00 30. " P30 ,Lock Status pin 30" "Not locked,Locked"
|
|
bitfld.long 0x00 29. " P29 ,Lock Status pin 29" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " P28 ,Lock Status pin 28" "Not locked,Locked"
|
|
bitfld.long 0x00 27. " P27 ,Lock Status pin 27" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " P26 ,Lock Status pin 26" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Lock Status pin 25" "Not locked,Locked"
|
|
bitfld.long 0x00 24. " P24 ,Lock Status pin 24" "Not locked,Locked"
|
|
bitfld.long 0x00 23. " P23 ,Lock Status pin 23" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Lock Status pin 22" "Not locked,Locked"
|
|
bitfld.long 0x00 21. " P21 ,Lock Status pin 21" "Not locked,Locked"
|
|
bitfld.long 0x00 20. " P20 ,Lock Status pin 20" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Lock Status pin 19" "Not locked,Locked"
|
|
bitfld.long 0x00 18. " P18 ,Lock Status pin 18" "Not locked,Locked"
|
|
bitfld.long 0x00 17. " P17 ,Lock Status pin 17" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Lock Status pin 16" "Not locked,Locked"
|
|
bitfld.long 0x00 15. " P15 ,Lock Status pin 15" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " P14 ,Lock Status pin 14" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Lock Status pin 13" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " P12 ,Lock Status pin 12" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " P11 ,Lock Status pin 11" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Lock Status pin 10" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " P9 ,Lock Status pin 9" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " P8 ,Lock Status pin 8" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Lock Status pin 7" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,Lock Status pin 6" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " P5 ,Lock Status pin 5" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Lock Status pin 4" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " P3 ,Lock Status pin 3" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " P2 ,Lock Status pin 2" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Lock Status pin 1" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,Lock Status pin 0" "Not locked,Locked"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in.
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PIO_SCHMITT,PIO Schmitt Trigger Register"
|
|
bitfld.long 0x00 31. " SCHMITT31 ,Schmitt Trigger pin 31 Disabled" "No,Yes"
|
|
bitfld.long 0x00 30. " SCHMITT30 ,Schmitt Trigger pin 30 Disabled" "No,Yes"
|
|
bitfld.long 0x00 29. " SCHMITT29 ,Schmitt Trigger pin 29 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SCHMITT28 ,Schmitt Trigger pin 28 Disabled" "No,Yes"
|
|
bitfld.long 0x00 27. " SCHMITT27 ,Schmitt Trigger pin 27 Disabled" "No,Yes"
|
|
bitfld.long 0x00 26. " SCHMITT26 ,Schmitt Trigger pin 26 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SCHMITT25 ,Schmitt Trigger pin 25 Disabled" "No,Yes"
|
|
bitfld.long 0x00 24. " SCHMITT24 ,Schmitt Trigger pin 24 Disabled" "No,Yes"
|
|
bitfld.long 0x00 23. " SCHMITT23 ,Schmitt Trigger pin 23 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCHMITT22 ,Schmitt Trigger pin 22 Disabled" "No,Yes"
|
|
bitfld.long 0x00 21. " SCHMITT21 ,Schmitt Trigger pin 21 Disabled" "No,Yes"
|
|
bitfld.long 0x00 20. " SCHMITT20 ,Schmitt Trigger pin 20 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SCHMITT19 ,Schmitt Trigger pin 19 Disabled" "No,Yes"
|
|
bitfld.long 0x00 18. " SCHMITT18 ,Schmitt Trigger pin 18 Disabled" "No,Yes"
|
|
bitfld.long 0x00 17. " SCHMITT17 ,Schmitt Trigger pin 17 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SCHMITT16 ,Schmitt Trigger pin 16 Disabled" "No,Yes"
|
|
bitfld.long 0x00 15. " SCHMITT15 ,Schmitt Trigger pin 15 Disabled" "No,Yes"
|
|
bitfld.long 0x00 14. " SCHMITT14 ,Schmitt Trigger pin 14 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCHMITT13 ,Schmitt Trigger pin 13 Disabled" "No,Yes"
|
|
bitfld.long 0x00 12. " SCHMITT12 ,Schmitt Trigger pin 12 Disabled" "No,Yes"
|
|
bitfld.long 0x00 11. " SCHMITT11 ,Schmitt Trigger pin 11 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SCHMITT10 ,Schmitt Trigger pin 10 Disabled" "No,Yes"
|
|
bitfld.long 0x00 9. " SCHMITT9 ,Schmitt Trigger pin 9 Disabled" "No,Yes"
|
|
bitfld.long 0x00 8. " SCHMITT8 ,Schmitt Trigger pin 8 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCHMITT7 ,Schmitt Trigger pin 7 Disabled" "No,Yes"
|
|
bitfld.long 0x00 6. " SCHMITT6 ,Schmitt Trigger pin 6 Disabled" "No,Yes"
|
|
bitfld.long 0x00 5. " SCHMITT5 ,Schmitt Trigger pin 5 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SCHMITT4 ,Schmitt Trigger pin 4 Disabled" "No,Yes"
|
|
bitfld.long 0x00 3. " SCHMITT3 ,Schmitt Trigger pin 3 Disabled" "No,Yes"
|
|
bitfld.long 0x00 2. " SCHMITT2 ,Schmitt Trigger pin 2 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCHMITT1 ,Schmitt Trigger pin 1 Disabled" "No,Yes"
|
|
bitfld.long 0x00 0. " SCHMITT0 ,Schmitt Trigger pin 0 Disabled" "No,Yes"
|
|
sif !cpuis("ATSAM4N*")
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "PIO_DELAYR,PIO I/O Delay Register"
|
|
bitfld.long 0x00 28.--31. " DELAY7 ,Gives the number of elements in the delay line associated to pad 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " DELAY6 ,Gives the number of elements in the delay line associated to pad 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " DELAY5 ,Gives the number of elements in the delay line associated to pad 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DELAY4 ,Gives the number of elements in the delay line associated to pad 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DELAY3 ,Gives the number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DELAY2 ,Gives the number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DELAY1 ,Gives the number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DELAY0 ,Gives the number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "PIO_PCMR,PIO Parallel Capture Mode Register"
|
|
bitfld.long 0x00 11. " FRSTS ,Parallel Capture Mode First Sample" "Even index,Odd index"
|
|
bitfld.long 0x00 10. " HALFS ,Parallel Capture Mode Half" "All data,One time out of two"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ALWYS ,Parallel Capture Mode Always Sampling" "No,Yes"
|
|
bitfld.long 0x00 4.--5. " DSIZE ,Parallel Capture Mode Data Size" "BYTE,HALF-WORD,WORD,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " PCEN ,Parallel Capture Mode Enable" "Disabled,Enabled"
|
|
rgroup.long 0x15C++0x03
|
|
line.long 0x00 "PIO_PCIMR,PIO Parallel Capture Interrupt Mask Register"
|
|
bitfld.long 0x00 3. " RXBUFF ,Reception Buffer Full Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " ENDRX ,End of Reception Transfer Interrupt Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OVRE ,Parallel Capture Mode Overrun Error Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " DRDY ,Parallel Capture Mode Data Ready Interrupt Mask" "Not masked,Masked"
|
|
group.long 0x160++0x3
|
|
line.long 0x00 "PIO_PCISR,PIO Parallel Capture Interrupt Status Register"
|
|
setclrfld.long 0x00 3. -0x0C 3. -0x08 3. " RXBUFF_set/clr ,Reception Buffer Full Interrupt Status" "Inactive,Active"
|
|
setclrfld.long 0x00 2. -0x0C 2. -0x08 2. " ENDRX_set/clr ,End of Reception Transfer Interrupt Status" "Inactive,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x0C 1. -0x08 1. " OVRE_set/clr ,Parallel Capture Mode Overrun Error Interrupt Status" "No error,Error"
|
|
setclrfld.long 0x00 0. -0x0C 0. -0x08 0. " DRDY_set/clr ,Parallel Capture Mode Data Ready Interrupt Status" "Not ready,Ready"
|
|
if ((d.l(ad:0x400E1200+0x150)&0x30)==0x00)
|
|
rgroup.long 0x164++0x3
|
|
line.long 0x00 "PIO_PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.byte 0x00 0.--8. 1. " RDATA ,Parallel Capture Mode Reception Data"
|
|
elif ((d.l(ad:0x400E1200+0x150)&0x30)==0x10)
|
|
rgroup.long 0x164++0x3
|
|
line.long 0x00 "PIO_PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.word 0x00 0.--16. 1. " RDATA ,Parallel Capture Mode Reception Data"
|
|
else
|
|
rgroup.long 0xF64++0x3
|
|
line.long 0x00 "PIO_PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
endif
|
|
endif
|
|
width 0xB
|
|
tree "PIOC PDC (Peripheral DMA Controller)"
|
|
base ad:0x400E1268
|
|
width 10.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "PIOC_RPR,Receive Pointer Register"
|
|
line.long 0x04 "PIOC_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "PIOC_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "PIOC_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "PIOC_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "PIOC_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "PIOC_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "PIOC_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "PIOC_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "PIOC_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
sif (cpu()=="ATSAM4E8E"||cpu()=="ATSAM4E16E")
|
|
tree "PIO D"
|
|
base ad:0x400E1400
|
|
width 13.
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PIO_PSR,PIO Status Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,PIO Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,PIO Status 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,PIO Status 29" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,PIO Status 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,PIO Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,PIO Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,PIO Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,PIO Status 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,PIO Status 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,PIO Status 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,PIO Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO Status 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO Status 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO Status 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO Status 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO Status 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO Status 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO Status 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO Status 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO Status 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO Status 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO Status 0" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PIO_OSR,PIO Output Status Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Status pin 31" "Input,Output"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Status pin 30" "Input,Output"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Status pin 29" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Status pin 28" "Input,Output"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Status pin 27" "Input,Output"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Status pin 26" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Status pin 25" "Input,Output"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Status pin 24" "Input,Output"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Status pin 23" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Status pin 22" "Input,Output"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Status pin 21" "Input,Output"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Status pin 20" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Status pin 19" "Input,Output"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Status pin 18" "Input,Output"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Status pin 17" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Status pin 16" "Input,Output"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Status pin 15" "Input,Output"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Status pin 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Status pin 13" "Input,Output"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Status pin 12" "Input,Output"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Status pin 11" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Status pin 10" "Input,Output"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Status pin 9" "Input,Output"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Status pin 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Status pin 7" "Input,Output"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Status pin 6" "Input,Output"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Status pin 5" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Status pin 4" "Input,Output"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Status pin 3" "Input,Output"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Status pin 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Status pin 1" "Input,Output"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Status pin 0" "Input,Output"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PIO_IFSR,PIO Input Filter Status Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Input Filer Status pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Input Filer Status pin 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Input Filer Status pin 29" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Input Filer Status pin 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Input Filer Status pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Input Filer Status pin 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Input Filer Status pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Input Filer Status pin 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Input Filer Status pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Input Filer Status pin 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Input Filer Status pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Input Filer Status pin 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Input Filer Status pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Input Filer Status pin 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Input Filer Status pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Input Filer Status pin 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Input Filer Status pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Filer Status pin 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Filer Status pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Filer Status pin 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Filer Status pin 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Filer Status pin 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Filer Status pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Filer Status pin 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Filer Status pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Filer Status pin 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Filer Status pin 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Filer Status pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Filer Status pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Filer Status pin 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Filer Status pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Filer Status pin 0" "Disabled,Enabled"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PIO_ODSR,PIO Output Data Status Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Data Status pin 31" "0,1"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Data Status pin 30" "0,1"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Data Status pin 29" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Data Status pin 28" "0,1"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Data Status pin 27" "0,1"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Data Status pin 26" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Data Status pin 25" "0,1"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Data Status pin 24" "0,1"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Data Status pin 23" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Data Status pin 22" "0,1"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Data Status pin 21" "0,1"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Data Status pin 20" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Data Status pin 19" "0,1"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Data Status pin 18" "0,1"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Data Status pin 17" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Data Status pin 16" "0,1"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Data Status pin 15" "0,1"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Data Status pin 14" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Data Status pin 13" "0,1"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Data Status pin 12" "0,1"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Data Status pin 11" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Data Status pin 10" "0,1"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Data Status pin 9" "0,1"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Data Status pin 8" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Data Status pin 7" "0,1"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Data Status pin 6" "0,1"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Data Status pin 5" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Data Status pin 4" "0,1"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Data Status pin 3" "0,1"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Data Status pin 2" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Data Status pin 1" "0,1"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Data Status pin 0" "0,1"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "PIO_PDSR,PIO Pin Data Status Register"
|
|
bitfld.long 0x00 31. " P31 ,Output Data Status pin 31" "Level 0,Level 1"
|
|
bitfld.long 0x00 30. " P30 ,Output Data Status pin 30" "Level 0,Level 1"
|
|
bitfld.long 0x00 29. " P29 ,Output Data Status pin 29" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " P28 ,Output Data Status pin 28" "Level 0,Level 1"
|
|
bitfld.long 0x00 27. " P27 ,Output Data Status pin 27" "Level 0,Level 1"
|
|
bitfld.long 0x00 26. " P26 ,Output Data Status pin 26" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Data Status pin 25" "Level 0,Level 1"
|
|
bitfld.long 0x00 24. " P24 ,Output Data Status pin 24" "Level 0,Level 1"
|
|
bitfld.long 0x00 23. " P23 ,Output Data Status pin 23" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Output Data Status pin 22" "Level 0,Level 1"
|
|
bitfld.long 0x00 21. " P21 ,Output Data Status pin 21" "Level 0,Level 1"
|
|
bitfld.long 0x00 20. " P20 ,Output Data Status pin 20" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Data Status pin 19" "Level 0,Level 1"
|
|
bitfld.long 0x00 18. " P18 ,Output Data Status pin 18" "Level 0,Level 1"
|
|
bitfld.long 0x00 17. " P17 ,Output Data Status pin 17" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Output Data Status pin 16" "Level 0,Level 1"
|
|
bitfld.long 0x00 15. " P15 ,Output Data Status pin 15" "Level 0,Level 1"
|
|
bitfld.long 0x00 14. " P14 ,Output Data Status pin 14" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Data Status pin 13" "Level 0,Level 1"
|
|
bitfld.long 0x00 12. " P12 ,Output Data Status pin 12" "Level 0,Level 1"
|
|
bitfld.long 0x00 11. " P11 ,Output Data Status pin 11" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Output Data Status pin 10" "Level 0,Level 1"
|
|
bitfld.long 0x00 9. " P9 ,Output Data Status pin 9" "Level 0,Level 1"
|
|
bitfld.long 0x00 8. " P8 ,Output Data Status pin 8" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Data Status pin 7" "Level 0,Level 1"
|
|
bitfld.long 0x00 6. " P6 ,Output Data Status pin 6" "Level 0,Level 1"
|
|
bitfld.long 0x00 5. " P5 ,Output Data Status pin 5" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Output Data Status pin 4" "Level 0,Level 1"
|
|
bitfld.long 0x00 3. " P3 ,Output Data Status pin 3" "Level 0,Level 1"
|
|
bitfld.long 0x00 2. " P2 ,Output Data Status pin 2" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Data Status pin 1" "Level 0,Level 1"
|
|
bitfld.long 0x00 0. " P0 ,Output Data Status pin 0" "Level 0,Level 1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PIO_IMR,PIO Interrupt Status Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Input Change Interrupt Mask pin 31" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Input Change Interrupt Mask pin 30" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Input Change Interrupt Mask pin 29" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Input Change Interrupt Mask pin 28" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Input Change Interrupt Mask pin 27" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Input Change Interrupt Mask pin 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Input Change Interrupt Mask pin 25" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Input Change Interrupt Mask pin 24" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Input Change Interrupt Mask pin 23" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Input Change Interrupt Mask pin 22" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Input Change Interrupt Mask pin 21" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Input Change Interrupt Mask pin 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Input Change Interrupt Mask pin 19" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Input Change Interrupt Mask pin 18" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Input Change Interrupt Mask pin 17" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Input Change Interrupt Mask pin 16" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Input Change Interrupt Mask pin 15" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Change Interrupt Mask pin 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Change Interrupt Mask pin 13" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Change Interrupt Mask pin 12" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Change Interrupt Mask pin 11" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Change Interrupt Mask pin 10" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Change Interrupt Mask pin 9" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Change Interrupt Mask pin 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Change Interrupt Mask pin 7" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Change Interrupt Mask pin 6" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Change Interrupt Mask pin 5" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Change Interrupt Mask pin 4" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Change Interrupt Mask pin 3" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Change Interrupt Mask pin 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Change Interrupt Mask pin 1" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Change Interrupt Mask pin 0" "No interrupt,Interrupt"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "PIO_ISR,PIO Interrupt Status Register"
|
|
bitfld.long 0x00 31. " P31 ,Input Change Interrupt Status pin 31" "Not detected,Detected"
|
|
bitfld.long 0x00 30. " P30 ,Input Change Interrupt Status pin 30" "Not detected,Detected"
|
|
bitfld.long 0x00 29. " P29 ,Input Change Interrupt Status pin 29" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 28. " P28 ,Input Change Interrupt Status pin 28" "Not detected,Detected"
|
|
bitfld.long 0x00 27. " P27 ,Input Change Interrupt Status pin 27" "Not detected,Detected"
|
|
bitfld.long 0x00 26. " P26 ,Input Change Interrupt Status pin 26" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Input Change Interrupt Status pin 25" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " P24 ,Input Change Interrupt Status pin 24" "Not detected,Detected"
|
|
bitfld.long 0x00 23. " P23 ,Input Change Interrupt Status pin 23" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Input Change Interrupt Status pin 22" "Not detected,Detected"
|
|
bitfld.long 0x00 21. " P21 ,Input Change Interrupt Status pin 21" "Not detected,Detected"
|
|
bitfld.long 0x00 20. " P20 ,Input Change Interrupt Status pin 20" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Input Change Interrupt Status pin 19" "Not detected,Detected"
|
|
bitfld.long 0x00 18. " P18 ,Input Change Interrupt Status pin 18" "Not detected,Detected"
|
|
bitfld.long 0x00 17. " P17 ,Input Change Interrupt Status pin 17" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Input Change Interrupt Status pin 16" "Not detected,Detected"
|
|
bitfld.long 0x00 15. " P15 ,Input Change Interrupt Status pin 15" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " P14 ,Input Change Interrupt Status pin 14" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Input Change Interrupt Status pin 13" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " P12 ,Input Change Interrupt Status pin 12" "Not detected,Detected"
|
|
bitfld.long 0x00 11. " P11 ,Input Change Interrupt Status pin 11" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Input Change Interrupt Status pin 10" "Not detected,Detected"
|
|
bitfld.long 0x00 9. " P9 ,Input Change Interrupt Status pin 9" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " P8 ,Input Change Interrupt Status pin 8" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Input Change Interrupt Status pin 7" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " P6 ,Input Change Interrupt Status pin 6" "Not detected,Detected"
|
|
bitfld.long 0x00 5. " P5 ,Input Change Interrupt Status pin 5" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Input Change Interrupt Status pin 4" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " P3 ,Input Change Interrupt Status pin 3" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " P2 ,Input Change Interrupt Status pin 2" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Input Change Interrupt Status pin 1" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " P0 ,Input Change Interrupt Status pin 0" "Not detected,Detected"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PIO_MDSR,PIO Multi-driver Status Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Multi Drive Status/Drive pin 31" "Low,High"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Multi Drive Status/Drive pin 30" "Low,High"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Multi Drive Status/Drive pin 29" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Multi Drive Status/Drive pin 28" "Low,High"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Multi Drive Status/Drive pin 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Multi Drive Status/Drive pin 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Multi Drive Status/Drive pin 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Multi Drive Status/Drive pin 24" "Low,High"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Multi Drive Status/Drive pin 23" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Multi Drive Status/Drive pin 22" "Low,High"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Multi Drive Status/Drive pin 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Multi Drive Status/Drive pin 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Multi Drive Status/Drive pin 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Multi Drive Status/Drive pin 18" "Low,High"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Multi Drive Status/Drive pin 17" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Multi Drive Status/Drive pin 16" "Low,High"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Multi Drive Status/Drive pin 15" "Low,High"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Multi Drive Status/Drive pin 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Multi Drive Status/Drive pin 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Multi Drive Status/Drive pin 12" "Low,High"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Multi Drive Status/Drive pin 11" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Multi Drive Status/Drive pin 10" "Low,High"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Multi Drive Status/Drive pin 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Multi Drive Status/Drive pin 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Multi Drive Status/Drive pin 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Multi Drive Status/Drive pin 6" "Low,High"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Multi Drive Status/Drive pin 5" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Multi Drive Status/Drive pin 4" "Low,High"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Multi Drive Status/Drive pin 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Multi Drive Status/Drive pin 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Multi Drive Status/Drive pin 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Multi Drive Status/Drive pin 0" "Low,High"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PIO_PUSR,PIO Pull Up Status Register"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31_set/clr ,Pull Up Status pin 31" "Enabled,Disabled"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30_set/clr ,Pull Up Status pin 30" "Enabled,Disabled"
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29_set/clr ,Pull Up Status pin 29" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28_set/clr ,Pull Up Status pin 28" "Enabled,Disabled"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27_set/clr ,Pull Up Status pin 27" "Enabled,Disabled"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26_set/clr ,Pull Up Status pin 26" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25_set/clr ,Pull Up Status pin 25" "Enabled,Disabled"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24_set/clr ,Pull Up Status pin 24" "Enabled,Disabled"
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_set/clr ,Pull Up Status pin 23" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_set/clr ,Pull Up Status pin 22" "Enabled,Disabled"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_set/clr ,Pull Up Status pin 21" "Enabled,Disabled"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Pull Up Status pin 20" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_set/clr ,Pull Up Status pin 19" "Enabled,Disabled"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_set/clr ,Pull Up Status pin 18" "Enabled,Disabled"
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_set/clr ,Pull Up Status pin 17" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_set/clr ,Pull Up Status pin 16" "Enabled,Disabled"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Pull Up Status pin 15" "Enabled,Disabled"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Pull Up Status pin 14" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Pull Up Status pin 13" "Enabled,Disabled"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Pull Up Status pin 12" "Enabled,Disabled"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Pull Up Status pin 11" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Pull Up Status pin 10" "Enabled,Disabled"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Pull Up Status pin 9" "Enabled,Disabled"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Pull Up Status pin 8" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Pull Up Status pin 7" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Pull Up Status pin 6" "Enabled,Disabled"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Pull Up Status pin 5" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Pull Up Status pin 4" "Enabled,Disabled"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Pull Up Status pin 3" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Pull Up Status pin 2" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr ,Pull Up Status pin 1" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Pull Up Status pin 0" "Enabled,Disabled"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "PIO_ABCDSR1,Peripheral Select Register 1"
|
|
bitfld.long 0x00 31. " P31 ,Peripheral Select pin 31 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 30. " P30 ,Peripheral Select pin 30 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 29. " P29 ,Peripheral Select pin 29 - A/C B/D" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 28. " P28 ,Peripheral Select pin 28 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 27. " P27 ,Peripheral Select pin 27 - A/C B/D" "PWML3/C,B/D"
|
|
bitfld.long 0x00 26. " P26 ,Peripheral Select pin 26 - A/C B/D" "PWML2/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Peripheral Select pin 25 - A/C B/D" "PWML1/C,B/D"
|
|
bitfld.long 0x00 24. " P24 ,Peripheral Select pin 24 - A/C B/D" "PWML0/C,B/D"
|
|
bitfld.long 0x00 23. " P23 ,Peripheral Select pin 23 - A/C B/D" "PWMH3/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Peripheral Select pin 22 - A/C B/D" "PWMH2/C,B/D"
|
|
bitfld.long 0x00 21. " P21 ,Peripheral Select pin 21 - A/C B/D" "PWMH1/C,B/D"
|
|
bitfld.long 0x00 20. " P20 ,Peripheral Select pin 20 - A/C B/D" "PWMH0/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Peripheral Select pin 19 - A/C B/D" "NCS3/C,B/D"
|
|
bitfld.long 0x00 18. " P18 ,Peripheral Select pin 18 - A/C B/D" "NCS1/C,B/D"
|
|
bitfld.long 0x00 17. " P17 ,Peripheral Select pin 17 - A/C B/D" "GTXER/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Peripheral Select pin 16 - A/C B/D" "GTX3/C,B/D"
|
|
bitfld.long 0x00 15. " P15 ,Peripheral Select pin 15 - A/C B/D" "GTX2/C,B/D"
|
|
bitfld.long 0x00 14. " P14 ,Peripheral Select pin 14 - A/C B/D" "GRXCK/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Peripheral Select pin 13 - A/C B/D" "GCOL/C,B/D"
|
|
bitfld.long 0x00 12. " P12 ,Peripheral Select pin 12 - A/C B/D" "GRX3/C,B/D"
|
|
bitfld.long 0x00 11. " P11 ,Peripheral Select pin 11 - A/C B/D" "GRX2/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Peripheral Select pin 10 - A/C B/D" "GCRS/C,B/D"
|
|
bitfld.long 0x00 9. " P9 ,Peripheral Select pin 9 - A/C B/D" "GMDIO/C,B/D"
|
|
bitfld.long 0x00 8. " P8 ,Peripheral Select pin 8 - A/C B/D" "GMDC/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Peripheral Select pin 7 - A/C B/D" "GRXER/C,B/D"
|
|
bitfld.long 0x00 6. " P6 ,Peripheral Select pin 6 - A/C B/D" "GRX/C,B/D"
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select pin 5 - A/C B/D" "GRX0/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select pin 4 - A/C B/D" "GCRSDV|GRXDV/C,B/D"
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select pin 3 - A/C B/D" "GTX1/C,B/D"
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select pin 2 - A/C B/D" "GTX0/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select pin 1 - A/C B/D" "GTXEN/C,B/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select pin 0 - A/C B/D" "GTXCK|GREFCK/C,B/D"
|
|
line.long 0x04 "PIO_ABCDSR2,Peripheral Select Register 2"
|
|
bitfld.long 0x04 31. " P31 ,Peripheral Select pin 31 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 30. " P30 ,Peripheral Select pin 30 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 29. " P29 ,Peripheral Select pin 29 - A/B C/D" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 28. " P28 ,Peripheral Select pin 28 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 27. " P27 ,Peripheral Select pin 27 - A/B C/D" "PWML3/B,C/D"
|
|
bitfld.long 0x04 26. " P26 ,Peripheral Select pin 26 - A/B C/D" "PWML2/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 25. " P25 ,Peripheral Select pin 25 - A/B C/D" "PWML1/B,C/D"
|
|
bitfld.long 0x04 24. " P24 ,Peripheral Select pin 24 - A/B C/D" "PWML0/B,C/D"
|
|
bitfld.long 0x04 23. " P23 ,Peripheral Select pin 23 - A/B C/D" "PWMH3/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 22. " P22 ,Peripheral Select pin 22 - A/B C/D" "PWMH2/B,C/D"
|
|
bitfld.long 0x04 21. " P21 ,Peripheral Select pin 21 - A/B C/D" "PWMH1/B,C/D"
|
|
bitfld.long 0x04 20. " P20 ,Peripheral Select pin 20 - A/B C/D" "PWMH0/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 19. " P19 ,Peripheral Select pin 19 - A/B C/D" "NCS3/B,C/D"
|
|
bitfld.long 0x04 18. " P18 ,Peripheral Select pin 18 - A/B C/D" "NCS1/B,C/D"
|
|
bitfld.long 0x04 17. " P17 ,Peripheral Select pin 17 - A/B C/D" "GTXER/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 16. " P16 ,Peripheral Select pin 16 - A/B C/D" "GTX3/B,C/D"
|
|
bitfld.long 0x04 15. " P15 ,Peripheral Select pin 15 - A/B C/D" "GTX2/B,C/D"
|
|
bitfld.long 0x04 14. " P14 ,Peripheral Select pin 14 - A/B C/D" "GRXCK/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 13. " P13 ,Peripheral Select pin 13 - A/B C/D" "GCOL/B,C/D"
|
|
bitfld.long 0x04 12. " P12 ,Peripheral Select pin 12 - A/B C/D" "GRX3/B,C/D"
|
|
bitfld.long 0x04 11. " P11 ,Peripheral Select pin 11 - A/B C/D" "GRX2/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 10. " P10 ,Peripheral Select pin 10 - A/B C/D" "GCRS/B,C/D"
|
|
bitfld.long 0x04 9. " P9 ,Peripheral Select pin 9 - A/B C/D" "GMDIO/B,C/D"
|
|
bitfld.long 0x04 8. " P8 ,Peripheral Select pin 8 - A/B C/D" "GMDC/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 7. " P7 ,Peripheral Select pin 7 - A/B C/D" "GRXER/B,C/D"
|
|
bitfld.long 0x04 6. " P6 ,Peripheral Select pin 6 - A/B C/D" "GRX/B,C/D"
|
|
bitfld.long 0x04 5. " P5 ,Peripheral Select pin 5 - A/B C/D" "GRX0/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 4. " P4 ,Peripheral Select pin 4 - A/B C/D" "GCRSDV|GRXDV/B,C/D"
|
|
bitfld.long 0x04 3. " P3 ,Peripheral Select pin 3 - A/B C/D" "GTX1/B,C/D"
|
|
bitfld.long 0x04 2. " P2 ,Peripheral Select pin 2 - A/B C/D" "GTX0/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 1. " P1 ,Peripheral Select pin 1 - A/B C/D" "GTXEN/B,C/D"
|
|
bitfld.long 0x04 0. " P0 ,Peripheral Select pin 0 - A/B C/D" "GTXCK|GREFCK/B,C/D"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PIO_IFSCSR,PIO Input Filter Slow Clock Status Register"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31_set/clr ,Glitch or Debouncing Filter Selection Status pin 31" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30_set/clr ,Glitch or Debouncing Filter Selection Status pin 30" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29_set/clr ,Glitch or Debouncing Filter Selection Status pin 29" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28_set/clr ,Glitch or Debouncing Filter Selection Status pin 28" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27_set/clr ,Glitch or Debouncing Filter Selection Status pin 27" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26_set/clr ,Glitch or Debouncing Filter Selection Status pin 26" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25_set/clr ,Glitch or Debouncing Filter Selection Status pin 25" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24_set/clr ,Glitch or Debouncing Filter Selection Status pin 24" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_set/clr ,Glitch or Debouncing Filter Selection Status pin 23" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_set/clr ,Glitch or Debouncing Filter Selection Status pin 22" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_set/clr ,Glitch or Debouncing Filter Selection Status pin 21" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Glitch or Debouncing Filter Selection Status pin 20" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_set/clr ,Glitch or Debouncing Filter Selection Status pin 19" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_set/clr ,Glitch or Debouncing Filter Selection Status pin 18" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_set/clr ,Glitch or Debouncing Filter Selection Status pin 17" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_set/clr ,Glitch or Debouncing Filter Selection Status pin 16" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Glitch or Debouncing Filter Selection Status pin 15" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status pin 14" "Glitch,Debouncing"
|
|
textline " "
|
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setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status pin 13" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status pin 12" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status pin 11" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status pin 10" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status pin 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status pin 8" "Glitch,Debouncing"
|
|
textline " "
|
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setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status pin 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status pin 6" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status pin 5" "Glitch,Debouncing"
|
|
textline " "
|
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setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status pin 4" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status pin 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status pin 2" "Glitch,Debouncing"
|
|
textline " "
|
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setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr ,Glitch or Debouncing Filter Selection Status pin 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status pin 0" "Glitch,Debouncing"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PIO_SCDR,PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow Clock Divider Selection for Debouncing - Tdiv_slclk = 2*(DIV+1)*Tslow_clock"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PIO_PPDSR,PIO Pad Pull Down Status Register"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31 ,Pull Down Status pin 31" "Enabled,Disabled"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30 ,Pull Down Status pin 30" "Enabled,Disabled"
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29 ,Pull Down Status pin 29" "Enabled,Disabled"
|
|
textline " "
|
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setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28 ,Pull Down Status pin 28" "Enabled,Disabled"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27 ,Pull Down Status pin 27" "Enabled,Disabled"
|
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setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26 ,Pull Down Status pin 26" "Enabled,Disabled"
|
|
textline " "
|
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setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25 ,Pull Down Status pin 25" "Enabled,Disabled"
|
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setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24 ,Pull Down Status pin 24" "Enabled,Disabled"
|
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setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23 ,Pull Down Status pin 23" "Enabled,Disabled"
|
|
textline " "
|
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setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22 ,Pull Down Status pin 22" "Enabled,Disabled"
|
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setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21 ,Pull Down Status pin 21" "Enabled,Disabled"
|
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setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20 ,Pull Down Status pin 20" "Enabled,Disabled"
|
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textline " "
|
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setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19 ,Pull Down Status pin 19" "Enabled,Disabled"
|
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setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18 ,Pull Down Status pin 18" "Enabled,Disabled"
|
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setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17 ,Pull Down Status pin 17" "Enabled,Disabled"
|
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textline " "
|
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setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16 ,Pull Down Status pin 16" "Enabled,Disabled"
|
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setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15 ,Pull Down Status pin 15" "Enabled,Disabled"
|
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setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14 ,Pull Down Status pin 14" "Enabled,Disabled"
|
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textline " "
|
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setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13 ,Pull Down Status pin 13" "Enabled,Disabled"
|
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setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12 ,Pull Down Status pin 12" "Enabled,Disabled"
|
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setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11 ,Pull Down Status pin 11" "Enabled,Disabled"
|
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textline " "
|
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setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10 ,Pull Down Status pin 10" "Enabled,Disabled"
|
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setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9 ,Pull Down Status pin 9" "Enabled,Disabled"
|
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setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8 ,Pull Down Status pin 8" "Enabled,Disabled"
|
|
textline " "
|
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setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7 ,Pull Down Status pin 7" "Enabled,Disabled"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6 ,Pull Down Status pin 6" "Enabled,Disabled"
|
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setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5 ,Pull Down Status pin 5" "Enabled,Disabled"
|
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textline " "
|
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setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4 ,Pull Down Status pin 4" "Enabled,Disabled"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3 ,Pull Down Status pin 3" "Enabled,Disabled"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2 ,Pull Down Status pin 2" "Enabled,Disabled"
|
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textline " "
|
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setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1 ,Pull Down Status pin 1" "Enabled,Disabled"
|
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setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0 ,Pull Down Status pin 0" "Enabled,Disabled"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PIO_OWSR,PIO Output Write Status Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Write Status pin 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Write Status pin 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Write Status pin 29" "Disabled,Enabled"
|
|
textline " "
|
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setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Write Status pin 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Write Status pin 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Write Status pin 26" "Disabled,Enabled"
|
|
textline " "
|
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setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Write Status pin 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Write Status pin 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Write Status pin 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Write Status pin 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Write Status pin 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Write Status pin 20" "Disabled,Enabled"
|
|
textline " "
|
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setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Write Status pin 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Write Status pin 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Write Status pin 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Write Status pin 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Write Status pin 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Write Status pin 14" "Disabled,Enabled"
|
|
textline " "
|
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setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Write Status pin 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Write Status pin 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Write Status pin 11" "Disabled,Enabled"
|
|
textline " "
|
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setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Write Status pin 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Write Status pin 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Write Status pin 8" "Disabled,Enabled"
|
|
textline " "
|
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setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Write Status pin 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Write Status pin 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Write Status pin 5" "Disabled,Enabled"
|
|
textline " "
|
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setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Write Status pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Write Status pin 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Write Status pin 2" "Disabled,Enabled"
|
|
textline " "
|
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setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Write Status pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Write Status pin 0" "Disabled,Enabled"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "PIO_AIMMR,PIO Additional Interrupt Modes Mask Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Peripheral CD Status pin 31" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
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setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Peripheral CD Status pin 30" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
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setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Peripheral CD Status pin 29" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Peripheral CD Status pin 28" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
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setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Peripheral CD Status pin 27" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
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setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Peripheral CD Status pin 26" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Peripheral CD Status pin 25" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
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setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Peripheral CD Status pin 24" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
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setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Peripheral CD Status pin 23" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Peripheral CD Status pin 22" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
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setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Peripheral CD Status pin 21" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
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setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Peripheral CD Status pin 20" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Peripheral CD Status pin 19" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
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setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Peripheral CD Status pin 18" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Peripheral CD Status pin 17" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Peripheral CD Status pin 16" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
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setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Peripheral CD Status pin 15" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
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setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Peripheral CD Status pin 14" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Peripheral CD Status pin 13" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Peripheral CD Status pin 12" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Peripheral CD Status pin 11" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Peripheral CD Status pin 10" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Peripheral CD Status pin 9" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
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setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Peripheral CD Status pin 8" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
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setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Peripheral CD Status pin 7" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Peripheral CD Status pin 6" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Peripheral CD Status pin 5" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Peripheral CD Status pin 4" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Peripheral CD Status pin 3" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Peripheral CD Status pin 2" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Peripheral CD Status pin 1" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Peripheral CD Status pin 0" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "PIO_ELSR,PIO Edge/Level Status Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Edge/Level Interrupt source selection pin 31" "Edge,Level"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Edge/Level Interrupt source selection pin 30" "Edge,Level"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Edge/Level Interrupt source selection pin 29" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Edge/Level Interrupt source selection pin 28" "Edge,Level"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Edge/Level Interrupt source selection pin 27" "Edge,Level"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Edge/Level Interrupt source selection pin 26" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Edge/Level Interrupt source selection pin 25" "Edge,Level"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Edge/Level Interrupt source selection pin 24" "Edge,Level"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Edge/Level Interrupt source selection pin 23" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Edge/Level Interrupt source selection pin 22" "Edge,Level"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Edge/Level Interrupt source selection pin 21" "Edge,Level"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Edge/Level Interrupt source selection pin 20" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Edge/Level Interrupt source selection pin 19" "Edge,Level"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Edge/Level Interrupt source selection pin 18" "Edge,Level"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Edge/Level Interrupt source selection pin 17" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Edge/Level Interrupt source selection pin 16" "Edge,Level"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Edge/Level Interrupt source selection pin 15" "Edge,Level"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection pin 14" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection pin 13" "Edge,Level"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection pin 12" "Edge,Level"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection pin 11" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection pin 10" "Edge,Level"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection pin 9" "Edge,Level"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection pin 8" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection pin 7" "Edge,Level"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection pin 6" "Edge,Level"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection pin 5" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection pin 4" "Edge,Level"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection pin 3" "Edge,Level"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection pin 2" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Edge/Level Interrupt source selection pin 1" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection pin 0" "Edge,Level"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "PIO_FRLHSR,PIO Fall/Rise - Low/High Status Register"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31_set/clr ,Edge /Level Interrupt Source Selection pin 31" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30_set/clr ,Edge /Level Interrupt Source Selection pin 30" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29_set/clr ,Edge /Level Interrupt Source Selection pin 29" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28_set/clr ,Edge /Level Interrupt Source Selection pin 28" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27_set/clr ,Edge /Level Interrupt Source Selection pin 27" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26_set/clr ,Edge /Level Interrupt Source Selection pin 26" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25_set/clr ,Edge /Level Interrupt Source Selection pin 25" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24_set/clr ,Edge /Level Interrupt Source Selection pin 24" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_set/clr ,Edge /Level Interrupt Source Selection pin 23" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_set/clr ,Edge /Level Interrupt Source Selection pin 22" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_set/clr ,Edge /Level Interrupt Source Selection pin 21" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Edge /Level Interrupt Source Selection pin 20" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_set/clr ,Edge /Level Interrupt Source Selection pin 19" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_set/clr ,Edge /Level Interrupt Source Selection pin 18" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_set/clr ,Edge /Level Interrupt Source Selection pin 17" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_set/clr ,Edge /Level Interrupt Source Selection pin 16" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Edge /Level Interrupt Source Selection pin 15" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Edge /Level Interrupt Source Selection pin 14" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Edge /Level Interrupt Source Selection pin 13" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Edge /Level Interrupt Source Selection pin 12" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Edge /Level Interrupt Source Selection pin 11" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Edge /Level Interrupt Source Selection pin 10" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Edge /Level Interrupt Source Selection pin 9" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Edge /Level Interrupt Source Selection pin 8" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Edge /Level Interrupt Source Selection pin 7" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Edge /Level Interrupt Source Selection pin 6" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Edge /Level Interrupt Source Selection pin 5" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Edge /Level Interrupt Source Selection pin 4" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Edge /Level Interrupt Source Selection pin 3" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Edge /Level Interrupt Source Selection pin 2" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr ,Edge /Level Interrupt Source Selection pin 1" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Edge /Level Interrupt Source Selection pin 0" "Falling/Low,Rising/High"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "PIO_LOCKSR,PIO Lock Status Register"
|
|
bitfld.long 0x00 31. " P31 ,Lock Status pin 31" "Not locked,Locked"
|
|
bitfld.long 0x00 30. " P30 ,Lock Status pin 30" "Not locked,Locked"
|
|
bitfld.long 0x00 29. " P29 ,Lock Status pin 29" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " P28 ,Lock Status pin 28" "Not locked,Locked"
|
|
bitfld.long 0x00 27. " P27 ,Lock Status pin 27" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " P26 ,Lock Status pin 26" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Lock Status pin 25" "Not locked,Locked"
|
|
bitfld.long 0x00 24. " P24 ,Lock Status pin 24" "Not locked,Locked"
|
|
bitfld.long 0x00 23. " P23 ,Lock Status pin 23" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " P22 ,Lock Status pin 22" "Not locked,Locked"
|
|
bitfld.long 0x00 21. " P21 ,Lock Status pin 21" "Not locked,Locked"
|
|
bitfld.long 0x00 20. " P20 ,Lock Status pin 20" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Lock Status pin 19" "Not locked,Locked"
|
|
bitfld.long 0x00 18. " P18 ,Lock Status pin 18" "Not locked,Locked"
|
|
bitfld.long 0x00 17. " P17 ,Lock Status pin 17" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P16 ,Lock Status pin 16" "Not locked,Locked"
|
|
bitfld.long 0x00 15. " P15 ,Lock Status pin 15" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " P14 ,Lock Status pin 14" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Lock Status pin 13" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " P12 ,Lock Status pin 12" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " P11 ,Lock Status pin 11" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P10 ,Lock Status pin 10" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " P9 ,Lock Status pin 9" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " P8 ,Lock Status pin 8" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Lock Status pin 7" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,Lock Status pin 6" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " P5 ,Lock Status pin 5" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4 ,Lock Status pin 4" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " P3 ,Lock Status pin 3" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " P2 ,Lock Status pin 2" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Lock Status pin 1" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,Lock Status pin 0" "Not locked,Locked"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in.
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PIO_SCHMITT,PIO Schmitt Trigger Register"
|
|
bitfld.long 0x00 31. " SCHMITT31 ,Schmitt Trigger pin 31 Disabled" "No,Yes"
|
|
bitfld.long 0x00 30. " SCHMITT30 ,Schmitt Trigger pin 30 Disabled" "No,Yes"
|
|
bitfld.long 0x00 29. " SCHMITT29 ,Schmitt Trigger pin 29 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SCHMITT28 ,Schmitt Trigger pin 28 Disabled" "No,Yes"
|
|
bitfld.long 0x00 27. " SCHMITT27 ,Schmitt Trigger pin 27 Disabled" "No,Yes"
|
|
bitfld.long 0x00 26. " SCHMITT26 ,Schmitt Trigger pin 26 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SCHMITT25 ,Schmitt Trigger pin 25 Disabled" "No,Yes"
|
|
bitfld.long 0x00 24. " SCHMITT24 ,Schmitt Trigger pin 24 Disabled" "No,Yes"
|
|
bitfld.long 0x00 23. " SCHMITT23 ,Schmitt Trigger pin 23 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCHMITT22 ,Schmitt Trigger pin 22 Disabled" "No,Yes"
|
|
bitfld.long 0x00 21. " SCHMITT21 ,Schmitt Trigger pin 21 Disabled" "No,Yes"
|
|
bitfld.long 0x00 20. " SCHMITT20 ,Schmitt Trigger pin 20 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SCHMITT19 ,Schmitt Trigger pin 19 Disabled" "No,Yes"
|
|
bitfld.long 0x00 18. " SCHMITT18 ,Schmitt Trigger pin 18 Disabled" "No,Yes"
|
|
bitfld.long 0x00 17. " SCHMITT17 ,Schmitt Trigger pin 17 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SCHMITT16 ,Schmitt Trigger pin 16 Disabled" "No,Yes"
|
|
bitfld.long 0x00 15. " SCHMITT15 ,Schmitt Trigger pin 15 Disabled" "No,Yes"
|
|
bitfld.long 0x00 14. " SCHMITT14 ,Schmitt Trigger pin 14 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCHMITT13 ,Schmitt Trigger pin 13 Disabled" "No,Yes"
|
|
bitfld.long 0x00 12. " SCHMITT12 ,Schmitt Trigger pin 12 Disabled" "No,Yes"
|
|
bitfld.long 0x00 11. " SCHMITT11 ,Schmitt Trigger pin 11 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SCHMITT10 ,Schmitt Trigger pin 10 Disabled" "No,Yes"
|
|
bitfld.long 0x00 9. " SCHMITT9 ,Schmitt Trigger pin 9 Disabled" "No,Yes"
|
|
bitfld.long 0x00 8. " SCHMITT8 ,Schmitt Trigger pin 8 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCHMITT7 ,Schmitt Trigger pin 7 Disabled" "No,Yes"
|
|
bitfld.long 0x00 6. " SCHMITT6 ,Schmitt Trigger pin 6 Disabled" "No,Yes"
|
|
bitfld.long 0x00 5. " SCHMITT5 ,Schmitt Trigger pin 5 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SCHMITT4 ,Schmitt Trigger pin 4 Disabled" "No,Yes"
|
|
bitfld.long 0x00 3. " SCHMITT3 ,Schmitt Trigger pin 3 Disabled" "No,Yes"
|
|
bitfld.long 0x00 2. " SCHMITT2 ,Schmitt Trigger pin 2 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCHMITT1 ,Schmitt Trigger pin 1 Disabled" "No,Yes"
|
|
bitfld.long 0x00 0. " SCHMITT0 ,Schmitt Trigger pin 0 Disabled" "No,Yes"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "PIO_DELAYR,PIO I/O Delay Register"
|
|
bitfld.long 0x00 28.--31. " DELAY7 ,Gives the number of elements in the delay line associated to pad 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " DELAY6 ,Gives the number of elements in the delay line associated to pad 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " DELAY5 ,Gives the number of elements in the delay line associated to pad 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DELAY4 ,Gives the number of elements in the delay line associated to pad 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DELAY3 ,Gives the number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DELAY2 ,Gives the number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DELAY1 ,Gives the number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DELAY0 ,Gives the number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "PIO_PCMR,PIO Parallel Capture Mode Register"
|
|
bitfld.long 0x00 11. " FRSTS ,Parallel Capture Mode First Sample" "Even index,Odd index"
|
|
bitfld.long 0x00 10. " HALFS ,Parallel Capture Mode Half" "All data,One time out of two"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ALWYS ,Parallel Capture Mode Always Sampling" "No,Yes"
|
|
bitfld.long 0x00 4.--5. " DSIZE ,Parallel Capture Mode Data Size" "BYTE,HALF-WORD,WORD,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " PCEN ,Parallel Capture Mode Enable" "Disabled,Enabled"
|
|
rgroup.long 0x15C++0x03
|
|
line.long 0x00 "PIO_PCIMR,PIO Parallel Capture Interrupt Mask Register"
|
|
bitfld.long 0x00 3. " RXBUFF ,Reception Buffer Full Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " ENDRX ,End of Reception Transfer Interrupt Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OVRE ,Parallel Capture Mode Overrun Error Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " DRDY ,Parallel Capture Mode Data Ready Interrupt Mask" "Not masked,Masked"
|
|
group.long 0x160++0x3
|
|
line.long 0x00 "PIO_PCISR,PIO Parallel Capture Interrupt Status Register"
|
|
setclrfld.long 0x00 3. -0x0C 3. -0x08 3. " RXBUFF_set/clr ,Reception Buffer Full Interrupt Status" "Inactive,Active"
|
|
setclrfld.long 0x00 2. -0x0C 2. -0x08 2. " ENDRX_set/clr ,End of Reception Transfer Interrupt Status" "Inactive,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x0C 1. -0x08 1. " OVRE_set/clr ,Parallel Capture Mode Overrun Error Interrupt Status" "No error,Error"
|
|
setclrfld.long 0x00 0. -0x0C 0. -0x08 0. " DRDY_set/clr ,Parallel Capture Mode Data Ready Interrupt Status" "Not ready,Ready"
|
|
if ((d.l(ad:0x400E1400+0x150)&0x30)==0x00)
|
|
rgroup.long 0x164++0x3
|
|
line.long 0x00 "PIO_PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.byte 0x00 0.--8. 1. " RDATA ,Parallel Capture Mode Reception Data"
|
|
elif ((d.l(ad:0x400E1400+0x150)&0x30)==0x10)
|
|
rgroup.long 0x164++0x3
|
|
line.long 0x00 "PIO_PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.word 0x00 0.--16. 1. " RDATA ,Parallel Capture Mode Reception Data"
|
|
else
|
|
rgroup.long 0xF64++0x3
|
|
line.long 0x00 "PIO_PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
endif
|
|
width 0xB
|
|
tree "PIOD PDC (Peripheral DMA Controller)"
|
|
base ad:0x400E1468
|
|
width 10.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "PIOD_RPR,Receive Pointer Register"
|
|
line.long 0x04 "PIOD_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "PIOD_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "PIOD_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "PIOD_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "PIOD_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "PIOD_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "PIOD_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "PIOD_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "PIOD_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "PIO E"
|
|
base ad:0x400E1600
|
|
width 13.
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PIO_PSR,PIO Status Register"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO Status 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO Status 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO Status 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO Status 0" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PIO_OSR,PIO Output Status Register"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Status pin 5" "Input,Output"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Status pin 4" "Input,Output"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Status pin 3" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Status pin 2" "Input,Output"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Status pin 1" "Input,Output"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Status pin 0" "Input,Output"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PIO_IFSR,PIO Input Filter Status Register"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Filer Status pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Filer Status pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Filer Status pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Filer Status pin 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Filer Status pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Filer Status pin 0" "Disabled,Enabled"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PIO_ODSR,PIO Output Data Status Register"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Data Status pin 5" "0,1"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Data Status pin 4" "0,1"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Data Status pin 3" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Data Status pin 2" "0,1"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Data Status pin 1" "0,1"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Data Status pin 0" "0,1"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "PIO_PDSR,PIO Pin Data Status Register"
|
|
bitfld.long 0x00 5. " P5 ,Output Data Status pin 5" "Level 0,Level 1"
|
|
bitfld.long 0x00 4. " P4 ,Output Data Status pin 4" "Level 0,Level 1"
|
|
bitfld.long 0x00 3. " P3 ,Output Data Status pin 3" "Level 0,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Output Data Status pin 2" "Level 0,Level 1"
|
|
bitfld.long 0x00 1. " P1 ,Output Data Status pin 1" "Level 0,Level 1"
|
|
bitfld.long 0x00 0. " P0 ,Output Data Status pin 0" "Level 0,Level 1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PIO_IMR,PIO Interrupt Status Register"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Change Interrupt Mask pin 5" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Change Interrupt Mask pin 4" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Change Interrupt Mask pin 3" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Change Interrupt Mask pin 2" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Change Interrupt Mask pin 1" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Change Interrupt Mask pin 0" "No interrupt,Interrupt"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "PIO_ISR,PIO Interrupt Status Register"
|
|
bitfld.long 0x00 5. " P5 ,Input Change Interrupt Status pin 5" "Not detected,Detected"
|
|
bitfld.long 0x00 4. " P4 ,Input Change Interrupt Status pin 4" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " P3 ,Input Change Interrupt Status pin 3" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Input Change Interrupt Status pin 2" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " P1 ,Input Change Interrupt Status pin 1" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " P0 ,Input Change Interrupt Status pin 0" "Not detected,Detected"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PIO_MDSR,PIO Multi-driver Status Register"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Multi Drive Status/Drive pin 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Multi Drive Status/Drive pin 4" "Low,High"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Multi Drive Status/Drive pin 3" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Multi Drive Status/Drive pin 2" "Low,High"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Multi Drive Status/Drive pin 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Multi Drive Status/Drive pin 0" "Low,High"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PIO_PUSR,PIO Pull Up Status Register"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Pull Up Status pin 5" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Pull Up Status pin 4" "Enabled,Disabled"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Pull Up Status pin 3" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Pull Up Status pin 2" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr ,Pull Up Status pin 1" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Pull Up Status pin 0" "Enabled,Disabled"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "PIO_ABCDSR1,Peripheral Select Register 1"
|
|
bitfld.long 0x00 5. " P5 ,Peripheral Select pin 5 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 4. " P4 ,Peripheral Select pin 4 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 3. " P3 ,Peripheral Select pin 3 - A/C B/D" "A/C,B/D"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Peripheral Select pin 2 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 1. " P1 ,Peripheral Select pin 1 - A/C B/D" "A/C,B/D"
|
|
bitfld.long 0x00 0. " P0 ,Peripheral Select pin 0 - A/C B/D" "A/C,B/D"
|
|
line.long 0x04 "PIO_ABCDSR2,Peripheral Select Register 2"
|
|
bitfld.long 0x04 5. " P5 ,Peripheral Select pin 5 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 4. " P4 ,Peripheral Select pin 4 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 3. " P3 ,Peripheral Select pin 3 - A/B C/D" "A/B,C/D"
|
|
textline " "
|
|
bitfld.long 0x04 2. " P2 ,Peripheral Select pin 2 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 1. " P1 ,Peripheral Select pin 1 - A/B C/D" "A/B,C/D"
|
|
bitfld.long 0x04 0. " P0 ,Peripheral Select pin 0 - A/B C/D" "A/B,C/D"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PIO_IFSCSR,PIO Input Filter Slow Clock Status Register"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status pin 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status pin 4" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status pin 3" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status pin 2" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr ,Glitch or Debouncing Filter Selection Status pin 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status pin 0" "Glitch,Debouncing"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PIO_SCDR,PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow Clock Divider Selection for Debouncing - Tdiv_slclk = 2*(DIV+1)*Tslow_clock"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PIO_PPDSR,PIO Pad Pull Down Status Register"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5 ,Pull Down Status pin 5" "Enabled,Disabled"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4 ,Pull Down Status pin 4" "Enabled,Disabled"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3 ,Pull Down Status pin 3" "Enabled,Disabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2 ,Pull Down Status pin 2" "Enabled,Disabled"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1 ,Pull Down Status pin 1" "Enabled,Disabled"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0 ,Pull Down Status pin 0" "Enabled,Disabled"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PIO_OWSR,PIO Output Write Status Register"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Write Status pin 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Write Status pin 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Write Status pin 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Write Status pin 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Write Status pin 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Write Status pin 0" "Disabled,Enabled"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "PIO_AIMMR,PIO Additional Interrupt Modes Mask Register"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Peripheral CD Status pin 5" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Peripheral CD Status pin 4" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Peripheral CD Status pin 3" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Peripheral CD Status pin 2" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Peripheral CD Status pin 1" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Peripheral CD Status pin 0" "Both Edge detection event,PIO_ELSR and PIO_FRLHSR"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "PIO_ELSR,PIO Edge/Level Status Register"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection pin 5" "Edge,Level"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection pin 4" "Edge,Level"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection pin 3" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection pin 2" "Edge,Level"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Edge/Level Interrupt source selection pin 1" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection pin 0" "Edge,Level"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "PIO_FRLHSR,PIO Fall/Rise - Low/High Status Register"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Edge /Level Interrupt Source Selection pin 5" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Edge /Level Interrupt Source Selection pin 4" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Edge /Level Interrupt Source Selection pin 3" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Edge /Level Interrupt Source Selection pin 2" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr ,Edge /Level Interrupt Source Selection pin 1" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Edge /Level Interrupt Source Selection pin 0" "Falling/Low,Rising/High"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "PIO_LOCKSR,PIO Lock Status Register"
|
|
bitfld.long 0x00 5. " P5 ,Lock Status pin 5" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " P4 ,Lock Status pin 4" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " P3 ,Lock Status pin 3" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Lock Status pin 2" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " P1 ,Lock Status pin 1" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,Lock Status pin 0" "Not locked,Locked"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "PIO_WPSR,PIO Write Protect Status Register"
|
|
in.
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PIO_SCHMITT,PIO Schmitt Trigger Register"
|
|
bitfld.long 0x00 5. " SCHMITT5 ,Schmitt Trigger pin 5 Disabled" "No,Yes"
|
|
bitfld.long 0x00 4. " SCHMITT4 ,Schmitt Trigger pin 4 Disabled" "No,Yes"
|
|
bitfld.long 0x00 3. " SCHMITT3 ,Schmitt Trigger pin 3 Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SCHMITT2 ,Schmitt Trigger pin 2 Disabled" "No,Yes"
|
|
bitfld.long 0x00 1. " SCHMITT1 ,Schmitt Trigger pin 1 Disabled" "No,Yes"
|
|
bitfld.long 0x00 0. " SCHMITT0 ,Schmitt Trigger pin 0 Disabled" "No,Yes"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "PIO_DELAYR,PIO I/O Delay Register"
|
|
bitfld.long 0x00 28.--31. " DELAY7 ,Gives the number of elements in the delay line associated to pad 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " DELAY6 ,Gives the number of elements in the delay line associated to pad 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " DELAY5 ,Gives the number of elements in the delay line associated to pad 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DELAY4 ,Gives the number of elements in the delay line associated to pad 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DELAY3 ,Gives the number of elements in the delay line associated to pad 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DELAY2 ,Gives the number of elements in the delay line associated to pad 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DELAY1 ,Gives the number of elements in the delay line associated to pad 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DELAY0 ,Gives the number of elements in the delay line associated to pad 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "PIO_PCMR,PIO Parallel Capture Mode Register"
|
|
bitfld.long 0x00 11. " FRSTS ,Parallel Capture Mode First Sample" "Even index,Odd index"
|
|
bitfld.long 0x00 10. " HALFS ,Parallel Capture Mode Half" "All data,One time out of two"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ALWYS ,Parallel Capture Mode Always Sampling" "No,Yes"
|
|
bitfld.long 0x00 4.--5. " DSIZE ,Parallel Capture Mode Data Size" "BYTE,HALF-WORD,WORD,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " PCEN ,Parallel Capture Mode Enable" "Disabled,Enabled"
|
|
rgroup.long 0x15C++0x03
|
|
line.long 0x00 "PIO_PCIMR,PIO Parallel Capture Interrupt Mask Register"
|
|
bitfld.long 0x00 3. " RXBUFF ,Reception Buffer Full Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " ENDRX ,End of Reception Transfer Interrupt Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OVRE ,Parallel Capture Mode Overrun Error Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " DRDY ,Parallel Capture Mode Data Ready Interrupt Mask" "Not masked,Masked"
|
|
group.long 0x160++0x3
|
|
line.long 0x00 "PIO_PCISR,PIO Parallel Capture Interrupt Status Register"
|
|
setclrfld.long 0x00 3. -0x0C 3. -0x08 3. " RXBUFF_set/clr ,Reception Buffer Full Interrupt Status" "Inactive,Active"
|
|
setclrfld.long 0x00 2. -0x0C 2. -0x08 2. " ENDRX_set/clr ,End of Reception Transfer Interrupt Status" "Inactive,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x0C 1. -0x08 1. " OVRE_set/clr ,Parallel Capture Mode Overrun Error Interrupt Status" "No error,Error"
|
|
setclrfld.long 0x00 0. -0x0C 0. -0x08 0. " DRDY_set/clr ,Parallel Capture Mode Data Ready Interrupt Status" "Not ready,Ready"
|
|
if ((d.l(ad:0x400E1600+0x150)&0x30)==0x00)
|
|
rgroup.long 0x164++0x3
|
|
line.long 0x00 "PIO_PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.byte 0x00 0.--8. 1. " RDATA ,Parallel Capture Mode Reception Data"
|
|
elif ((d.l(ad:0x400E1600+0x150)&0x30)==0x10)
|
|
rgroup.long 0x164++0x3
|
|
line.long 0x00 "PIO_PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.word 0x00 0.--16. 1. " RDATA ,Parallel Capture Mode Reception Data"
|
|
else
|
|
rgroup.long 0xF64++0x3
|
|
line.long 0x00 "PIO_PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
endif
|
|
width 0xB
|
|
tree "PIOE PDC (Peripheral DMA Controller)"
|
|
base ad:0x400E1668
|
|
width 10.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "PIOE_RPR,Receive Pointer Register"
|
|
line.long 0x04 "PIOE_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "PIOE_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "PIOE_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "PIOE_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "PIOE_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "PIOE_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "PIOE_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "PIOE_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "PIOE_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
base ad:0x40088000
|
|
width 13.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,SPI Control Register"
|
|
sif cpuis("ATSAME70*")
|
|
bitfld.long 0x00 31. "FIFODIS,FIFO disable" "No effect,Disabled"
|
|
bitfld.long 0x00 30. "FIFOEN,FIFO enable" "No effect,Enabled"
|
|
endif
|
|
bitfld.long 0x00 24. " LASTXFER ,Last transfer" "No effect,Deasserted"
|
|
sif cpuis("ATSAME70*")
|
|
bitfld.long 0x00 17. "RXFCLR,Receive FIFO clear" "Di,Enabled"
|
|
bitfld.long 0x00 16. "TXFCLR,Transmit FIFO clear" "No effect,Transmitted"
|
|
endif
|
|
bitfld.long 0x00 7. " SWRST ,SPI software reset" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI disable" "No effect,Yes"
|
|
bitfld.long 0x00 0. " SPIEN ,SPI enable" "No effect,Enabled"
|
|
sif cpuis("ATSAM4S*")||cpuis("ATSAMV7*")||cpuis("ATSAME70*")
|
|
if ((per.l(ad:0x40088000+0xE4)&0x01)==0x00)
|
|
if (((per.l((ad:0x40088000+0x04)))&0x07)==0x01)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40088000+0x04)))&0x07)==0x05)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40088000+0x04)))&0x07)==(0x03||0x07))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40088000+0x04)))&0x07)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40088000+0x04)))&0x07)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects belay"
|
|
newline
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
endif
|
|
else
|
|
if (((per.l((ad:0x40088000+0x04)))&0x07)==0x01)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40088000+0x04)))&0x07)==0x05)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40088000+0x04)))&0x07)==(0x03||0x07))
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40088000+0x04)))&0x07)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40088000+0x04)))&0x07)==0x04)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l((ad:0x40088000+0x04)))&0x07)==0x01)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40088000+0x04)))&0x07)==0x05)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40088000+0x04)))&0x07)==(0x03||0x07))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40088000+0x04)))&0x07)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40088000+0x04)))&0x07)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
endif
|
|
endif
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "RDR,SPI Receive Data Register"
|
|
in
|
|
if (((per.l((ad:0x40088000+0x04)))&0x06)==0x02)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last transfer" "No effect,Deasserted"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit data"
|
|
elif (((per.l((ad:0x40088000+0x04)))&0x06)==0x06)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last transfer" "No effect,Deasserted"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit data"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "TDR,SPI Transmit Data Register"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit data"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SR,SPI Status Register"
|
|
in
|
|
sif cpuis("AT91SAM3S*")||cpuis("AT91SAM3N*")||cpuis("ATSAM4E*")||cpuis("ATSAM4S*")||cpuis("ATSAMG51")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IMR_SET/CLR,SPI Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNDES ,Underrun error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY ,Transmission registers empty mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NSSR ,NSS rising interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " TXBUFE ,Transmit buffer empty interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " RXBUFF ,Receive buffer full interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " ENDTX ,End of transmit buffer interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDRX ,End of receive buffer interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " OVRES ,Overrun error interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MODF ,Mode fault error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TDRE ,SPI transmit data register empty interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RDRF ,Receive data register full interrupt mask" "Masked,Unmasked"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IMR_SET/CLR,SPI Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNDES ,Underrun error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY ,Transmission registers empty mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NSSR ,NSS rising interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " OVRES ,Overrun error interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MODF ,Mode fault error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TDRE ,SPI transmit data register empty interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RDRF ,Receive data register full interrupt mask" "Masked,Unmasked"
|
|
endif
|
|
sif cpuis("ATSAM4S*")||cpuis("ATSAMV7*")||cpuis("ATSAME70*")
|
|
if ((per.l(ad:0x40088000+0xE4)&0x01)==0x00)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock bit rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
endif
|
|
if ((per.l(ad:0x40088000+0xE4)&0x01)==0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock bit rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
endif
|
|
if ((per.l(ad:0x40088000+0xE4)&0x01)==0x00)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock bit rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
endif
|
|
if ((per.l(ad:0x40088000+0xE4)&0x01)==0x00)
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock bit rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
endif
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,SPI write protection key password"
|
|
bitfld.long 0x00 0. " WPEN ,SPI write protection enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,SPI Write Protection Status Register"
|
|
in
|
|
width 0x0B
|
|
tree "SPI PDC (Peripheral DMA Controller)"
|
|
width 10.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "SPI_RPR,Receive Pointer Register"
|
|
line.long 0x04 "SPI_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "SPI_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "SPI_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "SPI_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "SPI_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "SPI_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "SPI_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "SPI_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "SPI_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "TWI (Two-wire Interface)"
|
|
tree "TWI0"
|
|
base ad:0x400A8000
|
|
width 16.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TWI_CR,TWI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS Quick Command" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SVDIS ,TWI Slave Mode Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 4. " SVEN ,TWI Slave Mode Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSDIS ,TWI Master Transfer Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 2. " MSEN ,TWI Master Transfer Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP Condition" "No effect,Stop"
|
|
bitfld.long 0x00 0. " START ,Send a START Condition" "No effect,Start"
|
|
sif ((cpu()!="ATSAMG5*")||cpuis("ATSAM4S*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
endif
|
|
sif (cpuis("ATSAM4S*"))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR ,Slave Address"
|
|
endif
|
|
if (((d.l((ad:0x400A8000+0x04)))&0x300)==0x300)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x400A8000+0x04)))&0x300)==0x200)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x400A8000+0x04)))&0x300)==0x100)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IADR ,Internal Address"
|
|
else
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
endif
|
|
sif cpuis("ATSAM4S*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
sif cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 24.--28. " HOLD ,TWD Hold Time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16.--18. " CKDIV ,Clock Divider" "1,2,4,8,16,32,64,128"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TWI_SR,TWI Status Register"
|
|
in
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TWI_IMR,TWI Interrupt Mask Register"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " EOSACC_set/clr ,End Of Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " SCL_WS_set/clr ,Clock Wait State Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " ARBLST_set/clr ,Arbitration Lost Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NACK_set/clr ,Not Acknowledge" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " OVRE_set/clr ,Overrun Error" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " GACC_set/clr ,General Call Access Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " SVACC_set/clr ,Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " TXRDY_set/clr ,Transmit Holding Register Ready" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " RXRDY_set/clr ,Receive Holding Register Ready" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " TXCOMP_set/clr ,Transmission Completed" "Disabled,Enabled"
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "TWI_RHR,TWI Receive Holding Register"
|
|
in
|
|
sif cpuis("ATSAM4S*")
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
endif
|
|
sif cpuis("ATSAM4E*")
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TWI_WPROT_MODE,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " SECURITY_CODE ,Write protection mode security code"
|
|
bitfld.long 0x00 0. " WPROT ,Write protection bit" "Disabled,Enabled"
|
|
sif (cpu()=="ATSAMG5*")
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "TWI_WPROT_STATUS,TWI Write Protection Status Register"
|
|
in
|
|
endif
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree "TWI0 PDC (Peripheral DMA Controller)"
|
|
width 10.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "TWI0_RPR,Receive Pointer Register"
|
|
line.long 0x04 "TWI0_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "TWI0_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "TWI0_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "TWI0_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "TWI0_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "TWI0_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "TWI0_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "TWI0_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "TWI0_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "TWI1"
|
|
base ad:0x400AC000
|
|
width 16.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TWI_CR,TWI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS Quick Command" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SVDIS ,TWI Slave Mode Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 4. " SVEN ,TWI Slave Mode Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSDIS ,TWI Master Transfer Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 2. " MSEN ,TWI Master Transfer Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP Condition" "No effect,Stop"
|
|
bitfld.long 0x00 0. " START ,Send a START Condition" "No effect,Start"
|
|
sif ((cpu()!="ATSAMG5*")||cpuis("ATSAM4S*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
endif
|
|
sif (cpuis("ATSAM4S*"))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR ,Slave Address"
|
|
endif
|
|
if (((d.l((ad:0x400AC000+0x04)))&0x300)==0x300)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x400AC000+0x04)))&0x300)==0x200)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x400AC000+0x04)))&0x300)==0x100)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IADR ,Internal Address"
|
|
else
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
endif
|
|
sif cpuis("ATSAM4S*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
sif cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 24.--28. " HOLD ,TWD Hold Time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16.--18. " CKDIV ,Clock Divider" "1,2,4,8,16,32,64,128"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TWI_SR,TWI Status Register"
|
|
in
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TWI_IMR,TWI Interrupt Mask Register"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " EOSACC_set/clr ,End Of Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " SCL_WS_set/clr ,Clock Wait State Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " ARBLST_set/clr ,Arbitration Lost Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NACK_set/clr ,Not Acknowledge" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " OVRE_set/clr ,Overrun Error" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " GACC_set/clr ,General Call Access Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " SVACC_set/clr ,Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " TXRDY_set/clr ,Transmit Holding Register Ready" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " RXRDY_set/clr ,Receive Holding Register Ready" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " TXCOMP_set/clr ,Transmission Completed" "Disabled,Enabled"
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "TWI_RHR,TWI Receive Holding Register"
|
|
in
|
|
sif cpuis("ATSAM4S*")
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
endif
|
|
sif cpuis("ATSAM4E*")
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TWI_WPROT_MODE,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " SECURITY_CODE ,Write protection mode security code"
|
|
bitfld.long 0x00 0. " WPROT ,Write protection bit" "Disabled,Enabled"
|
|
sif (cpu()=="ATSAMG5*")
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "TWI_WPROT_STATUS,TWI Write Protection Status Register"
|
|
in
|
|
endif
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree "TWI1 PDC (Peripheral DMA Controller)"
|
|
width 10.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "TWI1_RPR,Receive Pointer Register"
|
|
line.long 0x04 "TWI1_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "TWI1_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "TWI1_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "TWI1_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "TWI1_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "TWI1_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "TWI1_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "TWI1_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "TWI1_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree.open "UART (Universal Asynchronous Receiver Transmitter)"
|
|
tree "UART0"
|
|
base ad:0x400E0600
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,UART Control Register"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,UART Mode Register"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal Mode,Automatic Echo,Local Loopback,Remote Loopback"
|
|
sif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*")||cpuis("ATSAM4S*"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Space,Mark,No,?..."
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Space,Mark,No,No,No,No"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IMR,UART Interrupt Mask Register"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36"))
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,RXBUFF Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,TXBUFE Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36"))
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Masked,Not masked"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "SR,UART Status Register"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RHR,UART Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "THR,Transmitter Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "BRGR,UART Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
width 0x0B
|
|
tree "UART0 PDC (Peripheral DMA Controller)"
|
|
width 11.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "UART0_RPR,Receive Pointer Register"
|
|
line.long 0x04 "UART0_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "UART0_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "UART0_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "UART0_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "UART0_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "UART0_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "UART0_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "UART0_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "UART0_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "UART1"
|
|
base ad:0x40060600
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,UART Control Register"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,UART Mode Register"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal Mode,Automatic Echo,Local Loopback,Remote Loopback"
|
|
sif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*")||cpuis("ATSAM4S*"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Space,Mark,No,?..."
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Space,Mark,No,No,No,No"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IMR,UART Interrupt Mask Register"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36"))
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,RXBUFF Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,TXBUFE Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36"))
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Masked,Not masked"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "SR,UART Status Register"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RHR,UART Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "THR,Transmitter Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "BRGR,UART Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
width 0x0B
|
|
tree "UART1 PDC (Peripheral DMA Controller)"
|
|
width 11.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "UART1_RPR,Receive Pointer Register"
|
|
line.long 0x04 "UART1_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "UART1_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "UART1_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "UART1_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "UART1_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "UART1_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "UART1_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "UART1_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "UART1_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree.open "USART (Universal Synchronous Asynchronous Receiver Transmitter)"
|
|
tree "USART0"
|
|
base ad:0x400A0000
|
|
width 10.
|
|
if ((d.l((ad:0x400A0000)+0x4)&0xF)==(0xE||0xF))
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
sif (!cpuis("AT91SAM3N*")&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Slave Select Line NSS = 0"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("AT91SAM3N*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
if ((d.l((ad:0x400A0000+0x04))&0x0f)==(0x0e||0x0f))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*")&&!cpuis("ATSAMA5D36"))
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
else
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-Low,Inactive-High"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))||(cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
sif cpuis("ATSAM4E*")||cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
else
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
elif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" ",,,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
elif ((d.l((ad:0x400A0000+0x04))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,1.5,2,?..."
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
endif
|
|
if (((d.l((ad:0x400A0000+0x4))&0x1f)==0xE)||(d.l((ad:0x400A0000+0x4))&0x1f)==0xF)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
sif (cpuis("AT91SAM3N*"))
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 31. -0x8 31. -0x4 31. " LINHTE_set/clr ,LIN Header Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x8 30. -0x4 30. " LINSTE_set/clr ,LIN Sync Tolerance Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Sync Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANEA_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*"))
|
|
sif !cpuis("ATSAM4N*")
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Max number of Repetitions Reached/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
elif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " UNRE_set/clr ,SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*"))
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
sif (cpuis("AT91SAM3N*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 31. -0x8 31. -0x4 31. " LINHTE_set/clr ,LIN Header Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x8 30. -0x4 30. " LINSTE_set/clr ,LIN Sync Tolerance Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Sync Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANEA_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAMA5D3*"))
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Max number of Repetitions Reached/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER_set/clr ,Max number of Repetitions Reached Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*")&&!cpuis("ATSAMA5D3*"))
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x0 "US_CSR,Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "US_RHR,Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US_THR,Transmitter Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20--0x2b
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1 x 1/8,2 x 1/8,3 x 1/8,4 x 1/8,5 x 1/8,6 x 1/8,7 x 1/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US_RTOR,Receiver Time-out Register"
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
else
|
|
hexmask.long.tbyte 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
endif
|
|
line.long 0x08 "US_TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,FI DI Ratio Register"
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
else
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("ATSAM4N*"))
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US_NER,Number of Errors Register"
|
|
in
|
|
else
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "US_NER,Number of Errors Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NB_ERRORS ,Number of Errors"
|
|
endif
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
width 10.
|
|
sif (!cpuis("AT91SAM3N*")&&!cpuis("ATSAM4N*"))
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT , Drift Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RX_MPOL , Receiver Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 24.--25. " RX_PP , Receiver Preamble Pattern Detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " RX_PL , Receiver Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
bitfld.long 0x00 12. " TX_MPOL , Transmitter Manchester Polarity" "0-to-1,1-to-0"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX_PP , Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 0.--3. " TX_PL , Transmitter Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long 0x54++0x7
|
|
line.long 0x00 "US_LINMR,USART LIN Mode Register"
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 17. " SYNCDIS ,Synchronization Disable" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " PDCM ,PDC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data Length Control"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "2.0,1.3"
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,4 and 5 bits Identifier"
|
|
else
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,5 and 6 bits Identifier"
|
|
endif
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "Enhanced,Classic"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "PUBLISH,SUBSCRIBE,IGNORE,?..."
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
line.long 0x04 "US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
if ((d.l(ad:0x400A0000+0x58)&0x0A)==0x0A)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "LINIR,LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "LINIR,LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "LINBRR,LIN Baud Rate Register"
|
|
bitfld.long 0x00 16.--18. " LINFP ,LIN Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--15. 1. " LINCD ,LIN Clock Divider after Synchronization"
|
|
endif
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "US_WPSR,USART Write Protect Status Register"
|
|
in
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*")&&!cpuis("AT91SAM3N*")&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
hgroup.long 0xec++0x3
|
|
hide.long 0x00 "US_VERSION,USART Version Register"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "VERSION,Version Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION ,Version number"
|
|
endif
|
|
width 0xb
|
|
tree "USART0 PDC (Peripheral DMA Controller)"
|
|
width 11.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "USART0_RPR,Receive Pointer Register"
|
|
line.long 0x04 "USART0_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART0_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "USART0_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART0_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "USART0_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART0_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "USART0_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART0_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART0_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "USART1"
|
|
base ad:0x400A4000
|
|
width 10.
|
|
if ((d.l((ad:0x400A4000)+0x4)&0xF)==(0xE||0xF))
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
sif (!cpuis("AT91SAM3N*")&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Slave Select Line NSS = 0"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("AT91SAM3N*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
if ((d.l((ad:0x400A4000+0x04))&0x0f)==(0x0e||0x0f))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*")&&!cpuis("ATSAMA5D36"))
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
else
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-Low,Inactive-High"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))||(cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
sif cpuis("ATSAM4E*")||cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
else
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
elif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" ",,,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
elif ((d.l((ad:0x400A4000+0x04))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,1.5,2,?..."
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
endif
|
|
if (((d.l((ad:0x400A4000+0x4))&0x1f)==0xE)||(d.l((ad:0x400A4000+0x4))&0x1f)==0xF)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
sif (cpuis("AT91SAM3N*"))
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 31. -0x8 31. -0x4 31. " LINHTE_set/clr ,LIN Header Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x8 30. -0x4 30. " LINSTE_set/clr ,LIN Sync Tolerance Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Sync Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANEA_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*"))
|
|
sif !cpuis("ATSAM4N*")
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Max number of Repetitions Reached/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
elif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " UNRE_set/clr ,SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*"))
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
sif (cpuis("AT91SAM3N*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 31. -0x8 31. -0x4 31. " LINHTE_set/clr ,LIN Header Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x8 30. -0x4 30. " LINSTE_set/clr ,LIN Sync Tolerance Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Sync Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANEA_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAMA5D3*"))
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Max number of Repetitions Reached/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER_set/clr ,Max number of Repetitions Reached Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*")&&!cpuis("ATSAMA5D3*"))
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x0 "US_CSR,Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "US_RHR,Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US_THR,Transmitter Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20--0x2b
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1 x 1/8,2 x 1/8,3 x 1/8,4 x 1/8,5 x 1/8,6 x 1/8,7 x 1/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US_RTOR,Receiver Time-out Register"
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
else
|
|
hexmask.long.tbyte 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
endif
|
|
line.long 0x08 "US_TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,FI DI Ratio Register"
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
else
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("ATSAM4N*"))
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US_NER,Number of Errors Register"
|
|
in
|
|
else
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "US_NER,Number of Errors Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NB_ERRORS ,Number of Errors"
|
|
endif
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
width 10.
|
|
sif (!cpuis("AT91SAM3N*")&&!cpuis("ATSAM4N*"))
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT , Drift Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RX_MPOL , Receiver Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 24.--25. " RX_PP , Receiver Preamble Pattern Detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " RX_PL , Receiver Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
bitfld.long 0x00 12. " TX_MPOL , Transmitter Manchester Polarity" "0-to-1,1-to-0"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX_PP , Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 0.--3. " TX_PL , Transmitter Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long 0x54++0x7
|
|
line.long 0x00 "US_LINMR,USART LIN Mode Register"
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 17. " SYNCDIS ,Synchronization Disable" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " PDCM ,PDC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data Length Control"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "2.0,1.3"
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,4 and 5 bits Identifier"
|
|
else
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,5 and 6 bits Identifier"
|
|
endif
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "Enhanced,Classic"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "PUBLISH,SUBSCRIBE,IGNORE,?..."
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
line.long 0x04 "US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
if ((d.l(ad:0x400A4000+0x58)&0x0A)==0x0A)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "LINIR,LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "LINIR,LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "LINBRR,LIN Baud Rate Register"
|
|
bitfld.long 0x00 16.--18. " LINFP ,LIN Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--15. 1. " LINCD ,LIN Clock Divider after Synchronization"
|
|
endif
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "US_WPSR,USART Write Protect Status Register"
|
|
in
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*")&&!cpuis("AT91SAM3N*")&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
hgroup.long 0xec++0x3
|
|
hide.long 0x00 "US_VERSION,USART Version Register"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "VERSION,Version Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION ,Version number"
|
|
endif
|
|
width 0xb
|
|
tree "USART1 PDC (Peripheral DMA Controller)"
|
|
width 11.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "USART1_RPR,Receive Pointer Register"
|
|
line.long 0x04 "USART1_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART1_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "USART1_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART1_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "USART1_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART1_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "USART1_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART1_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART1_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree.open "TC (Timer Counter)"
|
|
tree "TC0"
|
|
base ad:0x40090000
|
|
width 0x8
|
|
tree "Block Registers"
|
|
wgroup.long 0xc0++0x03
|
|
line.long 0x00 "TC_BCR,TC Block Control Register"
|
|
bitfld.long 0x00 0. " SYNC , Synchro Command" "No effect,Asserted"
|
|
group.long 0xc4++0x03
|
|
line.long 0x00 "TC_BMR,TC Block Mode Register"
|
|
bitfld.long 0x00 20.--25. " MAXFILT ,Maximum Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 19. " FILTER ,IDX,PHA ,IDX,PHA ,IDX,PHA, PHB input pins filter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IDXPHB ,Index pin is PHB pin" "TIOA1,TIOB0"
|
|
bitfld.long 0x00 16. " SWAP ,SWAP PHA and PHB" "No swap,Swap"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INVIDX ,Inverted Index" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " INVB ,Inverted PHB" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INVA ,Inverted PHA" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " EDGPHA ,Edge on PHA count mode" "PHA and PHB,PHA only"
|
|
textline " "
|
|
bitfld.long 0x00 11. " QDTRANS ,Quadrature Decoding Transparent" "Full,Transparent"
|
|
bitfld.long 0x00 10. " SPEEDEN ,Speed Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " POSEN ,Position Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " QDEN ,Quadrature Decoder Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External Clock Signal 2 Selection" "TCLK0,,TCLK1,TCLK2"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External Clock Signal 1 Selection" "TCLK0,,TCLK1,TCLK2"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External Clock Signal 0 Selection" "TCLK0,,TCLK1,TCLK2"
|
|
group.long 0xd0++0x3
|
|
line.long 0x00 "TC_QIMR,TC QDEC Interrupt Mask Register"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " IDX_set/clr ,Index" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " DIRCHG_set/clr ,Direction Change" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " QERR_set/clr ,Quadrature Error" "Disabled,Enabled"
|
|
hgroup.long 0xd4++0x3
|
|
hide.long 0x00 "TC_QISR,TC QDEC Interrupt Status Register"
|
|
in
|
|
sif (!cpuis("AT91SAM3N*"))
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "TC_FMR,TC Fault Mode Register"
|
|
bitfld.long 0x00 1. " ENCF1 ,Enable Compare Fault Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCF0 ,Enable Compare Fault Channel 0" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "TC_WPMR,TC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 0x9
|
|
sif cpuis("AT91SAM3N*A")
|
|
tree "TC Channel 0"
|
|
wgroup.long (0x0+0x00)++0x03
|
|
line.long 0x00 "TC0_CCR,TC0 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40090000+0x0+0x4)))&0x8000)==0x8000)
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register 0"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "TC0_CV,TC0 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (((data.long((ad:0x40090000+0x0+0x4)))&0x8000)==0x8000)
|
|
group.long (0x0+0x14)++0x7
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
group.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "TC0_RC,TC0 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
hgroup.long (0x0+0x20)++0x03
|
|
hide.long 0x00 "TC0_SR,TC0 Status Register"
|
|
in
|
|
group.long (0x0+0x2C)++0x03
|
|
line.long 0x00 "TC0_IMR,TC0 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 1"
|
|
wgroup.long (0x40+0x00)++0x03
|
|
line.long 0x00 "TC1_CCR,TC1 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40090000+0x40+0x4)))&0x8000)==0x8000)
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TC_SMMR1,TC Stepper Motor Mode Register 1"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "TC1_CV,TC1 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (((data.long((ad:0x40090000+0x40+0x4)))&0x8000)==0x8000)
|
|
group.long (0x40+0x14)++0x7
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "TC1_RC,TC1 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
hgroup.long (0x40+0x20)++0x03
|
|
hide.long 0x00 "TC1_SR,TC1 Status Register"
|
|
in
|
|
group.long (0x40+0x2C)++0x03
|
|
line.long 0x00 "TC1_IMR,TC1 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
else
|
|
tree "TC Channel 0"
|
|
wgroup.long (0x0+0x00)++0x03
|
|
line.long 0x00 "TC0_CCR,TC0 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40090000+0x0+0x4)))&0x8000)==0x8000)
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register 0"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
rgroup.long (0x0+0x0C)++0x07
|
|
line.long 0x00 "TC_RAB0,TC0 Register AB"
|
|
line.long 0x04 "TC_CV0,TC0 Counter Value Register"
|
|
else
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "TC0_CV,TC0 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40090000+0x0+0x4)))&0x8000)==0x8000)
|
|
group.long (0x0+0x14)++0x7
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
endif
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
endif
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
group.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "TC0_RC,TC0 Register C"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x0+0x20)++0x03
|
|
hide.long 0x00 "TC0_SR,TC0 Status Register"
|
|
in
|
|
group.long (0x0+0x2C)++0x03
|
|
line.long 0x00 "TC0_IMR,TC0 Interrupt Mask Register"
|
|
sif cpuis("ATSAM4E*")
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RXBUFF_set/clr ,Reception Buffer Full" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ENDRX_set/clr ,End of Receiver Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
group.long (0x0+0x30)++0x03
|
|
line.long 0x00 "TC_EMR0,TC0 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No Divided Clock" "TCCLKS defined,MCK"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger Source for Input B" "EXTERNAL_TIOB0,PWM0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger Source for Input A" "EXTERNAL_TIOA0,PWM0,?..."
|
|
endif
|
|
tree.end
|
|
tree "TC Channel 1"
|
|
wgroup.long (0x40+0x00)++0x03
|
|
line.long 0x00 "TC1_CCR,TC1 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40090000+0x40+0x4)))&0x8000)==0x8000)
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TC_SMMR1,TC Stepper Motor Mode Register 1"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
rgroup.long (0x40+0x0C)++0x07
|
|
line.long 0x00 "TC_RAB1,TC1 Register AB"
|
|
line.long 0x04 "TC_CV1,TC1 Counter Value Register"
|
|
else
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "TC1_CV,TC1 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40090000+0x40+0x4)))&0x8000)==0x8000)
|
|
group.long (0x40+0x14)++0x7
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
endif
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
endif
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "TC1_RC,TC1 Register C"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x40+0x20)++0x03
|
|
hide.long 0x00 "TC1_SR,TC1 Status Register"
|
|
in
|
|
group.long (0x40+0x2C)++0x03
|
|
line.long 0x00 "TC1_IMR,TC1 Interrupt Mask Register"
|
|
sif cpuis("ATSAM4E*")
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RXBUFF_set/clr ,Reception Buffer Full" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ENDRX_set/clr ,End of Receiver Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
group.long (0x40+0x30)++0x03
|
|
line.long 0x00 "TC_EMR1,TC1 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No Divided Clock" "TCCLKS defined,MCK"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger Source for Input B" "EXTERNAL_TIOB1,PWM1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger Source for Input A" "EXTERNAL_TIOA1,PWM1,?..."
|
|
endif
|
|
tree.end
|
|
tree "TC Channel 2"
|
|
wgroup.long (0x80+0x00)++0x03
|
|
line.long 0x00 "TC2_CCR,TC2 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40090000+0x80+0x4)))&0x8000)==0x8000)
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "TC_SMMR2,TC Stepper Motor Mode Register 2"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
rgroup.long (0x80+0x0C)++0x07
|
|
line.long 0x00 "TC_RAB2,TC2 Register AB"
|
|
line.long 0x04 "TC_CV2,TC2 Counter Value Register"
|
|
else
|
|
rgroup.long (0x80+0x10)++0x03
|
|
line.long 0x00 "TC2_CV,TC2 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40090000+0x80+0x4)))&0x8000)==0x8000)
|
|
group.long (0x80+0x14)++0x7
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
endif
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
endif
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
group.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "TC2_RC,TC2 Register C"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x80+0x20)++0x03
|
|
hide.long 0x00 "TC2_SR,TC2 Status Register"
|
|
in
|
|
group.long (0x80+0x2C)++0x03
|
|
line.long 0x00 "TC2_IMR,TC2 Interrupt Mask Register"
|
|
sif cpuis("ATSAM4E*")
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RXBUFF_set/clr ,Reception Buffer Full" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ENDRX_set/clr ,End of Receiver Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
group.long (0x80+0x30)++0x03
|
|
line.long 0x00 "TC_EMR2,TC2 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No Divided Clock" "TCCLKS defined,MCK"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger Source for Input B" "EXTERNAL_TIOB2,PWM2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger Source for Input A" "EXTERNAL_TIOA2,PWM2,?..."
|
|
endif
|
|
tree.end
|
|
endif
|
|
width 0xB
|
|
tree "TC0 PDC (Peripheral DMA Controller)"
|
|
width 8.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "TC0_RPR,Receive Pointer Register"
|
|
line.long 0x04 "TC0_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "TC0_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "TC0_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "TC0_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "TC0_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "TC0_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "TC0_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "TC0_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "TC0_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "TC1"
|
|
base ad:0x40094000
|
|
width 0x8
|
|
tree "Block Registers"
|
|
wgroup.long 0xc0++0x03
|
|
line.long 0x00 "TC_BCR,TC Block Control Register"
|
|
bitfld.long 0x00 0. " SYNC , Synchro Command" "No effect,Asserted"
|
|
group.long 0xc4++0x03
|
|
line.long 0x00 "TC_BMR,TC Block Mode Register"
|
|
bitfld.long 0x00 20.--25. " MAXFILT ,Maximum Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 19. " FILTER ,IDX,PHA ,IDX,PHA ,IDX,PHA, PHB input pins filter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IDXPHB ,Index pin is PHB pin" "TIOA1,TIOB0"
|
|
bitfld.long 0x00 16. " SWAP ,SWAP PHA and PHB" "No swap,Swap"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INVIDX ,Inverted Index" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " INVB ,Inverted PHB" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INVA ,Inverted PHA" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " EDGPHA ,Edge on PHA count mode" "PHA and PHB,PHA only"
|
|
textline " "
|
|
bitfld.long 0x00 11. " QDTRANS ,Quadrature Decoding Transparent" "Full,Transparent"
|
|
bitfld.long 0x00 10. " SPEEDEN ,Speed Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " POSEN ,Position Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " QDEN ,Quadrature Decoder Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External Clock Signal 2 Selection" "TCLK0,,TCLK1,TCLK2"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External Clock Signal 1 Selection" "TCLK0,,TCLK1,TCLK2"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External Clock Signal 0 Selection" "TCLK0,,TCLK1,TCLK2"
|
|
group.long 0xd0++0x3
|
|
line.long 0x00 "TC_QIMR,TC QDEC Interrupt Mask Register"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " IDX_set/clr ,Index" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " DIRCHG_set/clr ,Direction Change" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " QERR_set/clr ,Quadrature Error" "Disabled,Enabled"
|
|
hgroup.long 0xd4++0x3
|
|
hide.long 0x00 "TC_QISR,TC QDEC Interrupt Status Register"
|
|
in
|
|
sif (!cpuis("AT91SAM3N*"))
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "TC_FMR,TC Fault Mode Register"
|
|
bitfld.long 0x00 1. " ENCF1 ,Enable Compare Fault Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCF0 ,Enable Compare Fault Channel 0" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "TC_WPMR,TC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 0x9
|
|
sif cpuis("AT91SAM3N*A")
|
|
tree "TC Channel 0"
|
|
wgroup.long (0x0+0x00)++0x03
|
|
line.long 0x00 "TC0_CCR,TC0 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40094000+0x0+0x4)))&0x8000)==0x8000)
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register 0"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "TC0_CV,TC0 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (((data.long((ad:0x40094000+0x0+0x4)))&0x8000)==0x8000)
|
|
group.long (0x0+0x14)++0x7
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
group.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "TC0_RC,TC0 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
hgroup.long (0x0+0x20)++0x03
|
|
hide.long 0x00 "TC0_SR,TC0 Status Register"
|
|
in
|
|
group.long (0x0+0x2C)++0x03
|
|
line.long 0x00 "TC0_IMR,TC0 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 1"
|
|
wgroup.long (0x40+0x00)++0x03
|
|
line.long 0x00 "TC1_CCR,TC1 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40094000+0x40+0x4)))&0x8000)==0x8000)
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TC_SMMR1,TC Stepper Motor Mode Register 1"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "TC1_CV,TC1 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (((data.long((ad:0x40094000+0x40+0x4)))&0x8000)==0x8000)
|
|
group.long (0x40+0x14)++0x7
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "TC1_RC,TC1 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
hgroup.long (0x40+0x20)++0x03
|
|
hide.long 0x00 "TC1_SR,TC1 Status Register"
|
|
in
|
|
group.long (0x40+0x2C)++0x03
|
|
line.long 0x00 "TC1_IMR,TC1 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
else
|
|
tree "TC Channel 0"
|
|
wgroup.long (0x0+0x00)++0x03
|
|
line.long 0x00 "TC0_CCR,TC0 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40094000+0x0+0x4)))&0x8000)==0x8000)
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register 0"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
rgroup.long (0x0+0x0C)++0x07
|
|
line.long 0x00 "TC_RAB0,TC0 Register AB"
|
|
line.long 0x04 "TC_CV0,TC0 Counter Value Register"
|
|
else
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "TC0_CV,TC0 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40094000+0x0+0x4)))&0x8000)==0x8000)
|
|
group.long (0x0+0x14)++0x7
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
endif
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
endif
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
group.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "TC0_RC,TC0 Register C"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x0+0x20)++0x03
|
|
hide.long 0x00 "TC0_SR,TC0 Status Register"
|
|
in
|
|
group.long (0x0+0x2C)++0x03
|
|
line.long 0x00 "TC0_IMR,TC0 Interrupt Mask Register"
|
|
sif cpuis("ATSAM4E*")
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RXBUFF_set/clr ,Reception Buffer Full" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ENDRX_set/clr ,End of Receiver Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
group.long (0x0+0x30)++0x03
|
|
line.long 0x00 "TC_EMR0,TC0 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No Divided Clock" "TCCLKS defined,MCK"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger Source for Input B" "EXTERNAL_TIOB0,PWM0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger Source for Input A" "EXTERNAL_TIOA0,PWM0,?..."
|
|
endif
|
|
tree.end
|
|
tree "TC Channel 1"
|
|
wgroup.long (0x40+0x00)++0x03
|
|
line.long 0x00 "TC1_CCR,TC1 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40094000+0x40+0x4)))&0x8000)==0x8000)
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TC_SMMR1,TC Stepper Motor Mode Register 1"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
rgroup.long (0x40+0x0C)++0x07
|
|
line.long 0x00 "TC_RAB1,TC1 Register AB"
|
|
line.long 0x04 "TC_CV1,TC1 Counter Value Register"
|
|
else
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "TC1_CV,TC1 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40094000+0x40+0x4)))&0x8000)==0x8000)
|
|
group.long (0x40+0x14)++0x7
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
endif
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
endif
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "TC1_RC,TC1 Register C"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x40+0x20)++0x03
|
|
hide.long 0x00 "TC1_SR,TC1 Status Register"
|
|
in
|
|
group.long (0x40+0x2C)++0x03
|
|
line.long 0x00 "TC1_IMR,TC1 Interrupt Mask Register"
|
|
sif cpuis("ATSAM4E*")
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RXBUFF_set/clr ,Reception Buffer Full" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ENDRX_set/clr ,End of Receiver Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
group.long (0x40+0x30)++0x03
|
|
line.long 0x00 "TC_EMR1,TC1 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No Divided Clock" "TCCLKS defined,MCK"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger Source for Input B" "EXTERNAL_TIOB1,PWM1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger Source for Input A" "EXTERNAL_TIOA1,PWM1,?..."
|
|
endif
|
|
tree.end
|
|
tree "TC Channel 2"
|
|
wgroup.long (0x80+0x00)++0x03
|
|
line.long 0x00 "TC2_CCR,TC2 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40094000+0x80+0x4)))&0x8000)==0x8000)
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "TC_SMMR2,TC Stepper Motor Mode Register 2"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
rgroup.long (0x80+0x0C)++0x07
|
|
line.long 0x00 "TC_RAB2,TC2 Register AB"
|
|
line.long 0x04 "TC_CV2,TC2 Counter Value Register"
|
|
else
|
|
rgroup.long (0x80+0x10)++0x03
|
|
line.long 0x00 "TC2_CV,TC2 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40094000+0x80+0x4)))&0x8000)==0x8000)
|
|
group.long (0x80+0x14)++0x7
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
endif
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
endif
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
group.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "TC2_RC,TC2 Register C"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x80+0x20)++0x03
|
|
hide.long 0x00 "TC2_SR,TC2 Status Register"
|
|
in
|
|
group.long (0x80+0x2C)++0x03
|
|
line.long 0x00 "TC2_IMR,TC2 Interrupt Mask Register"
|
|
sif cpuis("ATSAM4E*")
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RXBUFF_set/clr ,Reception Buffer Full" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ENDRX_set/clr ,End of Receiver Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
group.long (0x80+0x30)++0x03
|
|
line.long 0x00 "TC_EMR2,TC2 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No Divided Clock" "TCCLKS defined,MCK"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger Source for Input B" "EXTERNAL_TIOB2,PWM2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger Source for Input A" "EXTERNAL_TIOA2,PWM2,?..."
|
|
endif
|
|
tree.end
|
|
endif
|
|
width 0xB
|
|
tree "TC1 PDC (Peripheral DMA Controller)"
|
|
width 8.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "TC1_RPR,Receive Pointer Register"
|
|
line.long 0x04 "TC1_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "TC1_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "TC1_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "TC1_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "TC1_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "TC1_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "TC1_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "TC1_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "TC1_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "TC2"
|
|
base ad:0x40098000
|
|
width 0x8
|
|
tree "Block Registers"
|
|
wgroup.long 0xc0++0x03
|
|
line.long 0x00 "TC_BCR,TC Block Control Register"
|
|
bitfld.long 0x00 0. " SYNC , Synchro Command" "No effect,Asserted"
|
|
group.long 0xc4++0x03
|
|
line.long 0x00 "TC_BMR,TC Block Mode Register"
|
|
bitfld.long 0x00 20.--25. " MAXFILT ,Maximum Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 19. " FILTER ,IDX,PHA ,IDX,PHA ,IDX,PHA, PHB input pins filter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IDXPHB ,Index pin is PHB pin" "TIOA1,TIOB0"
|
|
bitfld.long 0x00 16. " SWAP ,SWAP PHA and PHB" "No swap,Swap"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INVIDX ,Inverted Index" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " INVB ,Inverted PHB" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INVA ,Inverted PHA" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " EDGPHA ,Edge on PHA count mode" "PHA and PHB,PHA only"
|
|
textline " "
|
|
bitfld.long 0x00 11. " QDTRANS ,Quadrature Decoding Transparent" "Full,Transparent"
|
|
bitfld.long 0x00 10. " SPEEDEN ,Speed Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " POSEN ,Position Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " QDEN ,Quadrature Decoder Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External Clock Signal 2 Selection" "TCLK0,,TCLK1,TCLK2"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External Clock Signal 1 Selection" "TCLK0,,TCLK1,TCLK2"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External Clock Signal 0 Selection" "TCLK0,,TCLK1,TCLK2"
|
|
group.long 0xd0++0x3
|
|
line.long 0x00 "TC_QIMR,TC QDEC Interrupt Mask Register"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " IDX_set/clr ,Index" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " DIRCHG_set/clr ,Direction Change" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " QERR_set/clr ,Quadrature Error" "Disabled,Enabled"
|
|
hgroup.long 0xd4++0x3
|
|
hide.long 0x00 "TC_QISR,TC QDEC Interrupt Status Register"
|
|
in
|
|
sif (!cpuis("AT91SAM3N*"))
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "TC_FMR,TC Fault Mode Register"
|
|
bitfld.long 0x00 1. " ENCF1 ,Enable Compare Fault Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCF0 ,Enable Compare Fault Channel 0" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "TC_WPMR,TC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 0x9
|
|
sif cpuis("AT91SAM3N*A")
|
|
tree "TC Channel 0"
|
|
wgroup.long (0x0+0x00)++0x03
|
|
line.long 0x00 "TC0_CCR,TC0 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40098000+0x0+0x4)))&0x8000)==0x8000)
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register 0"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "TC0_CV,TC0 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (((data.long((ad:0x40098000+0x0+0x4)))&0x8000)==0x8000)
|
|
group.long (0x0+0x14)++0x7
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
group.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "TC0_RC,TC0 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
hgroup.long (0x0+0x20)++0x03
|
|
hide.long 0x00 "TC0_SR,TC0 Status Register"
|
|
in
|
|
group.long (0x0+0x2C)++0x03
|
|
line.long 0x00 "TC0_IMR,TC0 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 1"
|
|
wgroup.long (0x40+0x00)++0x03
|
|
line.long 0x00 "TC1_CCR,TC1 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40098000+0x40+0x4)))&0x8000)==0x8000)
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TC_SMMR1,TC Stepper Motor Mode Register 1"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "TC1_CV,TC1 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
if (((data.long((ad:0x40098000+0x40+0x4)))&0x8000)==0x8000)
|
|
group.long (0x40+0x14)++0x7
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "TC1_RC,TC1 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
hgroup.long (0x40+0x20)++0x03
|
|
hide.long 0x00 "TC1_SR,TC1 Status Register"
|
|
in
|
|
group.long (0x40+0x2C)++0x03
|
|
line.long 0x00 "TC1_IMR,TC1 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
else
|
|
tree "TC Channel 0"
|
|
wgroup.long (0x0+0x00)++0x03
|
|
line.long 0x00 "TC0_CCR,TC0 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40098000+0x0+0x4)))&0x8000)==0x8000)
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register 0"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
rgroup.long (0x0+0x0C)++0x07
|
|
line.long 0x00 "TC_RAB0,TC0 Register AB"
|
|
line.long 0x04 "TC_CV0,TC0 Counter Value Register"
|
|
else
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "TC0_CV,TC0 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40098000+0x0+0x4)))&0x8000)==0x8000)
|
|
group.long (0x0+0x14)++0x7
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
endif
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
endif
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
group.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "TC0_RC,TC0 Register C"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x0+0x20)++0x03
|
|
hide.long 0x00 "TC0_SR,TC0 Status Register"
|
|
in
|
|
group.long (0x0+0x2C)++0x03
|
|
line.long 0x00 "TC0_IMR,TC0 Interrupt Mask Register"
|
|
sif cpuis("ATSAM4E*")
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RXBUFF_set/clr ,Reception Buffer Full" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ENDRX_set/clr ,End of Receiver Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
group.long (0x0+0x30)++0x03
|
|
line.long 0x00 "TC_EMR0,TC0 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No Divided Clock" "TCCLKS defined,MCK"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger Source for Input B" "EXTERNAL_TIOB0,PWM0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger Source for Input A" "EXTERNAL_TIOA0,PWM0,?..."
|
|
endif
|
|
tree.end
|
|
tree "TC Channel 1"
|
|
wgroup.long (0x40+0x00)++0x03
|
|
line.long 0x00 "TC1_CCR,TC1 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40098000+0x40+0x4)))&0x8000)==0x8000)
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "TC_SMMR1,TC Stepper Motor Mode Register 1"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
rgroup.long (0x40+0x0C)++0x07
|
|
line.long 0x00 "TC_RAB1,TC1 Register AB"
|
|
line.long 0x04 "TC_CV1,TC1 Counter Value Register"
|
|
else
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "TC1_CV,TC1 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40098000+0x40+0x4)))&0x8000)==0x8000)
|
|
group.long (0x40+0x14)++0x7
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
endif
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
endif
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "TC1_RC,TC1 Register C"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x40+0x20)++0x03
|
|
hide.long 0x00 "TC1_SR,TC1 Status Register"
|
|
in
|
|
group.long (0x40+0x2C)++0x03
|
|
line.long 0x00 "TC1_IMR,TC1 Interrupt Mask Register"
|
|
sif cpuis("ATSAM4E*")
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RXBUFF_set/clr ,Reception Buffer Full" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ENDRX_set/clr ,End of Receiver Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
group.long (0x40+0x30)++0x03
|
|
line.long 0x00 "TC_EMR1,TC1 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No Divided Clock" "TCCLKS defined,MCK"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger Source for Input B" "EXTERNAL_TIOB1,PWM1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger Source for Input A" "EXTERNAL_TIOA1,PWM1,?..."
|
|
endif
|
|
tree.end
|
|
tree "TC Channel 2"
|
|
wgroup.long (0x80+0x00)++0x03
|
|
line.long 0x00 "TC2_CCR,TC2 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40098000+0x80+0x4)))&0x8000)==0x8000)
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "TC_SMMR2,TC Stepper Motor Mode Register 2"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
rgroup.long (0x80+0x0C)++0x07
|
|
line.long 0x00 "TC_RAB2,TC2 Register AB"
|
|
line.long 0x04 "TC_CV2,TC2 Counter Value Register"
|
|
else
|
|
rgroup.long (0x80+0x10)++0x03
|
|
line.long 0x00 "TC2_CV,TC2 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40098000+0x80+0x4)))&0x8000)==0x8000)
|
|
group.long (0x80+0x14)++0x7
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
endif
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
endif
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
group.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "TC2_RC,TC2 Register C"
|
|
sif !cpuis("ATSAM4E*")
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x80+0x20)++0x03
|
|
hide.long 0x00 "TC2_SR,TC2 Status Register"
|
|
in
|
|
group.long (0x80+0x2C)++0x03
|
|
line.long 0x00 "TC2_IMR,TC2 Interrupt Mask Register"
|
|
sif cpuis("ATSAM4E*")
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RXBUFF_set/clr ,Reception Buffer Full" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ENDRX_set/clr ,End of Receiver Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
group.long (0x80+0x30)++0x03
|
|
line.long 0x00 "TC_EMR2,TC2 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No Divided Clock" "TCCLKS defined,MCK"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger Source for Input B" "EXTERNAL_TIOB2,PWM2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger Source for Input A" "EXTERNAL_TIOA2,PWM2,?..."
|
|
endif
|
|
tree.end
|
|
endif
|
|
width 0xB
|
|
tree "TC2 PDC (Peripheral DMA Controller)"
|
|
width 8.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "TC2_RPR,Receive Pointer Register"
|
|
line.long 0x04 "TC2_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "TC2_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "TC2_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "TC2_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "TC2_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "TC2_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "TC2_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "TC2_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "TC2_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree "HSMCI (High Speed MultiMedia Card Interface)"
|
|
base ad:0x40080000
|
|
width 0xd
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "HSMCI_CR,MCI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 3. " PWSDIS ,Power Save Mode Disable" "No effect,Disables"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PWSEN ,Power Save Mode Enable" "No effect,Enables"
|
|
bitfld.long 0x00 1. " HSMCIDIS ,Multi-Media Interface Disable" "No effect,Disables"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MCIEN ,Multi-Media Interface Enable" "No effect,Enables"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "HSMCI_MR,MCI Mode Register"
|
|
sif (cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 16. " CLKODD ,Clock divider is odd" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PDCMODE ,PDC-oriented Mode" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("ATSAM4S*"))
|
|
bitfld.long 0x00 15. " PDCMODE ,PDC-oriented Mode" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
hexmask.long.word 0x00 16.--31. 1. " BLKLEN ,Data Block Length"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " PADV ,Padding Value" "0x00,0xFF"
|
|
bitfld.long 0x00 13. " FBYTE ,Force Byte Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " WRPROOF ,Write Proof Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RDPROOF ,Read Proof Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PWSDIV ,Power Saving Divider" "Clock/2,Clock/3,Clock/5,Clock/9,Clock/17,Clock/33,Clock/65,Clock/129"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLKDIV ,Clock Divider"
|
|
group.long 0x08++0xb
|
|
line.long 0x0 "HSMCI_DTOR,MCI Data Timeout Register"
|
|
bitfld.long 0x0 4.--6. " DTOMUL ,Data Timeout Multiplier" "1,16,128,256,1024,4096,65536,1048576"
|
|
bitfld.long 0x0 0.--3. " DTOCYC ,Data Timeout Cycle Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "HSMCI_SDCR,MCI SDCard Register"
|
|
bitfld.long 0x04 6.--7. " SDCBUS ,SDCard Bus Width" "1-bit,,4-bit,8-bit"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x04 0.--1. " SDCSEL ,SDCard Slot" "A,B,?..."
|
|
else
|
|
bitfld.long 0x04 0.--1. " SDCSEL ,SDCard Slot" "A,?..."
|
|
endif
|
|
line.long 0x08 "HSMCI_ARGR,MCI Argument Register"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "HSMCI_CMDR,MCI Command Register"
|
|
bitfld.long 0x00 27. " BOOT_ACK ,Boot Operation Acknowledge" "Not expected,Expect"
|
|
textline " "
|
|
bitfld.long 0x00 26. " ATACS ,ATA with Command Completion Signal" "Normal,With completion"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " IOSPCMD ,SDIO Special Command" "No SDIO Special,SDIO Suspend,SDIO Resume,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " TRTYP ,Transfer Type" "Single Block,Multiple Block,Stream,,SDIO Byte,SDIO Block,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " TRDIR ,Transfer Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " TRCMD ,Transfer Command" "No transferred,Start,Stop,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12. " MAXLAT ,Max Latency for Command to Response" "5-cycle,64-cycle"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPDCMD ,Open Drain Command" "Push pull,Open drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " SPCMD ,Special Command" "Not special,Initialization,Synchronize,CE-ATA Completion Signal disable,Interrupt command,Interrupt response,Boot Operation Request,End Boot Operation"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " RSPTYP ,Response Type" "No response,48-bit,136-bit,R1b"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " CMDNB ,Command Number"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "HSMCI_BLKR,Block Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BLKLEN ,Data Block Length"
|
|
hexmask.long.word 0x00 0.--15. 1. " BCNT ,MMC/SDIO Block Count - SDIO Byte Count"
|
|
line.long 0x04 "HSMCI_CSTOR,HSMCI Completion Signal Timeout Register"
|
|
bitfld.long 0x04 4.--6. " CSTOMUL ,Completion Signal Timeout Multiplier" "1,16,128,256,1024,4096,65536,1048576"
|
|
bitfld.long 0x04 0.--3. " CSTOCYC ,Completion Signal Timeout Cycle Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x20++0xF
|
|
line.long 0x00 "HSMCI_RSPR0,MCI Response Register 0"
|
|
line.long 0x04 "HSMCI_RSPR1,MCI Response Register 1"
|
|
line.long 0x08 "HSMCI_RSPR2,MCI Response Register 2"
|
|
line.long 0x0c "HSMCI_RSPR3,MCI Response Register 3"
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x0 "HSMCI_RDR,MCI Receive Data Register"
|
|
in
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "HSMCI_TDR,MCI Transmit Data Register"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "HSMCI_SR,MCI Status Register"
|
|
in
|
|
group.long 0x4c++0x3
|
|
line.long 0x0 "HSMCI_IMR,MCI Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x08 31. -0x4 31. " UNRE_set/clr ,UnderRun Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x08 30. -0x4 30. " OVRE_set/clr ,Overrun Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x08 29. -0x4 29. " ACKRCVE_set/clr ,Boot Operation Acknowledge Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x08 28. -0x4 28. " ACKRCV_set/clr ,Boot Operation Acknowledge Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x08 27. -0x4 27. " XFRDONE_set/clr ,Transfer Done Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x08 26. -0x4 26. " FIFOEMPTY_set/clr ,FIFO Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("ATSAM4S*")&&!cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x0 25. -0x08 25. -0x4 25. " DMADONE_set/clr ,DMA Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x08 24. -0x4 24. " BLKOVRE_set/clr ,DMA Block Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 23. -0x08 23. -0x4 23. " CSTOE_set/clr ,Completion Signal Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x08 22. -0x4 22. " DTOE_set/clr ,Data Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x08 21. -0x4 21. " DCRCE_set/clr ,Data CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x08 20. -0x4 20. " RTOE_set/clr ,Response Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x08 19. -0x4 19. " RENDE_set/clr ,Response End Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x08 18. -0x4 18. " RCRCE_set/clr ,Response CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x08 17. -0x4 17. " RDIRE_set/clr ,Response Direction Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x08 16. -0x4 16. " RINDE_set/clr ,Response Index Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ATSAM4S*")||cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x0 15. -0x08 15. -0x4 15. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x08 14. -0x4 14. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 13. -0x08 13. -0x4 13. " CSRCV_set/clr ,Completion Signal Received Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x08 12. -0x4 12. " SDIOWAIT_set/clr ,SDIO Read Wait Operation Status Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " SDIOIRQA_set/clr ,SDIOIRQA Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ATSAM4S*")||cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x0 7. -0x08 7. -0x4 7. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " NOTBUSY_set/clr ,Data Not Busy Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " DTIP_set/clr ,Data Transfer In Progress Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " BLKE_set/clr ,Data Block Ended Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " TXRDY_set/clr ,Transmit Ready Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " RXRDY_set/clr ,Receiver Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " CMDRDY_set/clr ,Command Ready Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAM4S*"))
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "HSMCI_DMA,HSMCI DMA Configuration Register"
|
|
bitfld.long 0x00 12. " ROPT ,Read Optimization with padding" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DMAEN ,DMA Hardware Handshaking Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CHKSIZE ,DMA Channel Read and Write Chunk Size" "1,4"
|
|
bitfld.long 0x00 0.--1. " OFFSET ,DMA Write Buffer Offset" "0,1,2,3"
|
|
endif
|
|
group.long 0x54++0x3
|
|
line.long 0x00 "HSMCI_CFG,HSMCI Configuration Register"
|
|
bitfld.long 0x00 12. " LSYNC ,Synchronize on the last block" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HSMODE ,High Speed Mode" "Normal,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FERRCTRL ,Flow Error flag reset control mode" "Write/Read command,Read status"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FIFOMODE ,HSMCI Internal FIFO control mode" "Sufficient level,One data written"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "HSMCI_WPMR,HSMCI Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WP_KEY ,HSMCI Write Protect Mode Register"
|
|
bitfld.long 0x00 0. " WP_EN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "HSMCI_WPSR,HSMCI Write Protect Status Register"
|
|
in
|
|
group.long 0x200++0x3
|
|
hide.long 0x00 "HSMCI_FIFO$2,HSMCI FIFO Memory Aperture"
|
|
button "FIFO Memory Aperture" "d (ad:0x40080000+0x200)--(ad:0x40080000+0x5FF) /long"
|
|
width 0xb
|
|
tree "HSMCI PDC (Peripheral DMA Controller)"
|
|
base ad:0x40080000
|
|
width 11.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "HSMCI_RPR,Receive Pointer Register"
|
|
line.long 0x04 "HSMCI_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "HSMCI_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "HSMCI_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "HSMCI_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "HSMCI_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "HSMCI_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "HSMCI_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "HSMCI_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "HSMCI_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "PWM (Pulse Width Modulation Controller)"
|
|
base ad:0x40000000
|
|
width 0x11
|
|
tree "Common Registers"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWM_CLK,PWM Clock Register"
|
|
bitfld.long 0x00 24.--27. " PREB ,Divider Input Clock" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,?..."
|
|
hexmask.long.byte 0x00 16.--23. 1. " DIVB ,CLKB Divide Factor"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " PREA ,Divider Input Clock" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIVA ,CLKA Divide Factor"
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "PWM_SR,PWM Disable/Enable and Status Register"
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " CHID3_set/clr ,PWM output for channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " CHID2_set/clr ,PWM output for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " CHID1_set/clr ,PWM output for channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " CHID0_set/clr ,PWM output for channel 0" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PWM_IMR1,PWM Interrupt Enable/Mask Register"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " FCHID3_set/clr ,Fault Protection Trigger on Channel 3 Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " FCHID2_set/clr ,Fault Protection Trigger on Channel 2 Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " FCHID1_set/clr ,Fault Protection Trigger on Channel 1 Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " FCHID0_set/clr ,Fault Protection Trigger on Channel 0 Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " CHID3_set/clr ,Counter Event on Channel 3 Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " CHID2_set/clr ,Counter Event on Channel 2 Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " CHID1_set/clr ,Counter Event on Channel 1 Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " CHID0_set/clr , Counter Event on Channel 0 Interrupt" "Disabled,Enabled"
|
|
hgroup.long 0x1c++0x03
|
|
hide.long 0x0 "PWM_ISR1,PWM Interrupt Status Register 1"
|
|
in
|
|
if ((d.l(ad:0x40000000+0x20)&0x30000)==0x20000)
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "PWM_SCM,PWM Sync Channels Mode Register"
|
|
bitfld.long 0x00 21.--23. " PTRCS ,PDC Transfer Request Comparison Selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. " PTRM ,PDC Transfer Request Mode (WRDY flag and PDC transfer request)" "Update period is elapsed,Selected comparison matches"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " UPDM ,Synchronous Channels Update Mode (write of duty-cycle update registers/update of synchronous channels)" "Manual/Manual,Manual/Automatic,Automatic/Automatic,?..."
|
|
bitfld.long 0x00 3. " SYNC3 ,Synchronous Channel 3" "Not synchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNC2 ,Synchronous Channel 2" "Not synchronous,Synchronous"
|
|
bitfld.long 0x00 1. " SYNC1 ,Synchronous Channel 1" "Not synchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SYNC0 ,Synchronous Channel 0" "Not synchronous,Synchronous"
|
|
elif ((d.l(ad:0x40000000+0x20)&0x30000)==0x10000)
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "PWM_SCM,PWM Sync Channels Mode Register"
|
|
bitfld.long 0x00 21.--23. " PTRCS ,PDC Transfer Request Comparison Selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. " PTRM ,PDC Transfer Request Mode (WRDY flag/PDC transfer request)" "Update period is elapsed/Never set,Update period is elapsed/Never set"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " UPDM ,Synchronous Channels Update Mode (write of duty-cycle update registers/update of synchronous channels)" "Manual/Manual,Manual/Automatic,Automatic/Automatic,?..."
|
|
bitfld.long 0x00 3. " SYNC3 ,Synchronous Channel 3" "Not synchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNC2 ,Synchronous Channel 2" "Not synchronous,Synchronous"
|
|
bitfld.long 0x00 1. " SYNC1 ,Synchronous Channel 1" "Not synchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SYNC0 ,Synchronous Channel 0" "Not synchronous,Synchronous"
|
|
else
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "PWM_SCM,PWM Sync Channels Mode Register"
|
|
bitfld.long 0x00 21.--23. " PTRCS ,PDC Transfer Request Comparison Selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. " PTRM ,PDC Transfer Request Mode(WRDY flag/PDC transfer request)" "Never set/Never set,Never set/Never set"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " UPDM ,Synchronous Channels Update Mode (write of duty-cycle update registers/update of synchronous channels)" "Manual/Manual,Manual/Automatic,Automatic/Automatic,?..."
|
|
bitfld.long 0x00 3. " SYNC3 ,Synchronous Channel 3" "Not synchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNC2 ,Synchronous Channel 2" "Not synchronous,Synchronous"
|
|
bitfld.long 0x00 1. " SYNC1 ,Synchronous Channel 1" "Not synchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SYNC0 ,Synchronous Channel 0" "Not synchronous,Synchronous"
|
|
endif
|
|
group.long 0x28++0x7
|
|
line.long 0x00 "PWM_SCUC,PWM Sync Channels Update Control Register"
|
|
bitfld.long 0x00 0. " UPDULOCK ,Synchronous Channels Update Unlock" "No effect,Update"
|
|
line.long 0x04 "PWM_SCUP,PWM Sync Channels Update Period Register"
|
|
bitfld.long 0x04 4.--7. " UPRCNT ,Update Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " UPR ,Update Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x30++0x3
|
|
line.long 0x00 "PWM_SCUPUPD,PWM Sync Channels Update Period Update Register"
|
|
bitfld.long 0x00 0.--3. " UPRUPD ,Update Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x3c++0x3
|
|
line.long 0x00 "PWM_IMR2,PWM Interrupt Mask Register 2"
|
|
setclrfld.long 0x00 23. -0x8 23. -0x4 23. " CMPU7_set/clr ,Comparison 7 Update Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x8 22. -0x4 22. " CMPU6_set/clr ,Comparison 6 Update Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x8 21. -0x4 21. " CMPU5_set/clr ,Comparison 5 Update Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x8 20. -0x4 20. " CMPU4_set/clr ,Comparison 4 Update Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CMPU3_set/clr ,Comparison 3 Update Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " CMPU2_set/clr ,Comparison 2 Update Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " CMPU1_set/clr ,Comparison 1 Update Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " CMPU0_set/clr ,Comparison 0 Update Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " CMPM7_set/clr ,Comparison 7 Match Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " CMPM6_set/clr ,Comparison 6 Match Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " CMPM5_set/clr ,Comparison 5 Match Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " CMPM4_set/clr ,Comparison 4 Match Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x8 11. -0x4 11. " CMPM3_set/clr ,Comparison 3 Match Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " CMPM2_set/clr ,Comparison 2 Match Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " CMPM1_set/clr ,Comparison 1 Match Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " CMPM0_set/clr ,Comparison 0 Match Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " UNRE_set/clr ,Synchronous Channels Update Underrun Error Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " TXBUFE_set/clr ,PDC TX Buffer Empty Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " ENDTX_set/clr ,PDC End of TX Buffer Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " WRDY_set/clr ,Write Ready for Synchronous Channels Update Interrupt" "Disabled,Enabled"
|
|
hgroup.long 0x40++0x3
|
|
hide.long 0x00 "PWM_ISR2,PWM Interrupt Status Register 2"
|
|
in
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "PWM_OOV,PWM Output Override Value Register"
|
|
bitfld.long 0x00 19. " OOVL3 ,Output Override Value for PWML output of the channel 3" "Low,High"
|
|
bitfld.long 0x00 18. " OOVL2 ,Output Override Value for PWML output of the channel 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " OOVL1 ,Output Override Value for PWML output of the channel 1" "Low,High"
|
|
bitfld.long 0x00 16. " OOVL0 ,Output Override Value for PWML output of the channel 0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OOVH3 ,Output Override Value for PWMH output of the channel 3" "Low,High"
|
|
bitfld.long 0x00 2. " OOVH2 ,Output Override Value for PWMH output of the channel 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OOVH1 ,Output Override Value for PWMH output of the channel 1" "Low,High"
|
|
bitfld.long 0x00 0. " OOVH0 ,Output Override Value for PWMH output of the channel 0" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "PWM_OS,PWM Output Selection Register"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " OSL3_set/clr ,Output Selection for PWML output of the channel 3" "DTOL3,OOVL3"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " OSL2_set/clr ,Output Selection for PWML output of the channel 2" "DTOL2,OOVL2"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " OSL1_set/clr ,Output Selection for PWML output of the channel 1" "DTOL1,OOVL1"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " OSL0_set/clr ,Output Selection for PWML output of the channel 0" "DTOL0,OOVL0"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " OSH3_set/clr ,Output Selection for PWMH output of the channel 3" "DTOH3,OOVH3"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " OSH2_set/clr ,Output Selection for PWMH output of the channel 2" "DTOH2,OOVH2"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " OSH1_set/clr ,Output Selection for PWMH output of the channel 1" "DTOH1,OOVH1"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " OSH0_set/clr ,Output Selection for PWMH output of the channel 0" "DTOH0,OOVH0"
|
|
group.long 0x54++0x7
|
|
line.long 0x00 "PWM_OSSUPD,PWM Output Selection Set Update Register"
|
|
bitfld.long 0x00 19. " OSSUPL3 ,Output Selection Set for PWML output of the channel 3" "No effect,OOVL3"
|
|
bitfld.long 0x00 18. " OSSUPL2 ,Output Selection Set for PWML output of the channel 2" "No effect,OOVL2"
|
|
textline " "
|
|
bitfld.long 0x00 17. " OSSUPL1 ,Output Selection Set for PWML output of the channel 1" "No effect,OOVL1"
|
|
bitfld.long 0x00 16. " OSSUPL0 ,Output Selection Set for PWML output of the channel 0" "No effect,OOVL0"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OSSUPH3 ,Output Selection Set for PWMH output of the channel 3" "No effect,OOVH3"
|
|
bitfld.long 0x00 2. " OSSUPH2 ,Output Selection Set for PWMH output of the channel 2" "No effect,OOVH2"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OSSUPH1 ,Output Selection Set for PWMH output of the channel 1" "No effect,OOVH1"
|
|
bitfld.long 0x00 0. " OSSUPH0 ,Output Selection Set for PWMH output of the channel 0" "No effect,OOVH0"
|
|
line.long 0x04 "PWM_OSCUPD,PWM Output Selection Clear Update Register"
|
|
bitfld.long 0x04 19. " OSCUPL3 ,Output Selection Clear for PWML output of the channel 3" "No effect,DTOL3"
|
|
bitfld.long 0x04 18. " OSCUPL2 ,Output Selection Clear for PWML output of the channel 2" "No effect,DTOL2"
|
|
textline " "
|
|
bitfld.long 0x04 17. " OSCUPL1 ,Output Selection Clear for PWML output of the channel 1" "No effect,DTOL1"
|
|
bitfld.long 0x04 16. " OSCUPL0 ,Output Selection Clear for PWML output of the channel 0" "No effect,DTOL0"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OSCUPH3 ,Output Selection Clear for PWMH output of the channel 3" "No effect,DTOH3"
|
|
bitfld.long 0x04 2. " OSCUPH2 ,Output Selection Clear for PWMH output of the channel 2" "No effect,DTOH2"
|
|
textline " "
|
|
bitfld.long 0x04 1. " OSCUPH1 ,Output Selection Clear for PWMH output of the channel 1" "No effect,DTOH1"
|
|
bitfld.long 0x04 0. " OSCUPH0 ,Output Selection Clear for PWMH output of the channel 0" "No effect,DTOH0"
|
|
group.long 0x5c++0x3
|
|
line.long 0x00 "PWM_FMR,PWM Fault Mode Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " FFIL ,Fault Filtering"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FMOD ,Fault Activation Mode"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " FPOL ,Fault Polarity"
|
|
rgroup.long 0x60++0x3
|
|
line.long 0x00 "PWM_FSR,PWM Fault Status Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FS ,Fault Status"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FIV ,Fault Input Value"
|
|
textline " "
|
|
wgroup.long 0x64++0x3
|
|
line.long 0x00 "PWM_FCR,PWM Fault Clear Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FCLR ,Fault Clear"
|
|
group.long 0x68++0x7
|
|
line.long 0x00 "PWM_FPV,PWM Fault Protection Value Register"
|
|
bitfld.long 0x00 19. " FPVL3 ,Fault Protection Value for PWML output on channel 3" "Low,High"
|
|
bitfld.long 0x00 18. " FPVL2 ,Fault Protection Value for PWML output on channel 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FPVL1 ,Fault Protection Value for PWML output on channel 1" "Low,High"
|
|
bitfld.long 0x00 16. " FPVL0 ,Fault Protection Value for PWML output on channel 0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FPVH3 ,Fault Protection Value for PWMH output on channel 3" "Low,High"
|
|
bitfld.long 0x00 2. " FPVH2 ,Fault Protection Value for PWMH output on channel 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FPVH1 ,Fault Protection Value for PWMH output on channel 1" "Low,High"
|
|
bitfld.long 0x00 0. " FPVH0 ,Fault Protection Value for PWMH output on channel 0" "Low,High"
|
|
line.long 0x04 "PWM_FPE,PWM Fault Protection Enable Register"
|
|
bitfld.long 0x04 27. " FPE3[3] ,Fault Protection Enable with Fault 3 for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " FPE3[2] ,Fault Protection Enable with Fault 2 for channel 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FPE3[1] ,Fault Protection Enable with Fault 1 for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " FPE3[0] ,Fault Protection Enable with Fault 0 for channel 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FPE2[3] ,Fault Protection Enable with Fault 3 for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " FPE2[2] ,Fault Protection Enable with Fault 2 for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FPE2[1] ,Fault Protection Enable with Fault 1 for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " FPE2[0] ,Fault Protection Enable with Fault 0 for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FPE1[3] ,Fault Protection Enable with Fault 3 for channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " FPE1[2] ,Fault Protection Enable with Fault 2 for channel 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FPE1[1] ,Fault Protection Enable with Fault 1 for channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " FPE1[0] ,Fault Protection Enable with Fault 0 for channel 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FPE0[3] ,Fault Protection Enable with Fault 3 for channel 0" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " FPE0[2] ,Fault Protection Enable with Fault 2 for channel 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FPE0[1] ,Fault Protection Enable with Fault 1 for channel 0" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " FPE0[0] ,Fault Protection Enable with Fault 0 for channel 0" "Disabled,Enabled"
|
|
group.long 0x7c++0x7
|
|
line.long 0x0 "PWM_EL0MR,PWM Event Line 0 Register"
|
|
bitfld.long 0x0 7. " CSEL7 , Comparison 7 Selection" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " CSEL6 , Comparison 6 Selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " CSEL5 , Comparison 5 Selection" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " CSEL4 , Comparison 4 Selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CSEL3 , Comparison 3 Selection" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " CSEL2 , Comparison 2 Selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CSEL1 , Comparison 1 Selection" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " CSEL0 , Comparison 0 Selection" "Disabled,Enabled"
|
|
line.long 0x4 "PWM_EL1MR,PWM Event Line 1 Register"
|
|
bitfld.long 0x4 7. " CSEL7 , Comparison 7 Selection" "Disabled,Enabled"
|
|
bitfld.long 0x4 6. " CSEL6 , Comparison 6 Selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 5. " CSEL5 , Comparison 5 Selection" "Disabled,Enabled"
|
|
bitfld.long 0x4 4. " CSEL4 , Comparison 4 Selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 3. " CSEL3 , Comparison 3 Selection" "Disabled,Enabled"
|
|
bitfld.long 0x4 2. " CSEL2 , Comparison 2 Selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 1. " CSEL1 , Comparison 1 Selection" "Disabled,Enabled"
|
|
bitfld.long 0x4 0. " CSEL0 , Comparison 0 Selection" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PWM_SSPR,PWM Spread Spectrum Register"
|
|
bitfld.long 0x00 24. " SPRDM ,Spread Spectrum Counter Mode" "Triangular,Random"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SPRD ,Spread Spectrum Limit Value"
|
|
wgroup.long 0xA4++0x03
|
|
line.long 0x00 "PWM_SSPUP,PWM Spectrum Update Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SPRDUP ,Spread Spectrum Limit Value Update"
|
|
endif
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "PWM_SMMR,PWM Stepper Motor Mode Register"
|
|
bitfld.long 0x00 17. " DOWN1 ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 16. " DOWN0 ,DOWN Count" "Up,Down"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GCEN1 ,Gray Count Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " GCEN0 ,Gray Count Enable" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "PWM_FPV2,PWM Fault Protection Value Register 2"
|
|
bitfld.long 0x00 19. " FPZL3 , Fault Protection to Hi-Z for PWML output on channel 3" "FPVL3,Hi-Z"
|
|
bitfld.long 0x00 18. " FPZL2 , Fault Protection to Hi-Z for PWML output on channel 3" "FPVL2,Hi-Z"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FPZL1 , Fault Protection to Hi-Z for PWML output on channel 2" "FPVL1,Hi-Z"
|
|
bitfld.long 0x00 16. " FPZL0 , Fault Protection to Hi-Z for PWML output on channel 2" "FPVL0,Hi-Z"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FPZH3 , FPZHx: Fault Protection to Hi-Z for PWMH output on channel 1" "FPVL3,Hi-Z"
|
|
bitfld.long 0x00 2. " FPZH2 , FPZHx: Fault Protection to Hi-Z for PWMH output on channel 1" "FPVL2,Hi-Z"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FPZH1 , FPZHx: Fault Protection to Hi-Z for PWMH output on channel 0" "FPVL1,Hi-Z"
|
|
bitfld.long 0x00 0. " FPZH0 , FPZHx: Fault Protection to Hi-Z for PWMH output on channel 0" "FPVL0,Hi-Z"
|
|
endif
|
|
wgroup.long 0xe4++0x3
|
|
line.long 0x00 "PWM_WPCR,PWM Write Protect Control Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect Key"
|
|
bitfld.long 0x00 7. " WPRG5 ,Write Protect Register Group 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " WPRG4 ,Write Protect Register Group 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " WPRG3 ,Write Protect Register Group 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WPRG2 ,Write Protect Register Group 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " WPRG1 ,Write Protect Register Group 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPRG0 ,Write Protect Register Group 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " WPCMD ,Write Protect Command" "Disable the Write Protect SW,Enable the Write Protect SW,Enable the Write Protect HW,No effect"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PWM_WPSR,PWM Write Protect Status Register"
|
|
in
|
|
tree.end
|
|
tree "Comparison Registers"
|
|
group.long (0x130+0x0)++0x03 "Comparison 0"
|
|
line.long 0x00 "PWM_CMP0V,PWM Comparison 0 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 0 Value Mode" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 0 Value"
|
|
wgroup.long (0x134+0x0)++0x3
|
|
line.long 0x00 "PWM_CMP0VUPD,Comparison 0 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 0 Value Mode Update" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 0 Value Update"
|
|
group.long (0x138+0x0)++0x3
|
|
line.long 0x00 "PWM_CMP0M,PWM Comparison 0 Mode Register"
|
|
bitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 0 Update Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 0 Update Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CPRCNT ,Comparison 0 Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 0 Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 0 Trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 0 Enable" "Disabled,Enabled"
|
|
wgroup.long (0x13c+0x0)++0x3
|
|
line.long 0x00 "PWM_CMP0MUPD,PWM Comparison 0 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 0 Update Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 0 Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 0 Trigger Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 0 Enable Update" "Disabled,Enabled"
|
|
group.long (0x130+0x10)++0x03 "Comparison 1"
|
|
line.long 0x00 "PWM_CMP1V,PWM Comparison 1 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 1 Value Mode" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 1 Value"
|
|
wgroup.long (0x134+0x10)++0x3
|
|
line.long 0x00 "PWM_CMP1VUPD,Comparison 1 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 1 Value Mode Update" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 1 Value Update"
|
|
group.long (0x138+0x10)++0x3
|
|
line.long 0x00 "PWM_CMP1M,PWM Comparison 1 Mode Register"
|
|
bitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 1 Update Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 1 Update Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CPRCNT ,Comparison 1 Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 1 Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 1 Trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 1 Enable" "Disabled,Enabled"
|
|
wgroup.long (0x13c+0x10)++0x3
|
|
line.long 0x00 "PWM_CMP1MUPD,PWM Comparison 1 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 1 Update Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 1 Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 1 Trigger Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 1 Enable Update" "Disabled,Enabled"
|
|
group.long (0x130+0x20)++0x03 "Comparison 2"
|
|
line.long 0x00 "PWM_CMP2V,PWM Comparison 2 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 2 Value Mode" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 2 Value"
|
|
wgroup.long (0x134+0x20)++0x3
|
|
line.long 0x00 "PWM_CMP2VUPD,Comparison 2 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 2 Value Mode Update" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 2 Value Update"
|
|
group.long (0x138+0x20)++0x3
|
|
line.long 0x00 "PWM_CMP2M,PWM Comparison 2 Mode Register"
|
|
bitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 2 Update Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 2 Update Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CPRCNT ,Comparison 2 Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 2 Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 2 Trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 2 Enable" "Disabled,Enabled"
|
|
wgroup.long (0x13c+0x20)++0x3
|
|
line.long 0x00 "PWM_CMP2MUPD,PWM Comparison 2 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 2 Update Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 2 Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 2 Trigger Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 2 Enable Update" "Disabled,Enabled"
|
|
group.long (0x130+0x30)++0x03 "Comparison 3"
|
|
line.long 0x00 "PWM_CMP3V,PWM Comparison 3 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 3 Value Mode" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 3 Value"
|
|
wgroup.long (0x134+0x30)++0x3
|
|
line.long 0x00 "PWM_CMP3VUPD,Comparison 3 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 3 Value Mode Update" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 3 Value Update"
|
|
group.long (0x138+0x30)++0x3
|
|
line.long 0x00 "PWM_CMP3M,PWM Comparison 3 Mode Register"
|
|
bitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 3 Update Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 3 Update Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CPRCNT ,Comparison 3 Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 3 Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 3 Trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 3 Enable" "Disabled,Enabled"
|
|
wgroup.long (0x13c+0x30)++0x3
|
|
line.long 0x00 "PWM_CMP3MUPD,PWM Comparison 3 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 3 Update Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 3 Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 3 Trigger Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 3 Enable Update" "Disabled,Enabled"
|
|
group.long (0x130+0x40)++0x03 "Comparison 4"
|
|
line.long 0x00 "PWM_CMP4V,PWM Comparison 4 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 4 Value Mode" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 4 Value"
|
|
wgroup.long (0x134+0x40)++0x3
|
|
line.long 0x00 "PWM_CMP4VUPD,Comparison 4 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 4 Value Mode Update" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 4 Value Update"
|
|
group.long (0x138+0x40)++0x3
|
|
line.long 0x00 "PWM_CMP4M,PWM Comparison 4 Mode Register"
|
|
bitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 4 Update Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 4 Update Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CPRCNT ,Comparison 4 Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 4 Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 4 Trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 4 Enable" "Disabled,Enabled"
|
|
wgroup.long (0x13c+0x40)++0x3
|
|
line.long 0x00 "PWM_CMP4MUPD,PWM Comparison 4 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 4 Update Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 4 Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 4 Trigger Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 4 Enable Update" "Disabled,Enabled"
|
|
group.long (0x130+0x50)++0x03 "Comparison 5"
|
|
line.long 0x00 "PWM_CMP5V,PWM Comparison 5 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 5 Value Mode" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 5 Value"
|
|
wgroup.long (0x134+0x50)++0x3
|
|
line.long 0x00 "PWM_CMP5VUPD,Comparison 5 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 5 Value Mode Update" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 5 Value Update"
|
|
group.long (0x138+0x50)++0x3
|
|
line.long 0x00 "PWM_CMP5M,PWM Comparison 5 Mode Register"
|
|
bitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 5 Update Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 5 Update Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CPRCNT ,Comparison 5 Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 5 Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 5 Trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 5 Enable" "Disabled,Enabled"
|
|
wgroup.long (0x13c+0x50)++0x3
|
|
line.long 0x00 "PWM_CMP5MUPD,PWM Comparison 5 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 5 Update Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 5 Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 5 Trigger Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 5 Enable Update" "Disabled,Enabled"
|
|
group.long (0x130+0x60)++0x03 "Comparison 6"
|
|
line.long 0x00 "PWM_CMP6V,PWM Comparison 6 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 6 Value Mode" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 6 Value"
|
|
wgroup.long (0x134+0x60)++0x3
|
|
line.long 0x00 "PWM_CMP6VUPD,Comparison 6 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 6 Value Mode Update" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 6 Value Update"
|
|
group.long (0x138+0x60)++0x3
|
|
line.long 0x00 "PWM_CMP6M,PWM Comparison 6 Mode Register"
|
|
bitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 6 Update Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 6 Update Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CPRCNT ,Comparison 6 Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 6 Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 6 Trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 6 Enable" "Disabled,Enabled"
|
|
wgroup.long (0x13c+0x60)++0x3
|
|
line.long 0x00 "PWM_CMP6MUPD,PWM Comparison 6 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 6 Update Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 6 Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 6 Trigger Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 6 Enable Update" "Disabled,Enabled"
|
|
group.long (0x130+0x70)++0x03 "Comparison 7"
|
|
line.long 0x00 "PWM_CMP7V,PWM Comparison 7 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 7 Value Mode" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 7 Value"
|
|
wgroup.long (0x134+0x70)++0x3
|
|
line.long 0x00 "PWM_CMP7VUPD,Comparison 7 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 7 Value Mode Update" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 7 Value Update"
|
|
group.long (0x138+0x70)++0x3
|
|
line.long 0x00 "PWM_CMP7M,PWM Comparison 7 Mode Register"
|
|
bitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 7 Update Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 7 Update Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CPRCNT ,Comparison 7 Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 7 Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 7 Trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 7 Enable" "Disabled,Enabled"
|
|
wgroup.long (0x13c+0x70)++0x3
|
|
line.long 0x00 "PWM_CMP7MUPD,PWM Comparison 7 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 7 Update Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 7 Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 7 Trigger Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 7 Enable Update" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Channel 0"
|
|
if ((d.l(ad:0x40000000+0x200+0x0)&0x100)==0x100)
|
|
group.long (0x200+0x0)++0x3
|
|
line.long 0x00 "PWM_CMR0,Channel 0 Mode Register"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-Time PWML0 Output Inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-Time PWMH0 Output Inverted" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DTE ,Dead-Time Generator Enable" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
bitfld.long 0x00 11. " UPDS ,Update Selection" "Next PWM period end,Next PWM half-period end"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 10. " CES ,Counter Event Selection" "At the end of period,At the end and half the period"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
else
|
|
group.long (0x200+0x0)++0x3
|
|
line.long 0x00 "PWM_CMR0,Channel 0 Mode Register"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-Time PWML0 Output Inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-Time PWMH0 Output Inverted" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DTE ,Dead-Time Generator Enable" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
bitfld.long 0x00 11. " UPDS ,Update Selection" "Next PWM period end,Next PWM period end"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 10. " CES ,Counter Event Selection" "At the end of period,At the end of period"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
endif
|
|
group.long (0x204+0x0)++0x3
|
|
line.long 0x00 "PWM_CDTY0,PWM Channel 0 Duty Cycle Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTY ,Channel Duty-Cycle"
|
|
wgroup.long (0x208+0x0)++0x3
|
|
line.long 0x00 "PWM_CPRD0,PWM Channel 0 Duty Cycle Update Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTYUPD ,Channel Duty-Cycle Update"
|
|
group.long (0x20c+0x0)++0x03
|
|
line.long 0x00 "PWM_CPRD0,PWM Channel 0 Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CPRD ,Channel Period"
|
|
wgroup.long (0x210+0x0)++0x03
|
|
line.long 0x00 "PWM_CPRDUPD0,Channel 0 Update Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " CPRDUPD ,Channel Period Update"
|
|
rgroup.long (0x214+0x0)++0x03
|
|
line.long 0x00 "PWM_CCNT0,PWM Channel 0 Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " CNT ,Channel Counter Register"
|
|
group.long (0x218+0x0)++0x03
|
|
line.long 0x00 "PWM_DT0,PWM Channel Dead Time Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " DTH ,Dead-Time Value for PWMH0 Output"
|
|
hexmask.long.word 0x00 0.--11. 1. " DTL ,Dead-Time Value for PWML0 Output"
|
|
wgroup.long (0x21c+0x0)++0x03
|
|
line.long 0x00 "PWM_DTUPD0,PWM Channel Dead Time Update Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " DTHUPD ,Dead-Time Value Update for PWMH0 Output"
|
|
hexmask.long.word 0x00 0.--11. 1. " DTLUPD ,Dead-Time Value Update for PWML0 Output"
|
|
tree.end
|
|
tree "Channel 1"
|
|
if ((d.l(ad:0x40000000+0x200+0x20)&0x100)==0x100)
|
|
group.long (0x200+0x20)++0x3
|
|
line.long 0x00 "PWM_CMR1,Channel 1 Mode Register"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-Time PWML1 Output Inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-Time PWMH1 Output Inverted" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DTE ,Dead-Time Generator Enable" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
bitfld.long 0x00 11. " UPDS ,Update Selection" "Next PWM period end,Next PWM half-period end"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 10. " CES ,Counter Event Selection" "At the end of period,At the end and half the period"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
else
|
|
group.long (0x200+0x20)++0x3
|
|
line.long 0x00 "PWM_CMR1,Channel 1 Mode Register"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-Time PWML1 Output Inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-Time PWMH1 Output Inverted" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DTE ,Dead-Time Generator Enable" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
bitfld.long 0x00 11. " UPDS ,Update Selection" "Next PWM period end,Next PWM period end"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 10. " CES ,Counter Event Selection" "At the end of period,At the end of period"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
endif
|
|
group.long (0x204+0x20)++0x3
|
|
line.long 0x00 "PWM_CDTY1,PWM Channel 1 Duty Cycle Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTY ,Channel Duty-Cycle"
|
|
wgroup.long (0x208+0x20)++0x3
|
|
line.long 0x00 "PWM_CPRD1,PWM Channel 1 Duty Cycle Update Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTYUPD ,Channel Duty-Cycle Update"
|
|
group.long (0x20c+0x20)++0x03
|
|
line.long 0x00 "PWM_CPRD1,PWM Channel 1 Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CPRD ,Channel Period"
|
|
wgroup.long (0x210+0x20)++0x03
|
|
line.long 0x00 "PWM_CPRDUPD1,Channel 1 Update Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " CPRDUPD ,Channel Period Update"
|
|
rgroup.long (0x214+0x20)++0x03
|
|
line.long 0x00 "PWM_CCNT1,PWM Channel 1 Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " CNT ,Channel Counter Register"
|
|
group.long (0x218+0x20)++0x03
|
|
line.long 0x00 "PWM_DT1,PWM Channel Dead Time Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " DTH ,Dead-Time Value for PWMH1 Output"
|
|
hexmask.long.word 0x00 0.--11. 1. " DTL ,Dead-Time Value for PWML1 Output"
|
|
wgroup.long (0x21c+0x20)++0x03
|
|
line.long 0x00 "PWM_DTUPD1,PWM Channel Dead Time Update Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " DTHUPD ,Dead-Time Value Update for PWMH1 Output"
|
|
hexmask.long.word 0x00 0.--11. 1. " DTLUPD ,Dead-Time Value Update for PWML1 Output"
|
|
tree.end
|
|
tree "Channel 2"
|
|
if ((d.l(ad:0x40000000+0x200+0x40)&0x100)==0x100)
|
|
group.long (0x200+0x40)++0x3
|
|
line.long 0x00 "PWM_CMR2,Channel 2 Mode Register"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-Time PWML2 Output Inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-Time PWMH2 Output Inverted" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DTE ,Dead-Time Generator Enable" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
bitfld.long 0x00 11. " UPDS ,Update Selection" "Next PWM period end,Next PWM half-period end"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 10. " CES ,Counter Event Selection" "At the end of period,At the end and half the period"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
else
|
|
group.long (0x200+0x40)++0x3
|
|
line.long 0x00 "PWM_CMR2,Channel 2 Mode Register"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-Time PWML2 Output Inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-Time PWMH2 Output Inverted" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DTE ,Dead-Time Generator Enable" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
bitfld.long 0x00 11. " UPDS ,Update Selection" "Next PWM period end,Next PWM period end"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 10. " CES ,Counter Event Selection" "At the end of period,At the end of period"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
endif
|
|
group.long (0x204+0x40)++0x3
|
|
line.long 0x00 "PWM_CDTY2,PWM Channel 2 Duty Cycle Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTY ,Channel Duty-Cycle"
|
|
wgroup.long (0x208+0x40)++0x3
|
|
line.long 0x00 "PWM_CPRD2,PWM Channel 2 Duty Cycle Update Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTYUPD ,Channel Duty-Cycle Update"
|
|
group.long (0x20c+0x40)++0x03
|
|
line.long 0x00 "PWM_CPRD2,PWM Channel 2 Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CPRD ,Channel Period"
|
|
wgroup.long (0x210+0x40)++0x03
|
|
line.long 0x00 "PWM_CPRDUPD2,Channel 2 Update Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " CPRDUPD ,Channel Period Update"
|
|
rgroup.long (0x214+0x40)++0x03
|
|
line.long 0x00 "PWM_CCNT2,PWM Channel 2 Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " CNT ,Channel Counter Register"
|
|
group.long (0x218+0x40)++0x03
|
|
line.long 0x00 "PWM_DT2,PWM Channel Dead Time Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " DTH ,Dead-Time Value for PWMH2 Output"
|
|
hexmask.long.word 0x00 0.--11. 1. " DTL ,Dead-Time Value for PWML2 Output"
|
|
wgroup.long (0x21c+0x40)++0x03
|
|
line.long 0x00 "PWM_DTUPD2,PWM Channel Dead Time Update Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " DTHUPD ,Dead-Time Value Update for PWMH2 Output"
|
|
hexmask.long.word 0x00 0.--11. 1. " DTLUPD ,Dead-Time Value Update for PWML2 Output"
|
|
tree.end
|
|
tree "Channel 3"
|
|
if ((d.l(ad:0x40000000+0x200+0x60)&0x100)==0x100)
|
|
group.long (0x200+0x60)++0x3
|
|
line.long 0x00 "PWM_CMR3,Channel 3 Mode Register"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-Time PWML3 Output Inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-Time PWMH3 Output Inverted" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DTE ,Dead-Time Generator Enable" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
bitfld.long 0x00 11. " UPDS ,Update Selection" "Next PWM period end,Next PWM half-period end"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 10. " CES ,Counter Event Selection" "At the end of period,At the end and half the period"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
else
|
|
group.long (0x200+0x60)++0x3
|
|
line.long 0x00 "PWM_CMR3,Channel 3 Mode Register"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-Time PWML3 Output Inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-Time PWMH3 Output Inverted" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DTE ,Dead-Time Generator Enable" "Disabled,Enabled"
|
|
sif cpuis("ATSAM4E*")
|
|
bitfld.long 0x00 11. " UPDS ,Update Selection" "Next PWM period end,Next PWM period end"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 10. " CES ,Counter Event Selection" "At the end of period,At the end of period"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
endif
|
|
group.long (0x204+0x60)++0x3
|
|
line.long 0x00 "PWM_CDTY3,PWM Channel 3 Duty Cycle Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTY ,Channel Duty-Cycle"
|
|
wgroup.long (0x208+0x60)++0x3
|
|
line.long 0x00 "PWM_CPRD3,PWM Channel 3 Duty Cycle Update Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTYUPD ,Channel Duty-Cycle Update"
|
|
group.long (0x20c+0x60)++0x03
|
|
line.long 0x00 "PWM_CPRD3,PWM Channel 3 Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CPRD ,Channel Period"
|
|
wgroup.long (0x210+0x60)++0x03
|
|
line.long 0x00 "PWM_CPRDUPD3,Channel 3 Update Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " CPRDUPD ,Channel Period Update"
|
|
rgroup.long (0x214+0x60)++0x03
|
|
line.long 0x00 "PWM_CCNT3,PWM Channel 3 Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " CNT ,Channel Counter Register"
|
|
group.long (0x218+0x60)++0x03
|
|
line.long 0x00 "PWM_DT3,PWM Channel Dead Time Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " DTH ,Dead-Time Value for PWMH3 Output"
|
|
hexmask.long.word 0x00 0.--11. 1. " DTL ,Dead-Time Value for PWML3 Output"
|
|
wgroup.long (0x21c+0x60)++0x03
|
|
line.long 0x00 "PWM_DTUPD3,PWM Channel Dead Time Update Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " DTHUPD ,Dead-Time Value Update for PWMH3 Output"
|
|
hexmask.long.word 0x00 0.--11. 1. " DTLUPD ,Dead-Time Value Update for PWML3 Output"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "UDP (USB Device Port)"
|
|
base ad:0x40084000
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "UDP_FRM_NUM,UDP Frame Number Register"
|
|
bitfld.long 0x00 17. " FRM_OK ,Frame OK" "SOF_PID,SOF_EOP"
|
|
bitfld.long 0x00 16. " FRM_ERR ,Frame Error" "No error,Error"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " FRM_NUM[10:0] ,Frame Number as Defined In the Packet Field Formats"
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "UDP_GLB_STAT,UDP Global State Register"
|
|
bitfld.long 0x00 4. " RMWUPE ,Remote Wake Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RSMINPR ,A Resume Has Been Sent to the Host" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ESR ,Enable Send Resume" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CONFG ,Configured" "Not configured,Configured"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FADDEN ,Function Address Enable" "Disabled,Enabled"
|
|
line.long 0x4 "UDP_FADDR,UDP Function Address Register"
|
|
bitfld.long 0x4 8. " FEN ,Function Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x4 0.--6. 1. " FADD[6:0] ,Function Address Value"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "UDP_IMR,UDP Interrupt Mask Register"
|
|
setclrfld.long 0x0 13. -0x08 13. -0x4 13. " WAKEUP_set/clr ,USB Bus WAKEUP Interrupt" "Masked,Not masked"
|
|
rbitfld.long 0x0 12. " BIT12 ,UDP_IMR Bit 12" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x08 11. -0x4 11. " SOFINT_set/clr ,Mask Start Of Frame Interrupt" "Masked,Not masked"
|
|
sif cpuis("ATSAM4E*")||cpuis("ATSAM4S*")||cpuis("ATSAMG55")
|
|
setclrfld.long 0x0 10. -0x08 10. -0x4 10. " EXTRSM_set/clr ,Mask External Resume Interrupt" "Masked,Not masked"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x08 9. -0x4 9. " RXRSM_set/clr ,Mask UDP Resume Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " RXSUSP_set/clr ,Mask UDP Suspend Interrupt" "Masked,Not masked"
|
|
textline " "
|
|
sif !cpuis("ATSAMG55")
|
|
setclrfld.long 0x0 7. -0x08 7. -0x4 7. " EP7INT_set/clr ,Mask Endpoint 7 Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " EP6INT_set/clr ,Mask Endpoint 6 Interrupt" "Masked,Not masked"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " EP5INT_set/clr ,Mask Endpoint 5 Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " EP4INT_set/clr ,Mask Endpoint 4 Interrupt" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " EP3INT_set/clr ,Mask Endpoint 3 Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " EP2INT_set/clr ,Mask Endpoint 2 Interrupt" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " EP1INT_set/clr ,Mask Endpoint 1 Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " EP0INT_set/clr ,Mask Endpoint 0 Interrupt" "Masked,Not masked"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "UDP_ISR,UDP Interrupt Status Register"
|
|
bitfld.long 0x0 13. " WAKEUP ,UDP Resume Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 12. " ENDBUSRES ,End of BUS Reset Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 11. " SOFINT ,Start of Frame Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 10. " EXTRSM ,External Resume Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 9. " RXRSM ,UDP Resume Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 8. " RXSUSP ,UDP Suspend Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif !cpuis("ATSAMG55")
|
|
bitfld.long 0x0 7. " EP7INT ,Endpoint 7 Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 6. " EP6INT ,Endpoint 6 Interrupt Status" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 5. " EP5INT ,Endpoint 5 Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 4. " EP4INT ,Endpoint 4 Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 3. " EP3INT ,Endpoint 3 Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 2. " EP2INT ,Endpoint 2 Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EP1INT ,Endpoint 1 Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 0. " EP0INT ,Endpoint 0 Interrupt Status" "No interrupt,Interrupt"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "UDP_ICR,UDP Interrupt Clear Register"
|
|
bitfld.long 0x0 13. " WAKEUP ,Clear Wakeup Interrupt" "No effect,Clear"
|
|
bitfld.long 0x00 12. " ENDBUSRES ,Clear End of BUS Reset Interrupt" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0 11. " SOFINT ,Clear Start Of Frame Interrupt" "No effect,Clear"
|
|
bitfld.long 0x0 10. " EXTRSM ,Clear External Resume Interrupt" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RXRSM ,Clear UDP Resume Interrupt" "No effect,Clear"
|
|
bitfld.long 0x00 8. " RXSUSP ,Clear UDP Suspend Interrupt" "No effect,Clear"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "UDP_RST_EP,UDP Reset Endpoint Register"
|
|
sif !cpuis("ATSAMG55")
|
|
bitfld.long 0x00 7. " EP7 ,Reset Endpoint 7" "No reset,Reset"
|
|
bitfld.long 0x00 6. " EP46 ,Reset Endpoint 6" "No reset,Reset"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " EP5 ,Reset Endpoint 5" "No reset,Reset"
|
|
bitfld.long 0x00 4. " EP4 ,Reset Endpoint 4" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EP3 ,Reset Endpoint 3" "No reset,Reset"
|
|
bitfld.long 0x00 2. " EP2 ,Reset Endpoint 2" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EP1 ,Reset Endpoint 1" "No reset,Reset"
|
|
bitfld.long 0x00 0. " EP0 ,Reset Endpoint 0" "No reset,Reset"
|
|
width 11.
|
|
tree "Endpoint Control and Status Registers"
|
|
if (((d.l((ad:0x40084000+0x30+0x0)))&0x700)==0x000)
|
|
group.long (0x30+0x0)++0x3
|
|
line.long 0x0 "UDP_CSR0,UDP Endpoint 0 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,,Bulk OUT,Interrupt OUT,,,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 7. " DIR ,Transfer Direction" "Data OUT,Data IN"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((d.l((ad:0x40084000+0x30+0x0)))&0x700)==(0x200||0x600)
|
|
group.long (0x30+0x0)++0x3
|
|
line.long 0x0 "UDP_CSR0,UDP Endpoint 0 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,,Bulk OUT,Interrupt OUT,,,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0x0)++0x3
|
|
line.long 0x0 "UDP_CSR0,UDP Endpoint 0 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,,Bulk OUT,Interrupt OUT,,,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
if ((d.l((ad:0x40084000+0x30+0x4)))&0x700)==(0x100||0x500)
|
|
group.long (0x30+0x4)++0x3
|
|
line.long 0x0 "UDP_CSR1,UDP Endpoint 1 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" ",Isochronous OUT,Bulk OUT,Interrupt OUT,,Isochronous IN,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " ISOERROR ,CRC Error in an Isochronous Transfer" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((d.l((ad:0x40084000+0x30+0x4)))&0x700)==(0x200||0x600)
|
|
group.long (0x30+0x4)++0x3
|
|
line.long 0x0 "UDP_CSR1,UDP Endpoint 1 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" ",Isochronous OUT,Bulk OUT,Interrupt OUT,,Isochronous IN,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0x4)++0x3
|
|
line.long 0x0 "UDP_CSR1,UDP Endpoint 1 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" ",Isochronous OUT,Bulk OUT,Interrupt OUT,,Isochronous IN,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
if ((d.l((ad:0x40084000+0x30+0x8)))&0x700)==(0x100||0x500)
|
|
group.long (0x30+0x8)++0x3
|
|
line.long 0x0 "UDP_CSR2,UDP Endpoint 2 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" ",Isochronous OUT,Bulk OUT,Interrupt OUT,,Isochronous IN,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " ISOERROR ,CRC Error in an Isochronous Transfer" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((d.l((ad:0x40084000+0x30+0x8)))&0x700)==(0x200||0x600)
|
|
group.long (0x30+0x8)++0x3
|
|
line.long 0x0 "UDP_CSR2,UDP Endpoint 2 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" ",Isochronous OUT,Bulk OUT,Interrupt OUT,,Isochronous IN,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0x8)++0x3
|
|
line.long 0x0 "UDP_CSR2,UDP Endpoint 2 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" ",Isochronous OUT,Bulk OUT,Interrupt OUT,,Isochronous IN,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
if (((d.l((ad:0x40084000+0x30+0xC)))&0x700)==0x000)
|
|
group.long (0x30+0xC)++0x3
|
|
line.long 0x0 "UDP_CSR3,UDP Endpoint 3 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,,Bulk OUT,Interrupt OUT,,,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 7. " DIR ,Transfer Direction" "Data OUT,Data IN"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((d.l((ad:0x40084000+0x30+0xC)))&0x700)==(0x200||0x600)
|
|
group.long (0x30+0xC)++0x3
|
|
line.long 0x0 "UDP_CSR3,UDP Endpoint 3 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,,Bulk OUT,Interrupt OUT,,,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0xC)++0x3
|
|
line.long 0x0 "UDP_CSR3,UDP Endpoint 3 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,,Bulk OUT,Interrupt OUT,,,Bulk IN,Interrupt IN"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
if ((d.l((ad:0x40084000+0x30+0x10)))&0x700)==(0x100||0x500)
|
|
group.long (0x30+0x10)++0x3
|
|
line.long 0x0 "UDP_CSR4,UDP Endpoint 4 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" ",Isochronous OUT,Bulk OUT,Interrupt OUT,,Isochronous IN,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " ISOERROR ,CRC Error in an Isochronous Transfer" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((d.l((ad:0x40084000+0x30+0x10)))&0x700)==(0x200||0x600)
|
|
group.long (0x30+0x10)++0x3
|
|
line.long 0x0 "UDP_CSR4,UDP Endpoint 4 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" ",Isochronous OUT,Bulk OUT,Interrupt OUT,,Isochronous IN,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0x10)++0x3
|
|
line.long 0x0 "UDP_CSR4,UDP Endpoint 4 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" ",Isochronous OUT,Bulk OUT,Interrupt OUT,,Isochronous IN,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
if ((d.l((ad:0x40084000+0x30+0x14)))&0x700)==(0x100||0x500)
|
|
group.long (0x30+0x14)++0x3
|
|
line.long 0x0 "UDP_CSR5,UDP Endpoint 5 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" ",Isochronous OUT,Bulk OUT,Interrupt OUT,,Isochronous IN,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " ISOERROR ,CRC Error in an Isochronous Transfer" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((d.l((ad:0x40084000+0x30+0x14)))&0x700)==(0x200||0x600)
|
|
group.long (0x30+0x14)++0x3
|
|
line.long 0x0 "UDP_CSR5,UDP Endpoint 5 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" ",Isochronous OUT,Bulk OUT,Interrupt OUT,,Isochronous IN,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0x14)++0x3
|
|
line.long 0x0 "UDP_CSR5,UDP Endpoint 5 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" ",Isochronous OUT,Bulk OUT,Interrupt OUT,,Isochronous IN,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
if ((d.l((ad:0x40084000+0x30+0x18)))&0x700)==(0x100||0x500)
|
|
group.long (0x30+0x18)++0x3
|
|
line.long 0x0 "UDP_CSR6,UDP Endpoint 6 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" ",Isochronous OUT,Bulk OUT,Interrupt OUT,,Isochronous IN,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " ISOERROR ,CRC Error in an Isochronous Transfer" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((d.l((ad:0x40084000+0x30+0x18)))&0x700)==(0x200||0x600)
|
|
group.long (0x30+0x18)++0x3
|
|
line.long 0x0 "UDP_CSR6,UDP Endpoint 6 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" ",Isochronous OUT,Bulk OUT,Interrupt OUT,,Isochronous IN,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0x18)++0x3
|
|
line.long 0x0 "UDP_CSR6,UDP Endpoint 6 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" ",Isochronous OUT,Bulk OUT,Interrupt OUT,,Isochronous IN,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
if ((d.l((ad:0x40084000+0x30+0x1C)))&0x700)==(0x100||0x500)
|
|
group.long (0x30+0x1C)++0x3
|
|
line.long 0x0 "UDP_CSR7,UDP Endpoint 7 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" ",Isochronous OUT,Bulk OUT,Interrupt OUT,,Isochronous IN,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " ISOERROR ,CRC Error in an Isochronous Transfer" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
elif ((d.l((ad:0x40084000+0x30+0x1C)))&0x700)==(0x200||0x600)
|
|
group.long (0x30+0x1C)++0x3
|
|
line.long 0x0 "UDP_CSR7,UDP Endpoint 7 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" ",Isochronous OUT,Bulk OUT,Interrupt OUT,,Isochronous IN,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced"
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
else
|
|
group.long (0x30+0x1C)++0x3
|
|
line.long 0x0 "UDP_CSR7,UDP Endpoint 7 Control and Status Register"
|
|
hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,Number of Bytes Available in the FIFO"
|
|
bitfld.long 0x0 15. " EPEDS ,Endpoint Enable Disable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1"
|
|
bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" ",Isochronous OUT,Bulk OUT,Interrupt OUT,,Isochronous IN,Bulk IN,Interrupt IN"
|
|
bitfld.long 0x0 6. " RX_DATA_BK1 ,Receive Data Bank 1" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Not ready,Ready"
|
|
bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RXSETUP ,Received Setup" "Not recieved,Recieved"
|
|
bitfld.long 0x0 1. " RX_DATA_BK0 ,Receive Data Bank 0" "Not received,Received"
|
|
bitfld.long 0x0 0. " TXCOMP ,Generates an IN Packet with Data Previously Written in the DPR" "Not acknowledged,Acknowledged"
|
|
endif
|
|
tree.end
|
|
tree "UDP Endpoint FIFO Data Registers"
|
|
textline " "
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "UDP_FDR0,UDP Endpoint 0 FIFO Data Register"
|
|
in
|
|
hgroup.long 0x54++0x03
|
|
hide.long 0x00 "UDP_FDR1,UDP Endpoint 1 FIFO Data Register"
|
|
in
|
|
hgroup.long 0x58++0x03
|
|
hide.long 0x00 "UDP_FDR2,UDP Endpoint 2 FIFO Data Register"
|
|
in
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "UDP_FDR3,UDP Endpoint 3 FIFO Data Register"
|
|
in
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "UDP_FDR4,UDP Endpoint 4 FIFO Data Register"
|
|
in
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "UDP_FDR5,UDP Endpoint 5 FIFO Data Register"
|
|
in
|
|
hgroup.long 0x68++0x03
|
|
hide.long 0x00 "UDP_FDR6,UDP Endpoint 6 FIFO Data Register"
|
|
in
|
|
hgroup.long 0x6C++0x03
|
|
hide.long 0x00 "UDP_FDR7,UDP Endpoint 7 FIFO Data Register"
|
|
in
|
|
; base vm:0x0
|
|
; wgroup 0x0++0x0
|
|
; base ad:0x40084000
|
|
tree.end
|
|
textline " "
|
|
width 14.
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "UDP_TXVC,UDP Transceiver Control Register"
|
|
bitfld.long 0x00 9. " PUON ,Pullup On" "Disconnected,Connected"
|
|
bitfld.long 0x00 8. " TXVDIS ,Transceiver Disable" "Enabled,Disabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "ACC (Analog Comparator Controller)"
|
|
base ad:0x400BC000
|
|
width 10.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "ACC_CR,ACC Control Register"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "No effect,Reset"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ACC_MR,ACC Mode Register"
|
|
bitfld.long 0x00 14. " FE ,Fault Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SELFS ,Selection of Fault Source" "CF flag,Analog Comparator flag"
|
|
textline " "
|
|
bitfld.long 0x00 12. " INV ,Invert comparator output" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--10. " EDGETYP ,EDGE TYPE" "RISING,FALLING,ANY,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " ACEN ,Analog Comparator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SELPLUS ,SELection for PLUS comparator input" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " SELMINUS ,Selection for MINUS comparator input" "TS,ADVREF,DAC0,DAC1,AD0,AD1,AD2,AD3"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ACC_IMR,ACC Interrupt Mask Register"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " CE ,Comparison Edge" "Disabled,Enabled"
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "ACC_ISR,ACC Interrupt Status Register"
|
|
in
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "ACC_ACR,ACC Analog Control Register"
|
|
sif (cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 1.--2. " HYST ,HYSTeresis selection" "0mV,15-50mV,15-50mV,30-90mV"
|
|
else
|
|
bitfld.long 0x00 1.--2. " HYST ,HYSTeresis selection" "0mV,16-50mV,16-50mV,35-90mV"
|
|
endif
|
|
bitfld.long 0x00 0. " ISEL ,Current Selection" "Low power,High speed"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "ACC_WPMR,ACC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
sif (cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 1. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "ACC_WPSR,ACC Write Protect Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "AFEC (Analog-Front-End Controller)"
|
|
tree "AFE 0"
|
|
base ad:0x400B0000
|
|
width 9.
|
|
wgroup.long 0x00++0x3
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x0 3. " AUTOCAL ,Automatic Calibration of AFE" "No effect,Calibrate"
|
|
bitfld.long 0x0 1. " START ,Start Conversion" "No effect,Start"
|
|
bitfld.long 0x0 0. " SWRST ,Software Reset" "No effect,Reset"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x0 31. " USEQ ,Use Sequence Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 28.--29. " TRANSFER ,Transfer Period (AFEClock periods)" "3,5,7,11"
|
|
bitfld.long 0x0 24.--27. " TRACKTIM ,Tracking Time (AFEClock periods)" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x0 23. " ANACH ,Analog Change" "Not allowed,Allowed"
|
|
bitfld.long 0x0 20.--21. " SETTLING ,Analog Settling Time (AFEClock periods)" "3,5,9,17"
|
|
bitfld.long 0x0 16.--19. " STARTUP ,Start Up Time (AFEClock periods)" "0,8,16,24,64,80,96,112,512,576,640,704,768,832,896,960"
|
|
textline " "
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRESCAL ,Prescaler Rate Selection"
|
|
bitfld.long 0x0 7. " FREERUN ,Free Run Mode" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " FWUP ,Fast Wake Up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " SLEEP ,Sleep Mode" "Disabled,Enabled"
|
|
bitfld.long 0x0 1.--3. " TRGSEL ,Trigger Selection" "ADTRG pin,TC Ch 0 TIO out,TC Ch 1 TIO out,TC Ch 2 TIO out,PWM Event Line 0,PWM Event Line 1,,"
|
|
textline " "
|
|
bitfld.long 0x0 0. " TRGEN ,Trigger Enable" "Disabled,Enabled"
|
|
; if EMR -> CMPALL == "Yes"
|
|
if (d.l((ad:0x400B0000)+0x08)&0x200)==0x200
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "EMR,Extended Mode Register"
|
|
bitfld.long 0x0 25. " STM ,Single Trigger Mode" "Multiple trigger,Single trigger"
|
|
bitfld.long 0x0 24. " TAG ,TAG of AFE_LDCR register" "Disabled,Enabled"
|
|
bitfld.long 0x0 16.--18. " RES ,Resolution" "12-bit (no avg),10-bit (no avg),13-bit (avg),14-bit (avg),15-bit (avg),16-bit (avg),,"
|
|
textline " "
|
|
bitfld.long 0x0 12.--13. " CMPFILTER ,Compare Event Filtering" "Disabled,2 compares,3 compares,4 compares"
|
|
bitfld.long 0x0 9. " CMPALL ,Compare All Channels" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " CMPMODE ,Comparison Mode" "Low,High,In,Out"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "EMR,Extended Mode Register"
|
|
bitfld.long 0x0 25. " STM ,Single Trigger Mode" "Multiple trigger,Single trigger"
|
|
bitfld.long 0x0 24. " TAG ,TAG of AFE_LDCR register" "Disabled,Enabled"
|
|
bitfld.long 0x0 16.--18. " RES ,Resolution" "12-bit (no avg),10-bit (no avg),13-bit (avg),14-bit (avg),15-bit (avg),16-bit (avg),,"
|
|
textline " "
|
|
bitfld.long 0x0 12.--13. " CMPFILTER ,Compare Event Filtering" "Disabled,2 compares,3 compares,4 compares"
|
|
bitfld.long 0x0 9. " CMPALL ,Compare All Channels" "No,Yes"
|
|
bitfld.long 0x0 3.--7. " CMPSEL ,Comparison Selected Channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,,,,,,,,"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " CMPMODE ,Comparison Mode" "Low,High,In,Out"
|
|
endif
|
|
; if AFE -> USEQ == "User Sequence Mode"
|
|
if (d.l((ad:0x400B0000)+0x04)&0x80000000)==0x80000000
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "SEQ1R,Channel Sequence 1 Register"
|
|
bitfld.long 0x0 28.--31. " USCH7 ,User Sequence Number 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 24.--27. " USCH6 ,User Sequence Number 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " USCH5 ,User Sequence Number 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " USCH4 ,User Sequence Number 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " USCH3 ,User Sequence Number 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " USCH2 ,User Sequence Number 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " USCH1 ,User Sequence Number 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 0.--3. " USCH0 ,User Sequence Number 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "SEQ2R,Channel Sequence 2 Register"
|
|
bitfld.long 0x4 28.--31. " USCH15 ,User Sequence Number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 24.--27. " USCH14 ,User Sequence Number 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " USCH13 ,User Sequence Number 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " USCH12 ,User Sequence Number 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " USCH11 ,User Sequence Number 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " USCH10 ,User Sequence Number 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " USCH9 ,User Sequence Number 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 0.--3. " USCH8 ,User Sequence Number 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.long 0x0C++0x07
|
|
hide.long 0x00 "SEQ1R,Channel Sequence 1 Register"
|
|
hide.long 0x04 "SEQ2R,Channel Sequence 2 Register"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CHSR,Channel Status Register"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " CH23 ,Channel 23 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " CH22 ,Channel 22 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " CH21 ,Channel 21 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 10. -0x04 20. " CH20 ,Channel 20 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " CH19 ,Channel 19 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " CH18 ,Channel 18 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " CH17 ,Channel 17 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " CH16 ,Channel 16 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " CH15 ,Channel 15 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " CH14 ,Channel 14 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " CH13 ,Channel 13 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " CH12 ,Channel 12 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " CH11 ,Channel 11 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " CH10 ,Channel 10 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " CH9 ,Channel 9 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " CH8 ,Channel 8 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " CH7 ,Channel 7 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " CH6 ,Channel 6 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " CH5 ,Channel 5 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CH4 ,Channel 4 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CH3 ,Channel 3 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CH2 ,Channel 2 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " CH1 ,Channel 1 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " CH0 ,Channel 0 Status" "Disabled,Enabled"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "LCDR,Last Converted Data Register"
|
|
bitfld.long 0x00 24.--27. " CHNB ,Channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " LDATA ,Last data converted"
|
|
group.long 0x2C++0x07
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " EOCAL ,End of Calibration Sequence Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " TEMPCHG ,Temperature Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " RXBUFF ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " ENDRX ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " COMPE ,Comparison Event Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " GOVRE ,General Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " DRDY ,Data Ready Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " EOC23 ,End of Conversion Interrupt Mask 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " EOC22 ,End of Conversion Interrupt Mask 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " EOC22 ,End of Conversion Interrupt Mask 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " EOC22 ,End of Conversion Interrupt Mask 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " EOC19 ,End of Conversion Interrupt Mask 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " EOC18 ,End of Conversion Interrupt Mask 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " EOC17 ,End of Conversion Interrupt Mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " EOC16 ,End of Conversion Interrupt Mask 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " EOC15 ,End of Conversion Interrupt Mask 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " EOC14 ,End of Conversion Interrupt Mask 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " EOC13 ,End of Conversion Interrupt Mask 13" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " EOC12 ,End of Conversion Interrupt Mask 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " EOC11 ,End of Conversion Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " EOC10 ,End of Conversion Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " EOC9 ,End of Conversion Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " EOC8 ,End of Conversion Interrupt Mask 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " EOC7 ,End of Conversion Interrupt Mask 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " EOC6 ,End of Conversion Interrupt Mask 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " EOC5 ,End of Conversion Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " EOC4 ,End of Conversion Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " EOC3 ,End of Conversion Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " EOC2 ,End of Conversion Interrupt Mask 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " EOC1 ,End of Conversion Interrupt Mask 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EOC0 ,End of Conversion Interrupt Mask 0" "Disabled,Enabled"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 31. " EOCAL ,End of Calibration Sequence" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " TEMPCHG ,Temperature Change" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " RXBUFF ,Receive Buffer Full" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ENDRX ,End of Receive Buffer" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " COMPE ,Comparison Event" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " GOVRE ,General Overrun Error" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DRDY ,Data Ready" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " EOC23 ,End of Conversion 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " EOC22 ,End of Conversion 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 21. " EOC22 ,End of Conversion 21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " EOC22 ,End of Conversion 20" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " EOC19 ,End of Conversion 19" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EOC18 ,End of Conversion 18" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " EOC17 ,End of Conversion 17" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " EOC16 ,End of Conversion 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EOC15 ,End of Conversion 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " EOC14 ,End of Conversion 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " EOC13 ,End of Conversion 13" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EOC12 ,End of Conversion 12" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " EOC11 ,End of Conversion 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " EOC10 ,End of Conversion 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EOC9 ,End of Conversion 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " EOC8 ,End of Conversion 8" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " EOC7 ,End of Conversion 7" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " EOC6 ,End of Conversion 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " EOC5 ,End of Conversion 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " EOC4 ,End of Conversion 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EOC3 ,End of Conversion 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " EOC2 ,End of Conversion 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " EOC1 ,End of Conversion 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EOC0 ,End of Conversion 0" "No interrupt,Interrupt"
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "OVER,Overrun Status Register"
|
|
in
|
|
group.long 0x50++0x07
|
|
line.long 0x00 "CWR,Compare Window Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " HIGHTHRES ,High Threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWTHRES ,Low Threshold"
|
|
line.long 0x04 "CGR,Channel Gain Register"
|
|
bitfld.long 0x04 30.--31. " GAIN15 ,Gain for channel 15 (DIFF15=0/DIFF15=1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x04 28.--29. " GAIN14 ,Gain for channel 14 (DIFF14=0/DIFF14=1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x04 26.--27. " GAIN13 ,Gain for channel 13 (DIFF13=0/DIFF13=1)" "1/0.5,1/1,2/2,4/2"
|
|
textline " "
|
|
bitfld.long 0x04 24.--25. " GAIN12 ,Gain for channel 12 (DIFF12=0/DIFF12=1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x04 22.--23. " GAIN11 ,Gain for channel 11 (DIFF11=0/DIFF11=1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x04 20.--21. " GAIN10 ,Gain for channel 10 (DIFF10=0/DIFF10=1)" "1/0.5,1/1,2/2,4/2"
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " GAIN9 ,Gain for channel 9 (DIFF9=0/DIFF9=1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x04 16.--17. " GAIN8 ,Gain for channel 8 (DIFF8=0/DIFF8=1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x04 14.--15. " GAIN7 ,Gain for channel 7 (DIFF7=0/DIFF7=1)" "1/0.5,1/1,2/2,4/2"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " GAIN6 ,Gain for channel 6 (DIFF6=0/DIFF6=1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x04 10.--11. " GAIN5 ,Gain for channel 5 (DIFF5=0/DIFF5=1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x04 8.--9. " GAIN4 ,Gain for channel 4 (DIFF4=0/DIFF4=1)" "1/0.5,1/1,2/2,4/2"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " GAIN3 ,Gain for channel 3 (DIFF3=0/DIFF3=1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x04 4.--5. " GAIN2 ,Gain for channel 2 (DIFF2=0/DIFF2=1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x04 2.--3. " GAIN1 ,Gain for channel 1 (DIFF1=0/DIFF1=1)" "1/0.5,1/1,2/2,4/2"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " GAIN0 ,Gain for channel 0 (DIFF0=0/DIFF0=1)" "1/0.5,1/1,2/2,4/2"
|
|
group.long 0x5C++0x07
|
|
line.long 0x00 "CDOR,Channel DC Offset Register"
|
|
bitfld.long 0x00 23. " OFF23 ,Offset for channel 23" "No offset,Offset"
|
|
bitfld.long 0x00 22. " OFF22 ,Offset for channel 22" "No offset,Offset"
|
|
bitfld.long 0x00 21. " OFF22 ,Offset for channel 21" "No offset,Offset"
|
|
textline " "
|
|
bitfld.long 0x00 20. " OFF22 ,Offset for channel 20" "No offset,Offset"
|
|
bitfld.long 0x00 19. " OFF19 ,Offset for channel 19" "No offset,Offset"
|
|
bitfld.long 0x00 18. " OFF18 ,Offset for channel 18" "No offset,Offset"
|
|
textline " "
|
|
bitfld.long 0x00 17. " OFF17 ,Offset for channel 17" "No offset,Offset"
|
|
bitfld.long 0x00 16. " OFF16 ,Offset for channel 16" "No offset,Offset"
|
|
bitfld.long 0x00 15. " OFF15 ,Offset for channel 15" "No offset,Offset"
|
|
textline " "
|
|
bitfld.long 0x00 14. " OFF14 ,Offset for channel 14" "No offset,Offset"
|
|
bitfld.long 0x00 13. " OFF13 ,Offset for channel 13" "No offset,Offset"
|
|
bitfld.long 0x00 12. " OFF12 ,Offset for channel 12" "No offset,Offset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OFF11 ,Offset for channel 11" "No offset,Offset"
|
|
bitfld.long 0x00 10. " OFF10 ,Offset for channel 10" "No offset,Offset"
|
|
bitfld.long 0x00 9. " OFF9 ,Offset for channel 9" "No offset,Offset"
|
|
textline " "
|
|
bitfld.long 0x00 8. " OFF8 ,Offset for channel 8" "No offset,Offset"
|
|
bitfld.long 0x00 7. " OFF7 ,Offset for channel 7" "No offset,Offset"
|
|
bitfld.long 0x00 6. " OFF6 ,Offset for channel 6" "No offset,Offset"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OFF5 ,Offset for channel 5" "No offset,Offset"
|
|
bitfld.long 0x00 4. " OFF4 ,Offset for channel 4" "No offset,Offset"
|
|
bitfld.long 0x00 3. " OFF3 ,Offset for channel 3" "No offset,Offset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OFF2 ,Offset for channel 2" "No offset,Offset"
|
|
bitfld.long 0x00 1. " OFF1 ,Offset for channel 1" "No offset,Offset"
|
|
bitfld.long 0x00 0. " OFF0 ,Offset for channel 0" "No offset,Offset"
|
|
line.long 0x04 "DIFFR,Channel Differential Register"
|
|
bitfld.long 0x04 23. " DIFF23 ,Differential inputs for channel 23" "Single ended,Differential"
|
|
bitfld.long 0x04 22. " DIFF22 ,Differential inputs for channel 22" "Single ended,Differential"
|
|
bitfld.long 0x04 21. " DIFF22 ,Differential inputs for channel 21" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x04 20. " DIFF22 ,Differential inputs for channel 20" "Single ended,Differential"
|
|
bitfld.long 0x04 19. " DIFF19 ,Differential inputs for channel 19" "Single ended,Differential"
|
|
bitfld.long 0x04 18. " DIFF18 ,Differential inputs for channel 18" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x04 17. " DIFF17 ,Differential inputs for channel 17" "Single ended,Differential"
|
|
bitfld.long 0x04 16. " DIFF16 ,Differential inputs for channel 16" "Single ended,Differential"
|
|
bitfld.long 0x04 15. " DIFF15 ,Differential inputs for channel 15" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x04 14. " DIFF14 ,Differential inputs for channel 14" "Single ended,Differential"
|
|
bitfld.long 0x04 13. " DIFF13 ,Differential inputs for channel 13" "Single ended,Differential"
|
|
bitfld.long 0x04 12. " DIFF12 ,Differential inputs for channel 12" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x04 11. " DIFF11 ,Differential inputs for channel 11" "Single ended,Differential"
|
|
bitfld.long 0x04 10. " DIFF10 ,Differential inputs for channel 10" "Single ended,Differential"
|
|
bitfld.long 0x04 9. " DIFF9 ,Differential inputs for channel 9" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x04 8. " DIFF8 ,Differential inputs for channel 8" "Single ended,Differential"
|
|
bitfld.long 0x04 7. " DIFF7 ,Differential inputs for channel 7" "Single ended,Differential"
|
|
bitfld.long 0x04 6. " DIFF6 ,Differential inputs for channel 6" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x04 5. " DIFF5 ,Differential inputs for channel 5" "Single ended,Differential"
|
|
bitfld.long 0x04 4. " DIFF4 ,Differential inputs for channel 4" "Single ended,Differential"
|
|
bitfld.long 0x04 3. " DIFF3 ,Differential inputs for channel 3" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x04 2. " DIFF2 ,Differential inputs for channel 2" "Single ended,Differential"
|
|
bitfld.long 0x04 1. " DIFF1 ,Differential inputs for channel 1" "Single ended,Differential"
|
|
bitfld.long 0x04 0. " DIFF0 ,Differential inputs for channel 0" "Single ended,Differential"
|
|
rgroup.long 0x64++0x07
|
|
line.long 0x00 "CSELR,Channel Selection Register"
|
|
bitfld.long 0x00 0.--3. " CSEL ,Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CDR,Channel Data Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " DATA ,Converted Data"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "COCR,Channel Offset Compensation Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " AOFF ,Analog Offset"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TEMPMR,Temperature Sensor Mode Register"
|
|
bitfld.long 0x00 4.--5. " TEMPCMPMOD ,Temperature Comparison Mode" "Low,High,In,Out"
|
|
bitfld.long 0x00 0. " RTCT ,Temperature Sensor RTC Trigger mode" "Not triggered,Triggered"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "TEMPCWR,Temperature Compare Window Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " THIGHTHRES ,Temperature High Threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " TLOWTHRES ,Temperature Low Threshold"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "ACR,Analog Control Register"
|
|
bitfld.long 0x00 8.--9. " IBCTL ,AFE Bias Current Control" "00,01,,"
|
|
; if WPMR -> WPKEY == 0x414443
|
|
if (d.l((ad:0x400B0000)+0xE4)&0x41444300)==0x41444300
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect Key (write 0x414443)"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect Key (write 0x414443)"
|
|
endif
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,Write Protect Status Register"
|
|
in
|
|
width 0xB
|
|
tree.end
|
|
tree "AFE 1"
|
|
base ad:0x400B4000
|
|
width 9.
|
|
wgroup.long 0x00++0x3
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x0 3. " AUTOCAL ,Automatic Calibration of AFE" "No effect,Calibrate"
|
|
bitfld.long 0x0 1. " START ,Start Conversion" "No effect,Start"
|
|
bitfld.long 0x0 0. " SWRST ,Software Reset" "No effect,Reset"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x0 31. " USEQ ,Use Sequence Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 28.--29. " TRANSFER ,Transfer Period (AFEClock periods)" "3,5,7,11"
|
|
bitfld.long 0x0 24.--27. " TRACKTIM ,Tracking Time (AFEClock periods)" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x0 23. " ANACH ,Analog Change" "Not allowed,Allowed"
|
|
bitfld.long 0x0 20.--21. " SETTLING ,Analog Settling Time (AFEClock periods)" "3,5,9,17"
|
|
bitfld.long 0x0 16.--19. " STARTUP ,Start Up Time (AFEClock periods)" "0,8,16,24,64,80,96,112,512,576,640,704,768,832,896,960"
|
|
textline " "
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRESCAL ,Prescaler Rate Selection"
|
|
bitfld.long 0x0 7. " FREERUN ,Free Run Mode" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " FWUP ,Fast Wake Up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " SLEEP ,Sleep Mode" "Disabled,Enabled"
|
|
bitfld.long 0x0 1.--3. " TRGSEL ,Trigger Selection" "ADTRG pin,TC Ch 0 TIO out,TC Ch 1 TIO out,TC Ch 2 TIO out,PWM Event Line 0,PWM Event Line 1,,"
|
|
textline " "
|
|
bitfld.long 0x0 0. " TRGEN ,Trigger Enable" "Disabled,Enabled"
|
|
; if EMR -> CMPALL == "Yes"
|
|
if (d.l((ad:0x400B4000)+0x08)&0x200)==0x200
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "EMR,Extended Mode Register"
|
|
bitfld.long 0x0 25. " STM ,Single Trigger Mode" "Multiple trigger,Single trigger"
|
|
bitfld.long 0x0 24. " TAG ,TAG of AFE_LDCR register" "Disabled,Enabled"
|
|
bitfld.long 0x0 16.--18. " RES ,Resolution" "12-bit (no avg),10-bit (no avg),13-bit (avg),14-bit (avg),15-bit (avg),16-bit (avg),,"
|
|
textline " "
|
|
bitfld.long 0x0 12.--13. " CMPFILTER ,Compare Event Filtering" "Disabled,2 compares,3 compares,4 compares"
|
|
bitfld.long 0x0 9. " CMPALL ,Compare All Channels" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " CMPMODE ,Comparison Mode" "Low,High,In,Out"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "EMR,Extended Mode Register"
|
|
bitfld.long 0x0 25. " STM ,Single Trigger Mode" "Multiple trigger,Single trigger"
|
|
bitfld.long 0x0 24. " TAG ,TAG of AFE_LDCR register" "Disabled,Enabled"
|
|
bitfld.long 0x0 16.--18. " RES ,Resolution" "12-bit (no avg),10-bit (no avg),13-bit (avg),14-bit (avg),15-bit (avg),16-bit (avg),,"
|
|
textline " "
|
|
bitfld.long 0x0 12.--13. " CMPFILTER ,Compare Event Filtering" "Disabled,2 compares,3 compares,4 compares"
|
|
bitfld.long 0x0 9. " CMPALL ,Compare All Channels" "No,Yes"
|
|
bitfld.long 0x0 3.--7. " CMPSEL ,Comparison Selected Channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,,,,,,,,"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " CMPMODE ,Comparison Mode" "Low,High,In,Out"
|
|
endif
|
|
; if AFE -> USEQ == "User Sequence Mode"
|
|
if (d.l((ad:0x400B4000)+0x04)&0x80000000)==0x80000000
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "SEQ1R,Channel Sequence 1 Register"
|
|
bitfld.long 0x0 28.--31. " USCH7 ,User Sequence Number 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 24.--27. " USCH6 ,User Sequence Number 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 20.--23. " USCH5 ,User Sequence Number 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " USCH4 ,User Sequence Number 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " USCH3 ,User Sequence Number 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " USCH2 ,User Sequence Number 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " USCH1 ,User Sequence Number 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 0.--3. " USCH0 ,User Sequence Number 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "SEQ2R,Channel Sequence 2 Register"
|
|
bitfld.long 0x4 28.--31. " USCH15 ,User Sequence Number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 24.--27. " USCH14 ,User Sequence Number 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 20.--23. " USCH13 ,User Sequence Number 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 16.--19. " USCH12 ,User Sequence Number 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " USCH11 ,User Sequence Number 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " USCH10 ,User Sequence Number 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 4.--7. " USCH9 ,User Sequence Number 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 0.--3. " USCH8 ,User Sequence Number 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.long 0x0C++0x07
|
|
hide.long 0x00 "SEQ1R,Channel Sequence 1 Register"
|
|
hide.long 0x04 "SEQ2R,Channel Sequence 2 Register"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CHSR,Channel Status Register"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " CH23 ,Channel 23 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " CH22 ,Channel 22 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " CH21 ,Channel 21 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x08 10. -0x04 20. " CH20 ,Channel 20 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " CH19 ,Channel 19 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " CH18 ,Channel 18 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " CH17 ,Channel 17 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " CH16 ,Channel 16 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " CH15 ,Channel 15 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " CH14 ,Channel 14 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " CH13 ,Channel 13 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " CH12 ,Channel 12 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " CH11 ,Channel 11 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " CH10 ,Channel 10 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " CH9 ,Channel 9 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " CH8 ,Channel 8 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " CH7 ,Channel 7 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " CH6 ,Channel 6 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " CH5 ,Channel 5 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CH4 ,Channel 4 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CH3 ,Channel 3 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CH2 ,Channel 2 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " CH1 ,Channel 1 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " CH0 ,Channel 0 Status" "Disabled,Enabled"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "LCDR,Last Converted Data Register"
|
|
bitfld.long 0x00 24.--27. " CHNB ,Channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " LDATA ,Last data converted"
|
|
group.long 0x2C++0x07
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " EOCAL ,End of Calibration Sequence Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " TEMPCHG ,Temperature Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " RXBUFF ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " ENDRX ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " COMPE ,Comparison Event Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " GOVRE ,General Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " DRDY ,Data Ready Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " EOC23 ,End of Conversion Interrupt Mask 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " EOC22 ,End of Conversion Interrupt Mask 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " EOC22 ,End of Conversion Interrupt Mask 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " EOC22 ,End of Conversion Interrupt Mask 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " EOC19 ,End of Conversion Interrupt Mask 19" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " EOC18 ,End of Conversion Interrupt Mask 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " EOC17 ,End of Conversion Interrupt Mask 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " EOC16 ,End of Conversion Interrupt Mask 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " EOC15 ,End of Conversion Interrupt Mask 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " EOC14 ,End of Conversion Interrupt Mask 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " EOC13 ,End of Conversion Interrupt Mask 13" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " EOC12 ,End of Conversion Interrupt Mask 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " EOC11 ,End of Conversion Interrupt Mask 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " EOC10 ,End of Conversion Interrupt Mask 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " EOC9 ,End of Conversion Interrupt Mask 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " EOC8 ,End of Conversion Interrupt Mask 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " EOC7 ,End of Conversion Interrupt Mask 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " EOC6 ,End of Conversion Interrupt Mask 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " EOC5 ,End of Conversion Interrupt Mask 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " EOC4 ,End of Conversion Interrupt Mask 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " EOC3 ,End of Conversion Interrupt Mask 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " EOC2 ,End of Conversion Interrupt Mask 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " EOC1 ,End of Conversion Interrupt Mask 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EOC0 ,End of Conversion Interrupt Mask 0" "Disabled,Enabled"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 31. " EOCAL ,End of Calibration Sequence" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " TEMPCHG ,Temperature Change" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " RXBUFF ,Receive Buffer Full" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ENDRX ,End of Receive Buffer" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " COMPE ,Comparison Event" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " GOVRE ,General Overrun Error" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DRDY ,Data Ready" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " EOC23 ,End of Conversion 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " EOC22 ,End of Conversion 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 21. " EOC22 ,End of Conversion 21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " EOC22 ,End of Conversion 20" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " EOC19 ,End of Conversion 19" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EOC18 ,End of Conversion 18" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " EOC17 ,End of Conversion 17" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " EOC16 ,End of Conversion 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EOC15 ,End of Conversion 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " EOC14 ,End of Conversion 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " EOC13 ,End of Conversion 13" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EOC12 ,End of Conversion 12" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " EOC11 ,End of Conversion 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " EOC10 ,End of Conversion 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EOC9 ,End of Conversion 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " EOC8 ,End of Conversion 8" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " EOC7 ,End of Conversion 7" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " EOC6 ,End of Conversion 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " EOC5 ,End of Conversion 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " EOC4 ,End of Conversion 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EOC3 ,End of Conversion 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " EOC2 ,End of Conversion 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " EOC1 ,End of Conversion 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EOC0 ,End of Conversion 0" "No interrupt,Interrupt"
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "OVER,Overrun Status Register"
|
|
in
|
|
group.long 0x50++0x07
|
|
line.long 0x00 "CWR,Compare Window Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " HIGHTHRES ,High Threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " LOWTHRES ,Low Threshold"
|
|
line.long 0x04 "CGR,Channel Gain Register"
|
|
bitfld.long 0x04 30.--31. " GAIN15 ,Gain for channel 15 (DIFF15=0/DIFF15=1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x04 28.--29. " GAIN14 ,Gain for channel 14 (DIFF14=0/DIFF14=1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x04 26.--27. " GAIN13 ,Gain for channel 13 (DIFF13=0/DIFF13=1)" "1/0.5,1/1,2/2,4/2"
|
|
textline " "
|
|
bitfld.long 0x04 24.--25. " GAIN12 ,Gain for channel 12 (DIFF12=0/DIFF12=1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x04 22.--23. " GAIN11 ,Gain for channel 11 (DIFF11=0/DIFF11=1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x04 20.--21. " GAIN10 ,Gain for channel 10 (DIFF10=0/DIFF10=1)" "1/0.5,1/1,2/2,4/2"
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " GAIN9 ,Gain for channel 9 (DIFF9=0/DIFF9=1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x04 16.--17. " GAIN8 ,Gain for channel 8 (DIFF8=0/DIFF8=1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x04 14.--15. " GAIN7 ,Gain for channel 7 (DIFF7=0/DIFF7=1)" "1/0.5,1/1,2/2,4/2"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " GAIN6 ,Gain for channel 6 (DIFF6=0/DIFF6=1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x04 10.--11. " GAIN5 ,Gain for channel 5 (DIFF5=0/DIFF5=1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x04 8.--9. " GAIN4 ,Gain for channel 4 (DIFF4=0/DIFF4=1)" "1/0.5,1/1,2/2,4/2"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " GAIN3 ,Gain for channel 3 (DIFF3=0/DIFF3=1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x04 4.--5. " GAIN2 ,Gain for channel 2 (DIFF2=0/DIFF2=1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x04 2.--3. " GAIN1 ,Gain for channel 1 (DIFF1=0/DIFF1=1)" "1/0.5,1/1,2/2,4/2"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " GAIN0 ,Gain for channel 0 (DIFF0=0/DIFF0=1)" "1/0.5,1/1,2/2,4/2"
|
|
group.long 0x5C++0x07
|
|
line.long 0x00 "CDOR,Channel DC Offset Register"
|
|
bitfld.long 0x00 23. " OFF23 ,Offset for channel 23" "No offset,Offset"
|
|
bitfld.long 0x00 22. " OFF22 ,Offset for channel 22" "No offset,Offset"
|
|
bitfld.long 0x00 21. " OFF22 ,Offset for channel 21" "No offset,Offset"
|
|
textline " "
|
|
bitfld.long 0x00 20. " OFF22 ,Offset for channel 20" "No offset,Offset"
|
|
bitfld.long 0x00 19. " OFF19 ,Offset for channel 19" "No offset,Offset"
|
|
bitfld.long 0x00 18. " OFF18 ,Offset for channel 18" "No offset,Offset"
|
|
textline " "
|
|
bitfld.long 0x00 17. " OFF17 ,Offset for channel 17" "No offset,Offset"
|
|
bitfld.long 0x00 16. " OFF16 ,Offset for channel 16" "No offset,Offset"
|
|
bitfld.long 0x00 15. " OFF15 ,Offset for channel 15" "No offset,Offset"
|
|
textline " "
|
|
bitfld.long 0x00 14. " OFF14 ,Offset for channel 14" "No offset,Offset"
|
|
bitfld.long 0x00 13. " OFF13 ,Offset for channel 13" "No offset,Offset"
|
|
bitfld.long 0x00 12. " OFF12 ,Offset for channel 12" "No offset,Offset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OFF11 ,Offset for channel 11" "No offset,Offset"
|
|
bitfld.long 0x00 10. " OFF10 ,Offset for channel 10" "No offset,Offset"
|
|
bitfld.long 0x00 9. " OFF9 ,Offset for channel 9" "No offset,Offset"
|
|
textline " "
|
|
bitfld.long 0x00 8. " OFF8 ,Offset for channel 8" "No offset,Offset"
|
|
bitfld.long 0x00 7. " OFF7 ,Offset for channel 7" "No offset,Offset"
|
|
bitfld.long 0x00 6. " OFF6 ,Offset for channel 6" "No offset,Offset"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OFF5 ,Offset for channel 5" "No offset,Offset"
|
|
bitfld.long 0x00 4. " OFF4 ,Offset for channel 4" "No offset,Offset"
|
|
bitfld.long 0x00 3. " OFF3 ,Offset for channel 3" "No offset,Offset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OFF2 ,Offset for channel 2" "No offset,Offset"
|
|
bitfld.long 0x00 1. " OFF1 ,Offset for channel 1" "No offset,Offset"
|
|
bitfld.long 0x00 0. " OFF0 ,Offset for channel 0" "No offset,Offset"
|
|
line.long 0x04 "DIFFR,Channel Differential Register"
|
|
bitfld.long 0x04 23. " DIFF23 ,Differential inputs for channel 23" "Single ended,Differential"
|
|
bitfld.long 0x04 22. " DIFF22 ,Differential inputs for channel 22" "Single ended,Differential"
|
|
bitfld.long 0x04 21. " DIFF22 ,Differential inputs for channel 21" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x04 20. " DIFF22 ,Differential inputs for channel 20" "Single ended,Differential"
|
|
bitfld.long 0x04 19. " DIFF19 ,Differential inputs for channel 19" "Single ended,Differential"
|
|
bitfld.long 0x04 18. " DIFF18 ,Differential inputs for channel 18" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x04 17. " DIFF17 ,Differential inputs for channel 17" "Single ended,Differential"
|
|
bitfld.long 0x04 16. " DIFF16 ,Differential inputs for channel 16" "Single ended,Differential"
|
|
bitfld.long 0x04 15. " DIFF15 ,Differential inputs for channel 15" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x04 14. " DIFF14 ,Differential inputs for channel 14" "Single ended,Differential"
|
|
bitfld.long 0x04 13. " DIFF13 ,Differential inputs for channel 13" "Single ended,Differential"
|
|
bitfld.long 0x04 12. " DIFF12 ,Differential inputs for channel 12" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x04 11. " DIFF11 ,Differential inputs for channel 11" "Single ended,Differential"
|
|
bitfld.long 0x04 10. " DIFF10 ,Differential inputs for channel 10" "Single ended,Differential"
|
|
bitfld.long 0x04 9. " DIFF9 ,Differential inputs for channel 9" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x04 8. " DIFF8 ,Differential inputs for channel 8" "Single ended,Differential"
|
|
bitfld.long 0x04 7. " DIFF7 ,Differential inputs for channel 7" "Single ended,Differential"
|
|
bitfld.long 0x04 6. " DIFF6 ,Differential inputs for channel 6" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x04 5. " DIFF5 ,Differential inputs for channel 5" "Single ended,Differential"
|
|
bitfld.long 0x04 4. " DIFF4 ,Differential inputs for channel 4" "Single ended,Differential"
|
|
bitfld.long 0x04 3. " DIFF3 ,Differential inputs for channel 3" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x04 2. " DIFF2 ,Differential inputs for channel 2" "Single ended,Differential"
|
|
bitfld.long 0x04 1. " DIFF1 ,Differential inputs for channel 1" "Single ended,Differential"
|
|
bitfld.long 0x04 0. " DIFF0 ,Differential inputs for channel 0" "Single ended,Differential"
|
|
rgroup.long 0x64++0x07
|
|
line.long 0x00 "CSELR,Channel Selection Register"
|
|
bitfld.long 0x00 0.--3. " CSEL ,Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CDR,Channel Data Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " DATA ,Converted Data"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "COCR,Channel Offset Compensation Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " AOFF ,Analog Offset"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TEMPMR,Temperature Sensor Mode Register"
|
|
bitfld.long 0x00 4.--5. " TEMPCMPMOD ,Temperature Comparison Mode" "Low,High,In,Out"
|
|
bitfld.long 0x00 0. " RTCT ,Temperature Sensor RTC Trigger mode" "Not triggered,Triggered"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "TEMPCWR,Temperature Compare Window Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " THIGHTHRES ,Temperature High Threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " TLOWTHRES ,Temperature Low Threshold"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "ACR,Analog Control Register"
|
|
bitfld.long 0x00 8.--9. " IBCTL ,AFE Bias Current Control" "00,01,,"
|
|
; if WPMR -> WPKEY == 0x414443
|
|
if (d.l((ad:0x400B4000)+0xE4)&0x41444300)==0x41444300
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect Key (write 0x414443)"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect Key (write 0x414443)"
|
|
endif
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,Write Protect Status Register"
|
|
in
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "GMAC (Ethernet MAC)"
|
|
base ad:0x40034000
|
|
width 11.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "NCR,Network Control Register"
|
|
sif (cpuis("ATSAME5*"))||(cpuis("ATSAMAD2*"))||(cpuis("ATSAMAD4*"))
|
|
bitfld.long 0x00 19. " LPI ,Low power idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " FNP ,Flush next packet" "No flush,Flush"
|
|
bitfld.long 0x00 17. " TXPBPF ,Transmit PFC priority-based pause frame" "Not transmitted,Transmitted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ENPBPR ,Enable PFC priority-based pause reception" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SRTSM ,Store receive time stamp to memory" "No effect,Stored"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TXZQPF ,Transmit zero quantum pause frame" "Not transmitted,Transmitted"
|
|
bitfld.long 0x00 11. " TXPF ,Transmit pause frame" "Not transmitted,Transmitted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " THALT ,Transmit halt" "Not halted,Halted"
|
|
bitfld.long 0x00 9. " TSTART ,Start transmission" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BP ,Back pressure" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " WESTAT ,Write enable for statistics registers" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INCSTAT ,Increment statistics registers" "No,Yes"
|
|
bitfld.long 0x00 5. " CLRSTAT ,Clear statistics registers" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MPE ,Management port enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TXEN ,Transmit enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RXEN ,Receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LBL ,Loop back local" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("ATSAM4E*")
|
|
bitfld.long 0x00 0. " LB ,Loopback pin control" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "NCFGR,Network Configuration Register"
|
|
bitfld.long 0x04 30. " IRXER ,Ignore IPG GRXER" "Not ignored,Ignored"
|
|
bitfld.long 0x04 29. " RXBP ,Receive bad preamble" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x04 28. " IPGSEN ,IP stretch enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " IRXFCS ,Ignore RX FCS" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x04 25. " EFRHD ,Enable frames received in half duplex" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " RXCOEN ,Receive checksum offload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " DCPF ,Disable copy of pause frames" "No,Yes"
|
|
textline " "
|
|
sif (!cpuis("ATSAME5*"))
|
|
bitfld.long 0x04 21.--22. " DBW ,Data bus width" "32-bit,64-bit,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 18.--20. " CLK ,MDC clock division" "MCK/8,MCK/16,MCK/32,MCK/48,MCK/64,MCK/96,?..."
|
|
bitfld.long 0x04 17. " RFCS ,Remove FCS" "Not removed,Removed"
|
|
textline " "
|
|
bitfld.long 0x04 16. " LFERD ,Length field error frame discard" "Disabled,Enabled"
|
|
bitfld.long 0x04 14.--15. " RXBUFO ,Receive buffer offset" "0 bytes,1 byte,2 bytes,3 bytes"
|
|
textline " "
|
|
bitfld.long 0x04 13. " PEN ,Pause enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RTY ,Retry test" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ATSAM4E*")||cpuis("ATSAMA5D4*")||cpuis("ATSAMA5D2?")||cpuis("ATSAME5*"))
|
|
bitfld.long 0x04 8. " MAXFS ,1536 maximum frame size" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x04 10. " GBE ,Gigabit mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " MAXFS ,1536 maximum frame size" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 7. " UNIHEN ,Unicast hash enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " MTIHEN ,Multicast hash enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " NBC ,No broadcast" "Broadcast,No broadcast"
|
|
bitfld.long 0x04 4. " CAF ,Copy all frames" "Not all frames,Copy all"
|
|
textline " "
|
|
bitfld.long 0x04 3. " JFRAME ,Jumbo frame size" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " DNVLAN ,Discard non-VLAN frames" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FD ,Full duplex" "Not full,Full"
|
|
bitfld.long 0x04 0. " SPD ,Speed" "10 Mbps,100 Mbps"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "NSR,Network Status Register"
|
|
sif (cpuis("ATSAMA5D2?"))||(cpuis("ATSAMA5D4?"))
|
|
bitfld.long 0x00 7. " RXLPIS ,LPI indication" "Not detected,Detected"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " IDLE ,PHY management logic idle" "Not idle,Idle"
|
|
bitfld.long 0x00 1. " MDIO ,MDIO input status" "0,1"
|
|
sif cpuis("ATSAM4E*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "UR,User Register"
|
|
bitfld.long 0x00 7. " BPDG ,Bypass deglitchers" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 6. " HDFC ,Half-duplex flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RMII ,Reduced MII mode" "MII,RMII"
|
|
elif (cpuis("ATSAMA5D4*")||cpuis("ATSAMA5D2?"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "UR,User Register"
|
|
bitfld.long 0x00 0. " RMII ,Reduced MII mode" "MII,RMII"
|
|
elif (cpuis("ATSAME5*"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "UR,User Register"
|
|
bitfld.long 0x00 0. " MII ,Reduced MII mode" "RMII,MII"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "UR,User Register"
|
|
bitfld.long 0x00 0. " RGMII ,Reduced GMII mode" "GMII,RGMII"
|
|
endif
|
|
sif cpuis("ATSAM4E*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "DCFGR,DMA Configuration Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DRBS ,DMA receive buffer size"
|
|
bitfld.long 0x00 11. " TXCOEN ,Transmitter checksum generation offload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ESPA ,Endian swap mode enable for packet data accesses" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ESMA ,Endian swap mode enable for management descriptor accesses" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " FBLDO ,Fixed burst length for DMA data operations" ",SINGLE,,,INCR4,INCR4,INCR4,INCR4,INCR8,INCR8,INCR8,INCR8,INCR8,INCR8,INCR8,INCR8,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16"
|
|
elif cpuis("ATSAMA5D4*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "DCFGR,DMA Configuration Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DRBS ,DMA receive buffer size"
|
|
bitfld.long 0x00 7. " ESPA ,Endian swap mode enable for packet data accesses" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ESMA ,Endian swap mode enable for management descriptor accesses" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " FBLDO ,Fixed burst length for DMA data operations" ",SINGLE,,,INCR4,INCR4,INCR4,INCR4,INCR8,INCR8,INCR8,INCR8,INCR8,INCR8,INCR8,INCR8,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "DCFGR,DMA Configuration Register"
|
|
bitfld.long 0x00 24. " DDRP ,DMA discard receive packets" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DRBS ,DMA receive buffer size"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TXCOEN ,Transmitter checksum generation offload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TXPBMS ,Transmitter packet buffer memory size select" "2 Kbytes,4 Kbytes"
|
|
textline " "
|
|
sif (cpuis("ATSAME5*"))||(cpuis("ATSAMA5D2?"))||(cpuis("ATSAMA5D3?"))
|
|
bitfld.long 0x00 8.--9. " RXBMS ,Receiver packet buffer memory size select" "RECEIVE_BUFFER_SIZE/8 KB,1 RECEIVE_BUFFER_SIZE/4 KB,RECEIVE_BUFFER_SIZE/2 KB,RECEIVE_BUFFER_SIZE KB"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--9. " RXBMS ,Receiver packet buffer memory size select" "1/2 Kbyte,1 Kbyte,2 Kbytes,4 Kbytes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " ESPA ,Endian swap mode enable for packet data accesses" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ESMA ,Endian swap mode enable for management descriptor accesses" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " FBLDO ,Fixed burst length for DMA data operations" ",SINGLE,,,INCR4,INCR4,INCR4,INCR4,INCR8,INCR8,INCR8,INCR8,INCR8,INCR8,INCR8,INCR8,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16,INCR16"
|
|
endif
|
|
group.long 0x14++0x0F
|
|
line.long 0x00 "TSR,Transmit Status Register"
|
|
eventfld.long 0x00 8. " HRESP ,HRESP not OK" "False,True"
|
|
textline " "
|
|
sif (!cpuis("ATSAMA5D4*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAMA5D2?")&&!cpuis("ATSAME5*"))
|
|
eventfld.long 0x00 7. " LCO ,Late collision occurred" "Not occurred,Occurred"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D2?")&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAME5*"))
|
|
bitfld.long 0x00 6. " UND ,Transmit under run" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 5. " TXCOMP ,Transmit complete" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 4. " TFC ,Transmit frame corruption due to AHB error" "No error,Error"
|
|
bitfld.long 0x00 3. " TXGO ,Transmit go" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 2. " RLE ,Retry limit exceeded" "Not exceeded,Exceeded"
|
|
eventfld.long 0x00 1. " COL ,Collision occurred" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " UBR ,Used bit read" "Disabled,Enabled"
|
|
line.long 0x04 "RBQB,Receive Buffer Queue Base Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " ADDR ,Receive buffer queue base address"
|
|
line.long 0x08 "TBQB,Transmit Buffer Queue Base Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " ADDR ,Transmit buffer queue base address"
|
|
line.long 0x0C "RSR,Receive Status Register"
|
|
eventfld.long 0x0C 3. " HNO ,HRESP not OK" "Disabled,Enabled"
|
|
eventfld.long 0x0C 2. " RXOVR ,Receive overrun" "No overrun,Overrun"
|
|
textline " "
|
|
eventfld.long 0x0C 1. " REC ,Frame received" "Not received,Received"
|
|
eventfld.long 0x0C 0. " BNA ,Buffer not available" "No,Yes"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "ISR,Interrupt Status Register"
|
|
in
|
|
sif (!cpuis("ATSAMA5D2?"))&&(!cpuis("ATSAMA5D4?"))&&(!cpuis("ATSAME5*"))
|
|
wgroup.long 0x28++0x07
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 28. " WOL ,Wake on LAN" "No effect,Enable"
|
|
bitfld.long 0x00 26. " SRI ,TSU seconds register increment" "No effect,Enable"
|
|
line.long 0x04 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x04 28. " WOL ,Wake on LAN" "No effect,Disable"
|
|
bitfld.long 0x04 26. " SRI ,TSU seconds register increment" "No effect,Disable"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "IMR,Interrupt Mask Register"
|
|
sif (cpuis("ATSAMA5D2?"))||(cpuis("ATSAMA5D4?"))||(cpuis("ATSAME5*"))
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " TSUTIMCOMP_set/clr ,TSU timer comparison" "Not masked,Masked"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " WOL_set/clr ,Wake on LAN" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " RXLPISBC_set/clr ,Enable RX LPI indication" "Not masked,Masked"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " SRI_set/clr ,TSU seconds register increment" "Not masked,Masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " PDRSFT_set/clr ,PDelay response frame transmitted" "Not masked,Masked"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " PDRQFT_set/clr ,PDelay request frame transmitted" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x8 23. -0x4 23. " PDRSFR_set/clr ,PDelay response frame received" "Not masked,Masked"
|
|
setclrfld.long 0x00 22. -0x8 22. -0x4 22. " PDRQFR_set/clr ,PDelay request frame received" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x8 21. -0x4 21. " SFT_set/clr ,PTP sync frame transmitted" "Not masked,Masked"
|
|
setclrfld.long 0x00 20. -0x8 20. -0x4 20. " DRQFT_set/clr ,PTP delay request frame transmitted" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " SFR_set/clr ,PTP sync frame received" "Not masked,Masked"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DRQFR_set/clr ,PTP delay request frame received" "Not masked,Masked"
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D4*")||cpuis("ATSAMA5D3*")||cpuis("ATSAMA5D2?")||cpuis("ATSAME5*"))
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " EXINT_set/clr ,External interrupt" "Not masked,Masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " PFTR_set/clr ,Pause frame transmitted" "Not masked,Masked"
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " PTZ_set/clr ,Pause time zero" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " PFNZ_set/clr ,Pause frame with non-zero pause quantum received" "Not masked,Masked"
|
|
setclrfld.long 0x00 11. -0x8 11. -0x4 11. " HRESP_set/clr ,HRESP not OK" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ROVR_set/clr ,Receive overrun" "Not masked,Masked"
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " TCOMP_set/clr ,Transmit complete" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " TFC_set/clr ,Transmit frame corruption due to AHB error" "Not masked,Masked"
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " RLEX_set/clr ,Retry limit exceeded or late collision" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " TUR_set/clr ,Transmit under run" "Not masked,Masked"
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " TXUBR_set/clr ,TX used bit read" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " RXUBR_set/clr ,RX used bit read" "Not masked,Masked"
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " RCOMP_set/clr ,Receive complete" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " MFS_set/clr ,Management frame sent" "Not masked,Masked"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "MAN,PHY Maintenance Register"
|
|
bitfld.long 0x00 31. " WZO ,Write ZERO" "0,?..."
|
|
bitfld.long 0x00 30. " CLTTO ,Clause 22 operation" "Clause 45,Clause 22"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " OP ,Operation" ",Write,Read,?..."
|
|
hexmask.long.byte 0x00 23.--27. 0x80 " PHYA ,PHY address"
|
|
textline " "
|
|
hexmask.long.byte 0x00 18.--22. 0x04 " REGA ,Register address"
|
|
bitfld.long 0x00 16.--17. " WTN ,Write ten (must be written to 10)" ",,10,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,PHY data"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "RPQ,Receive Pause Quantum Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RPQ ,Received pause quantum"
|
|
sif (cpuis("ATSAM4E*")||cpuis("ATSAMA5D4*"))
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TPQ,Transmit Pause Quantum Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TPQ ,Transmit pause quantum"
|
|
else
|
|
group.long 0x3C++0x0B
|
|
line.long 0x00 "TPQ,Transmit Pause Quantum Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TPQ ,Transmit pause quantum"
|
|
line.long 0x04 "TPSF,TX Partial Store and Forward Register"
|
|
bitfld.long 0x04 31. " ENTXP ,Enable TX partial store and forward operation" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 0.--11. 0x01 " TPB1ADR ,Transmit partial store and forward address"
|
|
line.long 0x08 "RPSF,RX Partial Store and Forward Register"
|
|
bitfld.long 0x08 31. " ENRXP ,Enable RX partial store and forward operation" "Disabled,Enabled"
|
|
hexmask.long.word 0x08 0.--11. 0x01 " RPB1ADR ,Receive partial store and forward address"
|
|
endif
|
|
sif (cpuis("ATSAMA5D2?")||cpuis("ATSAMA5D3*")||cpuis("ATSAMA5D4*")||cpuis("ATSAME5"))
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "RJFML,RX Jumbo Frame Max Length Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " FML ,Frame max length"
|
|
endif
|
|
sif (cpuis("ATSAME5*"))
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "HRB,Hash Register Bottom [31:0] Register"
|
|
line.long 0x04 "HRT,Hash Register Top [63:32] Register"
|
|
else
|
|
rgroup.long 0x80++0x07
|
|
line.long 0x00 "HRB,Hash Register Bottom [31:0] Register"
|
|
line.long 0x04 "HRT,Hash Register Top [63:32] Register"
|
|
endif
|
|
group.long 0x88++0x1F
|
|
line.long 0x00 "SAB1,Specific Address 1 Bottom [31:0] Register"
|
|
line.long 0x04 "SAT1,Specific Address 1 Top [47:32] Register"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " ADDR ,Specific address 1"
|
|
line.long 0x08 "SAB2,Specific Address 2 Bottom [31:0] Register"
|
|
line.long 0x0C "SAT2,Specific Address 2 Top [47:32] Register"
|
|
hexmask.long.word 0x0C 0.--15. 0x01 " ADDR ,Specific address 2"
|
|
line.long 0x10 "SAB3,Specific Address 3 Bottom [31:0] Register"
|
|
line.long 0x14 "SAT3,Specific Address 3 Top [47:32] Register"
|
|
hexmask.long.word 0x14 0.--15. 0x01 " ADDR ,Specific address 3"
|
|
line.long 0x18 "SAB4,Specific Address 4 Bottom [31:0] Register"
|
|
line.long 0x1C "SAT4,Specific Address 4 Top [47:32] Register"
|
|
hexmask.long.word 0x1C 0.--15. 0x01 " ADDR ,Specific address 4"
|
|
sif (cpuis("ATSAMA5D4*")||cpuis("ATSAMA5D3*")||cpuis("ATSAMA5D2?")||cpuis("ATSAME5*"))
|
|
group.long 0xA8++0x0F
|
|
line.long 0x00 "TIDM1,Type ID Match 1 Register"
|
|
bitfld.long 0x00 31. " ENID1 ,Enable copying of TID matched frames" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--15. 1. " TID ,Type ID match 1"
|
|
line.long 0x04 "TIDM2,Type ID Match 2 Register"
|
|
bitfld.long 0x04 31. " ENID2 ,Enable copying of TID matched frames" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 0.--15. 1. " TID ,Type ID match 2"
|
|
line.long 0x08 "TIDM3,Type ID Match 3 Register"
|
|
bitfld.long 0x08 31. " ENID3 ,Enable copying of TID matched frames" "Disabled,Enabled"
|
|
hexmask.long.word 0x08 0.--15. 1. " TID ,Type ID match 3"
|
|
line.long 0x0C "TIDM4,Type ID Match 4 Register"
|
|
bitfld.long 0x0C 31. " ENID4 ,Enable copying of TID matched frames" "Disabled,Enabled"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TID ,Type ID match 4"
|
|
else
|
|
group.long 0xA8++0x0F
|
|
line.long 0x00 "TIDM1,Type ID Match 1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TID ,Type ID match 1"
|
|
line.long 0x04 "TIDM2,Type ID Match 2 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TID ,Type ID match 2"
|
|
line.long 0x08 "TIDM3,Type ID Match 3 Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " TID ,Type ID match 3"
|
|
line.long 0x0C "TIDM4,Type ID Match 4 Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TID ,Type ID match 4"
|
|
endif
|
|
sif !cpuis("ATSAM4E*")
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "WOL,Wake on LAN Register"
|
|
bitfld.long 0x00 19. " MTI ,Multicast hash event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SA1 ,Specific address register 1 event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ARP ,ARP request event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " MAG ,Magic packet event enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 0x01 " IP ,ARP request IP address"
|
|
endif
|
|
group.long 0xBC++0x13
|
|
line.long 0x00 "IPGS,IPG Stretch Register"
|
|
hexmask.long.word 0X00 0.--15. 1. " FL ,Frame length"
|
|
line.long 0x04 "SVLAN,Stacked VLAN Register"
|
|
bitfld.long 0x04 31. " ESVLAN ,Enable stacked VLAN processing mode" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 0.--15. 1. " VLAN_TYPE ,User defined VLAN_TYPE field"
|
|
line.long 0x08 "TPFCP,Transmit PFC Pause Register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " PQ ,Pause quantum"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PEV ,Priority enable vector"
|
|
line.long 0x0C "SAMB1,Specific Address 1 Mask Bottom [31:0] Register"
|
|
line.long 0x10 "SAMT1,Specific Address Mask 1 Top [47:32] Register"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " ADDR ,Specific address 1 mask"
|
|
sif (cpuis("ATSAMA5D2?")||cpuis("ATSAMA5D3*")||cpuis("ATSAMA5D4*")||cpuis("ATSAME5*"))
|
|
group.long 0xDC++0x0B
|
|
line.long 0x00 "NSC,1588 Timer Nanosecond Comparison Register"
|
|
hexmask.long.tbyte 0x00 0.--21. 1. " NANOSEC ,1588 timer nanosecond comparison value"
|
|
line.long 0x04 "SCL,1588 Timer Second Comparison Low Register"
|
|
line.long 0x08 "SCH,1588 Timer Second Comparison High Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " SEC ,1588 timer second comparison value"
|
|
rgroup.long 0xE8++0x0F
|
|
line.long 0x00 "EFTSH,PTP Event Frame Transmitted Seconds High Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RUD ,Register update"
|
|
line.long 0x04 "EFRSH,PTP Event Frame Received Seconds High Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RUD ,Register update"
|
|
line.long 0x08 "PEFTSH,PTP Peer Event Frame Transmitted Seconds High Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " RUD ,Register update"
|
|
line.long 0x0C "PEFRSH,PTP Peer Event Frame Received Seconds High Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " RUD ,Register update"
|
|
endif
|
|
rgroup.long 0x100++0xB3
|
|
line.long 0x00 "OTLO,Octets Transmitted [31:0] Register"
|
|
line.long 0x04 "OTHI,Octets Transmitted [47:32] Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TXO ,Transmitted octets"
|
|
line.long 0x08 "FT,Frames Transmitted Register"
|
|
line.long 0x0C "BCFT,Broadcast Frames Transmitted Register"
|
|
line.long 0x10 "MFT,Multicast Frames Transmitted Register"
|
|
line.long 0x14 "PFT,Pause Frames Transmitted Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " PFTX ,Pause frames transmitted register"
|
|
line.long 0x18 "BFT64,64 Byte Frames Transmitted Register"
|
|
line.long 0x1C "TBFT127,65 to 127 Byte Frames Transmitted Register"
|
|
line.long 0x20 "TBFT255,128 to 255 Byte Frames Transmitted Register"
|
|
line.long 0x24 "TBFT511,256 to 511 Byte Frames Transmitted Register"
|
|
line.long 0x28 "TBFT1023,512 to 1023 Byte Frames Transmitted Register"
|
|
line.long 0x2C "TBFT1518,1024 to 1518 Byte Frames Transmitted Register"
|
|
line.long 0x30 "GTBFT1518,Greater Than 1518 Byte Frames Transmitted Register"
|
|
line.long 0x34 "TUR,Transmit Under Runs Register"
|
|
hexmask.long.word 0x34 0.--9. 1. " TXUNR ,Transmit underruns"
|
|
line.long 0x38 "SCF,Single Collision Frames Register"
|
|
hexmask.long.tbyte 0x38 0.--17. 1. " SCOL ,Single collision"
|
|
line.long 0x3C "MCF,Multiple Collision Frames Register"
|
|
hexmask.long.tbyte 0x3C 0.--17. 1. " MCOL ,Multiple collision"
|
|
line.long 0x40 "EC,Excessive Collisions Register"
|
|
hexmask.long.word 0x40 0.--9. 1. " XCOL ,Excessive collisions"
|
|
line.long 0x44 "LC,Late Collisions Register"
|
|
hexmask.long.word 0x44 0.--9. 1. " LCOL ,Late collisions"
|
|
line.long 0x48 "DTF,Deferred Transmission Frames Register"
|
|
hexmask.long.tbyte 0x48 0.--17. 1. " DEFT ,Deferred transmission"
|
|
line.long 0x4C "CSE,Carrier Sense Errors Register"
|
|
hexmask.long.word 0x4C 0.--9. 1. " CSR ,Carrier sense error"
|
|
line.long 0x50 "ORLO,Octets Received [31:0] Register"
|
|
line.long 0x54 "ORHI,Octets Received [47:32] Register"
|
|
hexmask.long.word 0x54 0.--15. 1. " RXO ,Received octets"
|
|
line.long 0x58 "FR,Frames Received Register"
|
|
line.long 0x5C "BCFR,Broadcast Frames Received Register"
|
|
line.long 0x60 "MFR,Multicast Frames Received Register"
|
|
line.long 0x64 "PFR,Pause Frames Received Register"
|
|
hexmask.long.word 0x64 0.--15. 1. " PFRX ,Pause frames received register"
|
|
line.long 0x68 "BFR64,64 Byte Frames Received Register"
|
|
line.long 0x6C "TBFR127,65 to 127 Byte Frames Received Register"
|
|
line.long 0x70 "TBFR255,128 to 255 Byte Frames Received Register"
|
|
line.long 0x74 "TBFR511,256 to 511 Byte Frames Received Register"
|
|
line.long 0x78 "TBFR1023,512 to 1023 Byte Frames Received Register"
|
|
line.long 0x7C "TBFR1518,1024 to 1518 Byte Frames Received Register"
|
|
line.long 0x80 "TMXBFR,1519 to Maximum Byte Frames Received Register"
|
|
line.long 0x84 "UFR,Undersized Frames Received Register"
|
|
hexmask.long.word 0x84 0.--9. 1. " UFRX ,Undersize frames received"
|
|
line.long 0x88 "OFR,Oversized Frames Received Register"
|
|
hexmask.long.word 0x88 0.--9. 1. " OFRX ,Oversized frames received"
|
|
line.long 0x8C "JR,Jabbers Received Register"
|
|
hexmask.long.word 0x8C 0.--9. 1. " JRX ,Jabbers received"
|
|
line.long 0x90 "FCSE,Frame Check Sequence Errors Register"
|
|
hexmask.long.word 0x90 0.--9. 1. " FCKR ,Frame check sequence errors"
|
|
line.long 0x94 "LFFE,Length Field Frame Errors Register"
|
|
hexmask.long.word 0x94 0.--9. 1. " LFER ,Length field frame errors"
|
|
line.long 0x98 "RSE,Receive Symbol Errors Register"
|
|
hexmask.long.word 0x98 0.--9. 1. " RXSE ,Receive symbol errors"
|
|
line.long 0x9C "AE,Alignment Errors Register"
|
|
hexmask.long.word 0x9C 0.--9. 1. " AER ,Alignment errors"
|
|
line.long 0xA0 "RRE,Receive Resource Errors Register"
|
|
hexmask.long.tbyte 0xA0 0.--17. 1. " RXRER ,Receive resource errors"
|
|
line.long 0xA4 "ROE,Receive Overruns Register"
|
|
hexmask.long.word 0xA4 0.--9. 1. " RXOVR ,Receive overruns"
|
|
line.long 0xA8 "IHCE,IP Header Checksum Errors Register"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " HCKER ,IP header checksum errors"
|
|
line.long 0xAC "TCE,TCP Checksum Errors Register"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " TCKER ,TCP checksum errors"
|
|
line.long 0xB0 "UCE,UDP Checksum Errors Register"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " UCKER ,UDP checksum errors"
|
|
sif (cpuis("ATSAMA5D2?")||cpuis("ATSAMA5D3*")||cpuis("ATSAMA5D4*")||cpuis("ATSAME5*"))
|
|
group.long 0x1BC++0x07
|
|
line.long 0x00 "TISUBN,1588 Timer Increment Sub-nanoseconds Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LSBTIR ,Lower significant bits of timer increment register"
|
|
line.long 0x04 "TSH,1588 Timer Seconds High Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " TCS ,Timer count in seconds"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "TSL,1588 Timer Seconds Low Register"
|
|
sif (cpuis("ATSAME5*"))
|
|
group.long 0x1C8++0x07
|
|
line.long 0x00 "TSSSL,1588 Timer Sync Strobe Seconds Register"
|
|
line.long 0x04 "TSSN,1588 Timer Sync Strobe Nanoseconds Register"
|
|
hexmask.long 0x04 0.--29. 1. " VTN ,Value timer nanoseconds register capture"
|
|
endif
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "TN,1588 Timer Nanoseconds Register"
|
|
hexmask.long 0x00 0.--29. 1. " TNS ,Timer count in nanoseconds"
|
|
wgroup.long 0x1D8++0x03
|
|
line.long 0x00 "TA,1588 Timer Adjust Register"
|
|
bitfld.long 0x00 31. " ADJ ,Adjust 1588 Timer" "Add,Subtract"
|
|
hexmask.long 0x00 0.--29. 1. " ITDT ,Increment/Decrement"
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "TI,1588 Timer Increment Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NIT ,Number of Increments"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ACNS ,Alternative count nanoseconds"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CNS ,Count nanoseconds"
|
|
else
|
|
group.long 0x1C8++0x17
|
|
line.long 0x00 "TSSS,1588 Timer Sync Strobe Seconds Register"
|
|
line.long 0x04 "TSSN,1588 Timer Sync Strobe Nanoseconds Register"
|
|
hexmask.long 0x04 0.--29. 1. " VTN ,Value timer nanoseconds register capture"
|
|
line.long 0x08 "TS,1588 Timer Seconds Register"
|
|
line.long 0x0C "TN,1588 Timer Nanoseconds Register"
|
|
hexmask.long 0x0C 0.--29. 1. " TNS ,Timer count in nanoseconds"
|
|
line.long 0x10 "TA,1588 Timer Adjust Register"
|
|
bitfld.long 0x10 31. " ADJ ,Adjust 1588 timer" "Addition,Subtraction"
|
|
hexmask.long 0x10 0.--29. 1. " ITDT ,Increment/Decrement"
|
|
line.long 0x14 "TI,1588 Timer Increment Register"
|
|
hexmask.long.byte 0x14 16.--23. 1. " NIT ,Number of increments"
|
|
hexmask.long.byte 0x14 8.--15. 1. " ACNS ,Alternative count nanoseconds"
|
|
textline " "
|
|
hexmask.long.byte 0x14 0.--7. 1. " CNS ,Count nanoseconds"
|
|
endif
|
|
sif (cpuis("ATSAMA5D2?")||cpuis("ATSAMA5D3*")||cpuis("ATSAMA5D4*")||cpuis("ATSAME5*"))
|
|
rgroup.long 0x1E0++0x1F
|
|
line.long 0x00 "EFTSL,PTP Event Frame Transmitted Seconds Low Register"
|
|
line.long 0x04 "EFTN,PTP Event Frame Transmitted Nanoseconds Register"
|
|
hexmask.long 0x04 0.--29. 1. " RUD ,Register update"
|
|
line.long 0x08 "EFRSL,PTP Event Frame Received Seconds Low Register"
|
|
line.long 0x0C "EFRN,PTP Event Frame Received Nanoseconds Register"
|
|
hexmask.long 0x0C 0.--29. 1. " RUD ,Register update"
|
|
line.long 0x10 "PEFTSL,PTP Peer Event Frame Transmitted Seconds Low Register"
|
|
line.long 0x14 "PEFTN,PTP Peer Event Frame Transmitted Nanoseconds Register"
|
|
hexmask.long 0x14 0.--29. 1. " RUD ,Register update"
|
|
line.long 0x18 "PEFRSL,PTP Peer Event Frame Received Seconds Low Register"
|
|
line.long 0x1C "PEFRN,PTP Peer Event Frame Received Nanoseconds Register"
|
|
hexmask.long 0x1C 0.--29. 1. " RUD ,Register update"
|
|
else
|
|
rgroup.long 0x1E0++0x1F
|
|
line.long 0x00 "EFTS,PTP Event Frame Transmitted Seconds Register"
|
|
line.long 0x04 "EFTN,PTP Event Frame Transmitted Nanoseconds Register"
|
|
hexmask.long 0x04 0.--29. 1. " RUD ,Register update"
|
|
line.long 0x08 "EFRS,PTP Event Frame Received Seconds Register"
|
|
line.long 0x0C "EFRN,PTP Event Frame Received Nanoseconds Register"
|
|
hexmask.long 0x0C 0.--29. 1. " RUD ,Register update"
|
|
line.long 0x10 "PEFTS,PTP Peer Event Frame Transmitted Seconds Register"
|
|
line.long 0x14 "PEFTN,PTP Peer Event Frame Transmitted Nanoseconds Register"
|
|
hexmask.long 0x14 0.--29. 1. " RUD ,Register update"
|
|
line.long 0x18 "PEFRS,PTP Peer Event Frame Received Seconds Register"
|
|
line.long 0x1C "PEFRN,PTP Peer Event Frame Received Nanoseconds Register"
|
|
hexmask.long 0x1C 0.--29. 1. " RUD ,Register update"
|
|
endif
|
|
sif (cpuis("ATSAMA5D2?"))||(cpuis("ATSAMA5D4?"))
|
|
hgroup.long 0x270++0x03
|
|
hide.long 0x00 "RXLPI,Received LPI Transitions"
|
|
in
|
|
hgroup.long 0x274++0x03
|
|
hide.long 0x00 "RXLPITIME,Received LPI Time"
|
|
in
|
|
hgroup.long 0x278++0x03
|
|
hide.long 0x00 "TXLPI,Transmit LPI Transitions"
|
|
in
|
|
hgroup.long 0x27C++0x03
|
|
hide.long 0x00 "TXLPITIME,Transmit LPI Time"
|
|
in
|
|
endif
|
|
sif cpuis("ATSAMA5D2?")
|
|
rgroup.long (0x3FC+0x0)++0x03
|
|
line.long 0x00 "ISRPQ1,Interrupt Status Register Priority Queue 1"
|
|
bitfld.long 0x00 11. " HRESP ,HRESP not OK" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ROVR ,Receive overrun" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TCOMP ,Transmit complete" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " TFC ,Transmit frame corruption due to AHB error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RLEX ,Retry limit exceeded or late collision" "No error,Error"
|
|
bitfld.long 0x00 2. " RXUBR ,RX used bit read" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCOMP ,Receive complete" "No completed,Completed"
|
|
rgroup.long (0x3FC+0x4)++0x03
|
|
line.long 0x00 "ISRPQ2,Interrupt Status Register Priority Queue 2"
|
|
bitfld.long 0x00 11. " HRESP ,HRESP not OK" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ROVR ,Receive overrun" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TCOMP ,Transmit complete" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " TFC ,Transmit frame corruption due to AHB error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RLEX ,Retry limit exceeded or late collision" "No error,Error"
|
|
bitfld.long 0x00 2. " RXUBR ,RX used bit read" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCOMP ,Receive complete" "No completed,Completed"
|
|
group.long (0x43C+0x0)++0x03
|
|
line.long 0x00 "TBQBAPQ1,Transmit Buffer Queue Base Address Priority Queue 1"
|
|
hexmask.long 0x00 2.--31. 0x04 " TXBQBA ,Transmit buffer queue base address"
|
|
group.long (0x43C+0x4)++0x03
|
|
line.long 0x00 "TBQBAPQ2,Transmit Buffer Queue Base Address Priority Queue 2"
|
|
hexmask.long 0x00 2.--31. 0x04 " TXBQBA ,Transmit buffer queue base address"
|
|
group.long (0x47C+0x0)++0x03
|
|
line.long 0x00 "RBQBAPQ1,Receive Buffer Queue Base Address Priority Queue 1"
|
|
hexmask.long 0x00 2.--31. 0x04 " RXBQBA ,Transmit buffer queue base address"
|
|
group.long (0x47C+0x4)++0x03
|
|
line.long 0x00 "RBQBAPQ2,Receive Buffer Queue Base Address Priority Queue 2"
|
|
hexmask.long 0x00 2.--31. 0x04 " RXBQBA ,Transmit buffer queue base address"
|
|
group.long (0x49C+0x0)++0x03
|
|
line.long 0x00 "RBSRPQ1,Receive Buffer Size Register Priority Queue 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " RBS ,Receive buffer size"
|
|
group.long (0x49C+0x4)++0x03
|
|
line.long 0x00 "RBSRPQ2,Receive Buffer Size Register Priority Queue 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " RBS ,Receive buffer size"
|
|
group.long 0x4BC++0x03
|
|
line.long 0x00 "CBSCR,Credit-Based Shaping Control Register"
|
|
bitfld.long 0x00 1. " QAE ,Enable credit-based shaping on queue A" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " QBE ,Enable credit-based shaping on queue B" "Disabled,Enabled"
|
|
group.long 0x4C0++0x07
|
|
line.long 0x00 "CBSISQA,Credit-Based Shaping IdleSlope Register for Queue A"
|
|
line.long 0x04 "CBSISQB,Credit-Based Shaping IdleSlope Register for Queue B"
|
|
group.long (0x500+0x0)++0x03
|
|
line.long 0x00 "ST1RPQ0,Screening Type1 Register Priority Queue 0"
|
|
bitfld.long 0x00 29. " UDPE ,UDP port match enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DSTCE ,Differentiated services or traffic class match enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 12.--27. 1. " UDPM ,UDP port match"
|
|
hexmask.long.byte 0x00 4.--11. 1. " DSTCM ,Differentiated services or traffic class match"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " QNB ,Que number" "0,1,2,?..."
|
|
group.long (0x500+0x4)++0x03
|
|
line.long 0x00 "ST1RPQ1,Screening Type1 Register Priority Queue 1"
|
|
bitfld.long 0x00 29. " UDPE ,UDP port match enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DSTCE ,Differentiated services or traffic class match enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 12.--27. 1. " UDPM ,UDP port match"
|
|
hexmask.long.byte 0x00 4.--11. 1. " DSTCM ,Differentiated services or traffic class match"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " QNB ,Que number" "0,1,2,?..."
|
|
group.long (0x500+0x8)++0x03
|
|
line.long 0x00 "ST1RPQ2,Screening Type1 Register Priority Queue 2"
|
|
bitfld.long 0x00 29. " UDPE ,UDP port match enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DSTCE ,Differentiated services or traffic class match enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 12.--27. 1. " UDPM ,UDP port match"
|
|
hexmask.long.byte 0x00 4.--11. 1. " DSTCM ,Differentiated services or traffic class match"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " QNB ,Que number" "0,1,2,?..."
|
|
group.long (0x500+0xC)++0x03
|
|
line.long 0x00 "ST1RPQ3,Screening Type1 Register Priority Queue 3"
|
|
bitfld.long 0x00 29. " UDPE ,UDP port match enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DSTCE ,Differentiated services or traffic class match enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 12.--27. 1. " UDPM ,UDP port match"
|
|
hexmask.long.byte 0x00 4.--11. 1. " DSTCM ,Differentiated services or traffic class match"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " QNB ,Que number" "0,1,2,?..."
|
|
group.long (0x540+0x0)++0x03
|
|
line.long 0x00 "ST2RPQ0,Screening Type2 Register Priority Queue 0"
|
|
bitfld.long 0x00 30. " COMPCE ,Compare C enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--29. " COMPC ,Index of screening type 2 compare word 0/word 1 register 0 (for compare C)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 24. " COMPBE ,Compare B enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19.--23. " COMPB ,Index of screening type 2 compare word 0/word 1 register 0 (for compare B)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 18. " COMPAE ,Compare A enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--17. " COMPA ,Index of screening type 2 compare word 0/word 1 register 0 (for compare A)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ETHE ,EtherType enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--11. " I2ETH ,Index of screening type 2 EtherType register 0" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 8. " VLANE ,VLAN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " VLANP ,VLAN priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " QNB ,Que number" "0,1,2,?..."
|
|
group.long (0x540+0x4)++0x03
|
|
line.long 0x00 "ST2RPQ1,Screening Type2 Register Priority Queue 1"
|
|
bitfld.long 0x00 30. " COMPCE ,Compare C enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--29. " COMPC ,Index of screening type 2 compare word 0/word 1 register 1 (for compare C)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 24. " COMPBE ,Compare B enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19.--23. " COMPB ,Index of screening type 2 compare word 0/word 1 register 1 (for compare B)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 18. " COMPAE ,Compare A enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--17. " COMPA ,Index of screening type 2 compare word 0/word 1 register 1 (for compare A)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ETHE ,EtherType enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--11. " I2ETH ,Index of screening type 2 EtherType register 1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 8. " VLANE ,VLAN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " VLANP ,VLAN priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " QNB ,Que number" "0,1,2,?..."
|
|
group.long (0x540+0x8)++0x03
|
|
line.long 0x00 "ST2RPQ2,Screening Type2 Register Priority Queue 2"
|
|
bitfld.long 0x00 30. " COMPCE ,Compare C enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--29. " COMPC ,Index of screening type 2 compare word 0/word 1 register 2 (for compare C)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 24. " COMPBE ,Compare B enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19.--23. " COMPB ,Index of screening type 2 compare word 0/word 1 register 2 (for compare B)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 18. " COMPAE ,Compare A enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--17. " COMPA ,Index of screening type 2 compare word 0/word 1 register 2 (for compare A)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ETHE ,EtherType enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--11. " I2ETH ,Index of screening type 2 EtherType register 2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 8. " VLANE ,VLAN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " VLANP ,VLAN priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " QNB ,Que number" "0,1,2,?..."
|
|
group.long (0x540+0xC)++0x03
|
|
line.long 0x00 "ST2RPQ3,Screening Type2 Register Priority Queue 3"
|
|
bitfld.long 0x00 30. " COMPCE ,Compare C enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--29. " COMPC ,Index of screening type 2 compare word 0/word 1 register 3 (for compare C)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 24. " COMPBE ,Compare B enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19.--23. " COMPB ,Index of screening type 2 compare word 0/word 1 register 3 (for compare B)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 18. " COMPAE ,Compare A enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--17. " COMPA ,Index of screening type 2 compare word 0/word 1 register 3 (for compare A)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ETHE ,EtherType enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--11. " I2ETH ,Index of screening type 2 EtherType register 3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 8. " VLANE ,VLAN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " VLANP ,VLAN priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " QNB ,Que number" "0,1,2,?..."
|
|
group.long (0x540+0x10)++0x03
|
|
line.long 0x00 "ST2RPQ4,Screening Type2 Register Priority Queue 4"
|
|
bitfld.long 0x00 30. " COMPCE ,Compare C enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--29. " COMPC ,Index of screening type 2 compare word 0/word 1 register 4 (for compare C)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 24. " COMPBE ,Compare B enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19.--23. " COMPB ,Index of screening type 2 compare word 0/word 1 register 4 (for compare B)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 18. " COMPAE ,Compare A enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--17. " COMPA ,Index of screening type 2 compare word 0/word 1 register 4 (for compare A)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ETHE ,EtherType enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--11. " I2ETH ,Index of screening type 2 EtherType register 4" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 8. " VLANE ,VLAN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " VLANP ,VLAN priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " QNB ,Que number" "0,1,2,?..."
|
|
group.long (0x540+0x14)++0x03
|
|
line.long 0x00 "ST2RPQ5,Screening Type2 Register Priority Queue 5"
|
|
bitfld.long 0x00 30. " COMPCE ,Compare C enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--29. " COMPC ,Index of screening type 2 compare word 0/word 1 register 5 (for compare C)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 24. " COMPBE ,Compare B enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19.--23. " COMPB ,Index of screening type 2 compare word 0/word 1 register 5 (for compare B)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 18. " COMPAE ,Compare A enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--17. " COMPA ,Index of screening type 2 compare word 0/word 1 register 5 (for compare A)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ETHE ,EtherType enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--11. " I2ETH ,Index of screening type 2 EtherType register 5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 8. " VLANE ,VLAN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " VLANP ,VLAN priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " QNB ,Que number" "0,1,2,?..."
|
|
group.long (0x540+0x18)++0x03
|
|
line.long 0x00 "ST2RPQ6,Screening Type2 Register Priority Queue 6"
|
|
bitfld.long 0x00 30. " COMPCE ,Compare C enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--29. " COMPC ,Index of screening type 2 compare word 0/word 1 register 6 (for compare C)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 24. " COMPBE ,Compare B enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19.--23. " COMPB ,Index of screening type 2 compare word 0/word 1 register 6 (for compare B)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 18. " COMPAE ,Compare A enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--17. " COMPA ,Index of screening type 2 compare word 0/word 1 register 6 (for compare A)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ETHE ,EtherType enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--11. " I2ETH ,Index of screening type 2 EtherType register 6" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 8. " VLANE ,VLAN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " VLANP ,VLAN priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " QNB ,Que number" "0,1,2,?..."
|
|
group.long (0x540+0x1C)++0x03
|
|
line.long 0x00 "ST2RPQ7,Screening Type2 Register Priority Queue 7"
|
|
bitfld.long 0x00 30. " COMPCE ,Compare C enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--29. " COMPC ,Index of screening type 2 compare word 0/word 1 register 7 (for compare C)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 24. " COMPBE ,Compare B enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19.--23. " COMPB ,Index of screening type 2 compare word 0/word 1 register 7 (for compare B)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 18. " COMPAE ,Compare A enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--17. " COMPA ,Index of screening type 2 compare word 0/word 1 register 7 (for compare A)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ETHE ,EtherType enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--11. " I2ETH ,Index of screening type 2 EtherType register 7" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 8. " VLANE ,VLAN enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " VLANP ,VLAN priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " QNB ,Que number" "0,1,2,?..."
|
|
group.long (0x63C+0x0)++0x03
|
|
line.long 0x00 "IMRPQ1,Interrupt Mask Register Priority Queue1"
|
|
setclrfld.long 0x00 11. -0x40 11. -0x20 11. " HRESP_set/clr ,HRESP not OK" "Not masked,Masked"
|
|
setclrfld.long 0x00 10. -0x40 10. -0x20 10. " ROVR_set/clr ,Receive overrun" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x40 7. -0x20 7. " TCOMP_set/clr ,Transmit complete" "Not masked,Masked"
|
|
setclrfld.long 0x00 6. -0x40 6. -0x20 6. " AHB_set/clr ,AHB error" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x40 5. -0x20 5. " RLEX_set/clr ,Retry limit exceeded or late collision" "Not masked,Masked"
|
|
setclrfld.long 0x00 2. -0x40 2. -0x20 2. " RXUBR_set/clr ,RX used bit read" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x40 1. -0x20 1. " RCOMP_set/clr ,Receive complete" "Not masked,Masked"
|
|
group.long (0x63C+0x4)++0x03
|
|
line.long 0x00 "IMRPQ2,Interrupt Mask Register Priority Queue2"
|
|
setclrfld.long 0x00 11. -0x40 11. -0x20 11. " HRESP_set/clr ,HRESP not OK" "Not masked,Masked"
|
|
setclrfld.long 0x00 10. -0x40 10. -0x20 10. " ROVR_set/clr ,Receive overrun" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x40 7. -0x20 7. " TCOMP_set/clr ,Transmit complete" "Not masked,Masked"
|
|
setclrfld.long 0x00 6. -0x40 6. -0x20 6. " AHB_set/clr ,AHB error" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x40 5. -0x20 5. " RLEX_set/clr ,Retry limit exceeded or late collision" "Not masked,Masked"
|
|
setclrfld.long 0x00 2. -0x40 2. -0x20 2. " RXUBR_set/clr ,RX used bit read" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x40 1. -0x20 1. " RCOMP_set/clr ,Receive complete" "Not masked,Masked"
|
|
group.long (0x6E0+0x0)++0x03
|
|
line.long 0x00 "ST2ER0,Screening Type 2 EtherType Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " COMPVAL ,Ethertype compare value"
|
|
group.long (0x6E0+0x4)++0x03
|
|
line.long 0x00 "ST2ER1,Screening Type 2 EtherType Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " COMPVAL ,Ethertype compare value"
|
|
group.long (0x6E0+0x8)++0x03
|
|
line.long 0x00 "ST2ER2,Screening Type 2 EtherType Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " COMPVAL ,Ethertype compare value"
|
|
group.long (0x6E0+0xC)++0x03
|
|
line.long 0x00 "ST2ER3,Screening Type 2 EtherType Register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " COMPVAL ,Ethertype compare value"
|
|
group.long (0x700+0x0)++0x03
|
|
line.long 0x00 "ST2CW00,Screening Type 2 Compare Word 0 Register 0"
|
|
hexmask.long.word 0x00 16.--31. 0x01 " COMPVAL ,Compare value"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " MASKVAL ,Mask value"
|
|
group.long (0x700+0x8)++0x03
|
|
line.long 0x00 "ST2CW01,Screening Type 2 Compare Word 0 Register 1"
|
|
hexmask.long.word 0x00 16.--31. 0x01 " COMPVAL ,Compare value"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " MASKVAL ,Mask value"
|
|
group.long (0x700+0x10)++0x03
|
|
line.long 0x00 "ST2CW02,Screening Type 2 Compare Word 0 Register 2"
|
|
hexmask.long.word 0x00 16.--31. 0x01 " COMPVAL ,Compare value"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " MASKVAL ,Mask value"
|
|
group.long (0x700+0x18)++0x03
|
|
line.long 0x00 "ST2CW03,Screening Type 2 Compare Word 0 Register 3"
|
|
hexmask.long.word 0x00 16.--31. 0x01 " COMPVAL ,Compare value"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " MASKVAL ,Mask value"
|
|
group.long (0x700+0x20)++0x03
|
|
line.long 0x00 "ST2CW04,Screening Type 2 Compare Word 0 Register 4"
|
|
hexmask.long.word 0x00 16.--31. 0x01 " COMPVAL ,Compare value"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " MASKVAL ,Mask value"
|
|
group.long (0x700+0x28)++0x03
|
|
line.long 0x00 "ST2CW05,Screening Type 2 Compare Word 0 Register 5"
|
|
hexmask.long.word 0x00 16.--31. 0x01 " COMPVAL ,Compare value"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " MASKVAL ,Mask value"
|
|
group.long (0x700+0x30)++0x03
|
|
line.long 0x00 "ST2CW06,Screening Type 2 Compare Word 0 Register 6"
|
|
hexmask.long.word 0x00 16.--31. 0x01 " COMPVAL ,Compare value"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " MASKVAL ,Mask value"
|
|
group.long (0x700+0x38)++0x03
|
|
line.long 0x00 "ST2CW07,Screening Type 2 Compare Word 0 Register 7"
|
|
hexmask.long.word 0x00 16.--31. 0x01 " COMPVAL ,Compare value"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " MASKVAL ,Mask value"
|
|
group.long (0x700+0x40)++0x03
|
|
line.long 0x00 "ST2CW08,Screening Type 2 Compare Word 0 Register 8"
|
|
hexmask.long.word 0x00 16.--31. 0x01 " COMPVAL ,Compare value"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " MASKVAL ,Mask value"
|
|
group.long (0x700+0x48)++0x03
|
|
line.long 0x00 "ST2CW09,Screening Type 2 Compare Word 0 Register 9"
|
|
hexmask.long.word 0x00 16.--31. 0x01 " COMPVAL ,Compare value"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " MASKVAL ,Mask value"
|
|
group.long (0x700+0x50)++0x03
|
|
line.long 0x00 "ST2CW010,Screening Type 2 Compare Word 0 Register 10"
|
|
hexmask.long.word 0x00 16.--31. 0x01 " COMPVAL ,Compare value"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " MASKVAL ,Mask value"
|
|
group.long (0x700+0x58)++0x03
|
|
line.long 0x00 "ST2CW011,Screening Type 2 Compare Word 0 Register 11"
|
|
hexmask.long.word 0x00 16.--31. 0x01 " COMPVAL ,Compare value"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " MASKVAL ,Mask value"
|
|
group.long (0x700+0x60)++0x03
|
|
line.long 0x00 "ST2CW012,Screening Type 2 Compare Word 0 Register 12"
|
|
hexmask.long.word 0x00 16.--31. 0x01 " COMPVAL ,Compare value"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " MASKVAL ,Mask value"
|
|
group.long (0x700+0x68)++0x03
|
|
line.long 0x00 "ST2CW013,Screening Type 2 Compare Word 0 Register 13"
|
|
hexmask.long.word 0x00 16.--31. 0x01 " COMPVAL ,Compare value"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " MASKVAL ,Mask value"
|
|
group.long (0x700+0x70)++0x03
|
|
line.long 0x00 "ST2CW014,Screening Type 2 Compare Word 0 Register 14"
|
|
hexmask.long.word 0x00 16.--31. 0x01 " COMPVAL ,Compare value"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " MASKVAL ,Mask value"
|
|
group.long (0x700+0x78)++0x03
|
|
line.long 0x00 "ST2CW015,Screening Type 2 Compare Word 0 Register 15"
|
|
hexmask.long.word 0x00 16.--31. 0x01 " COMPVAL ,Compare value"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " MASKVAL ,Mask value"
|
|
group.long (0x700+0x80)++0x03
|
|
line.long 0x00 "ST2CW016,Screening Type 2 Compare Word 0 Register 16"
|
|
hexmask.long.word 0x00 16.--31. 0x01 " COMPVAL ,Compare value"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " MASKVAL ,Mask value"
|
|
group.long (0x700+0x88)++0x03
|
|
line.long 0x00 "ST2CW017,Screening Type 2 Compare Word 0 Register 17"
|
|
hexmask.long.word 0x00 16.--31. 0x01 " COMPVAL ,Compare value"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " MASKVAL ,Mask value"
|
|
group.long (0x700+0x90)++0x03
|
|
line.long 0x00 "ST2CW018,Screening Type 2 Compare Word 0 Register 18"
|
|
hexmask.long.word 0x00 16.--31. 0x01 " COMPVAL ,Compare value"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " MASKVAL ,Mask value"
|
|
group.long (0x700+0x98)++0x03
|
|
line.long 0x00 "ST2CW019,Screening Type 2 Compare Word 0 Register 19"
|
|
hexmask.long.word 0x00 16.--31. 0x01 " COMPVAL ,Compare value"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " MASKVAL ,Mask value"
|
|
group.long (0x700+0xA0)++0x03
|
|
line.long 0x00 "ST2CW020,Screening Type 2 Compare Word 0 Register 20"
|
|
hexmask.long.word 0x00 16.--31. 0x01 " COMPVAL ,Compare value"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " MASKVAL ,Mask value"
|
|
group.long (0x700+0xA8)++0x03
|
|
line.long 0x00 "ST2CW021,Screening Type 2 Compare Word 0 Register 21"
|
|
hexmask.long.word 0x00 16.--31. 0x01 " COMPVAL ,Compare value"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " MASKVAL ,Mask value"
|
|
group.long (0x700+0xB0)++0x03
|
|
line.long 0x00 "ST2CW022,Screening Type 2 Compare Word 0 Register 22"
|
|
hexmask.long.word 0x00 16.--31. 0x01 " COMPVAL ,Compare value"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " MASKVAL ,Mask value"
|
|
group.long (0x700+0xB8)++0x03
|
|
line.long 0x00 "ST2CW023,Screening Type 2 Compare Word 0 Register 23"
|
|
hexmask.long.word 0x00 16.--31. 0x01 " COMPVAL ,Compare value"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " MASKVAL ,Mask value"
|
|
group.long (0x704+0x0)++0x03
|
|
line.long 0x00 "ST2CW10,Screening Type 2 Compare Word 1 Register 0"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " OFFSVAL ,Offset value in bytes"
|
|
bitfld.long 0x00 7.--8. " OFFSSTRT ,Ethernet frame offset start" "Frame start,EtherType field,IP field,TCP/UDP field"
|
|
group.long (0x704+0x8)++0x03
|
|
line.long 0x00 "ST2CW11,Screening Type 2 Compare Word 1 Register 1"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " OFFSVAL ,Offset value in bytes"
|
|
bitfld.long 0x00 7.--8. " OFFSSTRT ,Ethernet frame offset start" "Frame start,EtherType field,IP field,TCP/UDP field"
|
|
group.long (0x704+0x10)++0x03
|
|
line.long 0x00 "ST2CW12,Screening Type 2 Compare Word 1 Register 2"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " OFFSVAL ,Offset value in bytes"
|
|
bitfld.long 0x00 7.--8. " OFFSSTRT ,Ethernet frame offset start" "Frame start,EtherType field,IP field,TCP/UDP field"
|
|
group.long (0x704+0x18)++0x03
|
|
line.long 0x00 "ST2CW13,Screening Type 2 Compare Word 1 Register 3"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " OFFSVAL ,Offset value in bytes"
|
|
bitfld.long 0x00 7.--8. " OFFSSTRT ,Ethernet frame offset start" "Frame start,EtherType field,IP field,TCP/UDP field"
|
|
group.long (0x704+0x20)++0x03
|
|
line.long 0x00 "ST2CW14,Screening Type 2 Compare Word 1 Register 4"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " OFFSVAL ,Offset value in bytes"
|
|
bitfld.long 0x00 7.--8. " OFFSSTRT ,Ethernet frame offset start" "Frame start,EtherType field,IP field,TCP/UDP field"
|
|
group.long (0x704+0x28)++0x03
|
|
line.long 0x00 "ST2CW15,Screening Type 2 Compare Word 1 Register 5"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " OFFSVAL ,Offset value in bytes"
|
|
bitfld.long 0x00 7.--8. " OFFSSTRT ,Ethernet frame offset start" "Frame start,EtherType field,IP field,TCP/UDP field"
|
|
group.long (0x704+0x30)++0x03
|
|
line.long 0x00 "ST2CW16,Screening Type 2 Compare Word 1 Register 6"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " OFFSVAL ,Offset value in bytes"
|
|
bitfld.long 0x00 7.--8. " OFFSSTRT ,Ethernet frame offset start" "Frame start,EtherType field,IP field,TCP/UDP field"
|
|
group.long (0x704+0x38)++0x03
|
|
line.long 0x00 "ST2CW17,Screening Type 2 Compare Word 1 Register 7"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " OFFSVAL ,Offset value in bytes"
|
|
bitfld.long 0x00 7.--8. " OFFSSTRT ,Ethernet frame offset start" "Frame start,EtherType field,IP field,TCP/UDP field"
|
|
group.long (0x704+0x40)++0x03
|
|
line.long 0x00 "ST2CW18,Screening Type 2 Compare Word 1 Register 8"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " OFFSVAL ,Offset value in bytes"
|
|
bitfld.long 0x00 7.--8. " OFFSSTRT ,Ethernet frame offset start" "Frame start,EtherType field,IP field,TCP/UDP field"
|
|
group.long (0x704+0x48)++0x03
|
|
line.long 0x00 "ST2CW19,Screening Type 2 Compare Word 1 Register 9"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " OFFSVAL ,Offset value in bytes"
|
|
bitfld.long 0x00 7.--8. " OFFSSTRT ,Ethernet frame offset start" "Frame start,EtherType field,IP field,TCP/UDP field"
|
|
group.long (0x704+0x50)++0x03
|
|
line.long 0x00 "ST2CW110,Screening Type 2 Compare Word 1 Register 10"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " OFFSVAL ,Offset value in bytes"
|
|
bitfld.long 0x00 7.--8. " OFFSSTRT ,Ethernet frame offset start" "Frame start,EtherType field,IP field,TCP/UDP field"
|
|
group.long (0x704+0x58)++0x03
|
|
line.long 0x00 "ST2CW111,Screening Type 2 Compare Word 1 Register 11"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " OFFSVAL ,Offset value in bytes"
|
|
bitfld.long 0x00 7.--8. " OFFSSTRT ,Ethernet frame offset start" "Frame start,EtherType field,IP field,TCP/UDP field"
|
|
group.long (0x704+0x60)++0x03
|
|
line.long 0x00 "ST2CW112,Screening Type 2 Compare Word 1 Register 12"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " OFFSVAL ,Offset value in bytes"
|
|
bitfld.long 0x00 7.--8. " OFFSSTRT ,Ethernet frame offset start" "Frame start,EtherType field,IP field,TCP/UDP field"
|
|
group.long (0x704+0x68)++0x03
|
|
line.long 0x00 "ST2CW113,Screening Type 2 Compare Word 1 Register 13"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " OFFSVAL ,Offset value in bytes"
|
|
bitfld.long 0x00 7.--8. " OFFSSTRT ,Ethernet frame offset start" "Frame start,EtherType field,IP field,TCP/UDP field"
|
|
group.long (0x704+0x70)++0x03
|
|
line.long 0x00 "ST2CW114,Screening Type 2 Compare Word 1 Register 14"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " OFFSVAL ,Offset value in bytes"
|
|
bitfld.long 0x00 7.--8. " OFFSSTRT ,Ethernet frame offset start" "Frame start,EtherType field,IP field,TCP/UDP field"
|
|
group.long (0x704+0x78)++0x03
|
|
line.long 0x00 "ST2CW115,Screening Type 2 Compare Word 1 Register 15"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " OFFSVAL ,Offset value in bytes"
|
|
bitfld.long 0x00 7.--8. " OFFSSTRT ,Ethernet frame offset start" "Frame start,EtherType field,IP field,TCP/UDP field"
|
|
group.long (0x704+0x80)++0x03
|
|
line.long 0x00 "ST2CW116,Screening Type 2 Compare Word 1 Register 16"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " OFFSVAL ,Offset value in bytes"
|
|
bitfld.long 0x00 7.--8. " OFFSSTRT ,Ethernet frame offset start" "Frame start,EtherType field,IP field,TCP/UDP field"
|
|
group.long (0x704+0x88)++0x03
|
|
line.long 0x00 "ST2CW117,Screening Type 2 Compare Word 1 Register 17"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " OFFSVAL ,Offset value in bytes"
|
|
bitfld.long 0x00 7.--8. " OFFSSTRT ,Ethernet frame offset start" "Frame start,EtherType field,IP field,TCP/UDP field"
|
|
group.long (0x704+0x90)++0x03
|
|
line.long 0x00 "ST2CW118,Screening Type 2 Compare Word 1 Register 18"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " OFFSVAL ,Offset value in bytes"
|
|
bitfld.long 0x00 7.--8. " OFFSSTRT ,Ethernet frame offset start" "Frame start,EtherType field,IP field,TCP/UDP field"
|
|
group.long (0x704+0x98)++0x03
|
|
line.long 0x00 "ST2CW119,Screening Type 2 Compare Word 1 Register 19"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " OFFSVAL ,Offset value in bytes"
|
|
bitfld.long 0x00 7.--8. " OFFSSTRT ,Ethernet frame offset start" "Frame start,EtherType field,IP field,TCP/UDP field"
|
|
group.long (0x704+0xA0)++0x03
|
|
line.long 0x00 "ST2CW120,Screening Type 2 Compare Word 1 Register 20"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " OFFSVAL ,Offset value in bytes"
|
|
bitfld.long 0x00 7.--8. " OFFSSTRT ,Ethernet frame offset start" "Frame start,EtherType field,IP field,TCP/UDP field"
|
|
group.long (0x704+0xA8)++0x03
|
|
line.long 0x00 "ST2CW121,Screening Type 2 Compare Word 1 Register 21"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " OFFSVAL ,Offset value in bytes"
|
|
bitfld.long 0x00 7.--8. " OFFSSTRT ,Ethernet frame offset start" "Frame start,EtherType field,IP field,TCP/UDP field"
|
|
group.long (0x704+0xB0)++0x03
|
|
line.long 0x00 "ST2CW122,Screening Type 2 Compare Word 1 Register 22"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " OFFSVAL ,Offset value in bytes"
|
|
bitfld.long 0x00 7.--8. " OFFSSTRT ,Ethernet frame offset start" "Frame start,EtherType field,IP field,TCP/UDP field"
|
|
group.long (0x704+0xB8)++0x03
|
|
line.long 0x00 "ST2CW123,Screening Type 2 Compare Word 1 Register 23"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " OFFSVAL ,Offset value in bytes"
|
|
bitfld.long 0x00 7.--8. " OFFSSTRT ,Ethernet frame offset start" "Frame start,EtherType field,IP field,TCP/UDP field"
|
|
endif
|
|
sif cpuis("ATSAME5*")
|
|
hgroup.long 0x270++0x03
|
|
hide.long 0x00 "RLPITR,Received LPI Transitions"
|
|
in
|
|
hgroup.long 0x274++0x03
|
|
hide.long 0x00 "RLPITI,Received LPI Time"
|
|
in
|
|
rgroup.long 0x278++0x03
|
|
line.long 0x00 "TLPITR,Transmit LPI Transitions"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TLPITR ,Transmit LPI transitions"
|
|
hgroup.long 0x27C++0x03
|
|
hide.long 0x00 "TLPITI,Transmit LPI Time"
|
|
in
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DACC (Digital-to-Analog Converter Controller)"
|
|
base ad:0x400B8000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "DACC_CR,DACC Control Register"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "No effect,Reset"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DACC_MR,DACC Mode Register"
|
|
sif cpuis("ATSAM4E*")
|
|
bitfld.long 0x00 24.--29. " STARTUP ,Startup Time Selection (in DACClock periods)" "0,8,16,24,64,80,96,112,512,576,640,704,768,832,896,960,1024,1088,1152,1216,1280,1344,1408,1472,1536,1600,1664,1728,1792,1856,1920,1984,2048,2112,2176,2240,2304,2368,2432,2496,2560,2624,2688,2688,2816,2880,2944,3008,3072,3136,3200,3264,3328,3392,3456,3520,3584,3648,3712,3776,3840,3904,3968,4032"
|
|
bitfld.long 0x00 22. " CLKDIV ,Clock Divider" "MCK/2,MCK/4"
|
|
else
|
|
bitfld.long 0x00 24.--29. " STARTUP ,Startup Time Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " MAXS ,Max Speed Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TAG ,Tag Selection Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " USER_SEL ,User Channel Selection" "CHANNEL0,CHANNEL1,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " REFRESH ,Refresh Period"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FASTWKUP ,Fast Wake up Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SLEEP ,Sleep Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WORD ,Word Transfer" "Half-Word,Word"
|
|
bitfld.long 0x00 1.--3. " TRGSEL ,Trigger Selection" "External,TIO Output of the TC C0,TIO Output of the TC C1,TIO Output of the TC C2,PWM Event Line 0,PWM Event Line 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " TRGEN ,Trigger Enable" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DACC_CHSR,DACC Channel Status Register"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " CH1_set/clr ,Channel 1 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " CH0_set/clr ,Channel 0 Status" "Disabled,Enabled"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "DACC_CDR,DACC Conversion Data Register"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DACC_IMR,DACC Interrupt Mask Register"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " EOC_set/clr ,End of Conversion Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " TXRDY_set/clr ,Transmit Ready Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "DACC_ISR,DACC Interrupt Status Register"
|
|
in
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "DACC_ACR,DACC Analog Current Register"
|
|
bitfld.long 0x00 8.--9. " IBCTLDACCORE ,Bias Current Control for DAC Core" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " IBCTLCH1 ,Analog Output Current Control 1" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " IBCTLCH0 ,Analog Output Current Control 0" "0,1,2,3"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "DACC_WPMR,DACC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "DACC_WPSR,DACC Write Protect Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
textline ""
|